TW202215737A - Semiconductor protection device - Google Patents

Abstract

The semiconductor protection device of the invention comprises a first semiconductor, a second semiconductor, a third semiconductor, a fourth semiconductor, a first resistor, a second resistor, a third resistor, a fourth resistor and a first capacitor, constituting an application circuit with load overload or short circuit protection function of a DC load, which avoids the damage caused by overload or short circuit at both terminals of the load.

Description

Semiconductor protection device

The semiconductor protection device of the present invention has the protection function of overload or short circuit at both ends of the load during the application of the DC circuit, and includes a first semiconductor, a second semiconductor, a third semiconductor, a fourth semiconductor, a first resistor, a second semiconductor Electronic technology field of resistor, third resistor, fourth resistor and first capacitor.

As shown in Figure 1, please refer to Taiwan Patent Certificate No. Invention No. I583089 "Battery Discharge Protection Device", whose patentee is the same as the applicant of the present invention; when the charging operation is completed, change the charging device 100 to the load 200 , a first collector resistor 15 is connected between the positive terminal of the battery 11 and the collector C of the second semiconductor 14 , and the base B of the second semiconductor 14 and the drain D of the first semiconductor 12 are connected with In the first base resistor 16, when the load 200 is short-circuited during the discharge operation of the battery 11 to the load 200, the potential of the base B of the second semiconductor 14 is the circuit positive potential, so the potential of the base B of the second semiconductor 14 is high The second semiconductor 14 is turned on at the emitter E. At this time, the potentials of the gate G and the source S of the first semiconductor 12 are equal, so the first semiconductor 12 is opened, and the drain current of the first semiconductor 12 is stopped at this time. Protect the battery 11 due to the occurrence of The load 200 is short-circuited and the battery 11 is damaged. If you want to release the conduction state of the second semiconductor 14, you only need to remove the cause of the short circuit, then the conduction state of the second semiconductor 14 can be released, and the normal state of the first semiconductor 12 can be restored. as follows:

1. After removing the cause of the short circuit at both ends of the load 200, a switch should be set to open the load 200 (Off), and then the switch should be turned on (On) before the battery 11 can supply power to the load 200 again, thus increasing the cost of the device and application inconvenience.

2. To restore the normal circuit function, after removing the cause of the short circuit between the two ends of the load 200, and then re-powering the battery 11, a switch must be added, which increases the cost of the device and causes inconvenience in application.

Purpose of the present invention:

The present invention applies the first semiconductor, the second semiconductor, the third semiconductor, the fourth semiconductor, the first resistor, the second resistor, the third resistor, the fourth resistor and the first capacitor to achieve the power supply in the DC circuit. The DC power supply is protected in the event of load overload or short circuit.

When the load is short-circuited, the present invention uses the second semiconductor to perform the open-circuit action of the first semiconductor in a very short time, so as to achieve the function of protecting the DC power circuit and avoid various disasters caused by the load short-circuit.

The present invention is composed of a fourth semiconductor, a third resistor and a first capacitor to form a time delay circuit (Time Delay Circuits) to perform a delay action. When the present invention is turned on, the time delay circuit controls the third semiconductor to make the second semiconductor open. Delay action, when the cause of short circuit is eliminated, it is not necessary to send DC power again and there is no need to short circuit at both ends of the load After the cause is removed, a switch is required to perform the action of opening and conducting.

The present invention has the following features:

1. The first semiconductor of the present invention is responsible for the open circuit and conduction of the DC power supply to supply power to the load.

2. The second semiconductor of the present invention is responsible for controlling the open-circuit and conduction actions of the first semiconductor, so as to achieve the purpose of protecting the DC power supply circuit when a short circuit occurs at both ends of the load.

3. The third semiconductor of the present invention is responsible for controlling the open-circuit and conduction actions of the second semiconductor.

4. The present invention is composed of a fourth semiconductor, a third resistor and a first capacitor to form a delay circuit, which is responsible for executing the delay action and used to control the open circuit and conduction action of the third semiconductor.

5. In the present invention, the first resistor has the function of limiting current, so as to prevent the gate of the first semiconductor and the second semiconductor from having excessive current and damage the first semiconductor and the second semiconductor.

6. In the present invention, the second resistor has the function of limiting current to prevent the third semiconductor and the fourth semiconductor from being damaged due to excessive current in the gate or base and the fourth semiconductor.

7. The present invention is provided with a third resistor to control the charging time, so that the first semiconductor can be turned on smoothly.

8. In the present invention, the fourth resistor has the function of limiting current, so as to prevent the second semiconductor and the third semiconductor from being damaged due to excessive current in the gate or base and the third semiconductor.

9. In the present invention, the first capacitor has the function of controlling the charging time, so that the first semiconductor can be turned on smoothly.

10. The first semiconductor of the present invention is an N Channel Metal Oxide Semiconductor Field Effect Transistor (N Channel MOSFET), an Insulated Gate Bipolar Transistor (IGBT) Or N-type transistors (N Type Transistor) can be selected according to needs.

11. The second semiconductor of the present invention is an N-type transistor or an N-channel metal oxide semiconductor field effect transistor, which can be selected according to requirements.

12. The third semiconductor of the present invention is an N-type transistor or an N-channel metal-oxide-semiconductor field-effect transistor, which can be selected according to requirements.

13. The fourth semiconductor of the present invention is an N-type transistor or an N-channel metal-oxide-semiconductor field-effect transistor, which can be selected according to requirements.

14. Because the operation principle of the fourth semiconductor of the present invention is the same as that of the adjustable precision parallel regulator, it can be replaced by the adjustable precision parallel regulator.

10: The first DC power supply

11: The first switch

12: Load

20: Second DC power supply

21: Second switch

22: Adjustable precision parallel regulator

30: Semiconductor protection device of the present invention

31: First resistor

32: Second resistor

33: Third resistor

34: Fourth resistor

35: First capacitor

36: First Semiconductor

37: Second Semiconductor

38: Third Semiconductor

39: Fourth Semiconductor

40: The first terminal of the present invention

50: The second terminal of the present invention

60: The third terminal of the present invention

FIG. 1 is an embodiment of a conventional battery discharge protection device.

FIG. 2 is a first embodiment of the semiconductor protection device of the present invention.

FIG. 3 is a second embodiment of the semiconductor protection device of the present invention.

FIG. 4 is a third embodiment of the semiconductor protection device of the present invention.

As shown in FIG. 2, it is the first embodiment of the semiconductor protection device of the present invention. As can be seen from the figure, the semiconductor protection device 30 of the present invention includes a first semiconductor 36, a second semiconductor 37, a third semiconductor 38, a fourth semiconductor 39, The first resistor 31, the second resistor 32, the third resistor 33, the fourth resistor 34 and the first capacitor 35; the first DC power supply 10 is connected to the first end of the first switch 11, the first switch The second end of 11 is connected to the first end of the load 12, and the second end of the load 12 is connected to the second terminal 50, the drain D (Drain, D) of the first semiconductor 36 and the first end of the fourth resistor 34, The second end of the fourth resistor 34 is connected to the base B (Base, B) of the second semiconductor 37 and the collector C (Collector, C) of the third semiconductor 38 ; One end, the second end of the second switch 21 is connected to the first terminal 40, the first end of the first resistor 31, the first end of the second resistor 32 and the first end of the third resistor 33, the first The second end of the resistor 31 is connected to the gate G (Gate, G) of the first semiconductor 36 and the collector C of the second semiconductor 37 , and the second end of the second resistor 32 is connected to the base B of the third semiconductor 38 and the collector C of the second semiconductor 37 . The collector C of the fourth semiconductor 39, the second end of the third resistor 33 is connected to the base B of the fourth semiconductor 39 and the first end of the first capacitor 35; the source S (Source, S) of the first semiconductor 36 , the emitter E (Emitter, E) of the second semiconductor 37 , the emitter E of the third semiconductor 38 , the emitter E of the fourth semiconductor 39 , the second end of the first capacitor 35 , and the negative power of the first DC power supply 10 The terminal and the negative terminal of the second DC power supply 20 are connected to the third terminal 60 to become the ground terminal; the second DC power supply 20 can be regarded as a voltage source, and is not limited to a DC power supply, that is, a pulse power supply can be used instead; A semiconductor 36 is an N-channel metal oxide semiconductor field effect transistor, the second semiconductor 37 is an N-type transistor, the third semiconductor 38 is an N-type transistor, and the fourth semiconductor 39 is an N-type transistor.

As shown in FIG. 2 , the operating principle of the semiconductor protection device of the present invention is that when the first switch 11 is turned on, the current of the first DC power source 10 passes through the first switch 11 and the load 12 , and then passes through the second terminal 50 to the first DC power supply 10 . The drain D of the semiconductor 36 and the first end of the fourth resistor 34, the second end of the fourth resistor 34 goes to the base B of the second semiconductor 37 and the collector C of the third semiconductor 38, at this time the first semiconductor The gate G of the body 36 has no gate G voltage, so the drain D and the source S of the first semiconductor 36 are open circuited, while the collector C and the emitter E of the second semiconductor 37 are conductive, and the collector C of the third semiconductor 38 is connected. Open circuit with the emitter E, the collector C of the fourth semiconductor 39 is open circuit with the emitter E, because the second DC power supply 20 does not supply power, so the load 12 is not supplied by the first DC power supply 10; when the second switch 21 is turned on, the first DC power supply 10 is turned on. The current of the two DC power sources 20 passes through the first terminal 40, and then charges the first capacitor 35 through the third resistor 33. When the voltage at the base B and the emitter E of the fourth semiconductor 39 does not reach the collector C and the emitter When E is turned on, the second resistor 32 supplies power to the base B of the third semiconductor 38 at this time, so that the collector C and the emitter E of the third semiconductor 38 are turned on, so that the collector C and the emitter of the second semiconductor 37 are connected. E is open, and the first resistor 31 supplies power to the gate G of the first semiconductor 36, so the drain D of the first semiconductor 36 is connected to the source S. At this time, the first DC power supply 10 supplies power to the load 12; When the two switches 21 are open, since the gate G of the first semiconductor 36 is not supplied with power, the drain D and the source S of the first semiconductor 36 are open, and the first DC power supply 10 does not supply power to the load 12 at this time; It can be seen that, for practical application requirements, the N-channel metal oxide semiconductor field effect transistor applied to the first semiconductor 36 can be changed to an N-type transistor, because its operating principle is the same and is not self-limiting.

As shown in FIG. 2, the short-circuit protection action principle of the load 12 of the semiconductor protection device of the present invention is that when the first switch 11 and the second switch 21 are turned on, the load 12 is powered by the first DC power supply 10; when both ends of the load 12 are short-circuited , according to the output characteristic curve table (Output Characteristics) of the first semiconductor 36, when the drain current (Drain Current) of the first semiconductor 36 rises to its corresponding drain source voltage (Drain Source Voltage) reaches higher than the second On State Voltage between the base B and the emitter E of the semiconductor 37 At this time, the collector C and the emitter E of the second semiconductor 37 are turned on, so the drain D and the source S of the first semiconductor 36 are open-circuited, the first DC power supply 10 does not supply power to the short-circuit load 12, and makes the first The DC power supply 10 is protected; similarly, the overload protection function can also be achieved by properly selecting an overload (Over Load) sink current corresponding to the drain-source voltage of the first semiconductor 36 .

As shown in FIG. 3, it is the second embodiment of the semiconductor protection device of the present invention. As can be seen from the figure, the first semiconductor 36 in FIG. 2 is changed from an N-channel metal oxide semiconductor field effect transistor to an insulated gate bipolar Transistor, the second semiconductor 37 in FIG. 2 is changed from an N-type semiconductor to an N-channel metal oxide semiconductor field effect transistor, and the third semiconductor 38 in FIG. 2 is changed from an N-type semiconductor to an N-channel metal oxide semiconductor field effect transistor 2, the fourth semiconductor 39 in FIG. 2 is changed from an N-type semiconductor to an N-channel metal-oxide-semiconductor field effect transistor, and other circuit structures are the same as those in FIG. 2 and will not be repeated.

As shown in FIG. 3 , the operating principle of the semiconductor protection device of the present invention is that when the first switch 11 is turned on, the current of the first DC power supply 10 passes through the first switch 11 and the load 12 , and then passes through the second terminal 50 to the first DC power supply 10 . The collector C of the semiconductor 36 and the first end of the fourth resistor 34, the second end of the fourth resistor 34 goes to the gate G of the second semiconductor 37 and the drain D of the third semiconductor 38. At this time, the first The gate G of the semiconductor 36 has no gate G voltage, so the collector C and the emitter E of the first semiconductor 36 are open, while the drain D and the source S of the second semiconductor 37 are turned on, and the drain D of the third semiconductor 38 is connected. Open circuit with the source S, the drain D of the fourth semiconductor 39 is open with the source S, because the second DC power supply 20 does not supply power, so the load 12 is not supplied by the first DC power supply 10; when the second switch 21 is turned on, the first DC power supply 10 is not supplied. The currents of the two DC power sources 20 pass through the first terminal 40, and then pass through the third resistor 33 to charge the first capacitor 35. In the fourth half When the voltage of the gate G and the source S of the conductor 39 does not reach the drain D and the source S are turned on, the second resistor 32 supplies power to the gate G of the third semiconductor 38 at this time, so that the drain D of the third semiconductor 38 is turned on. It conducts with the source S, thus making the drain D and the source S of the second semiconductor 37 open, and at the same time the first resistor 31 supplies power to the gate G of the first semiconductor 36, so the collector C of the first semiconductor 36 is connected to the emitter The pole E is turned on, at this time the first DC power supply 10 supplies power to the load 12; when the second switch 21 is open, since it does not supply power to the gate G of the first semiconductor 36, the collector C and the emitter of the first semiconductor 36 E is open circuit, at this time, the first DC power supply 10 does not supply power to the load 12; it can be seen from the above that the insulated gate bipolar transistor used in the first semiconductor 36 can be changed to an N-type transistor for practical application requirements, because Its action principle is the same and not self-limiting.

As shown in FIG. 3, the short-circuit protection action principle of the load 12 of the semiconductor protection device of the present invention is that when the first switch 11 and the second switch 21 are turned on, the load 12 is powered by the first DC power supply 10; when both ends of the load 12 are short-circuited , according to the output characteristic curve table of the first semiconductor 36 , when the collector current of the first semiconductor 36 rises to its corresponding collector-emitter voltage (Collector Emitter Voltage) reaches higher than the gate G of the second semiconductor 37 and the source When the voltage is turned on between the electrodes S, the drain electrode D and the source electrode S of the second semiconductor 37 are turned on, so the collector C and the emitter E of the first semiconductor 36 are open circuited, and the first DC power supply 10 does not supply power to the short circuit. load 12, so that the first DC power supply 10 is protected; similarly, the overload protection function can also be achieved by properly selecting the overload collector current corresponding to the collector-emitter voltage of the first semiconductor 36. .

As shown in FIG. 4, it is the third embodiment of the semiconductor protection device of the present invention. As can be seen from the figure, the fourth semiconductor 39 in FIG. 3 is changed from an N-channel metal oxide semiconductor field effect transistor to an adjustable precision parallel Adjustable Precision Shunt Regulators 22 (Adjustable Precision Shunt Regulators, 22), the characteristics of the adjustable precision shunt regulator 22 include an anode terminal A (Anode, A), a cathode terminal K (Cathode, K) and a reference voltage terminal Vref (Reference Voltage , Vref), the anode terminal A of its adjustable precision parallel regulator 22 replaces the source S of the fourth semiconductor 39, and the cathode terminal K of its adjustable precision parallel regulator 22 replaces the drain D of the fourth semiconductor 39, which can The reference voltage terminal Vref of the precision shunt regulator 22 replaces the gate G of the fourth semiconductor 39, and other circuit structures are the same as those in FIG. 3 and will not be repeated.

As shown in FIG. 4 , the operating principle of the semiconductor protection device of the present invention is that when the first switch 11 is turned on, the current of the first DC power supply 10 passes through the first switch 11 and the load 12 , and then passes through the second terminal 50 to the first DC power supply 10 . The collector C of the semiconductor 36 and the first end of the fourth resistor 34, the second end of the fourth resistor 34 goes to the gate G of the second semiconductor 37 and the drain D of the third semiconductor 38. At this time, the first The gate G of the semiconductor 36 has no gate G voltage, so the collector C and the emitter E of the first semiconductor 36 are open, while the drain D and the source S of the second semiconductor 37 are turned on, and the drain D of the third semiconductor 38 is connected. Open circuit with the source S, the anode terminal A and the cathode terminal K of the adjustable precision parallel regulator 22 are open circuit, because the second DC power supply 20 does not supply power, so the load 12 is not supplied by the first DC power supply 10; when the second switch 21 is turned on When the current of the second DC power source 20 passes through the first terminal 40, and then charges the first capacitor 35 through the third resistor 33, the reference voltage terminal Vref and the anode terminal A of the adjustable precision parallel regulator 22 do not reach the negative When the terminal K and the anode terminal A are turned on, the second resistor 32 supplies power to the gate G of the third semiconductor 38, so that the drain D and the source S of the third semiconductor 38 are turned on, thus making the drain of the second semiconductor 37 conductive. The pole D and the source S are open-circuited, and at the same time the gate G of the first semiconductor 36 is powered by the first resistor 31, and The collector C and the emitter E of the first semiconductor 36 are turned on, and the first DC power supply 10 supplies power to the load 12; when the second switch 21 is open, since the gate G of the first semiconductor 36 is not supplied with power, the first DC power supply 10 supplies power to the load 12; The collector C and the emitter E of the semiconductor 36 are open-circuited, and the first DC power supply 10 does not supply power to the load 12 at this time; the voltage of the reference voltage terminal Vref of the adjustable precision parallel regulator 22 is about 2.5V, when the reference voltage terminal Vref When the voltage is greater than 2.5V, the anode terminal A and the cathode terminal K of the adjustable precision shunt regulator 22 are turned on, so the third semiconductor 38 can use the adjustable precision as long as the gate threshold voltage value is properly selected. The shunt regulator 22 replaces the fourth semiconductor 39, and the replacement of the fourth semiconductor 39 with the adjustable precision shunt regulator 22 is completely determined according to requirements and is not limited.

As shown in FIG. 4 , the operation principle of the short-circuit protection of the load 12 of the semiconductor protection device of the present invention is the same as that of FIG. 3 , and will not be repeated.

From the description of the above-mentioned operation principle and functional operation, it can be seen that the present invention can be implemented accordingly.

10: The first DC power supply

11: The first switch

12: Load

20: Second DC power supply

21: Second switch

30: Semiconductor protection device of the present invention

31: First resistor

32: Second resistor

33: Third resistor

34: Fourth resistor

35: First capacitor

36: First Semiconductor

37: Second Semiconductor

38: Third Semiconductor

39: Fourth Semiconductor

40: The first terminal of the present invention

50: The second terminal of the present invention

60: The third terminal of the present invention

Claims (10)

A semiconductor protection device, which has the function of protecting the DC power supply from overloading or short-circuiting of the DC power supply during the power supply process. The semiconductor protection device includes: a first semiconductor having a drain or collector, a source or emitter and a gate or base; A second semiconductor has a drain or collector, a source or emitter and a gate or base, the drain or collector is connected to the gate or base of the first semiconductor, the source or emitter electrode is connected to the source or emitter of the first semiconductor; a third semiconductor having a drain or collector, a source or emitter and a gate or base, the drain or collector is connected to the gate or base of the second semiconductor, the source or emitter connecting the source or emitter of the second semiconductor.; a fourth semiconductor having a drain or collector, a source or emitter and a gate or base, the source or emitter is connected to the third semiconductor source or emitter, the drain or collector connecting the gate or base of the third semiconductor; a first resistor with a first end and a second end, the second end is connected to the gate or base of the first semiconductor and the drain or collector of the second semiconductor; A second resistor has a first end and a second end, the first end is connected to the first end of the first resistor, the second end is connected to the gate or base of the third semiconductor and the first end Four semiconductor drains or collectors; a third resistor, having a first end and a second end, the first end is connected to the first end of the second resistor, and the second end is connected to the gate or base of the fourth semiconductor; a fourth resistor having a first end and a second end, the first a terminal connecting the drain or collector of the first semiconductor and a second terminal of the load, the second terminal connecting the gate or base of the second semiconductor and the drain or collector of the third semiconductor; and A first capacitor has a first end and a second end, the first end is connected to the gate or base of the fourth semiconductor and the second end of the third resistor, the second end is connected to the fourth The source or emitter of a semiconductor. The semiconductor protection device of claim 1, wherein the first end of the first resistor, the first end of the second resistor and the first end of the third resistor are connected together to form the first The terminal is used for connecting the positive terminal of the second DC power supply. The semiconductor protection device of claim 1, wherein the drain or collector of the first semiconductor and the first end of the fourth resistor are connected together to form a second terminal for providing load connection . The semiconductor protection device according to claim 1, wherein the source or emitter of the first semiconductor, the source or emitter of the second semiconductor, the source or emitter of the third semiconductor, the source or emitter of the first semiconductor The source or emitter of the four semiconductors and the second terminal of the first capacitor are connected together to form a third terminal for providing the negative terminal of the first DC power supply and the negative terminal of the second DC power supply. The semiconductor protection device of claim 1, wherein the first semiconductor is an N-channel metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor or an N-type transistor. The semiconductor protection device according to claim 1, wherein the second semiconductor is an N-channel metal-oxide-semiconductor field effect transistor or an N-type transistor. The semiconductor protection device according to claim 1, wherein the third semiconductor is an N-channel metal-oxide-semiconductor field effect transistor or an N-type transistor. The semiconductor protection device according to claim 1, wherein the fourth semiconductor is an N-channel metal oxide semiconductor field effect transistor or an N-type transistor. The semiconductor protection device of claim 1, wherein the time delay circuit with the function of controlling the time delay operation includes the fourth semiconductor, the third resistor and the first capacitor. The semiconductor protection device of claim 1, further comprising an adjustable precision shunt regulator for use in substitution with the fourth semiconductor.

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