TWI726365B - 半導體元件及其製造方法 - Google Patents
半導體元件及其製造方法 Download PDFInfo
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- TWI726365B TWI726365B TW108126055A TW108126055A TWI726365B TW I726365 B TWI726365 B TW I726365B TW 108126055 A TW108126055 A TW 108126055A TW 108126055 A TW108126055 A TW 108126055A TW I726365 B TWI726365 B TW I726365B
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Abstract
在製造半導體元件之方法中,鰭結構形成於底部鰭結構上方,其中鰭結構為交替堆疊第一半導體層及第二半導體層。具有側壁間隔物之犧牲閘極結構形成於鰭結構上方。去除未由犧牲閘極結構覆蓋之鰭結構之源極/汲極區域。橫向凹陷第二半導體層。介電內部間隔物形成在經凹陷第二半導體層之橫向端部。橫向凹陷第一半導體層。形成源極/汲極磊晶層以接觸經凹陷第一半導體層之橫向端部。去除第二半導體層,從而露出通道區域中之第一半導體層。圍繞第一半導體層形成閘極結構。
Description
本揭示係關於半導體元件及其製造方法。
隨著半導體工業已經發展到追求更高元件密度、更高效能及更低成本之奈米技術製程節點,在諸如多閘極場效電晶體(multi-gate field effect transistor)(包括鰭式場效電晶體(fin field effect transistor;Fin FET)及閘極全環繞場效電晶體(gate-all-around(GAA)FET)之三維設計之發展過程中遇到了來自製造及設計問題的雙重挑戰。在鰭式場效電晶體中,閘電極與通道區域之三個側表面相鄰,其中閘極介電層插入其間。因為閘極結構在三個表面上圍繞(包裹)鰭狀物,所以電晶體基本上具有控制穿過鰭或通道區域之電流的三個閘極。不幸地是,通道之第四側面,也就是通道的底部部分遠離閘電極且並不受嚴密的閘極控制。相反,在閘極全環繞場效電晶體中,通道區域之全部側表面被閘電極圍繞,這允許在通道區域中更充分消耗且由於更陡之亞閾值電流擺幅(sub-threshold current swing;SS)導致更少之短通道效應及更小之汲極誘導能障下降(drain induced barrier lowering;DIBL)。隨著電
晶體尺寸不斷縮小至10-15nm以下之技術節點,需要進一步改進閘極全環繞場效電晶體。
根據本揭露的多個實施方式,提供一種半導體元件的製造方法,包括以下步驟。形成鰭結構,其包含複數個第一半導體層及複數個第二半導體層交替堆疊於底部鰭結構上方。在鰭結構上方形成具有複數個側壁間隔物的犧牲閘極結構,側壁間隔物以垂直於半導體基板之主表面的方向形成。去除未被犧牲閘極結構覆蓋的鰭結構的源極/汲極區域。橫向凹陷第二半導體層。在經凹陷第二半導體層之橫向端部上形成複數個介電內部間隔物。橫向凹陷第一半導體層。形成源極/汲極磊晶層以接觸經凹陷第一半導體層之橫向端部。去除第二半導體層,從而露出通道區域中的第一半導體層。形成閘極結構圍繞第一半導體層。
根據本揭露的多個實施方式,提供一種半導體元件的製造方法,包括以下步驟。形成鰭結構,其中鰭結構包含複數個第一半導體層及複數個第二半導體層交替堆疊於底部鰭結構上方。在鰭結構上方形成具有複數個側壁間隔物的犧牲閘極結構,側壁間隔物以垂直於半導體基板之主表面的方向形成。去除未由犧牲閘極結構覆蓋之鰭結構的源極/汲極區域中的第二半導體層。形成介電層。在源極/汲極區域中蝕刻介電層及第一半導體層,從而在第二半導體層之橫向端部形成複數個介電內部間隔物。橫向凹陷第一半導體層。形成源極/汲極磊晶層以接觸經凹陷第一半導體層之橫
向端部。去除第二半導體層,從而露出通道區域中的第一半導體層。形成閘極結構圍繞第一半導體層。
根據本揭露的多個實施方式,提供一種半導體元件,包括垂直佈置的複數個半導體線,其每一者均具有通道區域;源極/汲極磊晶層,其連接至半導體線之複數個端部;閘極結構,具有圍繞半導體線形成之複數個側壁間隔物;以及複數個介電內部間隔物,設置在閘極結構與源極/汲極磊晶層之間,其中在半導體線中的至少一者與源極/汲極磊晶層之間的介面位於側壁間隔物中的一者之下。
10:基板
11:底部鰭結構
12:雜質離子
15:遮罩層
15A:第一遮罩層
15B:第二遮罩層
20:半導體線/第一半導體層
25:第二半導體層
27:腔體
30:鰭結構
35:鰭襯墊層
35A:第一鰭襯墊層
35B:第二鰭襯墊層
40:隔離絕緣層
41:凹陷絕緣材料層
50:犧牲閘極結構
52:犧牲閘極介電層
53:毯覆層
54:犧牲閘電極層
55:閘極側壁間隔物
56:墊氮化矽層
58:氧化矽遮罩層
60:介電材料層
62:介電內部間隔物
64:第二閘極側壁間隔物
80:源極/汲極磊晶層
85:襯墊層
90:層間介電層
100:閘極結構
102:界面層
104:閘極介電層
106:功函數調整層
108:閘電極層
A-A’、B-B’、C-C’:線
當結合附圖閱讀時,根據以下詳細描述可更好地理解本揭示之實施方式。應強調,根據工業中的標準實務,各種特徵未按比例繪製,並且僅用作說明目的。事實上,出於論述清晰之目的,各特徵之尺寸可任意地增加或縮小。
第1A圖、第1B圖、第1C圖及第1D圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之各種視圖。
第2A圖、第2B圖、第2C圖及第2D圖根據本揭示之另一實施例圖示閘極全環繞場效電晶體元件之各種視圖。
第3圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第4圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第5圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第6圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第7圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第8圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第9圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第10圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第11A圖及第11B圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第12A圖及第12B圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第13A圖及第13B圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第14A圖及第14B圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第15A圖及第15B圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第16A圖及第16B圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第17A圖及第17B圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第18A圖及第18B圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第19A圖及第19B圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第20A圖及第20B圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第21A圖及第21B圖根據本揭示之實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第22A圖及第22B圖根據本揭示之另一實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第23A圖及第23B圖根據本揭示之另一實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第24A圖及第24B圖根據本揭示之另一實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第25A圖及第25B圖根據本揭示之另一實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第26A圖及第26B圖根據本揭示之另一實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第27A圖及第27B圖根據本揭示之另一實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第28A圖及第28B圖根據本揭示之另一實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第29A圖及第29B圖根據本揭示之另一實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第30A圖及第30B圖根據本揭示之另一實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
第31A圖及第31B圖根據本揭示之另一實施例圖示閘極全環繞場效電晶體元件之連續製造製程之不同階段之一者的視圖。
應當理解,以下揭示內容提供許多不同實施例或實例,以便實施本揭示之一實施方式之不同特徵。下文描述組件及排列之特定實施例或實例以簡化本揭示之一實施方式。當然,此等實例僅為實例且不意欲為限制性。例如,元件之尺寸不限於本揭示之一實施方式之範圍或數值,但可取決於元件之處理條件及/或要求性質。此外,在隨後描述中在第二特徵上方或在第二特徵上第一特徵之形成可包括第一及第二特徵形成為直接接觸之實施例,以及亦可包括額外特徵可形成在第一及第二特徵之間,使得第一及第二特徵可不直接接觸之實施例。為簡單及清晰起見,不同特徵可能任意地以不同的比例繪製出。
另外,空間相對用語,諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者,在此為便於描述可用於描述諸圖中所圖示一個元件或特徵與另一(些)元件或(多個)特徵之關係。除圖形中描繪之方向外,空間相對用語意圖是包含元件在使用或操作中之不同的方向。設備可為不同朝向(旋轉90度或在其他的方向)及在此使用之空間相對的描述詞可因此同樣地解釋。另外,術語「由...製成」可意謂「包含」或者「由...組成」。在本揭示之一實施方式中,「A、B及C之一者」意謂著「A、B及/或C」(A,
B,C,A及B,A及C,B及C,或者A、B及C),並且並不意謂來自A之一個元件、來自B之一個元件及來自C之一個元件,除非另外描述。
在以下實施例中,除非另外描述,否則一個實施例之材料、配置、尺寸、操作及/或製程可用於另一實施例中,並且可忽略其細節說明。
在近十年已研究高遷移率通道材料及元件架構以延長摩耳定律之壽命。具有高Ge濃度之純Ge及SiGe,由於其具有更高之本質電洞(intrinsic hole)及電子遷移率之材料性質,為此種材料之有希望的候選者。對於Lg<12nm之良好回火(well-tempered)的元件縮放,將採用奈米線或奈米片結構以提供較好的短通道控制。因此,Ge或SiGe奈米線元件被認為是有希望且有潛力之候選者以用於進一步縮小邏輯元件應用。為了獲得卓越的Ge奈米線元件效能,存在待解決之若干問題,例如:(1)閘極側壁間隔物之下之高介面狀態密度(Dit)及(2)由於Ge(0.66eV)相對於矽(1.2eV)之狹窄能隙而造成之高元件漏電流。
在本揭示之一實施方式中,提供用於解決上述問題之元件結構及其製造方法。
第1A圖至第1D圖根據本揭示之一實施例圖示閘極全環繞場效電晶體元件之各種視圖。第1A圖圖示沿X方向之橫截面視圖,鰭結構及通道(奈米線)在X方向延伸。第1B圖、第1C圖及第1D圖圖示沿Y方向之橫截面視圖,閘電極沿Y方向延伸。第1B圖為對應於第1A圖之線A-A'切割
通道中心的橫截面視圖。第1C圖為對應於第1A圖之線B-B'切割閘極側壁間隔物中心的橫截面視圖。第1D圖為對應於第1A圖之線C-C'切割源極/汲極磊晶層的橫截面視圖。在一些實施例中,閘極全環繞場效電晶體為N通道場效電晶體。
如第1A圖至第1D圖圖示,底部鰭結構11設置於基板10上方。複數個半導體線20,作為通道,垂直佈置於底部鰭結構11上方。儘管在第1A圖及第1B圖中示出5條半導體線20,但垂直佈置的半導體線20之數目並不限於5條,且其可小至1且最高達15至20。在一些實施例中,半導體線20由Si1-xGex組成,其中x等於或大於約0.5,或半導體線20由Ge組成(x=1.0)。在一些實施例中,一或多個鰭襯墊層35設置於底部鰭結構11之側面上。在某些實施例中,鰭襯墊層35包括設置成與底部鰭結構11接觸之第一鰭襯墊層35A及第二鰭襯墊層35B,第二鰭襯墊層35B由不同於第一鰭襯墊層35A之材料組成且設置於第一鰭襯墊層35A上方。在一些實施例中,底部鰭結構11之至少最上方部分包括由SiGe組成之一層。
閘極結構100包括圍繞半導體線20包裹之閘極介電層104及設置於閘極介電層104上方之閘電極層108。在一些實施例中,界面層102設置於閘極介電層104與半導體線20之間。在一些實施例中,一或多個功函數調整層106設置於閘電極層108與閘極介電層104之間。在一些實施例中,閘電極層108並不設置於半導體線20之間且功函數調整層106填充相鄰半導體線20之間的縫隙。在其他實施例中,
閘電極層108環繞半導體線20,以及界面層102、閘極介電層104及功函數調整層106。此外,如第1A圖及第1C圖所示,閘極側壁間隔物55設置在閘極結構100之相對側面上。
此外,源極/汲極磊晶層80設置以連接至半導體線20之水平端部。如第1A圖圖示,半導體線20之水平端部具有凹形的V形狀或U形狀。襯墊層85,其可為接觸蝕刻停止層(contact etch stop layer;CESL),設置於源極/汲極磊晶層80上方,以及層間介電(interlayer dielectric;ILD)層90設置於襯墊層85上方。在一些實施例中,源極/汲極磊晶層80由一半導體材料組成,此半導體材料具有比半導體線20之半導體材料更高的能帶隙。在某些實施例中,源極/汲極磊晶層80由摻雜P之Si組成(SiP)。
在第1A圖至第1D圖中圖示之閘極全環繞場效電晶體進一步包括設置於閘極結構100與源極/汲極磊晶層80之間的介電內部間隔物62,閘極結構100設置於相鄰半導體線20之間。此外,由與介電內部間隔物62相同之材料組成的介電層60設置於源極/汲極磊晶層80與底部鰭結構11之間。
在一些實施例中,如第1A圖圖示,在多個半導體線20之至少一者與源極/汲極磊晶層80之間的介面位於多個閘極側壁間隔物55之一者之下。在某些實施例中,多個閘極側壁間隔物55之一者下面的位置對應於在X方向上切割閘極側壁間隔物55之中心的橫截面(Y-Z平面)。在一些實施例中,介面比閘極側壁間隔物55之中心線(第1A圖
之線B-B')更靠近閘極結構100。在一些實施例中,整個介電內部間隔物62位於閘極側壁間隔物55之下。
在一些實施例中,閘極側壁間隔物55並不與半導體線20接觸。
第2A圖至第2D圖根據本揭示之另一實施例圖示閘極全環繞場效電晶體元件之各種視圖。第2A圖圖示沿X方向之橫截面視圖,鰭結構及通道(奈米線)沿X方向延伸。第2B圖、第2C圖及第2D圖圖示沿Y方向之橫截面視圖,閘電極沿Y方向延伸。第2B圖為對應於切割通道中心之第2A圖之線A-A'的橫截面視圖。第2C圖為對應於切割第一閘極側壁間隔物中心之第2A圖之線B-B'的橫截面視圖。第2D圖為對應於切割源極/汲極磊晶層之第2A圖之線C-C'的橫截面視圖。在一些實施例中,閘極全環繞場效電晶體為N通道場效電晶體。
如第2A圖至第2D圖圖示,底部鰭結構11設置於基板10上方。複數個半導體線20,作為通道,垂直佈置於底部鰭結構11上方。儘管在第2A圖及第2B圖中示出五條半導體線20,但垂直佈置半導體線20之數目並不限於五,且其可小至1且最高達15至20。在一些實施例中,半導體線20由Si1-xGex組成,其中x等於或多於約0.5,或半導體線20由Ge組成(x=1.0)。在一些實施例中,一或多個鰭襯墊層35設置於底部鰭結構11之側面上。在某些實施例中,鰭襯墊層35包括設置成與底部鰭結構11接觸之第一鰭襯墊層35A及第二鰭襯墊層35B,第二鰭襯墊層35B由不同於第一
鰭襯墊層35A之材料組成且設置於第一鰭襯墊層35A上方。在一些實施例中,底部鰭結構11之至少最上方部分包括由SiGe組成之一層。
閘極結構100包括圍繞半導體線20包裹之閘極介電層104及設置於閘極介電層104上方之閘電極層108。在一些實施例中,界面層102設置於閘極介電層104與半導體線20之間。在一些實施例中,一或多個功函數調整層106設置於閘電極層108與閘極介電層104之間。在一些實施例中,閘電極層108並不設置於半導體奈米線20之間且功函數調整層106填充相鄰半導體線20之間的縫隙。在其他實施例中,閘電極層108環繞半導體線20,以及界面層102、閘極介電層104及功函數調整層106。此外,如第2A圖及第2C圖圖示,第一閘極側壁間隔物55設置在閘極結構100之相對側面上。
此外,源極/汲極磊晶層80設置以連接至半導體線20之水平端部。如第2A圖圖示,半導體線20之水平端部具有凹形的V形狀或U形狀。襯墊層85,其可為接觸蝕刻停止層(CESL),設置於源極/汲極磊晶層80上方,及層間介電(ILD)層90設置於襯墊層85上方。在一些實施例中,源極/汲極磊晶層80由一半導體材料組成,此半導體材料具有比半導體線20之半導體材料更高的能帶隙。在某些實施例中,源極/汲極磊晶層80由摻雜P之Si組成(SiP)。
在第2A圖至第2D圖中圖示之閘極全環繞場效電晶體進一步包括設置於閘極結構100與源極/汲極磊晶層
80之間的介電內部間隔物62,閘極結構100設置於相鄰半導體線20之間。此外,由與介電內部間隔物62相同之材料組成的介電層60設置於源極/汲極磊晶層80與底部鰭結構11之間。另外,由與介電內部間隔物62相同之材料組成之第二側壁間隔物64設置於第一閘極側壁間隔物55與第2A圖圖示之襯墊層85之間。
在一些實施例中,如第2A圖圖示,在多個半導體線20之至少一者與源極/汲極磊晶層80之間的介面位於多個第一閘極側壁間隔物55之一者之下。在某些實施例中,多個第一閘極側壁間隔物55之一者下面的位置對應於在X方向上切割第一閘極側壁間隔物55之中心的橫截面(Y-Z平面)。在一些實施例中,介面比第一閘極側壁間隔物55之中心線(第2A圖之線B-B')更靠近閘極結構100。在一些實施例中,整個介電內部間隔物62位於第一閘極側壁間隔物55下面。在其他的實施例中,在介電內部間隔物62與源極/汲極磊晶層80之間的介面位於第一側壁間隔物55之一者下面的區域外。
在一些實施例中,第一閘極側壁間隔物55並不與半導體線20接觸。在某些實施例中,第二閘極側壁間隔物64並不與半導體線20接觸。
第3圖至第21B圖根據本揭示之一實施例圖示用於製造第1A圖至第1D圖中圖示之閘極全環繞場效電晶體元件的連續製程。應理解,可以在由第3圖至第21B圖圖示之製程之前、期間及之後提供附加操作,並且可以替換或
除去如下所述之一些操作以獲得此方法的另外實施例。操作/製程之順序可為互換的。
如第3圖圖示,將雜質離子(摻雜劑)12植入矽基板10中以形成阱區域。執行離子植入以防止擊穿效應(punch-through effect)。在一些實施例中,基板10在至少其表面部分上包括單晶半導體層。基板10可包含單晶半導體材料,諸如但不限於Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP。在一個實施例中、基板10由晶體矽組成。
基板10在其表面區域中可包括一或多個緩衝層(未圖示)。緩衝層可用於將晶格常數從基板之晶格常數逐漸變化至源極/汲極區域之晶格常數。緩衝層可由磊晶生長之單晶半導體材料形成,此材料諸如但不限於Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP及InP。在特定實施例中,基板10包括磊晶生長於矽基板10上之矽鍺(SiGe)緩衝層。矽鍺緩衝層之鍺濃度可從最底部緩衝層之30原子%鍺增加至最頂部緩衝層之70原子%鍺。基板10可包括已適當摻雜有雜質(例如,P型或N型導電性)之各種區域。摻雜劑12例如為用於N型鰭式場效電晶體之硼(BF2)及用於P型鰭式場效電晶體之磷。
如第4圖圖示,堆疊半導體層形成於基板10上方。堆疊半導體層包括多個第一半導體層20及多個第二半導體層25。此外,遮罩層15形成於堆疊半導體層上方。
多個第一半導體層20及多個第二半導體層25由具有不同晶格常數之材料組成,且可包括一或多層Si、Ge、SiGe、GaAs、InSbGaPGaSb、InAlAs、InGaAs、GaSbP、GaAsSb或InP。
在一些實施例中,多個第一半導體層20及多個第二半導體層25由Si、Si化合物、SiGe、Ge或Ge化合物組成。在一個實施例中,多個第一半導體層20為Si1-xGex,其中x大於約0.5,或者為Ge(x=1.0),且第二半導體層25為Si或Si1-yGey,其中y等於或小於約0.6,且x>y。在本揭示之一實施方式中,「M」化合物或「M基化合物」意謂化合物之大多數為M。
在第4圖中,設置五層第一半導體層20及五層第二半導體層25。然而,層數並不限於五,且第一半導體層及第二半導體層的層數可分別小至1,及在一些實施例中,形成各2至20層第一半導體層20及第二半導體層25。藉由調整堆疊層數,可調整閘極全環繞場效電晶體元件之驅動電流。
第一半導體層20及第二半導體層25磊晶形成於基板10上方。第一半導體層20之厚度可等於或大於第二半導體層25之厚度,並且在一些實施例中,第一半導體層20之厚度在約5nm至約50nm之範圍中,及在其他實施例中,第一半導體層20之厚度在約10nm至約30nm之範圍中。第二半導體層25之厚度範圍在一些實施例中為約5nm至約30
nm,以及在其他實施例中為約10nm至約20nm。每個第一半導體層20之厚度可為相同的,或可不同。
在一些實施例中,底部第一半導體層20(最接近基板10之層)比其餘的第一半導體層20厚。底部第一半導體層20之厚度範圍在一些實施例中為約10nm至約50nm,或在其他實施例中為約20nm至約40nm。
在一些實施例中,遮罩層15包括第一遮罩層15A及第二遮罩層15B。第一遮罩層15A為由氧化矽組成之墊氧化層,其可藉由熱氧化而形成。第二遮罩層15B由氮化矽(SiN)組成,其藉由化學氣相沉積(chemical vapor deposition;CVD)形成,包括低壓化學氣相沉積(LPCVD)及電漿增強化學氣相沉積(PECVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適當製程而形成。藉由使用包括光微影及蝕刻之圖案化操作而將遮罩層15圖案化成遮罩圖案。
接下來,如第5圖圖示,藉由使用圖案化遮罩層而圖案化第一半導體層20及第二半導體層25之堆疊層,從而堆疊層形成為X方向上延伸之鰭結構30。
鰭片結構30可藉由任何適當方法圖案化。例如,可使用包括雙圖案化(double-patterning)或多圖案化(multi-patterning)製程之一或多個微影製程圖案化鰭結構。大體上,雙圖案化或多圖案化製程結合微影及自對準製程,從而允許產生之圖案的間距例如小於使用單個、直接的微影製程獲得的間距。例如,在一個實施例中,犧牲層形成
於基板上方並且使用微影製程來圖案化。使用自對準製程沿圖案化犧牲層形成間隔物。隨後去除犧牲層,則剩餘間隔物或心軸可用以圖案化鰭結構。
在第5圖中,在Y方向上佈置兩個鰭結構30。但鰭結構30數目並不受限,且可小至1個及大至三或更多個。在一些實施例中,一或多個虛設鰭結構形成於鰭結構30之兩側上以改進圖案化操作中之圖案保真度(pattern fidelity)。如第5圖圖示,鰭結構30具有由堆疊的第一半導體層20、第二半導體層25組成之上部部分及阱部分11,其對應於底部鰭結構。
鰭結構30之上部部分沿Y方向之寬度W1的範圍在一些實施例中為約10nm至約40nm,且在其他實施例中為約20nm至約30nm。鰭結構30沿Z方向之高度H1的範圍為約100nm至約200nm。
在形成鰭結構30之後,包括一或多層絕緣材料之絕緣材料層41形成於基板10上方以使鰭結構30完全嵌入絕緣層41中。絕緣層41之絕緣材料可包括氧化矽、氮化矽、氮氧化矽(SiON)、SiOCN、SiCN、氟摻雜矽玻璃(FSG)、或低介電常數介電材料,由低壓化學氣相沉積(LPCVD)、電漿化學氣相沉積或可流動化學氣相沉積形成。可在絕緣層41形成之後執行退火操作。隨後,執行平坦化操作,諸如化學機械拋光(chemical mechanical polishing;CMP)方法及/或回蝕刻方法,使得最上層第二半導體層25之頂表面從第6圖圖示之絕緣材料層41暴露出。
在一些實施例中,在形成絕緣材料層41之前,一或多個鰭襯墊層35形成於第5圖之結構上方,如第6圖圖示。襯墊層35由SiN或氮化矽基材料(例如,SiON、SiCN或SiOCN)組成。在一些實施例中,鰭襯墊層35包括形成於基板10上方之第一鰭襯墊層及底部鰭結構11之側面,及形成於第一鰭襯墊層35A上之第二鰭襯墊層35B。在一些實施例中,襯墊層每一者均具有約1nm與約20nm之間的厚度。在一些實施例中,第一鰭襯墊層35A包括氧化矽且具有約0.5nm與約5nm之間的厚度,以及第二鰭襯墊層35B包括氮化矽且具有約0.5nm與約5nm之間的厚度。鰭襯墊層35可經由諸如物理氣相沉積(PVD)、化學氣相沉積(CVD)或原子層沉積(ALD)之一或多個製程而沉積,但可利用任何可接受之製程。
隨後,如第7圖圖示,將絕緣材料層41凹陷以形成隔離絕緣層40,以便暴露鰭結構30之上部部分。在此操作中,鰭結構30藉由隔離絕緣層40彼此電分離,隔離絕緣層40也稱為淺溝槽隔離(shallow trench isolation;STI)。在第7圖圖示之實施例中,凹陷絕緣材料層41直到暴露最底部的第一半導體層20。在其他實施例中,也部分暴露阱層11之上部部分。第一半導體層20做為隨後部分去除之犧牲層,且第二半導體層25後續形成為閘極全環繞場效電晶體之通道層。
在形成隔離絕緣層40之後,形成犧牲閘極介電層52,如第8圖圖示。犧牲閘極介電層52包括一或多層絕緣
材料,諸如氧化矽基材料。在一個實施例中,使用由化學氣相沉積形成之氧化矽。在一些實施例中,犧牲閘極介電層52之厚度範圍為約1nm至約5nm。
第9圖圖示犧牲閘極結構50形成於暴露的鰭結構30上方之後的結構。犧牲閘極結構50包括犧牲閘電極54及犧牲閘極介電層52。犧牲閘極結構50形成於將成為通道區域之鰭結構30的部分之上。犧牲閘極結構50定義閘極全環繞場效電晶體之通道區域。
犧牲閘極結構50藉由首先將犧牲閘極介電層52毯覆式沉積於鰭結構30上方而形成,如第9圖圖示。隨後將犧牲閘電極層54毯覆式沉積於犧牲閘極介電層52上及鰭結構30上方,使得鰭結構30完全嵌入犧牲閘電極層54中。犧牲閘電極層54包括矽,諸如多晶矽或非晶矽。在一些實施例中,犧牲閘電極層54之厚度範圍為約100nm至約200nm。在一些實施例中,對犧牲閘電極層54進行平坦化操作。犧牲閘極介電層52及犧牲閘電極層54使用包括低壓化學氣相沉積及電漿增強化學氣相沉積之化學氣相沉積、物理氣相沉積、原子層沉積或其他適當的製程而沉積。隨後,遮罩層形成於犧牲閘電極層54上方。遮罩層包括墊氮化矽層56及氧化矽遮罩層58。
接下來,對遮罩層執行圖案化操作及將犧牲閘電極層54圖案化成犧牲閘極結構50,如第9圖圖示。犧牲閘極結構50包括犧牲閘極介電層52、犧牲閘電極層54(例如,多晶矽)、墊氮化矽層56及氧化矽遮罩層58。藉由圖案化
犧牲閘極結構50,第一半導體層20及第二半導體層25之堆疊層部分暴露於犧牲閘極結構50之相對側上,從而定義源極/汲極(source/drain;S/D)區域,如第9圖圖示。在本揭示之一實施方式中,源極及汲極可交互使用且其結構實質上相同。在第9圖中,形成一個犧牲閘極結構50,但犧牲閘極結構50之數目不限於一個。在一些實施例中,兩個或兩個以上犧牲閘極結構50以X方向佈置。在某些實施例中,一或多個虛設犧牲閘極結構形成於犧牲閘極結構50之兩側上以改進圖案保真度。
在形成犧牲閘極結構50之後,藉由使用化學氣相沉積或其他適當方法共形地形成用於閘極側壁間隔物55之絕緣材料的毯覆層53,如第10圖圖示。毯覆層53以共形方式沉積,以使其在犧牲閘極結構50之垂直表面(例如側壁)、水平表面及頂部上形成為具有實質上相等的厚度。在一些實施例中,沉積毯覆層53沉積至約2nm至約10nm之厚度範圍。在一些實施例中,毯覆層53之絕緣材料為氮化矽基材料,諸如SiN、SiON、SiOCN或SiCN及其組合。在某些實施例中,絕緣材料為SiOC、SiCON及SiCN之一者。
第11A圖及第11B圖圖示與第10圖相同之結構。第11A圖圖示透視圖及第11B圖圖示對應於切割鰭結構30之第11A圖之線X1-X1的橫截面視圖。在第11B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。
此外,如第12A圖及第12B圖圖示,閘極側壁間隔物55藉由非等向性(anisotropic)蝕刻而形成於犧牲閘
極結構50之相對側壁上,及隨後將鰭結構30之源極/汲極區域凹陷成等於或低於隔離絕緣層40之頂表面。第12A圖圖示透視圖及第12B圖圖示對應於第11A圖之線X1-X1的橫截面視圖。在第12B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。
在形成毯覆層53之後,使用例如反應性離子蝕刻(reactive ion etching;RIE)對毯覆層53執行非等向性蝕刻。在非等向性蝕刻製程期間,從水平面去除大部分絕緣材料,從而在諸如犧牲閘極結構50之側壁及所暴露鰭結構30之側壁的垂直表面上留下介電間隔物層。遮罩層58可從側壁間隔物暴露。在一些實施例中,隨後可執行等向性(isotropic)蝕刻製程以從所暴露鰭結構30之源極/汲極區域之上部部分去除絕緣材料。
隨後,藉由使用乾式蝕刻及/或濕式蝕刻,將鰭結構30之源極/汲極區域向下凹陷成等於或低於隔離絕緣層40之頂表面。如第12A圖及第12B圖圖示,亦去除形成於所暴露鰭結構30之源極/汲極區域上的閘極側壁間隔物55。在此階段,犧牲閘極結構50下面之第一半導體層20及第二半導體層25之堆疊層的端部部分具有實質上平坦的面,其與閘極側壁間隔物55齊平,如第12B圖圖示。在一些實施例中,略微水平蝕刻第一半導體層20及第二半導體層25之堆疊層的端部部分。
隨後,如第13A圖及第13B圖圖示,水平凹陷(蝕刻)第二半導體層25,以使第二半導體層25之邊緣實
質上位於閘極側壁間隔物55下方,且形成腔體27。第13A圖圖示透視圖及第13B圖圖示對應於切割鰭結構30之第11A圖之線X1-X1的橫截面視圖。在第13B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。如第13B圖圖示,第二半導體層25之端部部分(邊緣)具有凹形形狀,諸如V形狀或U形狀。將第二半導體層25從包括一個閘極側壁間隔物55之平面凹陷之深度D1的範圍為約5nm至約10nm。第二半導體層25之蝕刻步驟包括濕式蝕刻及/或乾式蝕刻。諸如氫氧化四甲銨(TMAH)溶液之濕蝕刻劑可用於選擇性地蝕刻第二半導體層25。
隨後,如第14A圖及第14B圖圖示,介電材料層60形成於第13A圖及第13B圖之結構上方。第14A圖圖示透視圖及第14B圖圖示對應於切割鰭結構30之第11A圖之線X1-X1的橫截面視圖。在第14B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。在一些實施例中,介電材料層60包括氮化矽基材料,諸如SiN、SiON、SiOCN或SiCN及其組合,且不同於閘極側壁間隔物55之材料。在某些實施例中,介電材料為氮化矽。介電材料層60完全填充第14B圖圖示之腔體27。介電材料層60可使用包括低壓化學氣相沉積及電漿增強化學氣相沉積之化學氣相沉積、物理氣相沉積、原子層沉積或其他適當的製程而形成。
接下來,如第15A圖及第15B圖圖示,執行一或多個蝕刻操作以形成介電內部間隔物62。第15A圖圖示透視圖及第15B圖圖示對應於切割鰭結構30之第11A圖之線
X1-X1的橫截面視圖。在第15B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。蝕刻操作包括一或多個濕式蝕刻及/或乾式蝕刻。在某些實施例中,蝕刻在一些實施例中為等向性蝕刻。在一些實施例中,介電內部間隔物62之沿Y方向的最大厚度範圍為約0.5nm至約5nm。如第15A圖及第15B圖圖示,介電材料層60之一部分保留在底部鰭結構11上方,而去除形成於閘極側壁間隔物55及隔離絕緣層40上之介電材料層60。
隨後,如第16A圖及第16B圖圖示,水平凹陷(蝕刻)第一半導體層20,以使第一半導體層20之邊緣實質上位於閘極側壁間隔物55下方,且形成腔體22。第16A圖圖示透視圖及第16B圖圖示對應於第11A圖之線X1-X1的橫截面視圖。在第16B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。如第16B圖圖示,第一半導體層20之端部部分(邊緣)具有凹形形狀,諸如V形狀或U形狀。將第一半導體層20從包括一個閘極側壁間隔物55之表面凹陷之深度D2的範圍為約7nm至約15nm。第一半導體層20之蝕刻步驟包括濕式蝕刻及/或乾式蝕刻。諸如氫氧化銨(NH4OH)、四甲銨溶液之濕蝕刻劑可用於選擇性地蝕刻第一半導體層20。在一些實施例中,深度D2大於深度D1。如第16A圖圖示,第一半導體層20藉由此蝕刻步驟與閘極側壁間隔物55及介電內部間隔物62分離。
在形成腔體22之後,形成源極/汲極(S/D)磊晶層80,如第17A圖及第17B圖圖示。第17A圖圖示透視圖及
第17B圖圖示對應於第11A圖之線X1-X1的橫截面視圖。在第17B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。源極/汲極磊晶層80包括用於N型通道場效電晶體之一或多層Si、SiP、SiC及SiCP。藉由使用化學氣相沉積、原子層沉積或分子束磊晶(molecular beam epitaxy;MBE)之磊晶生長方法,形成源極/汲極磊晶層80。如第17B圖圖示,在多個第一半導體層20之至少一者與源極/汲極磊晶層80之間的介面位於閘極側壁間隔物55之一者之下。
隨後,形成襯墊層85及隨後形成層間介電(ILD)層90,如第18A圖及第18B圖圖示。第18A圖圖示透視圖及第18B圖圖示對應於第11A圖之線X1-X1的橫截面視圖。
襯墊層85由氮化矽基材料,諸如氮化矽組成,其在後續蝕刻操作中作為接觸蝕刻停止層(CESL)。層間介電層90之材料包括諸如氧化矽、SiCOH及SiOC之化合物,此化合物包括Si、O、C及/或H。諸如聚合物之有機材料可用於層間介電層90。在形成層間介電層90之後,執行諸如化學機械拋光之平坦化操作,以便暴露犧牲閘電極層54,如第18A圖及第18B圖圖示。
接下來,如第19A圖及第19B圖圖示,去除犧牲閘電極層54及犧牲閘極介電層52,從而暴露鰭結構30之通道區域。第19A圖圖示透視圖及第19B圖圖示對應於第11A圖之線X1-X1的橫截面視圖。層間介電層90在去除犧牲閘極結構50期間保護源極/汲極磊晶層80。使用電漿乾式
蝕刻及/或濕式蝕刻可去除犧牲閘極結構50。當犧牲閘電極層54為多晶矽及層間介電層90為氧化矽時,可使用諸如TMAH溶液之濕蝕刻劑選擇性地去除犧牲閘電極層54。此後使用電漿乾式蝕刻及/或濕式蝕刻去除犧牲閘極介電層52。
在去除犧牲閘極結構50之後,去除鰭結構30之通道區域中的第二半導體層25,從而形成第一半導體層20之線,如第20A圖及第20B圖圖示。第20A圖圖示透視圖及第20B圖圖示對應於第11A圖之線X1-X1的橫截面視圖。
可使用可選擇性地蝕刻第二半導體層25之蝕刻劑去除或蝕刻第二半導體層25。當第一半導體層20為Si且第二半導體層25為Ge或SiGe時,可使用濕蝕刻劑選擇性地去除第一半導體層20,濕蝕刻劑諸如但不限於氫氧化四甲銨(TMAH)、乙二胺鄰苯二酚(EDP)或氫氧化鉀(KOH)溶液。
在形成第一半導體層20之線後,形成閘極結構100,如第21A圖及第21B圖圖示。第21A圖圖示透視圖及第21B圖圖示對應於第11A圖之線X1-X1的橫截面視圖。閘極介電層104圍繞每個通道層(第一半導體層20之線)形成,且閘電極層108形成於閘極介電層104上方。
在某些實施例中,閘極介電層104包括一或多層介電材料,諸如氧化矽、氮化矽或高介電常數介電材料、其他適合介電材料、及/或其組合。高介電常數介電材料之實例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、
HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他適合的高介電常數介電材料、及/或其組合。在一些實施例中,界面層102形成於通道層與閘極介電層104之間。閘極介電層104可藉由化學氣相沉積、原子層沉積或任何適合方法形成。在一個實施例中,閘極介電層104使用諸如原子層沉積之高度共形沉積製程而形成,以確保圍繞每個通道層形成具有均等厚度之閘極介電層104。在一個實施例中閘極介電層102之厚度範圍為約1nm至約6nm。
在一些實施例中,閘電極層108形成於閘極介電層104上方以圍繞每個通道層。閘電極108包括一或多層導電材料,諸如多晶矽、鋁、銅鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他適合材料、及/或其組合。閘電極層108可藉由化學氣相沉積、原子層沉積、電鍍或其他適當方法而形成。閘電極層108亦沉積於層間介電層90之頂表面上方。隨後藉由例如化學機械拋光將形成於層間介電層90上方之閘極介電層104及閘電極層108平坦化,直到露出層間介電層90。
在某些實施例中,一或多個功函數調整層106插入閘電極層108與閘極介電層104之間。功函數調整層106由導電材料組成,導電材料諸如單層TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC,或者兩種或更多種此等材料之多層。對於N型通
道場效電晶體,TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi之一或多種用作功函數調整層。功函數調整層106可藉由原子層沉積、物理氣相沉積、化學氣相沉積、電子束蒸發、或其他適當製程形成。此外,功函數調整層106可分別形成用於N型通道場效電晶體及P型通道場效電晶體,此N型通道場效電晶體及P型通道場效電晶體可使用不同金屬層。
應理解,閘極全環繞場效電晶體進行進一步CMOS製程以形成各種特徵,諸如觸點/通孔、互連金屬層、介電層、鈍化層等等。
第22A圖至第31B圖根據本揭示之另一實施例圖示用於製造第2A圖至第2D圖中圖示之閘極全環繞場效電晶體元件的連續製程。應理解,可以在由第22A圖至第31B圖圖示之製程之前、期間及之後提供附加操作,並且可以替換或除去如下所述之一些操作以獲得此方法的另外實施例。操作/製程之順序可為互換的。
第22A圖圖示透視圖及第22B圖圖示對應於第22A圖之線X1-X1的橫截面視圖。在第22B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。
在形成第11A圖及第11B圖圖示之結構之後,使用例如反應性離子蝕刻(RIE)對毯覆層53執行非等向性蝕刻。在非等向性蝕刻製程期間,從水平表面去除大部分絕緣材料,從而在垂直表面上留下介電間隔物層,例如犧牲閘極結構50的閘極側壁間隔物55。此外,亦去除形成於暴露
鰭結構30之源極/汲極區域之上部部分上方的絕緣材料53(毯覆層53),如第22A圖及第22B圖中圖示。因而,第一半導體層20及第二半導體層25之堆疊結構暴露在源極/汲極區域處。
隨後,如第23A圖及第23B圖圖示,水平凹陷(蝕刻)第二半導體層25,以使第二半導體層25之邊緣實質上位於閘極側壁間隔物55下方,且形成腔體27。第23A圖圖示透視圖及第23B圖圖示對應於切割鰭結構30之第22A圖之線X1-X1的橫截面視圖。在第23B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。如第23B圖圖示,在一些實施例中,第二半導體層25之端部部分(邊緣)具有凹形形狀,諸如V形狀或U形狀。第二半導體層25從包括一個閘極側壁間隔物55之平面凹陷之深度D3的範圍為約5nm至約10nm。第二半導體層25之蝕刻步驟包括濕式蝕刻及/或乾式蝕刻。諸如氫氧化四甲銨(TMAH)溶液之濕蝕刻劑可用於選擇性地蝕刻第二半導體層25,而不蝕刻第一半導體層20。
接下來,如第24A圖及第24B圖圖示,介電材料層60形成於第23A圖及第23B圖之結構上方。第24A圖圖示透視圖及第24B圖圖示對應於切割鰭結構30之第22A圖之線X1-X1的橫截面視圖。在第24B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。在一些實施例中,介電材料層60包括氮化矽基材料,諸如SiN、SiON、SiOCN或SiCN及其組合,且不同於閘極側壁間隔物55之材料。在某些實施例
中,介電材料為氮化矽。介電材料層60完全填充腔體27及相鄰第一半導體層20之間的間隙,如第24B圖圖示。介電材料層60可使用包括低壓化學氣相沉積及電漿增強化學氣相沉積之化學氣相沉積、物理氣相沉積、原子層沉積或其他適合製程形成。
接下來,如第25A圖及第25B圖圖示,執行一或多個蝕刻操作以形成介電內部間隔物62。第25A圖圖示透視圖及第25B圖圖示對應於第22A圖之線X1-X1的橫截面視圖。在第25B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。蝕刻操作包括一或多個濕式蝕刻操作及/或乾式蝕刻操作。在某些實施例中,蝕刻在一些實施例中為等向性蝕刻。在一些實施例中,介電內部間隔物62沿Y方向之最大厚度的範圍為約0.5nm至約5nm。如第25A圖及第25B圖圖示,介電材料層60之一部分保留在底部鰭結構11上方,且介電材料60之一部分保留在閘極側壁間隔物55上作為第二閘極側壁間隔物64。在一些實施例中,第二閘極側壁間隔物64之厚度範圍為約2nm至約15nm。去除形成於隔離絕緣層40上之介電材料層60。
隨後,如第26A圖及第26B圖圖示,水平凹陷(蝕刻)第一半導體層20,以使第一半導體層20之邊緣實質上位於閘極側壁間隔物55下方,且形成腔體22。第26A圖圖示透視圖及第26B圖圖示對應於第22A圖之線X1-X1的橫截面視圖。在第26B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。如第26B圖圖示,在一些實施例中,第一半導
體層20之端部部分(邊緣)具有凹形形狀,諸如V形狀或U形狀。第一半導體層20從包括一個閘極側壁間隔物55之表面之平面凹陷之深度D4的範圍為約7nm至約15nm。第一半導體層20之蝕刻步驟包括濕式蝕刻及/或乾式蝕刻。諸如氫氧化銨(NH4OH)、四甲銨溶液之濕蝕刻劑可用於選擇性地蝕刻第一半導體層20,而不蝕刻第二半導體層25。在一些實施例中,深度D4大於深度D3。如第26A圖圖示,第一半導體層20藉由此蝕刻步驟與第一閘極側壁間隔物55及第二閘極側壁間隔物64分離。
在形成腔體22之後,形成源極/汲極(S/D)磊晶層80,如第27A圖及第27B圖圖示。第27A圖圖示透視圖及第27B圖圖示對應於第22A圖之線X1-X1的橫截面視圖。在第27B圖中,未圖示墊氮化矽層56及氧化矽遮罩層58。源極/汲極磊晶層80包括用於N型通道場效電晶體之一或多層Si、SiP、SiC及SiCP。源極/汲極磊晶層80藉由使用化學氣相沉積、原子層沉積或分子束磊晶(MBE)之磊晶生長方法而形成。如第27B圖圖示,第一半導體層20之至少一者與源極/汲極磊晶層80之間的介面位於閘極側壁間隔物55之一者之下。
隨後,形成襯墊層85及隨後形成層間介電(ILD)層90,如第28A圖及第28B圖圖示。第28A圖圖示透視圖及第28B圖圖示對應於第22A圖之線X1-X1的橫截面視圖。
襯墊層85由諸如氮化矽之氮化矽基材料組成,並且在後續蝕刻操作中作為接觸蝕刻停止層(CESL)。層間介電層90之材料包括諸如氧化矽、SiCOH及SiOC之化合物,此化合物包括Si、O、C及/或H。諸如聚合物之有機材料可用於層間介電層90。在形成層間介電層90之後,執行諸如化學機械拋光之平坦化操作,以便暴露犧牲閘電極層54,如第28A圖及第28B圖圖示。
接下來,如第29A圖及第29B圖圖示,去除犧牲閘電極層54及犧牲閘極介電層52,從而暴露鰭結構30之通道區域。第29A圖圖示透視圖及第29B圖圖示對應於第22A圖之線X1-X1的橫截面視圖。層間介電層90在去除犧牲閘極結構50期間保護源極/汲極磊晶層80。可使用電漿乾式蝕刻及/或濕式蝕刻去除犧牲閘極結構50。當犧牲閘電極層54為多晶矽及層間介電層90為氧化矽時,諸如TMAH溶液之濕蝕刻劑可用於選擇性地去除犧牲閘電極層54。此後使用電漿乾式蝕刻及/或濕式蝕刻去除犧牲閘極介電層52。
在去除犧牲閘極結構50之後,去除鰭結構30之通道區域中的第二半導體層25,從而形成第一半導體層20之線,如第30A圖及第30B圖圖示。第30A圖圖示透視圖及第30B圖圖示對應於第22A圖之線X1-X1的橫截面視圖。
使用可選擇性蝕刻第二半導體層25之蝕刻劑去除或蝕刻第二半導體層25。當第一半導體層20為Si及第二半導體層25為Ge或SiGe時,第一半導體層20可使用一濕蝕刻劑選擇性地去除,此濕蝕刻劑諸如但不限於氫氧化四甲
銨(TMAH)、乙二胺鄰苯二酚(EDP)或氫氧化鉀(KOH)溶液。
在形成第一半導體層20之線之後,形成閘極結構100,如第31A圖及第31B圖圖示。第31A圖圖示透視圖及第31B圖圖示對應於第31A圖之線X1-X1的橫截面視圖。閘極介電層104圍繞每個通道層(第一半導體層20之線)形成,及閘電極層108形成於閘極介電層104上方。
在某些實施例中,閘極介電層104包括一或多層介電材料,諸如氧化矽、氮化矽或高介電常數介電材料,其他適合介電材料,及/或其組合。高介電常數介電材料之實例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他適合高介電常數介電材料,及/或其組合。在一些實施例中,界面層102形成於通道層與閘極介電層104之間。閘極介電層104可藉由化學氣相沉積、原子層沉積或任何適合方法而形成。在一個實施例中,使用諸如原子層沉積之高度共形沉積製程形成閘極介電層104,以確保圍繞每個通道層具有均勻厚度之閘極介電層的形成。在一個實施例中閘極介電層102之厚度範圍為約1nm至約6nm。
在一些實施例中,閘電極層108形成於閘極介電層104上方以圍繞每個通道層。閘電極層108包括一或多層導電材料,諸如多晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、
TaC、TaSiN、金屬合金、其他適合材料,及/或其組合。閘電極層108可藉由化學氣相沉積、原子層沉積、電鍍、或其他適合方法而形成。閘電極層亦沉積於層間介電層90之頂表面上方。接下來藉由使用例如化學機械拋光將形成於層間介電層90上方之閘極介電層104及閘電極層108平坦化,直到露出層間介電層90。
在某些實施例中,將一或多個功函數調整層106插入閘極介電層104與閘電極層108之間。功函數調整層106由導電材料組成,導電材料諸如單層TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC,或者兩種或更多種此等材料之多層。對於N型通道場效電晶體,TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi之一或多者用作功函數調整層。功函數調整層106可藉由原子層沉積、物理氣相沉積、化學氣相沉積、電子束蒸發或其他適當製程而形成。此外,可分別針對可使用不同金屬層之N型通道場效電晶體及P型通道場效電晶體形成功函數調整層106。
應理解,閘極全環繞場效電晶體經歷另外的CMOS製程以形成各種特徵,諸如觸點/通孔、互連金屬層、介電層、鈍化層等等。
本文描述之各種實施例或實例相較於現有技術提供若干優勢。例如,在本揭示之一實施方式中,通道(半導體線)不與閘極側壁間隔物接觸且閘極側壁間隔物不與源極/汲極磊晶層(SiP層)接觸。因此,可以減少閘極側壁間隔
物之下之介面狀態密度(Dit)。此外,藉由使用比通道之Ge或SiGe更大的能隙材料來接觸通道之端部,可能減少Ge能隙至能隙通道漏電流(band-to-band channel leakage)。另外,因為介電材料層之剩餘層設置在源極/汲極磊晶層之底部處,所以有可能減少基板漏電流。
應當理解,並非所有優點都必須在本文中論述,無特別的優點為所有實施例或實例所必需,並且其他實施例或實例可以提供不同的優點。
根據本揭示之一實施方式之一個態樣,在半導體元件之製造方法中,形成鰭結構,其中包括複數個第一半導體層及複數個第二半導體層交替堆疊,於底部鰭結構上方。具有複數個側壁間隔物之犧牲閘極結構形成於鰭結構上方。複數個側壁間隔物以垂直於半導體基板之主表面的方向形成。去除未被犧牲閘極結構覆蓋之鰭結構的源極/汲極區域。橫向凹陷第二半導體層。複數個介電內部間隔物形成於凹陷第二半導體層之橫向端部上。橫向凹陷第一半導體層。形成源極/汲極磊晶層以接觸凹陷第一半導體層之橫向端部。去除第二半導體層,從而露出通道區域中之第一半導體層。形成閘極結構圍繞第一半導體層。在上述及以下實施例之一或多者中,第一半導體層中的至少一者與源極/汲極磊晶層之間的介面位於側壁間隔物中的一者之下。在上述及以下實施例之一或多者中,介面比側壁間隔物中的一者的中心線更接近閘極結構。在上述及以下實施例之一或多者中,側壁間隔物不與第一半導體層接觸。在上述及以下實施例之一
或多者中,形成介電內部間隔物之步驟包括形成介電層及蝕刻此介電層,且源極/汲極磊晶層藉由此介電層之一部分與底部鰭結構分隔。在上述及以下實施例之一或多者中,側壁間隔物之材料不同於介電內部間隔物之材料。在上述及以下實施例之一或多者中,介電內部間隔物之材料為氮化矽。在上述及以下實施例之一或多者中,側壁間隔物之材料為SiOC、SiCON及SiCN中的一者。在上述及以下實施例之一或多者中,第一半導體層由Ge或Si1-xGex組成,其中0.5x<1,且第二半導體層由Si1-yGey組成,其中0.2y0.6且x>y。
根據本揭示之一實施方式之另一態樣,在半導體元件之製造方法中,形成鰭結構,其中鰭結構包含複數個第一半導體層及複數個第二半導體層交替堆疊,於底部鰭結構上方。形成具有複數個側壁間隔物的犧牲閘極結構於鰭結構上方。側壁間隔物以垂直於半導體基板之主表面的方向形成。去除未由犧牲閘極結構覆蓋之鰭結構的源極/汲極區域中的第二半導體層。形成介電層。蝕刻源極/汲極區域中之介電層及第一半導體層,從而在第二半導體層之橫向端部處形成複數個介電內部間隔物。橫向凹陷第一半導體層。形成源極/汲極磊晶層以接觸凹陷第一半導體層之橫向端部。去除第二半導體層,從而露出通道區域中的第一半導體層。形成閘極結構圍繞第一半導體層。在上述及以下實施例之一或多者中,第一半導體層中的至少一者與源極/汲極磊晶層之間的介面位於側壁間隔物中的一者之下。在上述及以下實施
例之一或多者中,側壁間隔物並不與第一半導體層接觸。在上述及以下實施例之一或多者中,側壁間隔物之材料不同於介電內部間隔物之材料。在上述及以下實施例之一或多者中,介電內部間隔物之材料為氮化矽。在上述及以下實施例之一或多者中,側壁間隔物之材料為SiOC、SiCON及SiCN中的一者。在上述及以下實施例之一或多者中,第一半導體層由Ge或Si1-xGex組成,其中0.5x<1,及第二半導體層由Si1-yGey組成,其中0.2y0.6且x>y。在上述及以下實施例之一或多者中,在形成介電內部間隔物之後,介電層之一部分保留在側壁間隔物上。在上述及以下實施例之一或多者中,源極/汲極磊晶層藉由介電層之一部分與底部鰭結構分離。
根據本揭示之一實施方式之另一態樣,在半導體元件之製造方法中,形成鰭結構,其中包括複數個第一半導體層及複數個第二半導體層交替堆疊,於底部鰭結構上方。犧牲閘極結構形成於鰭結構上方。側壁間隔物形成於犧牲閘極結構之相對側面上。去除鰭結構之源極/汲極區域。橫向凹陷第二半導體層。介電內部間隔物形成於凹陷第二半導體層之橫向端部上。橫向凹陷第一半導體層。形成源極/汲極磊晶層以接觸凹陷第一半導體層之橫向端部。形成層間介電層。去除犧牲閘極結構。去除第二半導體層,從而露出通道區域中之第一半導體層。閘極結構圍繞第一半導體層。在上述及以下實施例之一或多者中,側壁間隔物之材料不同於介電內部間隔物之材料。
根據本揭示之一實施方式之一個態樣,半導體元件包括垂直佈置的複數個半導體線,其每一者均具有通道區域、連接至半導體線之複數個端部的源極/汲極磊晶層、具有圍繞半導體線形成之複數個側壁間隔物的閘極結構、及設置於閘極結構與源極/汲極磊晶層之間之複數個介電內部間隔物。半導體線中的至少一者與源極/汲極磊晶層之間的介面位於側壁間隔物中的一者之下。在上述及以下實施例之一或多者中,側壁間隔物並不與半導體線接觸。在上述及以下實施例之一或多者中,介面比側壁間隔物中的一者的中心線更接近閘極結構。在上述及以下實施例之一或多者中,半導體線之端部具有V形或U形橫截面。在上述及以下實施例之一或多者中,側壁間隔物之材料不同於介電內部間隔物之材料。在上述及以下實施例之一或多者中,介電內部間隔物之材料為氮化矽。在上述及以下實施例之一或多者中,側壁間隔物之材料為SiOC、SiCON及SiCN中的一者。在上述及以下實施例之一或多者中,半導體線由Ge或Si1-xGex組成,其中0.5x<1.0。在上述及以下實施例之一或多者中,源極/汲極磊晶層包括SiP。在上述及以下實施例之一或多者中,整個介電內部間隔物位於側壁間隔物之下。
根據本揭示之一實施方式之另一態樣,半導體元件包括:垂直佈置的複數個半導體線,其每一者均具有通道區域;連接至半導體線之複數個端部的源極/汲極磊晶層;閘極結構,具有圍繞半導體線形成之複數個第一側壁間隔物;設置於閘極結構與源極/汲極磊晶層之間的複數個介
電內部間隔物;及設置在第一側壁間隔物上之第二側壁間隔物。第一側壁間隔物不與半導體線接觸。在上述及以下實施例之一或多者中,第二側壁間隔物並不與半導體線接觸。在上述及以下實施例之一或多者中,半導體導線之至少一者與源極/汲極磊晶層之間的介面位於第一側壁間隔物之一者之下。在上述及以下實施例之一或多者中,介電內部間隔物之至少一者與源極/汲極磊晶層之間的介面位於第一側壁間隔物之一者之下的區域外。在上述及以下實施例之一或多者中,第二側壁間隔物之材料與介電內部間隔物之材料相同。在上述及以下實施例之一或多者中,第一側壁間隔物之材料不同於介電內部間隔物之材料。在上述及以下實施例之一或多者中,介電內部間隔物之材料為氮化矽。在上述及以下實施例之一或多者中,第一側壁間隔物之材料為SiOC、SiCON及SiCN之一者。在上述及以下實施例之一或多者中,半導體線由Ge或Si1-xGex組成,其中0.5x<1.0。
根據本揭示之一實施方式之另一態樣,半導體元件包括垂直佈置的複數個半導體線,其每一者均具有通道區域、連接至半導體線之複數個端部的源極/汲極磊晶層、具有圍繞半導體線形成之複數個側壁間隔物的閘極結構、及設置於閘極結構與源極/汲極磊晶層之間之複數個介電內部間隔物。側壁間隔物不與半導體線接觸。
上文概述若干實施例之特徵或實例,使得熟習此項技術者可更好地理解本揭示之一實施方式之態樣。熟習此項技術者應瞭解,可輕易使用本揭示之一實施方式作為設
計或修改其他製程及結構的基礎,以便實施本文所介紹之實施例或實例的相同目的及/或實現相同優勢。熟習此項技術者亦應認識到,此類等效結構並未脫離本揭示之一實施方式之精神及範疇,且可在不脫離本揭示之一實施方式之精神及範疇的情況下產生本文的各種變化、替代及更改。
11:底部鰭結構
20:半導體線/第一半導體層
55:閘極側壁間隔物
60:介電層
62:介電內部間隔物
80:源極/汲極磊晶層
85:襯墊層
90:層間介電層
100:閘極結構
102:界面層
104:閘極介電層
106:功函數調整層
108:閘電極層
A-A’、B-B’、C-C’:線
Claims (10)
- 一種半導體元件的製造方法,包括以下步驟:形成一鰭結構,其包含複數個第一半導體層及複數個第二半導體層交替堆疊於一底部鰭結構上方;在該鰭結構上方形成具有複數個側壁間隔物的一犧牲閘極結構,該些側壁間隔物以垂直於一半導體基板之一主表面的一方向形成;去除未被該犧牲閘極結構覆蓋的該鰭結構的一源極/汲極區域;橫向凹陷該些第二半導體層;在經凹陷的該些第二半導體層之橫向端部上形成複數個介電內部間隔物;橫向凹陷該些第一半導體層;形成一源極/汲極磊晶層以接觸經凹陷的該些第一半導體層之橫向端部;去除該些第二半導體層,從而露出一通道區域中之該些第一半導體層;以及形成一閘極結構圍繞該些第一半導體層,其中該些第一半導體層的橫向端部具有凹形形狀,使得該些第一半導體層的中心長度小於底部長度。
- 如請求項1所述之方法,其中在該些第一半導體層中的至少一者與該源極/汲極磊晶層之間的一介面位於該些側壁間隔物中的一者之下。
- 如請求項1所述之方法,其中該些側壁間隔物不與該些第一半導體層接觸。
- 一種半導體元件的製造方法,包括以下步驟:形成一鰭結構,其中該鰭結構包含複數個第一半導體層及複數個第二半導體層交替堆疊於一底部鰭結構上方;在該鰭結構上方形成具有複數個側壁間隔物的一犧牲閘極結構,該些側壁間隔物以垂直於一半導體基板之一主表面的一方向形成;去除未由該犧牲閘極結構覆蓋之該鰭結構的一源極/汲極區域中的該些第二半導體層;形成一介電層;在該源極/汲極區域中蝕刻該介電層及該些第一半導體層,從而在該些第二半導體層之橫向端部形成複數個介電內部間隔物,其中在形成該些介電內部間隔物之後,該介電層之一部分保留在該些側壁間隔物上;橫向凹陷該些第一半導體層;形成一源極/汲極磊晶層以接觸經凹陷的該些第一半導體層之橫向端部;去除該些第二半導體層,從而露出一通道區域中的該些第一半導體層;以及 形成一閘極結構圍繞該些第一半導體層。
- 如請求項5所述之方法,其中該些側壁間隔物不與該些第一半導體層接觸。
- 如請求項5所述之方法,其中該些側壁間隔物之一材料不同於該些介電內部間隔物之一材料。
- 如請求項5所述之方法,其中該源極/汲極磊晶層藉由該介電層之另一部分與該底部鰭結構分隔。
- 一種半導體元件,包括:垂直佈置的複數個半導體線,其每一者均具有一通道區域和一凹形形狀端部,使得該些半導體線的中心長度小於底部長度;一源極/汲極磊晶層,其連接至該些半導體線之該些凹形形狀端部;一閘極結構,具有圍繞該些半導體線形成之複數個側壁間隔物;以及複數個介電內部間隔物,設置在該閘極結構與該源極/汲極磊晶層之間,其中在該些半導體線中的至少一者與該源極/汲極磊晶層之間的一介面位於該些側壁間隔物中的一者之下。
- 如請求項9所述之半導體元件,其中該些側壁間隔物不與該些半導體線接觸。
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