TWI704621B - 半導體裝置之製造方法 - Google Patents
半導體裝置之製造方法 Download PDFInfo
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Abstract
本實施形態之半導體裝置之製造方法包括:第1絕緣膜形成步驟,其以覆蓋具有呈鰭狀地隆起之源極及汲極由閘極覆蓋之構造之電晶體的上述閘極之表面之至少一部分之方式,形成第1絕緣膜;犧牲膜形成步驟,其於上述第1絕緣膜之上形成犧牲膜;硬質遮罩圖案形成步驟,其於上述犧牲膜之上形成具有所需圖案之硬質遮罩膜;第1開口形成步驟,其藉由將上述硬質遮罩膜作為蝕刻遮罩去除上述犧牲膜之一部分,而形成第1開口;第2絕緣膜形成步驟,其於上述第1開口形成材料與上述第1絕緣膜不同之第2絕緣膜;第2開口形成步驟,其於上述第2絕緣膜形成步驟後,去除上述犧牲膜,藉此於至少將上述源極之一部分或上述汲極與配線層電性連接之位置形成第2開口;及接觸插塞形成步驟,其於上述第2開口形成接觸插塞。
Description
本發明係關於一種半導體裝置之製造方法。
先前,已知有具有呈鰭狀地隆起之源極及汲極自左右之2個方向或左右與上方之3個方向由閘極覆蓋之構造的鰭式-場效型電晶體(FinFET)。
於FinFET中,藉由蝕刻使形成於源極及汲極之上之PMD(Pre Metal Dielectric,金屬前介電質)膜等絕緣膜之一部分開口,於開口之部分形成接觸插塞,藉此將源極及汲極與配線層電性連接。然而,存在如下情形:伴隨著圖案之微細化,產生起因於曝光精度或解析度之位置偏移,而難以於所需位置形成開口。
因此,使用於形成PMD膜之前藉由材料與PMD膜不同之絕緣膜覆蓋閘極並藉由高選擇比蝕刻而形成開口之被稱為自對準接觸(SAC:Self-Aligned Contact)的方法(例如參照專利文獻1)。
[專利文獻1]日本專利特開2014-531770號公報
然而,於上述方法中,存在於藉由高選擇比蝕刻形成開口時將覆蓋閘極之絕緣膜之一部分蝕刻之情形。若如此般將覆蓋閘極之絕緣
膜之一部分蝕刻,則形成於所開口之部分之接觸插塞與閘極之配線間之距離變短,故而於接觸插塞與閘極之配線間產生漏電流之增大或短路。
因此,尋求一種能夠抑制漏電流或短路之半導體裝置之製造方法。
為了達成上述目的,本發明之一態樣之半導體裝置之製造方法包括:第1絕緣膜形成步驟,其以覆蓋具有呈鰭狀地隆起之源極及汲極由閘極覆蓋之構造之電晶體的上述閘極之表面之至少一部分之方式,形成第1絕緣膜;犧牲膜形成步驟,其於上述第1絕緣膜之上形成犧牲膜;硬質遮罩圖案形成步驟,其於上述犧牲膜之上形成具有所需圖案之硬質遮罩膜;第1開口形成步驟,其藉由將上述硬質遮罩膜作為蝕刻遮罩去除上述犧牲膜之一部分,而形成第1開口;第2絕緣膜形成步驟,其於上述第1開口形成材料與上述第1絕緣膜不同之第2絕緣膜;第2開口形成步驟,其於上述第2絕緣膜形成步驟後,去除上述犧牲膜,藉此於至少將上述源極之一部分或上述汲極與配線層電性連接之位置形成第2開口;及接觸插塞形成步驟,其於上述第2開口形成接觸插塞。
根據揭示之半導體裝置之製造方法,可抑制漏電流或短路。
102‧‧‧閘極
104‧‧‧頂蓋介電膜
106‧‧‧第1絕緣膜
108‧‧‧犧牲膜
110‧‧‧保護膜
112‧‧‧硬質遮罩膜
112a‧‧‧硬質遮罩圖案
112A‧‧‧硬質遮罩膜
112B‧‧‧硬質遮罩膜
112C‧‧‧開口
112D‧‧‧開口
112s‧‧‧間隙圖案
114‧‧‧第1開口
116‧‧‧第2絕緣膜
118‧‧‧第2開口
120‧‧‧接觸插塞
152‧‧‧蝕刻遮罩
154‧‧‧第1切斷遮罩
156‧‧‧第2切斷遮罩
192‧‧‧第1蝕刻遮罩
194‧‧‧第2蝕刻遮罩
196‧‧‧第3蝕刻遮罩
1121‧‧‧線圖案
L1‧‧‧距離
L2‧‧‧距離
圖1係表示本實施形態之半導體裝置之製造方法之一例的流程圖。
圖2係表示本實施形態之半導體裝置之製造方法之一例的步驟圖(1)。
圖3係表示本實施形態之半導體裝置之製造方法之一例的步驟圖
(2)。
圖4係表示本實施形態之半導體裝置之製造方法之一例的步驟圖(3)。
圖5係表示本實施形態之半導體裝置之製造方法之一例的步驟圖(4)。
圖6係表示本實施形態之半導體裝置之製造方法之一例的步驟圖(5)。
圖7係表示本實施形態之半導體裝置之製造方法之一例的步驟圖(6)。
圖8係表示本實施形態之半導體裝置之製造方法之一例的步驟圖(7)。
圖9係表示本實施形態之半導體裝置之製造方法之一例的步驟圖(8)。
圖10係表示本實施形態之半導體裝置之製造方法之一例的步驟剖視圖(9)。
圖11係表示硬質遮罩圖案形成步驟之一例之流程圖。
圖12A係表示硬質遮罩圖案形成步驟之一例之步驟圖(1)。
圖12B係表示硬質遮罩圖案形成步驟之一例之步驟圖(1)。
圖13A係表示硬質遮罩圖案形成步驟之一例之步驟圖(2)。
圖13B係表示硬質遮罩圖案形成步驟之一例之步驟圖(2)。
圖14A係表示硬質遮罩圖案形成步驟之一例之步驟圖(3)。
圖14B係表示硬質遮罩圖案形成步驟之一例之步驟圖(3)。
圖15A係表示硬質遮罩圖案形成步驟之一例之步驟圖(4)。
圖15B係表示硬質遮罩圖案形成步驟之一例之步驟圖(4)。
圖16係對本實施形態之半導體裝置之製造方法之作用、效果進行說明的圖(1)。
圖17係對本實施形態之半導體裝置之製造方法之作用、效果進行說明的圖(2)。
圖18係對本實施形態之半導體裝置之製造方法之作用、效果進行說明的圖(3)。
圖19係對本實施形態之半導體裝置之製造方法之作用、效果進行說明的圖(4)。
以下,參照圖式,對用以實施本發明之形態進行說明。再者,於本說明書及圖式中,對實質上相同之構成標註相同符號,藉此省略重複之說明。
以下,以製造具有呈鰭狀地隆起之源極及汲極自左右與上方之3個方向由閘極覆蓋之構造的FinFET作為半導體裝置之情形為例進行說明,但並不限定於該形態。作為半導體裝置,例如亦可為具有呈鰭狀地隆起之源極及汲極自左右之2個方向由閘極覆蓋之構造的FinFET。
於本實施形態之半導體裝置之製造方法中,首先,於形成將呈鰭狀地隆起之源極及汲極與配線層電性連接之接觸插塞之位置形成犧牲膜,並且於不形成接觸插塞之位置形成材料與犧牲膜不同之絕緣膜。繼而,於殘存有絕緣膜之狀態下去除犧牲膜,於去除犧牲膜之部分形成接觸插塞。藉此,可製造所需源極及汲極(以下亦稱為「源極/汲極區域」)與配線層經由接觸插塞而電性連接之FinFET,又,可抑制漏電流或短路。於下文對可抑制漏電流或短路之理由進行敍述。
以下,對本實施形態之半導體裝置之製造方法進行詳細說明。圖1係表示本實施形態之半導體裝置之製造方法之一例的流程圖。圖2至圖10係表示本實施形態之半導體裝置之製造方法之一例的步驟剖視圖。再者,於圖2至圖10中,省略源極/汲極區域之圖示。
如圖1所示,本實施形態之半導體裝置之製造方法包括第1絕緣
膜形成步驟S10、犧牲膜形成步驟S20、硬質遮罩圖案形成步驟S30、第1開口形成步驟S40、第2絕緣膜形成步驟S50、硬質遮罩膜去除步驟S60、第2開口形成步驟S70、第1絕緣膜去除步驟S80、及接觸插塞形成步驟S90。
首先,如圖2所示,以覆蓋具有呈鰭狀地隆起之源極及汲極自左右與上方之3個方向由閘極102覆蓋之構造之電晶體的閘極102之表面之至少一部分之方式,形成第1絕緣膜106(第1絕緣膜形成步驟S10)。於圖2中,於閘極102之兩側面形成有第1絕緣膜106。又,於閘極102之上表面形成有頂蓋介電膜104。再者,於圖2中,於頂蓋介電膜104之上表面未形成第1絕緣膜106,但第1絕緣膜106亦可形成於頂蓋介電膜104之上表面。
第1絕緣膜106係於形成用於將源極/汲極區域與配線層電性連接之接觸插塞120之開口時防止閘極102被蝕刻之絕緣膜,且為接觸蝕刻終止層(CESL:Contact Etch Stop Layer)。第1絕緣膜106例如較佳為氮化矽膜(SiN膜)。再者,於下文對接觸插塞120進行敍述。
第1絕緣膜106之形成方法並無特別限定,可根據形成之膜之材料或膜厚等任意選擇。於第1絕緣膜106為SiN膜之情形時,例如可使用化學氣相沈積(CVD:Chemical Vapor Deposition)。又,亦可使用原子層沈積(ALD:Atomic Layer Deposition)或分子層沈積(MDL:Molecular Layer Deposition)。
繼而,如圖3所示,於在第1絕緣膜形成步驟S10中形成之第1絕緣膜106之上形成犧牲膜108(犧牲膜形成步驟S20)。
犧牲膜108係將於下述第2開口形成步驟S70中去除之膜,例如為虛設插塞。犧牲膜108係材料與第1絕緣膜106不同之膜,較佳為相對於第1絕緣膜106及下述第2絕緣膜具有較高之蝕刻選擇性之膜。於第1絕緣膜106為SiN膜之情形時,犧牲膜108例如可使用SOC(Spin On
Carbon,旋塗碳)膜、非晶矽(a-Si)膜、SOD(Spin On Dielectric,旋塗介電質)膜。其中,就相對於SiN膜具有特別高之蝕刻選擇性之觀點而言,較佳為SOC膜。
又,亦可於形成犧牲膜108之後,進行使犧牲膜108之上表面平坦化之平坦化處理。平坦化處理之方法並無特別限定,於犧牲膜108為SOC膜之情形時,例如可使用對犧牲膜108照射紫外線(UV)之方法。又,亦可於平坦化處理之後,於經平坦化之犧牲膜108之上表面進一步形成犧牲膜108。
繼而,如圖4所示,於在犧牲膜形成步驟S20中形成之犧牲膜108之上形成具有所需圖案之硬質遮罩膜112(硬質遮罩圖案形成步驟S30)。
具體而言,於在犧牲膜形成步驟S20中形成之犧牲膜108之上,例如形成藉由SiN膜形成之保護膜110,於保護膜110之上,形成將不形成接觸插塞120之位置之硬質遮罩膜112去除之硬質遮罩圖案112a。即,形成使形成下述接觸插塞120之位置之硬質遮罩膜112殘存之硬質遮罩圖案112a,故而可藉由於形成線與間隙圖案(L & S圖案)之後將線圖案之一部分切斷之所謂一維(1D)佈局而形成硬質遮罩圖案112a。因此,邊緣位置之誤差(EPE:Edge Placement Error)容限變大。再者,於下文對在硬質遮罩膜112形成所需圖案之方法之詳細情況進行敍述。
繼而,如圖5所示,藉由將於硬質遮罩圖案形成步驟S30中形成之具有所需圖案之硬質遮罩膜112作為蝕刻遮罩去除犧牲膜108,而形成第1開口114(第1開口形成步驟S40)。
去除犧牲膜108之方法並無特別限定,可根據所去除之膜之材料等任意選擇,例如較佳為使用反應性離子蝕刻(RIE:Reactive Ion Etching)。
繼而,如圖6所示,於在第1開口形成步驟S40中形成之第1開口114形成第2絕緣膜116(第2絕緣膜形成步驟S50)。藉由於第1開口114形成第2絕緣膜116,即便於在第1開口形成步驟S40中第1絕緣膜106之一部分被蝕刻之情形時,亦可於被蝕刻之部分重新形成第2絕緣膜116。因此,可防止被蝕刻之部分成為漏電流或短路之路徑。
第2絕緣膜116係形成於源極/汲極區域之上之絕緣膜,例如為PMD膜。第2絕緣膜116係材料與第1絕緣膜106及犧牲膜108不同之膜,較佳為相對於犧牲膜108具有較高之蝕刻選擇性之膜。於犧牲膜108為SOC膜之情形時,第2絕緣膜116例如較佳為SOD膜、氧化矽膜(SiO2膜)。於犧牲膜108為a-Si膜之情形時,第2絕緣膜116例如較佳為SOD膜或SiO2膜。於犧牲膜108為SOD膜之情形時,第2絕緣膜116例如較佳為SiO2膜。
繼而,如圖7所示,於在第2絕緣膜形成步驟S50中形成第2絕緣膜116之後,將硬質遮罩膜112及形成於硬質遮罩膜112之上之第2絕緣膜116去除(硬質遮罩膜去除步驟S60)。
去除硬質遮罩膜112之方法並無特別限定,例如可使用化學機械研磨(CMP:Chemical Mechanical Polishing)、乾式蝕刻、濕式蝕刻。具體而言,例如可藉由利用CMP進行研磨直至犧牲膜108之上表面露出為止,而將第2絕緣膜116及硬質遮罩膜112去除。又,亦可於藉由CMP進行研磨直至硬質遮罩膜112之上表面露出為止之後,例如藉由乾式蝕刻、濕式蝕刻去除硬質遮罩膜112。又,於能夠於下述第2開口形成步驟S70中與去除犧牲膜108同時去除硬質遮罩膜112之情形時,亦可於第2開口形成步驟S70之前不進行硬質遮罩膜去除步驟S60,可省略硬質遮罩膜去除步驟S60。
繼而,如圖8所示,於在硬質遮罩膜去除步驟S60中去除硬質遮罩膜112之後,去除犧牲膜108,藉此形成第2開口118(第2開口形成步
驟S70)。藉此,於將源極/汲極區域與配線層電性連接之位置形成開口(第2開口118)。
去除犧牲膜108之方法並無特別限定,可根據犧牲膜108及第2絕緣膜116之材料等任意選擇。
於犧牲膜108為SOC膜,第1絕緣膜106為SiN膜,第2絕緣膜116為SOD膜或SiO2膜之情形時,例如較佳為使用灰化。於藉由灰化去除SOC膜時,由於SOC膜相對於SiN膜、SOD膜及SiO2膜具有較高之蝕刻選擇性,故而SiN膜、SOD膜及SiO2膜幾乎不會被切削。即,第1絕緣膜106及頂蓋介電膜104幾乎不會被切削,而可維持形狀。
於犧牲膜108為a-Si膜,第1絕緣膜106為SiN膜,第2絕緣膜116為SOD膜或SiO2膜之情形時,例如較佳為使用利用包含氯或溴之氣體之乾式蝕刻。於藉由使用包含氯或溴之氣體之乾式蝕刻去除a-Si膜時,由於a-Si膜相對於SiN膜、SOD膜及SiO2膜具有較高之蝕刻選擇性,故而SiN膜、SOD膜及SiO2膜幾乎不會被切削。即,第1絕緣膜106及頂蓋介電膜104幾乎不會被切削,而可維持形狀。
於犧牲膜108為SOD膜,第1絕緣膜106為SiN膜,第2絕緣膜116為SiO2膜之情形時,例如較佳為使用濕式蝕刻。於藉由濕式蝕刻去除SOD膜時,由於SOD膜相對於SiN膜及SiO2膜具有較高之蝕刻選擇性,故而SiN膜及SiO2膜幾乎不會被切削。即,第1絕緣膜106及頂蓋介電膜104幾乎不會被切削,而可維持形狀。
繼而,如圖9所示,將殘存於在第2開口形成步驟S70中形成之第2開口118之底部之第1絕緣膜106去除(第1絕緣膜去除步驟S80)。藉此,源極/汲極區域露出於第2開口118之底部。
去除第1絕緣膜106之方法並無特別限定,例如較佳為使用RIE。於使源極/汲極區域露出於第2開口118之底部時,位於閘極102之上部之第1絕緣膜106及頂蓋介電膜104亦被切削一部分,但由於在形成第2
開口118之步驟(第2開口形成步驟S70)中維持第1絕緣膜106及頂蓋介電膜104之形狀,故而可抑制最終之切削量。藉此,維持第2開口118與閘極102之配線間之距離,故而可抑制接觸插塞120與閘極102之配線間之漏電流或短路。
繼而,如圖10所示,於在第2開口形成步驟S70及第1絕緣膜去除步驟S80中形成之供源極/汲極區域露出於底部之第2開口118形成接觸插塞120(接觸插塞形成步驟S90)。
接觸插塞120係將源極/汲極區域與配線層電性連接之膜,例如為導電膜。導電膜並無特別限定,例如較佳為使用鎢(W)、銅(Cu)、聚矽(Poly-Si)。
接觸插塞120之形成方法並無特別限定,可根據導電膜之材料等任意選擇。又,亦可於在第2開口118形成氮化鈦膜(TiN膜)與鈦膜(Ti膜)之積層膜等障壁金屬膜之後,形成接觸插塞120。
藉由以上步驟,可製造所需之源極/汲極區域與配線層電性連接之FinFET。
其次,對在硬質遮罩膜112形成所需圖案之方法(硬質遮罩圖案形成步驟S30)進行說明。圖11係表示硬質遮罩圖案形成步驟之一例之流程圖。圖12至圖15係表示硬質遮罩圖案形成步驟之一例之步驟圖。再者,圖12A係俯視圖,圖12B係於圖12A中之單點鏈線12A-12B切斷所得之剖視圖。圖13A係俯視圖,圖13B係於圖13A中之單點鏈線13A-13B切斷所得之剖視圖。圖14A係俯視圖,圖14B係於圖14A中之單點鏈線14A-14B切斷所得之剖視圖。圖15A係俯視圖,圖15B係於圖15A中之單點鏈線15A-15B切斷所得之剖視圖。再者,於圖12至圖15中,省略源極/汲極區域之圖示。
如圖11所示,硬質遮罩圖案形成步驟S30包括硬質遮罩膜形成步驟S31、L & S圖案形成步驟S32、及線圖案切斷步驟S33。
首先,如圖12所示,於在犧牲膜形成步驟S20中形成之犧牲膜108之上形成保護膜110,於保護膜110之上形成硬質遮罩膜112(硬質遮罩膜形成步驟S31)。
硬質遮罩膜112只要為於在第1開口形成步驟S40中對犧牲膜108進行蝕刻時作為蝕刻遮罩發揮功能之膜即可。於犧牲膜108為SOC膜之情形時,硬質遮罩膜112例如較佳為SiO2膜與SiN膜之積層膜、SiO2膜與TiN膜之積層膜等相對於SOC膜具有較高之蝕刻選擇性的膜。於犧牲膜108為SOD膜之情形時,硬質遮罩膜112例如較佳為矽膜(Si膜)、TiN膜等相對於SOD膜具有較高之蝕刻選擇性之膜。
硬質遮罩膜112之形成方法並無特別限定,可根據所形成之膜之材料或膜厚等任意選擇。
繼而,如圖13所示,於在硬質遮罩膜形成步驟S31中形成之硬質遮罩膜112形成L & S圖案(L & S圖案形成步驟S32)。
具體而言,以對應於源極/汲極區域之位置成為線圖案1121,對應於閘極102之位置成為間隙圖案112s之方式,將硬質遮罩膜112圖案化。
將硬質遮罩膜112圖案化之方法並無特別限定,例如可使用於硬質遮罩膜112之上形成抗蝕圖案並將抗蝕圖案作為蝕刻遮罩而對硬質遮罩膜112進行蝕刻之方法。抗蝕圖案以對應於源極/汲極區域之位置成為線圖案,對應於閘極102之位置成為間隙圖案之方式,並例如藉由光微影法而形成。再者,於形成比曝光裝置之解析極限更微細之圖案之情形時,亦可藉由SAMP(Self-Aligned Multiple Patterning,自我對齊多重圖案化)而於硬質遮罩膜112形成L & S圖案。
繼而,如圖14及圖15所示,將具有於L & S圖案形成步驟S32中形成之L & S圖案之硬質遮罩膜112之線圖案1121的一部分切斷(線圖案切斷步驟S33)。
具體而言,將硬質遮罩膜112之線圖案1121中之不形成將源極/汲極區域與配線層電性連接之接觸插塞120的位置之線圖案去除,藉此將硬質遮罩膜112之線圖案之一部分切斷。
將線圖案之一部分切斷之方法並無特別限定,可使用於硬質遮罩膜112之上藉由光微影法形成切斷遮罩並將切斷遮罩作為蝕刻遮罩而對硬質遮罩膜112進行蝕刻之方法。以對應於線圖案1121中之欲切斷之區域之位置成為開口之圖案的方式形成切斷遮罩。
又,於線圖案切斷步驟S33中,例如於形成比曝光裝置之解析極限更微細之圖案之情形時,亦可使用複數個切斷遮罩。即,使用複數個切斷遮罩形成具有所需圖案之硬質遮罩膜112。具體而言,如圖14所示,首先,於硬質遮罩膜112之上形成第1切斷遮罩,將第1切斷遮罩作為蝕刻遮罩而將具有L & S圖案之硬質遮罩膜112之線圖案1121之一部分切斷。繼而,如圖15所示,將與第1切斷遮罩不同之第2切斷遮罩作為蝕刻遮罩而將具有L & S圖案之硬質遮罩膜112之線圖案之其他部分切斷。藉此,可形成具有比曝光裝置之解析極限更微細之圖案之硬質遮罩膜112。
再者,於圖14及圖15中,對藉由使用2個不同之切斷遮罩將線圖案1121之一部分切斷而形成具有所需圖案之硬質遮罩膜112的形態進行了說明,但並不限定於該形態。例如亦可藉由使用3個以上之不同之切斷遮罩將線圖案1121之一部分切斷,而形成具有所需圖案之硬質遮罩膜112。又,亦可藉由使用1個切斷遮罩將線圖案1121之一部分切斷,而形成具有所需圖案之硬質遮罩膜112。
藉由以上步驟,可形成具有所需圖案之硬質遮罩膜112。
繼而,基於圖16至圖19,對在形成L & S圖案之後將線圖案1121之一部分切斷,藉此形成具有所需圖案之硬質遮罩膜112之情形時的作用、效果進行說明。
圖16至圖19係對本實施形態之半導體裝置之製造方法之作用、效果進行說明的圖。具體而言,圖16係對本實施形態之硬質遮罩圖案形成步驟進行說明之概略立體圖,圖17係對藉由圖16所示之硬質遮罩圖案形成步驟獲得之硬質遮罩圖案進行說明之圖。又,圖18係對先前之硬質遮罩圖案形成步驟進行說明之概略立體圖,圖19係對藉由圖18所示之硬質遮罩圖案形成步驟獲得之硬質遮罩圖案進行說明之圖。
於本實施形態中,如上所述,以將不形成接觸插塞120之位置之硬質遮罩膜112去除且使形成接觸插塞120之位置之硬質遮罩膜112殘存之方式,將硬質遮罩膜112圖案化。
具體而言,如圖16所示,首先,對硬質遮罩膜112使用具有L & S圖案之蝕刻遮罩152而將L & S圖案轉印至硬質遮罩膜112(步驟LE1)。繼而,將第1切斷遮罩154作為蝕刻遮罩,將於步驟LE1中形成之硬質遮罩膜112之線圖案1121之一部分切斷(步驟LE2)。繼而,將與第1切斷遮罩154不同之第2切斷遮罩156作為蝕刻遮罩,將於步驟LE2中切斷之線圖案1121之其他部分切斷(步驟LE3)。藉此,獲得於形成接觸插塞120之位置殘存有硬質遮罩膜112之硬質遮罩圖案112a。
且說,存在因對位(對準)精度之影響而於步驟LE1、步驟LE2及步驟LE3之各步驟中使用之蝕刻遮罩之位置產生偏移之情形。然而,於本實施形態之半導體裝置之製造方法中,即便於步驟LE1、步驟LE2及步驟LE3之各步驟中使用之蝕刻遮罩之位置於X方向上偏移之情形時,亦如圖17所示,於X方向上相鄰之硬質遮罩膜112(例如圖17中之硬質遮罩膜112A與硬質遮罩膜112B)由於使用一個切斷遮罩形成,故而於X方向上相鄰之硬質遮罩膜112間之距離L1不產生變化而不會相互接觸。其結果,EPE容限變大。
相對於此,先前,以將形成接觸插塞120之位置之硬質遮罩膜112去除且使不形成接觸插塞120之位置之硬質遮罩膜112殘存的方式,將
硬質遮罩膜112圖案化。
具體而言,如圖18所示,使用具有第1開口圖案之第1蝕刻遮罩192,將第1開口圖案轉印至硬質遮罩膜112(步驟LE1)。繼而,使用具有與第1開口圖案不同之第2開口圖案之第2蝕刻遮罩194,將第2開口圖案轉印至於步驟LE1中形成第1開口圖案之硬質遮罩膜112(步驟LE2)。繼而,使用具有與第1開口圖案及第2開口圖案不同之第3開口圖案之第3蝕刻遮罩196,將第3開口圖案轉印至於步驟LE2中形成第2開口圖案之硬質遮罩膜112(步驟LE3)。藉此,獲得將形成接觸插塞120之位置之硬質遮罩膜112去除所得之硬質遮罩圖案112a。
因此,於先前之方法中,於因對準精度之影響而於步驟LE1、步驟LE2及步驟LE3之各步驟中使用之蝕刻遮罩之位置於X方向上偏移的情形時,如圖19所示,在X方向上相鄰之開口(例如圖19中之開口112C與開口112D)由於使用不同之蝕刻遮罩形成,故而存在以於X方向上相鄰之開口間之距離L2縮短之方式於X方向上移動之情形。其結果,EPE容限變小。
如以上所說明,於本實施形態之半導體裝置之製造方法中,於形成將呈鰭狀地隆起之源極及汲極與配線層電性連接之接觸插塞120之位置形成犧牲膜108,並且於不形成接觸插塞120之位置形成材料與犧牲膜108不同之第2絕緣膜116。繼而,於殘存有第2絕緣膜116之狀態下去除犧牲膜108,於去除犧牲膜108之部分形成接觸插塞120。藉此,可製造所需之源極/汲極區域與配線層電性連接之FinFET,且可抑制漏電流或短路。
又,於本實施形態之半導體裝置之製造方法中,於硬質遮罩圖案形成步驟S30中,形成將不形成接觸插塞120之位置之硬質遮罩膜112去除所得之硬質遮罩圖案112a。因此,於形成具有所需圖案之硬質遮罩膜112時,例如可藉由形成L & S圖案且將線圖案之一部分切斷
之所謂1D佈局,而將硬質遮罩膜112圖案化。其結果,EPE容限變大。
以上,藉由上述實施形態對半導體裝置之製造方法進行了說明,但本發明並不限定於上述實施形態,可於本發明之範圍內進行各種變化及改良。
本申請案係主張於2016年3月24日向日本專利廳提出申請之基礎申請案2016-059716號之優先權者,將其全部內容以參照之形式引用於本文。
Claims (8)
- 一種半導體裝置之製造方法,其包括:第1絕緣膜形成步驟,其以將具有呈鰭狀地隆起之源極及汲極由閘極覆蓋之構造之電晶體的上述閘極之表面中之至少上述閘極之兩側面覆蓋之方式,形成第1絕緣膜;犧牲膜形成步驟,其於上述第1絕緣膜之上形成犧牲膜;硬質遮罩圖案形成步驟,其於上述犧牲膜之上形成具有所需圖案之硬質遮罩膜;第1開口形成步驟,其藉由將上述硬質遮罩膜作為蝕刻遮罩而去除上述犧牲膜之一部分,形成第1開口;第2絕緣膜形成步驟,其於上述第1開口形成材料與上述第1絕緣膜不同之第2絕緣膜;第2開口形成步驟,其於上述第2絕緣膜形成步驟之後,去除上述犧牲膜,藉此於至少將上述源極之一部分或上述汲極與配線層電性連接之位置形成第2開口;及接觸插塞形成步驟,其於上述第2開口形成接觸插塞;且上述第2絕緣膜形成步驟中,至少於上述閘極之兩側面殘存有上述第1絕緣膜之狀態下,於上述第1開口形成上述第2絕緣膜。
- 如請求項1之半導體裝置之製造方法,其中上述硬質遮罩圖案形成步驟包括:於上述犧牲膜之上形成線與間隙圖案之硬質遮罩膜之步驟;及藉由將上述線與間隙圖案之線圖案之一部分切斷而形成上述所需圖案之步驟。
- 如請求項1之半導體裝置之製造方法,其 於上述第2絕緣膜形成步驟之後且上述第2開口形成步驟之前,具有去除上述硬質遮罩膜之硬質遮罩膜去除步驟。
- 如請求項1之半導體裝置之製造方法,其中上述硬質遮罩膜係相對於上述犧牲膜具有較高之蝕刻選擇性之膜。
- 如請求項1之半導體裝置之製造方法,其中上述第1絕緣膜為SiN膜。
- 如請求項5之半導體裝置之製造方法,其中上述犧牲膜為SOC膜,上述第2絕緣膜為SOD膜或SiO2膜,且於上述第2開口形成步驟中,藉由灰化而去除上述犧牲膜。
- 如請求項5之半導體裝置之製造方法,其中上述犧牲膜為a-Si膜,上述第2絕緣膜為SOD膜或SiO2膜,且於上述第2開口形成步驟中,藉由使用包含氯或溴之氣體之乾式蝕刻,而去除上述犧牲膜。
- 如請求項5之半導體裝置之製造方法,其中上述犧牲膜為SOD膜,上述第2絕緣膜為SiO2膜,且於上述第2開口形成步驟中,藉由濕式蝕刻而去除上述犧牲膜。
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- 2016-06-27 KR KR1020207029482A patent/KR102270250B1/ko active IP Right Grant
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US20190109205A1 (en) | 2019-04-11 |
DE112016006630T5 (de) | 2018-12-13 |
KR20200120771A (ko) | 2020-10-21 |
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CN107924844B (zh) | 2021-07-20 |
TW202044418A (zh) | 2020-12-01 |
US20210020758A1 (en) | 2021-01-21 |
US10840359B2 (en) | 2020-11-17 |
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CN113539832A (zh) | 2021-10-22 |
SG11201808293UA (en) | 2018-10-30 |
TWI759814B (zh) | 2022-04-01 |
JPWO2017163438A1 (ja) | 2019-01-31 |
JP6903114B2 (ja) | 2021-07-14 |
WO2017163438A1 (ja) | 2017-09-28 |
JP2020043356A (ja) | 2020-03-19 |
KR102195781B1 (ko) | 2020-12-28 |
US11557661B2 (en) | 2023-01-17 |
CN107924844A (zh) | 2018-04-17 |
TW201735175A (zh) | 2017-10-01 |
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