TWI703440B - 記憶體系統、其處理系統以及操作記憶體堆疊的方法 - Google Patents

記憶體系統、其處理系統以及操作記憶體堆疊的方法 Download PDF

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TWI703440B
TWI703440B TW106118496A TW106118496A TWI703440B TW I703440 B TWI703440 B TW I703440B TW 106118496 A TW106118496 A TW 106118496A TW 106118496 A TW106118496 A TW 106118496A TW I703440 B TWI703440 B TW I703440B
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memory
tag
command
tag value
address
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TW106118496A
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TW201804328A (zh
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泰勒 斯托克斯戴爾
張牧天
鄭宏忠
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南韓商三星電子股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5643—Multilevel memory comprising cache storage devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW106118496A 2016-07-26 2017-06-05 記憶體系統、其處理系統以及操作記憶體堆疊的方法 TWI703440B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662367062P 2016-07-26 2016-07-26
US62/367,062 2016-07-26
US15/272,339 2016-09-21
US15/272,339 US10180906B2 (en) 2016-07-26 2016-09-21 HBM with in-memory cache manager

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TW201804328A TW201804328A (zh) 2018-02-01
TWI703440B true TWI703440B (zh) 2020-09-01

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US (1) US10180906B2 (enExample)
JP (1) JP2018018513A (enExample)
KR (1) KR102404643B1 (enExample)
CN (1) CN107656878B (enExample)
TW (1) TWI703440B (enExample)

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CN111679785B (zh) 2019-03-11 2025-03-11 三星电子株式会社 用于处理操作的存储器装置及其操作方法、数据处理系统
KR102879034B1 (ko) * 2019-03-11 2025-10-29 삼성전자주식회사 연산 처리를 수행하는 메모리 장치 및 메모리 장치의 동작방법
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US11436165B2 (en) * 2019-05-01 2022-09-06 Samsung Electronics Co., Ltd. High bandwidth memory system
US10915451B2 (en) * 2019-05-10 2021-02-09 Samsung Electronics Co., Ltd. Bandwidth boosted stacked memory
US11216385B2 (en) * 2019-05-15 2022-01-04 Samsung Electronics Co., Ltd. Application processor, system-on chip and method of operating memory management unit
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US11226816B2 (en) * 2020-02-12 2022-01-18 Samsung Electronics Co., Ltd. Systems and methods for data placement for in-memory-compute
WO2022056757A1 (en) * 2020-09-17 2022-03-24 Alibaba Group Holding Limited Three-dimensional stacked processing systems
KR20220127601A (ko) * 2021-03-11 2022-09-20 삼성전자주식회사 인터페이스를 이용하여 내부 프로세싱을 수행하는 메모리 시스템, 메모리 장치 및 메모리 장치의 동작 방법
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KR102404643B1 (ko) 2022-06-02
CN107656878A (zh) 2018-02-02
US10180906B2 (en) 2019-01-15
TW201804328A (zh) 2018-02-01
CN107656878B (zh) 2023-06-13
US20180032437A1 (en) 2018-02-01
KR20180012180A (ko) 2018-02-05
JP2018018513A (ja) 2018-02-01

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