CN107656878B - 具有内存高速缓存管理器的高带宽存储器 - Google Patents

具有内存高速缓存管理器的高带宽存储器 Download PDF

Info

Publication number
CN107656878B
CN107656878B CN201710515631.0A CN201710515631A CN107656878B CN 107656878 B CN107656878 B CN 107656878B CN 201710515631 A CN201710515631 A CN 201710515631A CN 107656878 B CN107656878 B CN 107656878B
Authority
CN
China
Prior art keywords
memory
tag value
command
tag
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710515631.0A
Other languages
English (en)
Chinese (zh)
Other versions
CN107656878A (zh
Inventor
泰勒·施托克赛达尔
张牧天
郑宏忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN107656878A publication Critical patent/CN107656878A/zh
Application granted granted Critical
Publication of CN107656878B publication Critical patent/CN107656878B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893Caches characterised by their organisation or structure
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement
    • G06F2212/1024Latency reduction
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory
    • G06F2212/6028Prefetching based on hints or prefetch instructions
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/107Serial-parallel conversion of data or prefetch
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564Miscellaneous aspects
    • G11C2211/5643Multilevel memory comprising cache storage devices
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201710515631.0A 2016-07-26 2017-06-29 具有内存高速缓存管理器的高带宽存储器 Active CN107656878B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662367062P 2016-07-26 2016-07-26
US62/367,062 2016-07-26
US15/272,339 2016-09-21
US15/272,339 US10180906B2 (en) 2016-07-26 2016-09-21 HBM with in-memory cache manager

Publications (2)

Publication Number Publication Date
CN107656878A CN107656878A (zh) 2018-02-02
CN107656878B true CN107656878B (zh) 2023-06-13

Family

ID=61010011

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710515631.0A Active CN107656878B (zh) 2016-07-26 2017-06-29 具有内存高速缓存管理器的高带宽存储器

Country Status (5)

Country Link
US (1) US10180906B2 (enExample)
JP (1) JP2018018513A (enExample)
KR (1) KR102404643B1 (enExample)
CN (1) CN107656878B (enExample)
TW (1) TWI703440B (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10936221B2 (en) 2017-10-24 2021-03-02 Micron Technology, Inc. Reconfigurable memory architectures
US10628354B2 (en) * 2017-12-11 2020-04-21 Micron Technology, Inc. Translation system for finer grain memory architectures
KR102505913B1 (ko) * 2018-04-04 2023-03-07 삼성전자주식회사 메모리 모듈 및 메모리 모듈을 포함하는 메모리 시스템
CN111971660B (zh) * 2018-06-05 2025-03-11 拉姆伯斯公司 高速缓存动态随机存取存储器
KR102605205B1 (ko) * 2018-07-25 2023-11-24 에스케이하이닉스 주식회사 메모리 장치 및 프로세싱 시스템
US11138135B2 (en) * 2018-09-20 2021-10-05 Samsung Electronics Co., Ltd. Scale-out high bandwidth memory system
CN110928810B (zh) * 2018-09-20 2023-11-14 三星电子株式会社 向外扩展高带宽存储系统
KR102693213B1 (ko) * 2018-11-30 2024-08-09 에스케이하이닉스 주식회사 메모리 시스템
CN111679785B (zh) 2019-03-11 2025-03-11 三星电子株式会社 用于处理操作的存储器装置及其操作方法、数据处理系统
KR102879034B1 (ko) * 2019-03-11 2025-10-29 삼성전자주식회사 연산 처리를 수행하는 메모리 장치 및 메모리 장치의 동작방법
DE102020105628A1 (de) 2019-03-11 2020-09-17 Samsung Electronics Co., Ltd. Verfahren zur Durchführung interner Verarbeitungsvorgänge mit vordefinierter Protokollschnittstelle einer Speichervorrichtung
DE102020106357A1 (de) 2019-03-11 2020-09-17 Samsung Electronics Co., Ltd. Speichereinrichtung und verfahren mit anweisungsringspeicherwarteschlange
US11436165B2 (en) * 2019-05-01 2022-09-06 Samsung Electronics Co., Ltd. High bandwidth memory system
US10915451B2 (en) * 2019-05-10 2021-02-09 Samsung Electronics Co., Ltd. Bandwidth boosted stacked memory
US11216385B2 (en) * 2019-05-15 2022-01-04 Samsung Electronics Co., Ltd. Application processor, system-on chip and method of operating memory management unit
EP4553663A3 (en) * 2019-12-26 2025-07-30 Micron Technology, Inc. Truth table extension for stacked memory systems
US11226816B2 (en) * 2020-02-12 2022-01-18 Samsung Electronics Co., Ltd. Systems and methods for data placement for in-memory-compute
WO2022056757A1 (en) * 2020-09-17 2022-03-24 Alibaba Group Holding Limited Three-dimensional stacked processing systems
KR20220127601A (ko) * 2021-03-11 2022-09-20 삼성전자주식회사 인터페이스를 이용하여 내부 프로세싱을 수행하는 메모리 시스템, 메모리 장치 및 메모리 장치의 동작 방법
US11901035B2 (en) * 2021-07-09 2024-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of differentiated thermal throttling of memory and system therefor
JP2023178769A (ja) 2022-06-06 2023-12-18 富士通株式会社 演算処理装置および演算処理方法
US12455824B2 (en) 2022-09-10 2025-10-28 Rambus Inc. DRAM cache with stacked, heterogenous tag and data dies
KR20240119562A (ko) * 2023-01-30 2024-08-06 삼성전자주식회사 캐시 바이패싱 동작을 수행하는 메모리 시스템 및 그것의 캐시 관리 방법

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105446900A (zh) * 2015-04-03 2016-03-30 上海兆芯集成电路有限公司 处理器和区分系统管理模式条目的方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1278125A2 (en) * 1994-10-14 2003-01-22 MIPS Technologies, Inc. Indexing and multiplexing of interleaved cache memory arrays
GB2297398B (en) * 1995-01-17 1999-11-24 Advanced Risc Mach Ltd Accessing cache memories
JPH11212868A (ja) * 1998-01-28 1999-08-06 Oki Electric Ind Co Ltd スヌープキャッシュメモリ制御システム
US8341352B2 (en) * 2007-04-17 2012-12-25 International Business Machines Corporation Checkpointed tag prefetcher
KR101728067B1 (ko) * 2010-09-03 2017-04-18 삼성전자 주식회사 반도체 메모리 장치
KR20120079682A (ko) * 2011-01-05 2012-07-13 삼성전자주식회사 디램 캐시를 포함하는 메모리 장치 및 이를 포함하는 시스템
US20120221785A1 (en) * 2011-02-28 2012-08-30 Jaewoong Chung Polymorphic Stacked DRAM Memory Architecture
US20120297256A1 (en) 2011-05-20 2012-11-22 Qualcomm Incorporated Large Ram Cache
JP6012263B2 (ja) * 2011-06-09 2016-10-25 株式会社半導体エネルギー研究所 半導体記憶装置
US9753858B2 (en) * 2011-11-30 2017-09-05 Advanced Micro Devices, Inc. DRAM cache with tags and data jointly stored in physical rows
US9189399B2 (en) * 2012-11-21 2015-11-17 Advanced Micro Devices, Inc. Stack cache management and coherence techniques
US9053039B2 (en) 2012-12-21 2015-06-09 Advanced Micro Devices, Inc. Installation cache
US9170948B2 (en) * 2012-12-23 2015-10-27 Advanced Micro Devices, Inc. Cache coherency using die-stacked memory device with logic die
US9477605B2 (en) 2013-07-11 2016-10-25 Advanced Micro Devices, Inc. Memory hierarchy using row-based compression
US9286948B2 (en) * 2013-07-15 2016-03-15 Advanced Micro Devices, Inc. Query operations for stacked-die memory device
CN104575584B (zh) 2013-10-23 2018-11-30 钰创科技股份有限公司 具有嵌入式内存的系统级封装内存模块
KR20150062646A (ko) * 2013-11-29 2015-06-08 삼성전자주식회사 전자 시스템 및 이의 동작 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105446900A (zh) * 2015-04-03 2016-03-30 上海兆芯集成电路有限公司 处理器和区分系统管理模式条目的方法

Also Published As

Publication number Publication date
KR102404643B1 (ko) 2022-06-02
TWI703440B (zh) 2020-09-01
CN107656878A (zh) 2018-02-02
US10180906B2 (en) 2019-01-15
TW201804328A (zh) 2018-02-01
US20180032437A1 (en) 2018-02-01
KR20180012180A (ko) 2018-02-05
JP2018018513A (ja) 2018-02-01

Similar Documents

Publication Publication Date Title
CN107656878B (zh) 具有内存高速缓存管理器的高带宽存储器
US11568907B2 (en) Data bus and buffer management in memory device for performing in-memory data operations
KR102665410B1 (ko) 메모리 장치의 내부 프로세싱 동작 방법
CN102084428B (zh) 多模式存储器装置和方法
EP3140749B1 (en) In-memory lightweight coherency
TWI285810B (en) Method, apparatus, and system for partitioning a shared cache of a chip multi-processor, and computer-readable recording medium having stored thereon related instructions
US8868843B2 (en) Hardware filter for tracking block presence in large caches
JP7036925B2 (ja) キャッシュ制御を考慮したメモリコントローラ
JP7108141B2 (ja) データ領域を記憶するためのキャッシュ
KR102789083B1 (ko) 집단화된 메모리 장치에 대한 메모리 요청 스케줄링
CN103597450B (zh) 具有存储在存储器页的一部分中的元数据的存储器
US20190371400A1 (en) High-performance on-module caching architectures for non-volatile dual in-line memory module (nvdimm)
TW201841119A (zh) 管理揮發性記憶體快取的方法和快取管理器
US20170091099A1 (en) Memory controller for multi-level system memory having sectored cache
US20190114264A1 (en) Memory system
US9990143B2 (en) Memory system
TW200915179A (en) Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same
US10445003B2 (en) Memory system for dualizing first memory based on operation mode
CN107783909B (zh) 一种内存地址总线扩展方法及装置
US12321291B2 (en) Memory controller, system, and method of scheduling memory access execution order based on locality information
EP4071593B1 (en) Stacked cache system based on sedram, and control method and cache device
KR20250032780A (ko) 전자 장치, 메모리 장치, 및 메모리 장치의 동작 방법
US20170109069A1 (en) Memory system

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant