TWI703440B - Memory system, processing system thereof and method for operating memory stack - Google Patents

Abstract

A system and method for using high bandwidth memory as cache memory. A high bandwidth memory may include a logic die, and, stacked on the logic die, a plurality of dynamic random access memory dies. The logic die may include a cache manager, that may interface to external systems through an external interface conforming to the JESD235A standard, and that may include an address translator, a command translator, and a tag comparator. The address translator may translate each physical address received through the external interface into a tag value, a tag address in the stack of memory dies, and a data address in the stack of memory dies. The tag comparator may determine whether a cache hit or cache miss has occurred, according to whether the tag value generated by the address translator matches the tag value stored at the tag address.

Description

Memory system, its processing system and operating memory stack Methods

This application claims the priority of the U.S. Provisional Application No. 62/367062 filed on July 26, 2016 and titled "HBM WITH IN-MEMORY CACHE MANAGER" Rights and rights, the content of the US provisional application is incorporated herein for reference in its entirety.

One or more aspects according to the embodiments of the present invention are related to high-bandwidth memory, and more specifically, to a system and method for using high-bandwidth memory as a cache memory.

High Bandwidth Memory (HBM) is a high-performance (random access memory) interface of three dimensional (3D) stacked dynamic random access memory (DRAM). The prior art system using high bandwidth memory as the cache memory may have a cache manager on the host to perform cache management functions. This configuration may It puts a burden on the host and the interface between the host and the high-bandwidth memory.

Therefore, there is a need for an improved system and method that uses high-bandwidth memory as cache memory.

Each aspect of the embodiments of the present invention relates to a system and method that uses a high-bandwidth memory as a cache memory. The high-bandwidth memory may include a logic die and a plurality of dynamic random access memory die stacked on the logic die. The logic die may include a cache manager, which may interface to an external system via an external interface compliant with the JESD235A standard and may include an address translator, a command translator, and a tag comparator. The address translator can translate each physical address received via the external interface into a tag value, a tag address in the memory die stack, and a data address in the memory die stack. The tag comparator can determine whether a cache hit or a cache miss occurs according to whether the tag value generated by the address translator matches the tag value stored at the tag address. The command generator can generate commands. For example, when receiving a write command via an external interface, the command generator can first generate a command for extracting tag values to determine whether a cache hit occurs, and if a cache hit occurs, the command generator can generate a write command.

According to an embodiment of the present invention, a memory system is provided. The memory system includes: a memory stack including a plurality of memory dies; and a logic die, the memory dies stacked on and connected to the A logic die, the logic die having an external interface that interfaces with the memory system, and the logic die includes a cache Manager.

In one embodiment, the cache manager includes an address translator configured to translate an address received via the external interface to generate: a first tag value; the memory The data address in the memory stack; and the tag address in the memory stack.

In one embodiment, the cache manager includes a command translator configured to generate in response to a read command received via the external interface: a first command for retrieving tags; and The second command used to extract data characters.

In one embodiment, the cache manager includes a tag comparator for generating a cache hit signal, the cache hit signal: when the first tag value is equal to the value obtained by executing the first command When the value of is a true value; and when the first tag value is not equal to the value obtained by executing the first command, it has a false value.

In one embodiment, the tag comparator is configured to send the cache hit signal via the first pin of the external interface.

In one embodiment, the cache manager is configured to send the value of the bad bit and/or the value of the valid bit via the second pin of the external interface.

In one embodiment, the cache manager is configured to send the cache hit signal via the first pin during a first time interval, and send via the first pin during a second interval The value of the bad bit.

In one embodiment, the cache manager is configured to Execute the first command.

In one embodiment, the cache manager includes a mode selector, the mode selector instructs to select a parallel operation mode or a serial operation mode, and the cache manager is configured to: when the mode selector When the parallel operation mode is instructed to be selected, execute the first command and the second command in parallel; and when the mode selector instructs to select the serial operation mode, execute all the commands before executing the second command. The first order.

In one embodiment, the mode selector is configured to be controlled via the external interface.

In one embodiment, for any two data characters that are stored in the first memory bank in the memory die and can be accessed through different pseudo channels, in different sub-arrays of the memory stack Two corresponding tags are stored.

In one embodiment, the external interface is configured to operate according to the Joint Electron Device Engineering Council (Joint Electron Device Engineering Council) standard JESD235A.

According to an embodiment of the present invention, there is provided a processing system including: a host processor; a first memory system connected to the host processor; and a second memory system connected to the host processor , The first memory system includes: a memory stack including a plurality of memory dies; and a logic die, the memory die being stacked on and connected to the logic die, the logic die having An external interface that interfaces with the first memory system, the logic die includes a cache manager, and the second memory system is configured to become the first memory system Backup storage.

In one embodiment, the cache manager includes an address translator configured to translate the address received from the host processor via the external interface into: a first tag value ; The data address in the memory stack; and the tag address in the memory stack.

In one embodiment, the cache manager includes a command translator configured to generate in response to a read command received from the host processor via the external interface: for retrieving tags The first command; and the second command for extracting data characters.

In one embodiment, the cache manager includes a tag comparator for generating a cache hit signal, the cache hit signal: when the first tag value is equal to the value obtained by executing the first command When the value of is a true value; and when the first tag value is not equal to the value obtained by executing the first command, it has a false value.

In one embodiment, the external interface is configured to operate according to the JESD235A standard of the Joint Electronic Device Engineering Committee.

According to an embodiment of the present invention, there is provided a method of operating a memory stack, the memory stack including a plurality of memory dies and logic dies, the memory dies are stacked on and connected to the logic dies, The logic die has an external interface that interfaces with a memory system, and the method includes: translating, by the logic die, an address received through the external interface to generate: a first tag value; the memory The data address in the memory stack; and the tag address in the memory stack.

In one embodiment, the method includes generating by the logic die in response to a read command received via the external interface: a first command for extracting tags; and a second command for extracting data characters command.

In one embodiment, the method includes generating a cache hit signal from the logic die, the cache hit signal: when the first tag value is equal to the value obtained by executing the first command , Has a true value; and when the first tag value is not equal to the value obtained by executing the first command, has a false value.

105: High bandwidth memory stack

110: Logic Die

115: dynamic random access memory stack

205: host processor

210: core

215: Level 1 cache

220: Level 2 cache

225: The first memory controller

230: Off-chip main memory

235: second memory controller

240: silicon board

245: High bandwidth memory interface

305: command and address line

310: Command translator

315: address translator

320: Tag Comparator

325: Scheduler

330: data buffer

Bk0~Bk7: memory bank

Ch0~Ch7, PCh0, PCh1: channel

Sa0~Sa14: sub-array

These and other features and advantages of the present invention will be understood and understood with reference to the specification, scope of patent application and drawings. In the drawings:

FIG. 1 is a perspective view of a high-bandwidth memory stack according to an embodiment of the invention.

2A is a block diagram of a processing system using a high-bandwidth memory stack as a 3-level cache according to an embodiment of the present invention.

FIG. 2B is a block diagram of a high-bandwidth memory stack according to an embodiment of the present invention.

FIG. 3 is a block diagram of a high-bandwidth memory stack according to an embodiment of the invention.

Fig. 4A is a storage diagram according to an embodiment of the present invention.

Figure 4B is a storage diagram according to an embodiment of the present invention.

The following detailed description with reference to the accompanying drawings is intended to serve as an exemplary embodiment of a high-bandwidth memory with an in-memory cache manager provided by the present invention The description is not intended to represent the only form in which the invention can be conceived or utilized. This description presents the features of the invention in conjunction with the illustrated embodiment. However, it should be understood that the same or equivalent functions and structures can be achieved by different embodiments that are also intended to be included in the spirit and scope of the present invention. As indicated elsewhere herein, the same element numbers are intended to represent the same elements or features.

High-bandwidth memory (HBM) is a high-performance three-dimensional (3D) stacked dynamic random access memory RAM (DRAM). The second-generation high-bandwidth memory can include up to 8 dies per stack and provide pin transfer rates of up to 2 giga transfers per second (GT/s). The interface can include 8 channels, each of which is 128 bits wide to achieve a total of 1024 bits wide access. The second-generation high-bandwidth memory can reach a memory bandwidth of 256 billion bits per second (GB/s) per package, and can have a storage capacity of up to 8 billion bits per package. The interface of the second-generation high-bandwidth memory can be based on the standard accepted by the Joint Electronic Device Engineering Committee (JEDEC), which is the standard JESD235A.

1, the physical configuration of the high-bandwidth memory stack 105 can include logic die 110 and three-dimensional dynamic random access memory or "dynamic random access memory stack" 115, three-dimensional dynamic random access memory or "dynamic random access memory" 115 The "memory stack" 115 includes a plurality of dynamic random access memory dies (for example, 8 such dies) stacked on top of the logic die 110. A through-silicon via (TSV) is used to form interconnects in the stack. The prior art high-bandwidth memory stacked in the logic die can include connecting lines and signal conditioning circuitry, thereby providing a high-speed bandwidth to the external interface of the high-bandwidth memory. The host processor provides a dynamic random access memory channel interface that does not change substantially.

2A, the high-bandwidth memory stack 105 may be connected to the host processor 205 (for example, a central processing unit (CPU) or a graphics processing unit (GPU)). The host processor 205 may include a plurality of cores 210, each of which has its own level 1 cache 215. The level 2 cache 220 may be connected to the level 1 cache 215, and the first memory controller 225 may Provides an interface for off-chip main memory 230. The second memory controller 235 can provide an interface with the high-bandwidth memory stack 105. The high bandwidth memory stack 105 may include a cache manager (CM) in the logic die of the high bandwidth memory stack 105. The host processor 205 can use the high-bandwidth memory stack 105 and the integrated cache manager of the high-bandwidth memory stack 105 as a level 3 cache (or, for example, as a level 4 cache in a system that also has a level 3 cache) . The high-bandwidth memory interface 245 can be an interface compliant with JESD235A, that is, the high-bandwidth memory interface 245 can provide a conductor and a signal protocol specified by JESD235A.

2B, in some embodiments, the high-bandwidth memory stack 105 may include logic die 110, and the logic die 110 may pass through eight internal interfaces (referred to as channels, and are shown as Ch0 to Ch7 in FIG. 2B). ) Connected to the dynamic random access memory in the dynamic random access memory stack 115.

3, in one embodiment, the high-bandwidth memory stack 105 includes a dynamic random access memory stack 115 and a logic die 110 as described above, and the logic die The pellet 110 may include multiple components for implementing a cache manager. The command and address lines 305 in the high-bandwidth memory interface 245 can be connected to the command translator 310 and the address translator 315 in the logic die 110 of the high-bandwidth memory stack 105. For each of the 8 channels of the high bandwidth memory interface 245, the command and address lines 305 may include, for example, 6 column command/address lines and 8 row command/address lines.

In operation, the address translator 315 may periodically receive the physical memory address of the command to be executed (for example, a read command or a write command). The address translator 315 can then translate the address into a tag value, a tag address, and a data address. The tag value can be used to determine whether a "cache hit" has occurred, that is, whether the address in the cache is currently allocated to the address received through the high-bandwidth memory interface 245. For example, the cache manager can read (or "extract") the tag value at the tag address and compare it with the tag value generated by the address translator 315 (for example, using the following detailed description Tag comparator 320). If the tag value formed by the received physical address (by the address translator 315) matches the tag value stored at the tag address in the dynamic random access memory stack 115, a cache hit has occurred, That is, the address in the cache is currently allocated to the receiving address in the physical memory space of the processor. If the tag value formed by the received physical address does not match the tag value stored at the tag address in the dynamic random access memory stack 115 (this is referred to as a "cache miss" situation), The address in the cache is currently not allocated to the receiving address in the physical memory space of the processor.

The tag comparator 320 can be used for comparison, that is, to compare the tag value formed by the received physical address with the tag value stored at the tag address. The output of the tag comparator 320 may be a signal called a cache hit signal, which has a true value (for example, a binary value of 1) when a cache hit occurs, and a false value when a cache miss occurs ( For example, the binary value 0).

The command translator 310 can generate a command to be executed on the dynamic random access memory stack 115 in response to the command received through the high-bandwidth memory interface 245. For example, if the command received via the high-bandwidth memory interface 245 is a read command, the command translator 310 can generate a command for reading the data characters stored at the data address and for reading the data stored in the tag The command of the tag value at the address. Each of these commands may include multiple micro-operations (for example, composed of multiple micro-operations), for example, the read command may include an activation operation after the read operation.

If the command received via the high-bandwidth memory interface 245 is a write command, the command translator 310 can first generate a command for reading the tag stored at the tag address, and if the tag value is the same as that generated by the address translator 315 If the tag value of is matched, a write command for writing data to the dynamic random access memory stack 115 can then be generated. In this way, the logic die 110 includes a cache manager so that the second command (write command) can be generated in the logic die 110 instead of the host processor 205, so that the host processor 205 does not need to implement a cache manager, which will increase efficiency.

The extraction of tag values and data can be performed in parallel or serially. For example, when the cache manager operates in parallel mode, the tag value and data can be extracted in parallel, and the extracted tag value can be compared by the tag comparator 320 with the tag value generated by the address translator 315, and If the two tag values match, you can record The memory interface 245 returns the read data. Otherwise, a cache miss signal can be sent to the host processor 205 via the high bandwidth memory interface 245, as discussed in more detail below. When the cache manager operates in serial mode, the tag value can be extracted first, and the extracted tag value can be compared by the tag comparator 320 with the tag value generated by the address translator 315, and if the two tag values If it matches, the data can be extracted and returned via the high-bandwidth memory interface 245. Otherwise, a cache miss signal can be sent to the host processor 205 via the high-bandwidth memory interface 245. The operation of the serial mode can be more energy-efficient than the operation of the parallel mode, because in the serial mode, the data extraction operation is only executed in the case of a cache hit. The operation of the parallel mode can be faster than the operation of the serial mode, because in the parallel mode, the label value extraction and the data extraction can be executed simultaneously. The cache manager may include a mode selector (for example, a bit in the control register), and the mode selector may control whether the cache manager operates in parallel mode or serial mode. The mode selector can be controlled by the high-bandwidth memory interface 245 (for example, by the host processor 205), for example, by a command for writing a new value to the control register.

The cache manager can use each tag to store two-digit metadata: (i) a bit indicating whether the corresponding data character is valid or invalid ("valid bit"), and (ii) indicating the corresponding data Whether the character is a bad bit ("bad bit"). If the data in the cache has been updated, but the corresponding data in the backup storage has not been updated, the data in the cache is considered bad (and otherwise not bad), and if the data in the backup storage has been If the corresponding data in the cache is updated but not updated, the data in the cache is deemed invalid (and otherwise valid).

In addition, the command received via the high-bandwidth memory interface 245 can obtain the true value or the false value of the cache hit signal (corresponding to the cache hit or the cache miss respectively) as described above. Upon completion of any command received by the high-bandwidth memory stack 105 via the high-bandwidth memory interface 245, the cache manager can generate three values. The three values are the cache hit signal, the bad bit, and the valid bit. The value of yuan. These values can use one or more pins of the high-bandwidth memory interface 245 that are not used for other functions (for example, neither of (i) any of the 212 pins of each of the eight channels, It is not (ii) any one of the RESET pin, TEMP[2:0] pin, or CATTRIP pin) to be transmitted to the host processor 205 via the high-bandwidth memory interface 245. The pins that are reserved for future use (pins that are reserved for future use, RFU pins) defined by the JESD235A standard can be used. For example, in one embodiment, the pins reserved for future use are used to transmit the cache hit signal during the first data cycle of the data burst after the command is executed, and in the next data burst During the data cycle, the value of the bad bit is transmitted. The sending of the cache hit signal and bad bits can be carried out simultaneously with the sending of the data of the data burst. In some embodiments, multiple pins reserved for future use are used to transmit cache hit signals, bad bits, and/or valid bits.

In order to invalidate the data in the cache, the host processor 205 can send the "failure" signal along with the address of the data to be invalidated to the logic die 110 via the high-bandwidth memory interface 245. The "failure" signal can be sent through the same pin of the high-bandwidth memory interface 245 that is used to send the cache hit signal to the host processor 205 (for example, a pin reserved for future use). Address can pass through high bandwidth memory The command/address (Command/Address) bus of the interface 245 is sent. Using this information, the logic die 110 can then update the corresponding valid bits stored in the dynamic random access memory stack 115.

In some embodiments, pins reserved for future use are also used to maintain cache coherency, for example, to maintain backup memory (for example, off-chip main memory 230) and multi-core systems (for example, The coherence between the caches in the system shown in Figure 2A). In the system shown in Figure 2A, the three-level cache (which is implemented in the high-bandwidth memory stack 105) and the backing memory can be achieved by Each of the cores 210 performs reading and/or modification.

The scheduler 325 in the logic die 110 can receive commands and addresses from the command translator 310 and the address translator 315, respectively, and schedule the execution of these commands on the dynamic random access memory stack 115 . The data buffer 330 in the logic die 110 can be used to temporarily store data after the data is received through the high-bandwidth memory interface 245 and/or after the data is read from the dynamic random access memory stack 115. Both the scheduler 325 and the data buffer 330 can help adapt to changes in rate when performing the following operations: (i) receiving commands via the high-bandwidth memory interface 245; (ii) executing commands on the dynamic random access memory stack 115 (Iii) Send or receive data via the high-bandwidth memory interface 245; and (iv) Read data from the dynamic random access memory stack 115 or write data to the dynamic random access memory stack 115.

The JESD235A standard provides a pseudo-channel mode of operation, in which each of the eight 128-bit channels is used as two semi-independent pseudo channels (semi-independent pseudo channel) operation. In this mode, each pair of pseudo channels share the channel's column and row command bus and CK and CKE input terminals, but the two pseudo channels independently decode commands and execute them. In some embodiments, this mode is used to store tag values. Each tag value can be 32-bit characters, so that the entire 128-bit wide data bus ("DQ" bus) of the channel in use can read or write tag values from the dynamic random access memory stack 115 Entering into the dynamic random access memory stack 115 will cause significant inefficiency (for example, 25% efficiency). In the pseudo channel mode, only half of the bus width (ie, 64 bits) can be used to read or write the tag value, thereby obtaining a higher efficiency (eg, 50%).

Each memory bank (Memory Bank Bk0~Memory Bank Bk7) of the dynamic random access memory may include 16 sub-arrays (that is, composed of 16 sub-arrays). 4A, in some embodiments, each data character can be 64 bytes (512 bits) long, and each tag value can be 4 bytes (32 bits) long, or That is, the ratio of the length of the data character to the length of the tag value may be 16:1. The tag value and data can be accessed through different channels; for example, the data can be accessed via channel 1 to channel 15 (channel PCh1), and the tag value can be accessed via channel 0 (channel PCh0). In this embodiment, data can be accessed in parallel, but tag access may experience memory conflicts, as shown by the dashed oval. Therefore, referring to FIG. 4B, in one embodiment, tags are stored in different sub-arrays Sa0~Sa14, and the sub-arrays can be paralleled using a method called subarray level parallelism (SALP) herein. To access. In this embodiment, All tag accesses can be processed at the same time, that is, tag access conflicts can be avoided even when accessing the same memory bank.

In view of the foregoing, compared to the prior art high-bandwidth memory stack without a cache manager, the high-bandwidth memory stack 105 including a cache manager in the logic die 110 may have several advantages. Using a high-bandwidth memory stack 105 that includes a cache manager can eliminate the need to include a cache manager in the host processor 205, which can potentially reduce the size of the host processor, reduce the cost and power consumption of the host processor, or The same resources can be used for other purposes in the host processor 205. In addition, compared to when the conditional execution involves the host processor 205, such conditional execution may be faster when executed entirely in the high-bandwidth memory stack 105. For example, in the cache hit event, compared with the cache hit determination in the cache manager in the host processor 205, when the cache hit determination is performed in the high-bandwidth memory stack 105, write Commands can be executed more quickly.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, These elements, components, regions, layers and/or sections should not be restricted by these terms. These terms are only used to distinguish individual elements, components, regions, layers or sections. Therefore, the first element, component, region, layer or section discussed below may be referred to as a second element, component, region, layer or section, which does not depart from the spirit and scope of the concept of the present invention.

For ease of explanation, for example, "beneath", "below", "lower", "under" can be used in this article , "Above", "upper" and other spatial relative terms Explain the relationship between one element or feature shown in the drawings and another or other elements or features. It should be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the figure. For example, if the device in the drawing is turned over, then elements described as being located "below" or "below" or "below" other elements or features can now be oriented to be located at the other elements or features. Above". Therefore, the exemplary terms "below" and "below" can cover both orientations of above and below. The device can be in other orientations (for example, rotated by 90 degrees or in other orientations) and the description of the spatial relationship used herein should be explained accordingly. In addition, it should also be understood that when a layer is referred to as being "between two layers," it can be the only layer between the two layers, or one or more intermediate layers may also be present.

The terms used herein are only for the purpose of describing specific embodiments, and are not intended to limit the concept of the present invention. The terms "substantially", "about" and similar terms used in this article are used as approximate terms, not as terms of degree, and are intended to take into account the measurement values that those with ordinary knowledge in this technology would know Or the inherent deviation of the calculated value. The term "main component" used herein means a component that constitutes at least half of the composition by weight, and when applied to multiple items, the term "main component" means at least half of the items.

Unless the context clearly indicates otherwise, the singular form "一 (a and an)" used herein is intended to also include the plural form. It should be understood that when the term "comprises (comprises and/or comprising)" is used in this specification, it refers to the existence of the stated features, integers, steps, operations, elements and/or components, but does not exclude one or more Other features, integers, steps, operations, elements, components and/ Or the existence or addition of its group. The term "and/or" as used herein includes any and all combinations of one or more of the related listed items. When an expression such as "at least one of" appears before a series of elements, it modifies the entire series of elements, but does not modify individual elements in the series. In addition, the use of "may" when describing embodiments of the concept of the present invention refers to "one or more embodiments of the present invention." In addition, the term "exemplary" is intended to refer to an example or illustration. The terms “use”, “using” and “used” used in this article can be regarded as the terms “utilize”, “utilizing” and “utilized” respectively. )" is synonymous.

It should be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to” or “adjacent to” another element or layer In the case of an element or layer, the element or layer may be directly on, directly connected to, directly coupled to, or directly adjacent to the other element or layer, or there may be one or more intervening elements Elements or layers. In contrast, when a component or layer is called “directly on”, “directly connected to”, “directly coupled to” or “directly on (immediately adjacent to)" When another element or layer, there is no intermediate element or layer.

Any numerical range described herein is intended to include all sub-ranges of the same numerical precision that fall within the stated range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the minimum value 1.0 and the maximum value 10.0 (and including the minimum value 1.0 and the maximum value 10.0). That is, have equal or greater A minimum value of 1.0 and a maximum value of 10.0 or less, such as (for example) 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits subsumed therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits subsumed therein.

Although an exemplary embodiment of a high-bandwidth memory with an in-memory cache manager has been specifically illustrated and described in this article, many modifications and changes will be obvious to those familiar with the art. Therefore, it should be understood that the high-bandwidth memory with an in-memory cache manager conceived according to the principles of the present invention can be implemented in other ways than those specifically described herein. The present invention is also defined in the scope of the following patent applications and their equivalent scope.

105: High bandwidth memory stack

110: Logic Die

115: dynamic random access memory stack

Claims (20)

A memory system includes: a memory stack, including a plurality of memory die; and a logic die, the memory die stacked on and connected to the logic die, the logic die having a host processing An external interface interfaced by a device, the logical die includes a cache manager configured to: translate an address received as part of a command via the external interface to generate: a first tag value And a tag address, extracting a second tag value from a position corresponding to the tag address in the memory stack, comparing the first tag value with the second tag value, and based on the first The comparison of the tag value and the second tag value executes the command. The memory system according to claim 1, wherein the cache manager includes an address translator configured to translate the address received via the external interface To generate: the first tag value; the data address in the memory stack; and the tag address in the memory stack. The memory system according to claim 2, wherein the cache manager includes a command translator, and the command translator is configured to generate in response to a read command received via the external interface: A first command for extracting the second tag value; and a second command for extracting data characters. The memory system described in item 3 of the scope of application, wherein the cache manager includes a tag comparator for generating a cache hit signal, the cache hit signal: when the first tag value is equal to all When the second tag value, it has a true value; and when the first tag value is not equal to the second tag value, it has a false value. The memory system according to claim 4, wherein the tag comparator is configured to send the cache hit signal via the first pin of the external interface. The memory system of claim 5, wherein the cache manager is configured to send the value of the bad bit and/or the value of the valid bit via the second pin of the external interface. The memory system of claim 5, wherein the cache manager is configured to send the cache hit signal via the first pin during a first interval of time, and in the second interval During the interval, the value of the bad bit is sent via the first pin. The memory system described in claim 3, wherein the cache manager is configured to execute the first command via a pseudo channel. As described in item 3 of the scope of patent application, wherein the cache manager includes a mode selector, the mode selector instructs to select the parallel operation mode or the serial operation mode, and the cache manager It is configured to: when the mode selector instructs to select the parallel operation mode, execute the first command and the second command in parallel; and when the mode selector instructs to select the serial operation mode Execute the first command before executing the second command. The memory system described in claim 9, wherein the mode selector is configured to be controlled via the external interface. The memory system described in the first item of the patent application, wherein for any two data characters stored in the first memory bank in the memory die and accessible through different pseudo channels, Two corresponding tags are stored in different sub-arrays of the memory stack. The memory system described in the first item of the patent application, wherein the external interface is configured to operate in accordance with the JESD235A standard of the Joint Electronic Device Engineering Committee. A processing system comprising: a host processor; a first memory system connected to the host processor; and a second memory system connected to the host processor, the first memory system comprising: memory Stack, including multiple memory die; and A logic die, the memory die is stacked on and connected to the logic die, the logic die has an external interface that interfaces with the host processor, the logic die includes a cache manager, The cache manager is configured to: translate the address received as part of the command via the external interface to generate: a first tag value; and a tag address from the memory stack and the tag bit Extracting a second tag value from a location corresponding to the address, comparing the first tag value with the second tag value, and executing the command based on the comparison between the first tag value and the second tag value, the The second memory system is configured as a backup storage for the first memory system. The processing system according to claim 13, wherein the cache manager includes an address translator configured to transfer all data received from the host processor via the external interface The address is translated to generate: the first tag value; the data address in the memory stack; and the tag address in the memory stack. The processing system according to claim 14, wherein the cache manager includes a command translator configured to respond to reads received from the host processor via the external interface The commands are generated: a first command for extracting the second tag value; and a second command for extracting data characters. According to the processing system described in claim 15, wherein the cache manager includes a tag comparator for generating a cache hit signal, the cache hit signal: when the first tag value is equal to the When the second tag value, it has a true value; and when the first tag value is not equal to the second tag value, it has a false value. The processing system described in claim 13, wherein the external interface is configured to operate according to the JESD235A standard of the Joint Electronic Device Engineering Committee. A method for operating a memory stack, the memory stack includes a plurality of memory dies and logic dies, the memory dies are stacked on and connected to the logic dies, the logic dies have and An external interface interfaced by a host processor, and the method includes: translating, by the logic die, an address of a part received as a command via the external interface to generate: a first tag value; the memory stack The data address of; and the label address in the memory stack; Extracting a second tag value from a position in the memory stack corresponding to the tag address; comparing the first tag value with the second tag value; and based on the first tag value and the first tag value The comparison of the two tag values executes the command. According to the method described in item 18 of the scope of the patent application, the logic die is generated in response to the read command received via the external interface: a first command for extracting the second tag value; and The second command used to extract data characters. The method described in item 19 of the scope of patent application further includes generating a cache hit signal from the logic die, the cache hit signal: when the first tag value is equal to the second tag value, True value; and when the first tag value is not equal to the second tag value, it has a false value.

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