TWI702733B - Mounting method of light-emitting element - Google Patents
Mounting method of light-emitting element Download PDFInfo
- Publication number
- TWI702733B TWI702733B TW105128175A TW105128175A TWI702733B TW I702733 B TWI702733 B TW I702733B TW 105128175 A TW105128175 A TW 105128175A TW 105128175 A TW105128175 A TW 105128175A TW I702733 B TWI702733 B TW I702733B
- Authority
- TW
- Taiwan
- Prior art keywords
- light
- layer
- emitting element
- substrate
- mounting
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 160
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 239000000463 material Substances 0.000 claims abstract description 28
- 239000013078 crystal Substances 0.000 claims description 17
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 3
- 238000003780 insertion Methods 0.000 claims 1
- 230000037431 insertion Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 192
- 238000005530 etching Methods 0.000 description 53
- 238000007788 roughening Methods 0.000 description 30
- 235000012431 wafers Nutrition 0.000 description 29
- 230000000052 comparative effect Effects 0.000 description 23
- 238000011282 treatment Methods 0.000 description 20
- 230000006378 damage Effects 0.000 description 18
- 230000005496 eutectics Effects 0.000 description 15
- 239000002184 metal Substances 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 14
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 12
- 239000010408 film Substances 0.000 description 12
- 230000001681 protective effect Effects 0.000 description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 239000010931 gold Substances 0.000 description 9
- 239000000243 solution Substances 0.000 description 9
- 239000000203 mixture Substances 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005253 cladding Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 239000011259 mixed solution Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000011630 iodine Substances 0.000 description 2
- 229910052740 iodine Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 101100365087 Arabidopsis thaliana SCRA gene Proteins 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000007522 mineralic acids Chemical class 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
- Led Device Packages (AREA)
Abstract
一種發光元件的安裝方法,係於起始基板上,以起始基板相晶格匹配 系材料,藉由磊晶成長依序形成第一半導體層、活性層、第二半導體層及緩衝層;於緩衝層上,以對於起始基板為非晶格匹配系材料,藉由磊晶成長形成窗層兼支承基板;去除起始基板;於第一半導體層上形成第一歐姆電極;於部分形成露出第二半導體層、緩衝層或窗層兼支承基板的除去部而設置段差;於除去部形成第二歐姆電極;分離形成有第一及第二歐姆電極的發光元件而製作發光元件晶片,以及於安裝基板覆晶安裝發光元件晶片,使發光元件晶片的形成第一及第二歐姆電極側為安裝基板側。 A method for mounting light-emitting elements on a starting substrate, with the starting substrate phase lattice matching The first semiconductor layer, the active layer, the second semiconductor layer, and the buffer layer are sequentially formed by epitaxial growth; on the buffer layer, the non-lattice-matched material for the starting substrate is formed by epitaxial growth Forming the window layer and supporting substrate; removing the starting substrate; forming the first ohmic electrode on the first semiconductor layer; forming part of the exposed second semiconductor layer, buffer layer or window layer and supporting substrate to remove the part to set the step; Part forms the second ohmic electrode; separates the light-emitting element formed with the first and second ohmic electrodes to produce a light-emitting element chip, and flip-chip mounts the light-emitting element chip on the mounting substrate to form the first and second ohmic electrodes on the light-emitting element chip The side is the mounting board side.
Description
本發明係關於發光元件的安裝方法,特別是關於將發光元件晶片予以覆晶安裝於安裝基板的發光元件的安裝方法。 The present invention relates to a mounting method of a light-emitting element, and particularly relates to a mounting method of a light-emitting element in which a light-emitting element chip is flip-chip mounted on a mounting substrate.
Chip On Board(COB)等的製品,在LED元件的散熱性係為優異,因而在照明等的用途之中係為被採用的一種LED晶片安裝方法。在COB等安裝LED的情況下,將晶片直接接合於板子的覆晶安裝係為必須。在覆晶安裝LED元件的情況下,有藉由超音波的Au-Au接合、共晶焊接等的方法。 Products such as Chip On Board (COB) are excellent in the heat dissipation of LED elements, so they are an LED chip mounting method used in lighting and other applications. In the case of mounting LEDs such as COB, a flip-chip mounting system that directly bonds the chip to the board is necessary. In the case of flip-chip mounting of LED components, there are methods such as Au-Au bonding by ultrasonic waves and eutectic soldering.
在藉由黃色至紅色LED而製作覆晶安裝晶片的情況下,於發光層係使用AlGaInP系的材料。由於AlGaInP系材料並未存在晶塊,並且藉由磊晶法形成LED部的緣故,起始基板則被選擇為與AlGaInP為相異的材料。起始基板多半為選擇GaAs或Ge的情況,由於這些基板對可見光具有光吸收的特性的緣故,在製作覆晶安裝晶片的情況下會去除起始基板。 In the case of fabricating flip-chip mounted chips using yellow to red LEDs, AlGaInP-based materials are used for the light-emitting layer. Since there is no crystal block in AlGaInP-based materials and the LED part is formed by epitaxial method, the starting substrate is selected as a different material from AlGaInP. The starting substrate is mostly selected as GaAs or Ge. Because these substrates have light absorption characteristics for visible light, the starting substrate will be removed when fabricating flip-chip mounted chips.
然而,由於形成發光層的磊晶層係為極薄膜的緣故,在去除起始基板後而無法獨立而存。因此,必須以具有在發光層對發光波長為略透明而作為窗層的功能,並且具有作為用於獨立而存而有充分厚度的支承基板的功能的材料、構造,而置換起始基板。 However, since the epitaxial layer forming the light-emitting layer is an extremely thin film, it cannot survive independently after removing the starting substrate. Therefore, it is necessary to replace the starting substrate with a material and structure that has a function as a window layer when the light-emitting layer is slightly transparent to the emission wavelength, and has a function as a supporting substrate for independent existence and a sufficient thickness.
如同前述,由於AlGaInP系材料並未存在有晶塊的緣故,作為具有前述的窗層兼支承基板的功能的材料,會選擇GaP、GaAsP及藍寶石等。無論 選擇其中哪一種的材料,也由於與AlGaInP為相異的緣故,熱膨脹係數或楊氏模量等的機械特性與AlGaInP系為相異。 As mentioned above, since there is no crystal block in AlGaInP-based materials, GaP, GaAsP, sapphire, etc. are selected as the material having the function of the aforementioned window layer and supporting substrate. regardless Which of these materials is selected is also different from AlGaInP, and mechanical properties such as thermal expansion coefficient and Young's modulus are different from AlGaInP.
藉由超音波的Au-Au接合,如一非專利文獻1所記載,有難以將晶片不傾斜地支承,並有無法效率佳地對晶片傳播超音波,以及有在超音波傳播時晶片會破損等問題。
With the ultrasonic Au-Au bonding, as described in a
為了解決以上的問題,形成AuSn共晶凸塊,並且藉由熱熔融(回流焊溫度211~280℃)而進行與基板的接合的技術已被揭示。共晶方式與超音波方式相比,難以引起伴隨超音波的物理的破壞。但是,共晶焊接的熔融、固化的過程中,共晶金屬本身會熱收縮。其結果,在共晶金屬與LED相接的半導體側交界面附近會發生應力,此應力會引起晶片破壞而造成問題。 In order to solve the above problems, the technique of forming AuSn eutectic bumps and performing bonding with the substrate by thermal melting (reflow temperature 211~280°C) has been disclosed. Compared with the ultrasonic method, the eutectic method is less likely to cause physical damage accompanying the ultrasonic wave. However, during the melting and solidification process of eutectic welding, the eutectic metal itself will heat shrink. As a result, stress occurs in the vicinity of the semiconductor-side interface where the eutectic metal and the LED are in contact, and this stress can cause damage to the wafer and cause problems.
再者,窗層兼支承基板的材料與AlGaInP發光層的材料差異所引起的熱膨脹係數的差異,也會使由於上述的熱熔融步驟所導致的問題變大。亦即,對於AlGaInP系材料的線膨脹係數5.4E-6[/k],GaP的線膨脹係數為4.5E-6[/k],藍寶石的線膨脹係數為7.0E-6[/k]。因此,在藉由熱熔融處理而安裝的情況,窗層兼支承基板為GaP的情況下,於AlGaInP發光層發生壓縮應力,於窗層兼支承基板發生拉扯應力。窗層兼支承基板為藍寶石的情況,於AlGaInP發光層發生拉扯應力,於窗層兼支承基板發生壓縮應力。此應力也會引起晶片破壞。 Furthermore, the difference in thermal expansion coefficient caused by the difference between the material of the window layer and supporting substrate and the material of the AlGaInP light-emitting layer will also increase the problems caused by the above-mentioned thermal melting step. That is, the linear expansion coefficient of AlGaInP-based materials is 5.4E-6[/k], the linear expansion coefficient of GaP is 4.5E-6[/k], and the linear expansion coefficient of sapphire is 7.0E-6[/k]. Therefore, in the case of mounting by thermal fusion treatment, when the window layer and supporting substrate is GaP, compressive stress occurs in the AlGaInP light-emitting layer, and tensile stress occurs in the window layer and supporting substrate. When the window layer and support substrate is sapphire, tensile stress occurs in the AlGaInP light-emitting layer, and compressive stress occurs in the window layer and support substrate. This stress can also cause wafer damage.
覆晶安裝時,形成於發光元件晶片的第一以及第二歐姆電極側的表面會壓迫安裝基板側。此時,雖然由於發光元件晶片的壓迫,使安裝表面側的金屬部變形的緣故,發光元件晶片會沉入安裝表面側,但是此變形不大。因此,在設置於安裝表面的發光元件晶片上的第一歐姆電極及第二歐姆電極的段 差大的情況下,相接於安裝表面的第一歐姆電極的金屬的變形量不足,雖然第一歐姆電極表面充分地接觸於安裝表面,但是會發生第二歐姆電極表面未接觸於安裝表面的現象。結果會發生短路,如此則會有無法安裝的問題。因此,一般而言,是於第一歐姆電極以及第二歐姆電極上設置凸塊而使在電極的變形量增加。但是,凸塊係必須使用鍍金法等將Au(金)等而厚厚地形成,材料費會變得非常地昂貴。 During flip chip mounting, the surfaces formed on the first and second ohmic electrode sides of the light-emitting element chip will press the mounting substrate side. At this time, although the light-emitting element chip sinks into the mounting surface side due to the deformation of the metal portion on the mounting surface side due to the pressure of the light-emitting element chip, the deformation is not large. Therefore, the section of the first ohmic electrode and the second ohmic electrode on the light-emitting element chip disposed on the mounting surface In the case of a large difference, the amount of deformation of the metal of the first ohmic electrode connected to the mounting surface is insufficient. Although the surface of the first ohmic electrode fully contacts the mounting surface, it may happen that the surface of the second ohmic electrode does not contact the mounting surface. phenomenon. As a result, there will be a short circuit, so there will be a problem that it cannot be installed. Therefore, generally speaking, bumps are provided on the first ohmic electrode and the second ohmic electrode to increase the deformation of the electrode. However, the bump system must be thickly formed of Au (gold) using a gold plating method or the like, and the material cost becomes very expensive.
〔非專利文獻1〕日經Electronics,日經BP社,2008年02月11日號 [Non-Patent Document 1] Nikkei Electronics, Nikkei BP, February 11, 2008
鑒於如同前述的問題,本發明係提供一種發光元件的安裝方法,能抑制伴隨著使用超音波的覆晶安裝的破損,以及能抑制在使用共晶焊接的覆晶安裝之中由於熱收縮所導致的應力破壞,更進一步,即使在第一歐姆電極與第二歐姆電極的段差為大的情況下,也能容易地進行發光元件晶片的安裝。 In view of the above-mentioned problems, the present invention provides a method for mounting light-emitting elements that can suppress the damage accompanying the use of ultrasonic flip-chip mounting, and can suppress the heat shrinkage caused by the flip-chip mounting using eutectic soldering Furthermore, even when the step difference between the first ohmic electrode and the second ohmic electrode is large, the light-emitting element chip can be easily mounted.
為了達成上述的目的,藉由本發明而提供一種發光元件的安裝方法,包含下列步驟:於起始基板上,以與該起始基板相晶格匹配系的材料,藉由磊晶成長而成長,依序形成第一半導體層、活性層、第二半導體層以及緩衝層;於該緩衝層之上,以對於該起始基板為非晶格匹配系的材料,藉由磊晶成 長而形成窗層兼支承基板;去除該起始基板;於該第一半導體層之上形成第一歐姆電極;於部分形成使該第二半導體層、該緩衝層或是該窗層兼支承基板露出的除去部而設置段差;於該除去部形成第二歐姆電極;將經形成有該第一及第二歐姆電極的發光元件予以分離而製作發光元件晶片,以及於該安裝基板覆晶安裝該發光元件晶片,而使該發光元件晶片的經形成有該第一及第二歐姆電極之側成為安裝基板側。 In order to achieve the above-mentioned object, the present invention provides a method for mounting a light-emitting element, which includes the following steps: on a starting substrate, growing by epitaxial growth with a material that is lattice-matched to the starting substrate, A first semiconductor layer, an active layer, a second semiconductor layer, and a buffer layer are sequentially formed; on the buffer layer, a material that is non-lattice-matched to the starting substrate is formed by epitaxy Long and forming a window layer and supporting substrate; removing the starting substrate; forming a first ohmic electrode on the first semiconductor layer; forming part of the second semiconductor layer, the buffer layer or the window layer and supporting substrate The exposed removal part is provided with a step; a second ohmic electrode is formed in the removed part; the light-emitting element formed with the first and second ohmic electrodes is separated to produce a light-emitting element chip, and the flip chip is mounted on the mounting substrate The light-emitting element wafer is formed on the side on which the first and second ohmic electrodes are formed as the mounting substrate side.
如此一來,藉由以磊晶成長形成窗層兼支承基板而於窗層兼支承基板插入大量的差排的緣故,在超音波安裝時,受到對晶片施加壓力的應力時,藉由窗層兼支承基板會沿著差排面而變形,而能抑制晶片的應力破壞。再者,在利用共晶金屬的覆晶安裝之中,在由於加熱的膨脹,回到室溫時的收縮之中,藉由窗層兼支承基板會沿著差排面而變形,而能抑制晶片的應力破壞。更進一步,即使有第一歐姆電極與第二歐姆電極的段差為大的情況,也能防止覆晶安裝時的發光元件的破損,並且容易地進行發光元件晶片的安裝。 In this way, by forming the window layer and support substrate by epitaxial growth, a large number of rows are inserted into the window layer and support substrate. When ultrasonic mounting is subjected to stress that applies pressure to the chip, the window layer The supporting substrate is deformed along the differential surface, which can suppress the stress damage of the wafer. Furthermore, in flip-chip mounting using eutectic metal, the window layer and support substrate will deform along the differential surface due to the expansion due to heating and the shrinkage when returning to room temperature, which can suppress Stress failure of the wafer. Furthermore, even if the level difference between the first ohmic electrode and the second ohmic electrode is large, it is possible to prevent damage to the light-emitting element during flip-chip mounting, and to easily mount the light-emitting element chip.
此時,該第一半導體層、該活性層及該第二半導體層為AlGaInP或是AlGaAs為佳。 At this time, the first semiconductor layer, the active layer, and the second semiconductor layer are preferably AlGaInP or AlGaAs.
如此一來,作為第一半導體層、活性層及第二半導體層,能合適地使用如同上述的材料。 In this way, as the first semiconductor layer, the active layer, and the second semiconductor layer, the materials described above can be suitably used.
再者此時,該窗層兼支承基板為GaP或是GaAsP為佳。 In addition, at this time, the window layer and supporting substrate are preferably GaP or GaAsP.
如此一來,作為窗層兼支承基板,使用如同上述的材料,作為窗層係為合適的同時,能確實地於覆晶安裝時抑制晶片的應力破壞。 In this way, as the window layer and supporting substrate, the same material as described above is used, which is suitable as the window layer system and can reliably suppress the stress breakage of the wafer during flip chip mounting.
再者此時,該第一歐姆電極與該第二歐姆電極的段差能為3μm以上11μm以下。 Furthermore, at this time, the step difference between the first ohmic electrode and the second ohmic electrode can be 3 μm or more and 11 μm or less.
如此一來,第一歐姆電極與第二歐姆電極的段差即使如上述般大,也能充分地發揮效果。 In this way, even if the step difference between the first ohmic electrode and the second ohmic electrode is large as described above, the effect can be fully exerted.
本發明的發光元件的安裝方法,藉由以磊晶成長形成窗層兼支承基板而於窗層兼支承基板插入大量的差排的緣故,在超音波安裝時,受到對晶片施加壓力的應力時,藉由窗層兼支承基板會沿著差排面而變形,而能抑制晶片的應力破壞,在利用共晶金屬的覆晶安裝之中,在由於加熱的膨脹,回到室溫時的收縮之中,藉由窗層兼支承基板會沿著差排面而變形,而能抑制晶片的應力破壞。更進一步,即使有第一歐姆電極與第二歐姆電極的段差為大的情況,也能防止覆晶安裝時的發光元件的破損,並且容易地進行發光元件晶片的安裝。 The mounting method of the light-emitting element of the present invention, by forming the window layer and support substrate by epitaxial growth and inserting a large number of rows into the window layer and support substrate, when ultrasonic mounting is subjected to stress that applies pressure to the chip Because the window layer and supporting substrate deform along the differential surface, the stress damage of the chip can be suppressed. In the flip chip mounting using eutectic metal, the expansion due to heating shrinks when returning to room temperature Among them, since the window layer and supporting substrate deform along the differential surface, stress damage of the chip can be suppressed. Furthermore, even if the level difference between the first ohmic electrode and the second ohmic electrode is large, it is possible to prevent damage to the light-emitting element during flip-chip mounting, and to easily mount the light-emitting element chip.
1:發光元件晶片 1: Light-emitting element chip
11:發光元件晶片 11: Light-emitting component chip
101:起始基板 101: starting substrate
102:選擇蝕刻層 102: Select etching layer
102A:第二選擇蝕刻層 102A: second choice etching layer
102B:第一選擇蝕刻層 102B: First choice etching layer
103:第一半導體層 103: The first semiconductor layer
103A:低Al組成層 103A: Low Al composition layer
103B:高Al組成層 103B: High Al composition layer
104:活性層 104: active layer
105:第二半導體層 105: second semiconductor layer
106:緩衝層 106: buffer layer
107:窗層兼支承基板 107: Window layer and supporting substrate
108:發光部 108: light-emitting part
109:磊晶基板 109: Epitaxy substrate
110:發光元件基板 110: Light-emitting element substrate
121:第一歐姆電極 121: first ohm electrode
122:第二歐姆電極 122: second ohm electrode
122a:預定範圍 122a: predetermined range
123:光阻遮罩 123: photoresist mask
140:範圍 140: range
141:形成部 141: Formation Department
142:刻劃範圍 142: Scribe range
150:絕緣保護膜 150: insulating protective film
170:除去部 170: removal part
180:非除去部 180: Non-removal part
201:發光元件晶片 201: light-emitting element chip
301:起始基板 301: Starting substrate
302:選擇蝕刻層 302: Select etching layer
302A:第二選擇蝕刻層 302A: second selective etching layer
302B:第一選擇蝕刻層 302B: First choice etching layer
303:第一半導體層 303: The first semiconductor layer
304:活性層 304: active layer
305:第二半導體層 305: second semiconductor layer
306:緩衝層 306: buffer layer
307:電流擴散層 307: Current Diffusion Layer
308:發光部 308: Light-emitting part
309:磊晶基板 309: Epitaxy substrate
310:GaP單結晶基板 310: GaP single crystal substrate
311:發光元件基板 311: Light-emitting element substrate
321:第一歐姆電極 321: first ohm electrode
322:第二歐姆電極 322: second ohm electrode
340:範圍 340: range
342:刻劃範圍 342: Scribe Range
350:絕緣保護膜 350: insulating protective film
380:非除去部 380: Non-removal part
第1圖係顯示本發明的發光元件的安裝方法的一範例的步驟圖。 Fig. 1 is a step diagram showing an example of the mounting method of the light-emitting element of the present invention.
第2圖係顯示本發明的發光元件的安裝方法的於起始基板上成長有選擇蝕刻層、發光部及窗層兼支承基板的磊晶基板的概略圖。 Fig. 2 is a schematic diagram of an epitaxial substrate having a selective etching layer, a light emitting portion, and a window layer and supporting substrate grown on a starting substrate in the method for mounting a light emitting element of the present invention.
第3圖係顯示本發明的發光元件的安裝方法的自磊晶基板去除起始基板以及第二選擇蝕刻層的發光元件基板的概略圖。 FIG. 3 is a schematic view of the light-emitting element substrate in which the starting substrate and the second selective etching layer are removed from the epitaxial substrate in the method of mounting a light-emitting element of the present invention.
第4圖係顯示本發明的發光元件的安裝方法的形成有第一歐姆電極的發光元件基板的概略圖。 Fig. 4 is a schematic view of a light-emitting element substrate on which a first ohmic electrode is formed in the method of mounting a light-emitting element of the present invention.
第5圖係顯示本發明的發光元件的安裝方法的已進行第一表面粗糙化處理的發光元件基板的概略圖。 Fig. 5 is a schematic view of a light-emitting element substrate that has been subjected to the first surface roughening treatment in the light-emitting element mounting method of the present invention.
第6圖係顯示本發明的發光元件的安裝方法的已進行除去部、段差形成步驟的發光元件基板的概略圖。 Fig. 6 is a schematic view of the light-emitting element substrate on which the removed portion and step formation step of the light-emitting element mounting method of the present invention have been performed.
第7圖係顯示本發明的發光元件的安裝方法的形成有第二歐姆電極並且形成有絕緣保護膜的發光元件基板的概略圖。 Fig. 7 is a schematic view of a light-emitting element substrate on which a second ohmic electrode is formed and an insulating protective film is formed in the light-emitting element mounting method of the present invention.
第8圖係顯示本發明的發光元件的安裝方法的分離發光元件而製作的發光元件晶片的概略圖。 Fig. 8 is a schematic diagram showing a light-emitting element wafer produced by separating light-emitting elements in the method of mounting a light-emitting element of the present invention.
第9圖係實施例的已進行第一表面粗糙化處理的發光元件基板的概略圖。 Fig. 9 is a schematic diagram of a light-emitting element substrate subjected to the first surface roughening treatment according to the embodiment.
第10圖係顯示實施例的已進行除去部、段差形成步驟的發光元件基板的概略圖。 Fig. 10 is a schematic view showing the light-emitting element substrate on which the step of forming the removed portion and the step of the embodiment has been performed.
第11圖係顯示實施例的形成有第二歐姆電極並且形成有絕緣保護膜的發光元件基板的概略圖。 Fig. 11 is a schematic diagram showing a light-emitting element substrate on which a second ohmic electrode is formed and an insulating protective film is formed according to the embodiment.
第12圖係顯示實施例的分離發光元件而製作的發光元件晶片的概略圖。 Fig. 12 is a schematic diagram showing a light-emitting element wafer produced by separating the light-emitting elements of the example.
第13圖係顯示比較例的於起始基板上成長有選擇蝕刻層、發光部及窗層兼支承基板的磊晶基板的概略圖。 FIG. 13 is a schematic view showing an epitaxial substrate in which a selective etching layer, a light-emitting portion, and a window layer and supporting substrate are grown on the starting substrate of the comparative example.
第14圖係顯示比較例的於磊晶基板接合GaP單結晶基板的基板的概略圖。 Fig. 14 is a schematic diagram showing a substrate in which a GaP single crystal substrate is bonded to an epitaxial substrate of a comparative example.
第15圖係顯示比較例的自磊晶基板去除起始基板以及第二選擇蝕刻層的接合基板的概略圖。 FIG. 15 is a schematic diagram showing the bonding substrate in which the starting substrate and the second selective etching layer are removed from the epitaxial substrate of the comparative example.
第16圖係顯示比較例的形成有第一歐姆電極的接合基板的概略圖。 Fig. 16 is a schematic view showing the bonded substrate on which the first ohmic electrode is formed in the comparative example.
第17圖係顯示比較例的已進行第一表面粗糙化處理的接合基板的概略圖。 Fig. 17 is a schematic diagram showing the bonded substrate on which the first surface roughening treatment has been performed in the comparative example.
第18圖係顯示比較例的已進行除去部、段差形成步驟、形成有第二歐姆電極的接合基板的概略圖。 Fig. 18 is a schematic view showing the bonded substrate on which the removed portion, the step forming step, and the second ohmic electrode are formed in the comparative example.
第19圖係顯示比較例的形成有絕緣保護膜的接合基板的概略圖。 Fig. 19 is a schematic view showing a bonded substrate on which an insulating protective film is formed in a comparative example.
第20圖係顯示比較例的分離發光元件而製作的發光元件晶片的概略圖。 Fig. 20 is a schematic diagram showing a light-emitting element wafer prepared by separating the light-emitting elements of the comparative example.
第21圖係顯示實施例以及比較例的使用超音波進行安裝時的不良發生率的圖。 Fig. 21 is a graph showing the incidence of defects when mounting using ultrasonic waves in Examples and Comparative Examples.
第22圖係顯示實施例以及比較例的使用共晶金屬層進行安裝時的不良發生率的圖。 Fig. 22 is a graph showing the incidence of defects when mounting using a eutectic metal layer in Examples and Comparative Examples.
第23圖係顯示實施例以及比較例的第一歐姆電極與第二歐姆電極的段差變化時的與直通率的關係的圖。 Fig. 23 is a graph showing the relationship between the first ohmic electrode and the second ohmic electrode in the example and the comparative example when the step difference is changed.
以下,對本發明的實施例進行說明,但是本發明並非限定於此。 Hereinafter, examples of the present invention will be described, but the present invention is not limited to these.
如同上述,於覆晶安裝時,存在引起發光元件晶片的破壞的問題。於此,本發明人們為了解決如此的問題而努力地研究。結果發現,藉由對於起始基板以非晶格匹配系的材料磊晶成長窗層兼支承基板,而發現於窗層兼支承基板插入有許多的差排。藉此發現,能抑制在超音波安裝時以及利用共晶金屬的覆晶安裝之中晶片的破壞,更進一步,即使在第一歐姆電極與第二歐姆電極的段差大的情況下,也能在防止覆晶安裝時的發光元件的破損的同時,容易地進行發光元件晶片的安裝。 As mentioned above, there is a problem of causing damage to the light-emitting device chip during flip-chip mounting. Herein, the inventors of the present invention have studied diligently to solve such problems. As a result, it was found that by epitaxially growing the window layer and support substrate with a non-lattice-matched material for the starting substrate, it was discovered that there are many gaps inserted in the window layer and support substrate. It was found that it is possible to suppress the destruction of the chip during ultrasonic mounting and flip-chip mounting using eutectic metal. Furthermore, even when the step difference between the first ohmic electrode and the second ohmic electrode is large, it can be While preventing the damage of the light-emitting element during flip-chip mounting, the light-emitting element chip is easily mounted.
以下,關於本發明的發光元件的安裝方法,參考第1圖至第8圖而進行說明。 Hereinafter, the mounting method of the light-emitting element of the present invention will be described with reference to FIGS. 1 to 8.
首先,準備如第2圖所示的起始基板101(第1圖的SP1)。
First, the starting
作為起始基板101,使用結晶軸為〔001〕方向往〔110〕方向傾斜的起始基板101為佳。再者,作為起始基板101,能合適地使用GaAs或是Ge。如此一來,由於能將後述的活性層104的材料以晶格匹配系進行磊晶成長的緣故,而能易於提升活性層104的品質,得到亮度上升或壽命特性的提升。
As the starting
接下來,亦可於起始基板101之上形成選擇蝕刻層102(第1圖的SP2)。選擇蝕刻層102係於起始基板101之上,能藉由例如MOVPE法(有機金屬氣相成長法)、MBE(分子線磊晶法)或CBE(化學線磊晶法)而成長。
Next, a selective etching layer 102 (SP2 in FIG. 1) may also be formed on the starting
選擇蝕刻層102係自二層以上的層構造構成,至少具有相接於起始基板101的第二選擇蝕刻層102A及相接於後述的第一半導體層103的第一選擇蝕刻層102B為佳。第二選擇蝕刻層102A及第一選擇蝕刻層102B係自相異的材料或是組成所構成為佳。
The
接下來,於起始基板101,藉由磊晶成長而成長,依序形成由第一導電型的第一半導體層103、活性層104及第二導電型的第二半導體層105所構成的發光部108以及緩衝層106(第1圖的SP3)。
Next, on the starting
第一半導體層103、活性層104以及第二半導體層105為AlGaInP或是AlGaAs為佳。如此,能合適地使用如同上述的材料而作為第一半導體層、活性層以及第二半導體層。
The
再者,以InGaP形成緩衝層106為佳。
Furthermore, it is better to form the
為了提升第一半導體層103或是第二半導體層105的特性,而於各層內包含有複數層係為一般,自不待言,第一半導體層103或是第二半導體層105也並非限定於單一層。
In order to improve the characteristics of the
此時,第一半導體層103可為二層以上的構造所構成。第一半導體層103的後述的實施表面粗糙化處理之側的低Al組成層103A,相比於活性層側的高Al組成層103B,能藉由Al組成較少的材料所構成者而形成。
At this time, the
如此一來,維持包覆層的載體侷限效果的同時,抑制由於過度蝕刻所導致的焊墊電極的機械強度的下降以及在引線接合時發生的晶片破損,而能製造得到所求凹凸大小的粗糙面的發光元件。 In this way, while maintaining the carrier limitation effect of the cladding layer, the decrease in the mechanical strength of the pad electrode due to over-etching and the chip breakage during wire bonding can be suppressed, and the roughness of the required unevenness can be manufactured. Surface of the light-emitting element.
接下來,於緩衝層106之上,對於起始基板101,以非晶格匹配系的材料,藉由磊晶成長而形成窗層兼支承基板107,而製作磊晶基板109(第1圖的SP4)。
Next, on the
作為窗層兼支承基板107,以GaP或者是GaAsP為佳。
As the window layer and supporting
接下來,自磊晶基板109去除起始基板101以及第二選擇蝕刻層102A,如同第3圖所示,於發光元件基板110的第一半導體層103的表面僅殘留第一選擇蝕刻層102B(第1圖的SP5)。
Next, the starting
具體而言,自磊晶基板109,透過使用第二選擇蝕刻層102A並且藉由濕式蝕刻法而去除起始基板101,而能於第一半導體層103的表面僅殘留第一選擇蝕刻層102B。
Specifically, from the
接下來,如第4圖所示,於第一半導體層103上的第一選擇蝕刻層102B的表面,將為了對發光元件供給電位的第一歐姆電極121予以形成(第1圖的SP6)。
Next, as shown in FIG. 4, on the surface of the first
接下來,如第4圖所示,去除第一歐姆電極121的底部以外的範圍的第一選擇蝕刻層102B(第1圖的SP7)。
Next, as shown in FIG. 4, the first
具體而言,將第一歐姆電極121作為蝕刻遮罩,而能藉由蝕刻去除第一歐姆電極121的底部以外的範圍的第一選擇蝕刻層102B。
Specifically, using the first
接下來,如第5圖所示,能進行第一表面粗糙化處理步驟,而將第一半導體層103的表面上的第一歐姆電極121的形成部以外的至少一部份予以表面粗糙化(第1圖的SP8)。
Next, as shown in FIG. 5, a first surface roughening treatment step can be performed, and at least a part of the surface of the
具體而言,例如能藉由無機酸與有機酸的混合液所構成的第一表面粗糙液,而於除了第一半導體層103的表面上的第一歐姆電極121的形成部的部分進行第一表面粗糙化處理。
Specifically, for example, a first surface roughening solution composed of a mixture of inorganic acid and organic acid can be used to perform the first surface roughening solution on the surface of the
接下來,如第6圖所示,進行於部分形成使第二半導體層、緩衝層或是窗層兼支承基板露出的除去部170而設置段差的步驟(除去部、段差形成步驟,第1圖的SP9)。如第6圖所示,於除去部170及其以外的非除去部180之間設置段差。
Next, as shown in FIG. 6, a step of forming a step (removed portion, step forming step, step 1) is performed to partially form the removed
具體而言,例如能藉由材料選擇性低的ICP乾式蝕刻法,而自範圍140的第一半導體層至窗層兼支承基板的一部份進行蝕刻。如此一來,能形成如第6圖所示的已露出窗層兼支承基板107的部分(除去部170)。除去部170係繼承以第一表面粗糙化處理步驟所形成的表面粗糙圖案的緣故,而具有表面粗糙圖案。
Specifically, for example, the ICP dry etching method with low material selectivity can be used to etch from the first semiconductor layer in the
接下來,如第7圖所示,於除去部170的窗層兼支承基板107的表面上形成第二歐姆電極122(第1圖的SP10)。
Next, as shown in FIG. 7, the second ohmic electrode 122 (SP10 in FIG. 1) is formed on the surface of the window layer and supporting
如此一來,第一歐姆電極121與第二歐姆電極122之間係具有段差而被形成。在本發明之中,例如,第一歐姆電極121與第二歐姆電極122的段差能為3μm以上且11μm以下。如此一來,即使第一歐姆電極與第二歐姆電極的段差大,亦如同後述,能在防止覆晶安裝時的發光元件的破損的同時,容易地進行發光元件晶片的安裝。
In this way, the first
接下來,如第7圖所示,能藉由絕緣保護膜150而覆蓋第一半導體層103的表面以及發光部108的側面的至少一部份(第1圖的SP11)。
Next, as shown in FIG. 7, at least a part of the surface of the
若為透明並且具有絕緣性的材料,絕緣保護膜150可為任一種材料。作為絕緣保護膜150,使用例如SiO或是SiNx係為合適。若為如此者,藉由光微影法及含有氟酸的蝕刻液,而能容易地於第一歐姆電極121以及第二歐姆電極122的頂部進行開口的加工。
If it is a transparent and insulating material, the insulating
接下來,進行將形成有第一以及第二歐姆電極121、122的發光元件予以分離而製作發光元件晶片的步驟(第1圖的SP12)。
Next, a step of separating the light-emitting element formed with the first and second
具體而言,能沿著刻劃範圍142(參考第7圖)而刻劃刻劃線,藉由進行裂片(breaking)而分離發光元件,而製作發光元件晶片1(晶粒)。 Specifically, the scribe line can be scribed along the scribe area 142 (refer to FIG. 7), and the light-emitting element can be separated by breaking, thereby fabricating the light-emitting element chip 1 (die).
接下來,如第8圖所示,能藉由第二表面粗糙液進行第二表面粗糙化處理步驟,而將窗層兼支承基板107的側面以及反面予以表面粗糙化。
Next, as shown in FIG. 8, the second surface roughening treatment step can be performed by the second surface roughening liquid, so that the side surface and the back surface of the window layer and supporting
另外,由於藉由第二表面粗糙化處理而使發光角度擴大的緣故,在不想讓發光角度擴大的情況下不進行處理亦可。 In addition, since the light-emitting angle is expanded by the second surface roughening treatment, the treatment may not be performed if the light-emitting angle is not desired to be expanded.
接下來,進行於該安裝基板覆晶安裝該發光元件晶片的步驟(第1圖的SP14),而使該發光元件晶片1的經形成有該第一及第二歐姆電極之側成為安裝基板(未圖示)之側。
Next, the step of flip-chip mounting the light-emitting element chip on the mounting substrate (SP14 in Fig. 1) is performed so that the side of the light-emitting
在上述的覆晶安裝步驟(SP14)之中,在第一實施方式之中,對安裝基板(安裝板)的晶固後,能藉由超音波接合而進行覆晶安裝。此時,第一歐姆電極的安裝接合部係設置於晶片邊緣部。 In the above-mentioned flip-chip mounting step (SP14), in the first embodiment, after the mounting substrate (mounting board) is crystal-fixed, the flip-chip mounting can be performed by ultrasonic bonding. At this time, the mounting joint portion of the first ohmic electrode is provided at the edge of the wafer.
在第一實施方式之中,在超音波安裝時,由於超音波傳播係在滑動面(貫穿差排面)以外的單結晶部傳播的緣故,有效率地進行之外,一方面也在自頂部壓住晶片時,窗層兼支承基板部會容易沿著滑動面變形的緣故,而不易破損。 In the first embodiment, during the ultrasonic installation, because the ultrasonic propagation system propagates in the single crystal part other than the sliding surface (through the differential surface), in addition to being efficiently performed, it is also from the top When the wafer is pressed, the window layer and supporting substrate are easily deformed along the sliding surface and are not easily damaged.
在上述的覆晶安裝步驟(SP14)之中,在第二實施方式之中,作為於第一歐姆電極上以及第二歐姆電極上更進一步積層共晶金屬的構造,晶粒接合後,能藉由透過加熱、冷卻處理而進行覆晶安裝。 In the above-mentioned flip chip mounting step (SP14), in the second embodiment, as a structure in which eutectic metal is further laminated on the first ohmic electrode and the second ohmic electrode, after die bonding, it can be used Flip-chip mounting is performed through heating and cooling treatments.
於第一歐姆電極上以及第二歐姆電極上具有低熔點的AuSn等的共晶焊接層,窗層兼支承基板為具有高密度的貫穿差排的覆晶晶片構造。在第二實施方式之中,共晶焊接的熱收縮時,雖然於窗層兼支承基板施加拉扯應力,但是由於具有滑動面(貫穿差排面),而比單結晶變形更大的緣故,應力並未集中,而能迴避晶片破損。 The first ohmic electrode and the second ohmic electrode have eutectic solder layers such as AuSn with a low melting point, and the window layer and supporting substrate have a flip-chip structure with high-density through-difference rows. In the second embodiment, during the thermal contraction of the eutectic welding, although tensile stress is applied to the window layer and support substrate, it has a sliding surface (penetrating the differential row surface), which is larger than the single crystal deformation. It is not concentrated, but can avoid chip damage.
如此一來,藉由以對於起始基板之非晶格整合系的材料而磊晶成長窗層兼支承基板,而於窗層兼支承基板插入大量的差排(差排密度10個/cm2以上)。藉由使窗層兼支承基板具有高密度的差排,在利用超音波的覆晶安裝時(第一實施方式),受到對晶片施加壓力的應力時,藉由窗層兼支承基板會沿著差排面變形,而能抑制晶片的破損。再者,在利用共晶金屬的覆晶安裝(第二實施方式)之中,在由於加熱的膨脹,回復至室溫時的收縮之中,藉由窗層兼支承基板會沿著差排面變形,而能抑制晶片的破損。 In this way, by epitaxially growing the window layer and supporting substrate with a non-lattice-integrated material for the starting substrate, a large number of differential rows are inserted into the window layer and supporting substrate (the differential row density is 10/cm 2 the above). By making the window layer and supporting substrate have high-density differential rows, during flip-chip mounting using ultrasonic waves (first embodiment), when stress is applied to the chip, the window layer and supporting substrate will follow The differential surface is deformed, and the breakage of the wafer can be suppressed. Furthermore, in the flip-chip mounting using eutectic metal (the second embodiment), due to the expansion of heating and the shrinkage when returning to room temperature, the window layer and supporting substrate will follow the differential surface Deformation can suppress chip breakage.
更進一步,如同本發明形成除去部而設置段差的緣故,即使在第一歐姆電極與第二歐姆電極的段差大的情況下,於覆晶安裝時的發光元件晶片壓迫時,由於發光元件晶片會變形的緣故,而能防止覆晶安裝時的發光元件的破損。特別是窗層兼支承基板具有滑動面的緣故,而對於發光元件晶片壓迫會容易變形,而於第一歐姆電極121接觸於安裝面的同時,第二歐姆電極122也接觸於安裝面的緣故,在覆晶安裝中不一定需要凸塊。藉此,能容易地進行發光元件晶片的安裝。
Furthermore, as in the present invention, the step difference is provided when the removed portion is formed. Even when the step difference between the first ohmic electrode and the second ohmic electrode is large, when the light-emitting element chip is pressed during flip-chip mounting, the light-emitting element chip will Due to the deformation, it is possible to prevent damage to the light-emitting element during flip-chip mounting. In particular, because the window layer and supporting substrate has a sliding surface, it is easy to deform when pressed against the light-emitting element chip. While the first
具體而言,第一歐姆電極與第二歐姆電極的段差如同上述,能為3μm以上11μm以下。如此一來,即使第一歐姆電極與第二歐姆電極的段差大,本發明也能充分地發揮功效。 Specifically, the step difference between the first ohmic electrode and the second ohmic electrode can be 3 μm or more and 11 μm or less as described above. In this way, even if the step difference between the first ohmic electrode and the second ohmic electrode is large, the present invention can fully exert its effect.
以下表示本發明的實施例以及比較例而更具體地說明本發明,但是本發明並非限定於此。 Examples and comparative examples of the present invention are shown below to explain the present invention more specifically, but the present invention is not limited to these.
於自結晶軸〔001〕方向向〔110〕方向傾斜15°的厚度280μm的n型GaAs所構成的起始基板101上,藉由MOVPE法(有機金屬氣相成長法)將n型GaAs緩衝層(未圖示)成長為0.5μm、由n型AlInP層所構成的第二選擇蝕刻層102A成長為1μm,以及由n型GaAs層所構成的第一選擇蝕刻層102B成長為1μm後,將以AlGaInP所構成的n型包覆層(第一半導體層103)、活性層104及p型包覆層(第二半導體層105)所構成的發光部108予以形成出5.5μm,於其之上,將由p型GaInP所構成的緩衝層106形成出0.3μm,將由p型Gap所構成的窗層兼支承基板107的一
部分予以成長1.0μm。接下來,移送至HVPE爐,將自p型GaP所構成的窗層兼支承基板107成長120μm,而得到磊晶基板109(參考第2圖)。
On a starting
接下來,自磊晶基板109,將起始基板101、GaAs緩衝層及第二選擇蝕刻層102A予以蝕刻去除,而製作僅殘留第一選擇蝕刻層102B的發光元件基板110(參考第3圖)。具體而言,自磊晶基板109,將第二選擇蝕刻層102A作為選擇蝕刻層,利用濕式蝕刻法去除起始基板101,而成為發光元件基板110。
Next, from the
接下來,將係為對發光元件的電位供給用電極的第一歐姆電極121予以形成。具體而言,如第4圖所示,於發光元件基板110的第一選擇蝕刻層102B上形成第一歐姆電極121。然後,將第一歐姆電極121作為遮罩,藉由蝕刻而將第一歐姆電極121以外的範圍的第一選擇蝕刻層102B予以去除。
Next, the first
接下來,如第9圖所示,藉由光微影法,於第二歐姆電極形成預定範圍122a設置光阻遮罩123,藉由第一表面粗糙液,進行第一表面粗糙化處理。第一表面粗糙液係以醋酸及鹽酸的混合液製作,藉由在常溫下蝕刻1分鐘而進行表面粗糙化。
Next, as shown in FIG. 9, by photolithography, a
接下來,藉由光微影法,在範圍140(參考第9圖)形成已開口的圖案,藉由含有鹽酸氣體的ICP電漿蝕刻法而實施除去部、段差形成步驟,去除發光部108以及緩衝層106,而形成露出窗層兼支承基板107的去除部170以及其外的非除去部180(參考第10圖)。此時,雖然除去部170繼承有在第一表面粗糙化處理步驟中所形成的表面粗糙圖案,第二歐姆電極的形成部141的部分,並未在第一表面粗糙化處理步驟中形成粗糙面,並未成為表面粗糙圖案而形成為平坦的表面。
Next, by photolithography, an open pattern is formed in the area 140 (refer to FIG. 9), and the step of removing the portion and step formation is performed by the ICP plasma etching method containing hydrochloric acid gas to remove the light-emitting
接下來,於第10圖的第二歐姆電極的形成部141形成第二歐姆電極122(參考第11圖)。接下來,積層由SiO2所構成的絕緣保護膜150,而將覆蓋第一半導體層103表面以及發光部108的側面的由SiO2所構成的絕緣保護膜150予以形成。
Next, the second
接下來,沿著刻劃範圍142刻劃刻劃線,沿著刻劃線將裂紋線予以延伸,之後藉由進行裂片而分離元件,而形成發光元件晶片11。
Next, a scribe line is scribed along the
發光元件晶片11形成後,於支承膠帶轉印發光元件晶片11而使設置有第一歐姆電極121的表面為膠帶面之側,之後,藉由第二表面粗糙液,而實施表面粗糙化窗層兼支承基板107的側面以及背面的第二表面粗糙化處理步驟(參考第12圖)。作為第二表面粗糙液,製作醋酸、氟酸及碘的混合液。然後,藉由在常溫下1分鐘的蝕刻而進行第二表面粗糙化處理。
After the light-emitting
於自結晶軸〔001〕方向向〔110〕方向傾斜15°的厚度280μm的n型GaAs所構成的起始基板301上,藉由MOVPE法將n型GaAs緩衝層(未圖示)成長為0.5μm、由n型AlInP層所構成的第二選擇蝕刻層302A成長為1μm,以及由n型GaAs層所構成的第一選擇蝕刻層302B成長為1μm後,於此具有第二選擇蝕刻層302A及第一選擇蝕刻層302B的選擇蝕刻層302上,將以AlGaInP所構成的n型包覆層(第一半導體層303)、活性層304及p型包覆層(第二半導體層305)所構成的發光部308予以形成出5.5μm,於其之上,將由p型GaInP所構成的緩衝層306形成出0.3μm,藉由將電流擴散層307予以磊晶成長1.0μm,而製作磊晶基板309(參考第13圖)。
On a starting
接下來,如第14圖所示,於磊晶基板309接合厚度為300μm的GaP單結晶基板310。於磊晶晶版309與GaP單結晶基板310的接合,以鹼系的溶液洗淨磊晶基板309及GaP單結晶基板310兩者,利用BCB黏著劑而接合。
Next, as shown in FIG. 14, a GaP
接下來,自磊晶基板309,將起始基板301、GaAs緩衝層及第二選擇蝕刻層302A予以蝕刻去除,而製作僅殘留第一選擇蝕刻層302B的發光元件基板311(參考第15圖)。具體而言,自磊晶基板309,將第二選擇蝕刻層302A作為選擇蝕刻層,利用濕式蝕刻法去除起始基板301,而成為發光元件基板311。
Next, from the
接下來,將係為對發光元件的電位供給用電極的第一歐姆電極321予以形成。具體而言,如第16圖所示,於接合基板311的第一選擇蝕刻層302B上形成第一歐姆電極321。然後,將第一歐姆電極321作為遮罩,藉由蝕刻而將第一歐姆電極321以外的範圍的第一選擇蝕刻層302B予以去除。
Next, the first
接下來,如第17圖所示,藉由第一表面粗糙液,進行第一表面粗糙化處理。第一表面粗糙液係以醋酸及鹽酸的混合液製作,藉由在常溫下蝕刻1分鐘而進行表面粗糙化。 Next, as shown in FIG. 17, the first surface roughening liquid is used to perform the first surface roughening treatment. The first surface roughening solution is made of a mixed solution of acetic acid and hydrochloric acid, and the surface is roughened by etching at room temperature for 1 minute.
接下來,藉由光微影法,在範圍340(參考第17圖)形成已開口的圖案,藉由含有鹽酸氣體的ICP電漿蝕刻法而實施除去部、段差形成步驟,蝕刻範圍340,而形成露出電流擴散層307以及其外的非除去部380(參考第18圖)。
Next, by the photolithography method, an opened pattern is formed in the area 340 (refer to FIG. 17), and the step of removing the part and the step is performed by the ICP plasma etching method containing hydrochloric acid gas, and the
接下來,如第18圖所示,形成第二歐姆電極322。接下來,如第19圖所示,積層由SiO2所構成的絕緣保護膜350,而形成覆蓋第一半導體層303表面以及發光部308的側面的由SiO2所構成的絕緣保護膜350。
Next, as shown in FIG. 18, the second
接下來,沿著刻劃範圍342(參考第19圖)刻劃刻劃線,沿著刻劃線將裂紋線予以延伸,之後藉由進行裂片而分離元件,如第20圖所示,形成發光元件晶片201。
Next, scribe the scribe line along the scribe area 342 (refer to Figure 19), extend the crack line along the scribe line, and then separate the elements by splitting, as shown in Figure 20, to form a light emitting
發光元件晶片201形成後,於支承膠帶轉印發光元件晶片201而使設置有第一歐姆電極321的表面為膠帶面之側,之後,藉由第二表面粗糙液,而實施表面粗糙化GaP單結晶基板310的側面以及背面的第二表面粗糙化處理步驟(參考第20圖)。作為第二表面粗糙液,製作醋酸、氟酸及碘的混合液。然後,藉由在常溫下1分鐘的蝕刻而進行第二表面粗糙化處理。
After the light-emitting
將實施例以及比較例所製造的發光元件晶片,各100個分別進行Au-Au超音波安裝,並且將進行比較的結果表示於第21圖。在比較例之中,被認為是原因的晶片壓黏或是超音波印加時的震動所導致的破損會發生,不良率上升。另一方面,在實施例之中,相比於比較例,起因於同樣原因的晶片破損的發生率較少。 100 of the light-emitting element wafers manufactured in the Examples and Comparative Examples were respectively subjected to Au-Au ultrasonic mounting, and the results of the comparison are shown in FIG. 21. In the comparative example, damage caused by the wafer pressure bonding or the vibration during ultrasonic printing, which is considered to be the cause, occurs, and the defect rate increases. On the other hand, in the examples, compared with the comparative examples, the occurrence rate of wafer breakage due to the same reason is less.
接下來,將實施例以及比較例所製造的發光元件晶片,各100個分別於電極上以及安裝基板上設置AuSn層,進行熱熔融(220℃以上)而進行安裝,並且將進行比較的結果表示於第22圖。在比較例以及實施例之中,被認為是起因為熱熔融後的AuSn的熱收縮的破損雖然會發生,但是如第22圖所示,相比於比較例,實施例的破損率為少。 Next, 100 of the light-emitting element wafers manufactured in the Examples and Comparative Examples were each provided with an AuSn layer on the electrode and on the mounting substrate, and then thermally melted (above 220°C) to mount, and the results of comparison were shown In Figure 22. In the comparative examples and the examples, it is considered that the damage due to the thermal shrinkage of AuSn after thermal fusion occurs, but as shown in Fig. 22, the damage rate of the examples is smaller than that of the comparative example.
在實施例之中,由於窗層兼支承基板107係藉由磊晶成長而形成的緣故,在600~800℃程度的溫度範圍形成。線膨脹係數,相較於GaP,AlGaInP為更大,於成長後降溫至室溫時,由於膨脹係數差異,對於基板除去面,會發生凹形狀的翹曲。再者,於AlGaInP/GaP之間,晶格定數差存在3.7%,此晶格定
數差也會使翹曲增大。另一方面,由於晶格定數差,而於窗層兼支承基板存在高密度的差排。如此一來,於實施例的窗層兼支承基板具有高密度的貫穿差排。由於差排面具有在施加外力於結晶時發生滑動的特性的緣故,振動或壓黏時的應力施加於結晶時,於破壞結晶前,藉由結晶沿著滑動面滑動,而避開安裝時的應力,其結果,能想到晶片破損率會低下。
In the embodiment, since the window layer and supporting
另一方面,在比較例之中,雖然線膨脹差異所導致的與實施例相同的翹曲會發生,但是接合溫度為350℃,相較於實施例的情況係較低溫的緣故,相較於實施例,翹曲為1/10以下。 On the other hand, in the comparative example, although the warpage caused by the difference in linear expansion is the same as that of the example, the bonding temperature is 350°C, which is lower than the case of the example. In the examples, the warpage is 1/10 or less.
接下來,在實施例以及比較例之中,將第一歐姆電極與第二歐姆電極的段差予以變化而製造發光元件晶片,在製造的發光元件晶片並未設置凸塊,而進行覆晶安裝時的生產率的測定。於第23圖表示此結果。在第23圖之中,橫軸作為實施例以及比較例的第一歐姆電極與第二歐姆電極的段差,縱軸則表示為在安裝時能安裝完成的晶片數的生產率。 Next, in the examples and comparative examples, the step difference between the first ohmic electrode and the second ohmic electrode is changed to manufacture a light-emitting element chip. When the manufactured light-emitting element chip is not provided with bumps, and when flip chip mounting is performed Determination of productivity. This result is shown in Figure 23. In Fig. 23, the horizontal axis represents the step difference between the first ohmic electrode and the second ohmic electrode of the examples and comparative examples, and the vertical axis represents the productivity of the number of wafers that can be mounted during mounting.
覆晶安裝時,發光元件晶片會對安裝面壓迫。由於發光元件晶片的壓迫,安裝面之側的金屬部會變形的緣故,雖然發光元件晶片會沉入安裝面之側,但是此變形不大。因此,在比較例之中,如第23圖所示,若設置於安裝面的發光元件晶片上的第一歐姆電極321與第二歐姆電極322的段差為3μm以上,接觸於安裝面的第一歐姆電極321的金屬的變形量不足,雖然第一歐姆電極321表面充分地接觸安裝面,但是第二歐姆電極322會發生未接觸安裝面的現象。此結果會導致短路,而無法安裝。因此,為了使在電極的變形量變大,一般而言,會於第一歐姆電極321以及第二歐姆電極322上設置凸塊。但是,凸塊必須使用鍍金法等將Au(金)等有厚厚地形成,材料費會變得非常地高昂。
During flip-chip mounting, the light-emitting element chip will be pressed against the mounting surface. Due to the pressure of the light-emitting element chip, the metal part on the side of the mounting surface may be deformed. Although the light-emitting element chip may sink to the side of the mounting surface, the deformation is not large. Therefore, in the comparative example, as shown in FIG. 23, if the level difference between the first
另一方面,在實施例之中,窗層兼支承基板具有滑動面,作為其結果,形狀係為可變而發揮另外的功效。具體而言,於覆晶安裝時的發光元件晶片壓迫時,由於發光元件晶片會變形的緣故,在覆晶安裝之中不一定必須要凸塊。亦即,由於窗層兼支承基板具有滑動面的緣故,對於發光元件晶片壓迫會容易變形,第一歐姆電極121接觸於安裝面的同時,第二歐姆電極122也接觸於安裝面。由於第一歐姆電極121以及第二歐姆電極122兩者會接觸於安裝面的緣故,而能藉由超音波接合法等,在安裝面與電極之間形成堅固的接合。因此,如第23圖所示,實施例的第一歐姆電極與第二歐姆電極的段差即使在3μm以上11μm以下的範圍之中,也能不使用高價的凸塊,進行生產率良好的覆晶安裝。
On the other hand, in the embodiment, the window layer and supporting substrate has a sliding surface, and as a result, the shape is variable to exert another effect. Specifically, when the light-emitting element chip is pressed during flip-chip mounting, because the light-emitting element chip is deformed, bumps are not necessary in flip-chip mounting. That is, because the window layer and support substrate have a sliding surface, the light-emitting element chip is easily deformed by pressing, and when the first
此外,本發明並不限定於上述的實施例。上述實施例為舉例說明,凡具有與本發明的申請專利範圍所記載之技術思想實質上同樣之構成,產生相同的功效者,不論為何物皆包含在本發明的技術範圍內。 In addition, the present invention is not limited to the above-mentioned embodiment. The above-mentioned embodiments are examples. Anything that has substantially the same structure as the technical idea described in the scope of the patent application of the present invention and produces the same effect is included in the technical scope of the present invention.
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015182133 | 2015-09-15 | ||
JP2015-182133 | 2015-09-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201724551A TW201724551A (en) | 2017-07-01 |
TWI702733B true TWI702733B (en) | 2020-08-21 |
Family
ID=58288455
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105128175A TWI702733B (en) | 2015-09-15 | 2016-09-01 | Mounting method of light-emitting element |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP6575603B2 (en) |
CN (1) | CN107851699B (en) |
TW (1) | TWI702733B (en) |
WO (1) | WO2017047011A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112993138B (en) * | 2020-10-22 | 2022-02-25 | 重庆康佳光电技术研究院有限公司 | Chip substrate and manufacturing method thereof |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6274399B1 (en) * | 1998-06-05 | 2001-08-14 | Lumileds Lighting, U.S. Llc | Method of strain engineering and impurity control in III-V nitride semiconductor films and optoelectronic devices |
JP2006352089A (en) * | 2005-04-05 | 2006-12-28 | Philips Lumileds Lightng Co Llc | LED OF AlInGaP WITH ALLEVIATED TEMPERATURE DEPENDENCY |
TW200701503A (en) * | 2005-06-21 | 2007-01-01 | South Epitaxy Corp | Light-emitting diode and method for manufacturing the same |
JP2007335462A (en) * | 2006-06-12 | 2007-12-27 | Stanley Electric Co Ltd | Semiconductor compound element, and its fabrication process |
JP2011091443A (en) * | 2006-03-17 | 2011-05-06 | Shogen Koden Kofun Yugenkoshi | Method for manufacturing light-emitting diode |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001015803A (en) * | 1999-06-29 | 2001-01-19 | Showa Denko Kk | AlGaInP LIGHT EMITTING DIODE |
JP5407359B2 (en) * | 2009-01-23 | 2014-02-05 | 信越半導体株式会社 | Light emitting diode |
-
2016
- 2016-08-29 WO PCT/JP2016/003914 patent/WO2017047011A1/en active Application Filing
- 2016-08-29 CN CN201680042450.4A patent/CN107851699B/en active Active
- 2016-08-29 JP JP2017540470A patent/JP6575603B2/en active Active
- 2016-09-01 TW TW105128175A patent/TWI702733B/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6274399B1 (en) * | 1998-06-05 | 2001-08-14 | Lumileds Lighting, U.S. Llc | Method of strain engineering and impurity control in III-V nitride semiconductor films and optoelectronic devices |
JP2006352089A (en) * | 2005-04-05 | 2006-12-28 | Philips Lumileds Lightng Co Llc | LED OF AlInGaP WITH ALLEVIATED TEMPERATURE DEPENDENCY |
TW200701503A (en) * | 2005-06-21 | 2007-01-01 | South Epitaxy Corp | Light-emitting diode and method for manufacturing the same |
JP2011091443A (en) * | 2006-03-17 | 2011-05-06 | Shogen Koden Kofun Yugenkoshi | Method for manufacturing light-emitting diode |
JP2007335462A (en) * | 2006-06-12 | 2007-12-27 | Stanley Electric Co Ltd | Semiconductor compound element, and its fabrication process |
Also Published As
Publication number | Publication date |
---|---|
WO2017047011A1 (en) | 2017-03-23 |
TW201724551A (en) | 2017-07-01 |
CN107851699B (en) | 2019-06-04 |
CN107851699A (en) | 2018-03-27 |
JPWO2017047011A1 (en) | 2018-04-26 |
JP6575603B2 (en) | 2019-09-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2063469B1 (en) | Method of manufacturing vertical light emitting diode | |
JP4758857B2 (en) | Manufacturing method of vertical structure light emitting diode | |
JP2010056458A (en) | Method of manufacturing light emitting element | |
JP2005108863A (en) | Vertical gallium nitride light emitting diode and its manufacturing method | |
JP2008042143A (en) | Group iii nitride compound semiconductor light emitting element, and its manufacturing method | |
US11670514B2 (en) | Method for manufacturing semiconductor device and semiconductor substrate | |
JP6068165B2 (en) | Semiconductor optical device and method of manufacturing semiconductor optical device | |
JP2008306021A (en) | Manufacturing method for led chip | |
WO2016079929A1 (en) | Light emitting element and method for producing light emitting element | |
JP2007180302A (en) | Nitride semiconductor light-emitting device and manufacturing method thereof | |
TWI702733B (en) | Mounting method of light-emitting element | |
JP2007096090A (en) | Semiconductor light emitting element and method of manufacturing the same | |
KR100990635B1 (en) | Method for forming vertically structured Light Emitting Diode device | |
TWI807028B (en) | Light emitting element and its manufacturing method | |
US9048090B2 (en) | Semiconductor element and method of manufacturing same | |
JP2007081360A (en) | Vertical type light emitting diode and its manufacture | |
WO2023021972A1 (en) | Provisionally bonded wafer and method for producing same | |
TWI796504B (en) | Manufacturing method of semiconductor element and semiconductor substrate | |
KR102649711B1 (en) | Method for manufacturing ultra-thin type semiconductor die | |
JP7193840B2 (en) | Semiconductor device manufacturing method and semiconductor substrate | |
JP3708342B2 (en) | Method for manufacturing light-emitting diode element | |
KR20150073506A (en) | Supporting substrate for light eimming device and method of manufacturing a light emitting device using the same | |
JPH08116002A (en) | Semiconductor device and its manufacturing method |