TW201724551A - Method of mounting light-emitting element - Google Patents

Method of mounting light-emitting element Download PDF

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TW201724551A
TW201724551A TW105128175A TW105128175A TW201724551A TW 201724551 A TW201724551 A TW 201724551A TW 105128175 A TW105128175 A TW 105128175A TW 105128175 A TW105128175 A TW 105128175A TW 201724551 A TW201724551 A TW 201724551A
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light
layer
substrate
emitting element
mounting
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TW105128175A
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TWI702733B (en
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Junya Ishizaki
Shogo Furuya
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Shin-Etsu Handotai Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)

Abstract

The present invention provides a method of mounting a light-emitting element, including: employing epitaxial growth to grow and form a first semiconductor layer, an active layer, a second semiconductor layer and a buffer layer successively on a starting substrate using a material that is lattice-matched to the starting substrate; employing epitaxial growth to form, on the buffer layer, a window layer/support substrate using a material that is not lattice-matched to the starting substrate; removing the starting substrate; forming a first ohmic electrode on the first semiconductor layer; forming a partial removed portion exposing the second semiconductor layer, the buffer layer or the window layer/support substrate, to provide a step; forming a second ohmic electrode in the removed portion; fabricating a light-emitting element chip by separating a light-emitting element in which the first and second ohmic electrodes are formed; and flip-mounting the light-emitting element chip onto a mounting substrate in such a way that the side of the light-emitting element chip on which the first and second ohmic electrodes are formed is closest to the mounting substrate.

Description

發光元件的安裝方法Light-emitting component mounting method

本發明係關於發光元件的安裝方法,特別是關於將發光元件晶片予以覆晶安裝於安裝基板的發光元件的安裝方法。The present invention relates to a method of mounting a light-emitting element, and more particularly to a method of mounting a light-emitting element in which a light-emitting element wafer is flip-chip mounted on a mounting substrate.

Chip On Board(COB)等的製品,在LED元件的散熱性係為優異,因而在照明等的用途之中係為被採用的一種LED晶片安裝方法。在COB等安裝LED的情況下,將晶片直接接合於板子的覆晶安裝係為必須。在覆晶安裝LED元件的情況下,有藉由超音波的Au-Au接合、共晶焊接等的方法。Products such as Chip On Board (COB) are excellent in heat dissipation properties of LED elements, and thus are used as an LED chip mounting method for applications such as illumination. In the case where an LED is mounted on a COB or the like, it is necessary to directly bond the wafer to the flip chip mounting system of the board. In the case where the LED element is mounted on a flip chip, there is a method of Au-Au bonding by ultrasonic, eutectic soldering or the like.

在藉由黃色至紅色LED而製作覆晶安裝晶片的情況下,於發光層係使用AlGaInP系的材料。由於AlGaInP系材料並未存在晶塊,並且藉由磊晶法形成LED部的緣故,起始基板則被選擇為與AlGaInP為相異的材料。起始基板多半為選擇GaAs或Ge的情況,由於這些基板對可見光具有光吸收的特性的緣故,在製作覆晶安裝晶片的情況下會去除起始基板。When a flip chip mounted wafer is produced by a yellow to red LED, an AlGaInP-based material is used for the light-emitting layer. Since the AlGaInP-based material does not have a crystal ingot, and the LED portion is formed by the epitaxial method, the starting substrate is selected to be a material different from AlGaInP. Most of the starting substrates are GaAs or Ge. Since these substrates have light absorption characteristics for visible light, the starting substrate is removed in the case of fabricating a flip chip mounted wafer.

然而,由於形成發光層的磊晶層係為極薄膜的緣故,在去除起始基板後而無法獨立而存(JC:請全文修正)。因此,必須以具有在發光層對發光波長為略透明而作為窗層的功能,並且具有作為用於獨立而存而有充分厚度的支承基板的功能的材料、構造,而置換起始基板。However, since the epitaxial layer forming the light-emitting layer is a very thin film, it cannot be stored independently after removing the starting substrate (JC: Please correct it in its entirety). Therefore, it is necessary to replace the starting substrate with a function of having a function as a window layer in which the light-emitting layer is slightly transparent to the light-emitting wavelength, and having a function as a support substrate having a sufficient thickness for independence.

如同前述,由於AlGaInP系材料並未存在有晶塊的緣故,作為具有前述的窗層兼支承基板的功能的材料,會選擇GaP、GaAsP及藍寶石等。無論選擇其中哪一種的材料,也由於與AlGaInP為相異的緣故,熱膨脹係數或楊氏模量等的機械特性與AlGaInP系為相異。As described above, since the AlGaInP-based material does not have a crystal ingot, GaP, GaAsP, sapphire, or the like is selected as a material having the function of the above-described window layer and supporting substrate. Regardless of which material is selected, the mechanical properties such as the coefficient of thermal expansion or the Young's modulus are different from those of the AlGaInP system because of the difference from AlGaInP.

藉由超音波的Au-Au接合,如一非專利文獻1所記載,有難以將晶片不傾斜地支承,並有無法效率佳地對晶片傳播超音波,以及有在超音波傳播時晶片會破損等問題。By the Au-Au bonding of the ultrasonic wave, as described in Non-Patent Document 1, it is difficult to support the wafer without tilting, and it is difficult to efficiently propagate the ultrasonic wave to the wafer, and the wafer may be damaged when the ultrasonic wave propagates. .

為了解決以上的問題,形成AuSn共晶凸塊,並且藉由熱熔融(回流焊溫度211~280℃)而進行與基板的接合的技術已被揭示。共晶方式與超音波方式相比,難以引起伴隨超音波的物理的破壞。但是,共晶焊接的熔融、固化的過程中,共晶金屬本身會熱收縮。其結果,在共晶金屬與LED相接的半導體側交界面附近會發生應力,此應力會引起晶片破壞而造成問題。In order to solve the above problems, a technique of forming AuSn eutectic bumps and bonding to a substrate by heat fusion (reflow temperature of 211 to 280 ° C) has been disclosed. The eutectic method is less likely to cause physical damage accompanying ultrasonic waves than the ultrasonic method. However, during the melting and solidification of the eutectic solder, the eutectic metal itself thermally shrinks. As a result, stress occurs in the vicinity of the interface of the semiconductor side where the eutectic metal is in contact with the LED, and this stress causes a problem of wafer destruction.

再者,窗層兼支承基板的材料與AlGaInP發光層的材料差異所引起的熱膨脹係數的差異,也會使由於上述的熱熔融步驟所導致的問題變大。亦即,對於AlGaInP系材料的線膨脹係數5.4E-6[/k],GaP的線膨脹係數為4.5E-6[/k],藍寶石的線膨脹係數為7.0E-6[/k]。因此,在藉由熱熔融處理而安裝的情況,窗層兼支承基板為GaP的情況下,於AlGaInP發光層發生壓縮應力,於窗層兼支承基板發生拉扯應力。於AlGaInP發光層為藍寶石的情況,於AlGaInP發光層發生拉扯應力,於窗層兼支承基板發生壓縮應力。此應力也會引起晶片破壞。Further, the difference in thermal expansion coefficient between the material of the window layer and the support substrate and the material difference of the AlGaInP light-emitting layer also causes a problem due to the above-described heat-melting step. That is, for the coefficient of linear expansion of the AlGaInP-based material of 5.4E-6 [/k], the coefficient of linear expansion of GaP is 4.5E-6 [/k], and the coefficient of linear expansion of sapphire is 7.0E-6 [/k]. Therefore, in the case where the window layer and the support substrate are GaP when mounted by the heat fusion treatment, compressive stress is generated in the AlGaInP light-emitting layer, and tensile stress is generated in the window layer and the support substrate. In the case where the AlGaInP light-emitting layer is sapphire, a tensile stress is generated in the AlGaInP light-emitting layer, and a compressive stress is generated in the window layer and the support substrate. This stress can also cause wafer damage.

覆晶安裝時,形成於發光元件晶片的第一以及第二歐姆電極側的表面會壓迫安裝基板側。此時,雖然由於發光元件晶片的壓迫,使安裝表面側的金屬部變形的緣故,發光元件晶片會沉入安裝表面側,但是此變形不大。因此,在設置於安裝表面的發光元件晶片上的第一歐姆電極及第二歐姆電極的段差大的情況下,相接於安裝表面的第一歐姆電極的金屬的變形量不足,雖然第一歐姆電極表面充分地接觸於安裝表面,但是會發生第二歐姆電極表面未接觸於安裝表面的現象。結果會發生短路,如此則會有無法安裝的問題。因此,一般而言,是於第一歐姆電極以及第二歐姆電極上設置凸塊而使在電極的變形量增加。但是,凸塊係必須使用鍍金法等將Au(金)等而厚厚地形成,材料費會變得非常地昂貴。 [先前技術文獻] [非專利文獻]At the time of flip chip mounting, the surfaces formed on the first and second ohmic electrode sides of the light-emitting element wafer press the mounting substrate side. At this time, although the metal portion on the mounting surface side is deformed by the pressing of the light-emitting element wafer, the light-emitting element wafer sinks on the mounting surface side, but this deformation is not large. Therefore, in the case where the step difference between the first ohmic electrode and the second ohmic electrode on the light-emitting element wafer provided on the mounting surface is large, the amount of deformation of the metal of the first ohmic electrode that is in contact with the mounting surface is insufficient, although the first ohm is The electrode surface is in sufficient contact with the mounting surface, but the phenomenon that the second ohmic electrode surface is not in contact with the mounting surface occurs. As a result, a short circuit occurs, and there is a problem that it cannot be installed. Therefore, in general, bumps are provided on the first ohmic electrode and the second ohmic electrode to increase the amount of deformation of the electrode. However, the bumps must be formed thickly by Au (gold) or the like using a gold plating method or the like, and the material cost becomes extremely expensive. [Prior Technical Literature] [Non-Patent Literature]

[非專利文獻1]日經Electronics,日經BP社,2008年02月11日號[Non-Patent Document 1] Nikkei Electronics, Nikkei BP, February 11, 2008

[發明所欲解決之問題] 鑒於如同前述的問題,本發明係提供一種發光元件的安裝方法,能抑制伴隨著使用超音波的覆晶安裝的破損,以及能抑制在使用共晶焊接的覆晶安裝之中由於熱收縮所導致的應力破壞,更進一步,即使在第一歐姆電極與第二歐姆電極的段差為大的情況下,也能容易地進行發光元件晶片的安裝。 [解決問題之技術手段][Problems to be Solved by the Invention] In view of the foregoing problems, the present invention provides a method of mounting a light-emitting element, which can suppress breakage of a flip-chip mounting accompanying the use of ultrasonic waves, and can suppress flip-chip bonding using eutectic soldering. Further, in the case of stress destruction due to heat shrinkage during mounting, even in the case where the step difference between the first ohmic electrode and the second ohmic electrode is large, the mounting of the light-emitting element wafer can be easily performed. [Technical means to solve the problem]

為了達成上述的目的,藉由本發明而提供一種發光元件的安裝方法,包含下列步驟:於起始基板上,以與該起始基板相晶格匹配系的材料,藉由磊晶成長而成長,依序形成第一半導體層、活性層、第二半導體層以及緩衝層;於該緩衝層之上,以對於該起始基板為非晶格匹配系的材料,藉由磊晶成長而形成窗層兼支承基板;去除該起始基板;於該第一半導體層之上形成第一歐姆電極;於部分形成使該第二半導體層、該緩衝層或是該窗層兼支承基板露出的除去部而設置段差;於該除去部形成第二歐姆電極;將經形成有該第一及第二歐姆電極的發光元件予以分離而製作發光元件晶片,以及於該安裝基板覆晶安裝該發光元件晶片,而使該發光元件晶片的經形成有該第一及第二歐姆電極之側成為安裝基板側。In order to achieve the above object, a method for mounting a light-emitting element according to the present invention includes the steps of: growing on a starting substrate by a crystal lattice matching with the starting substrate, by epitaxial growth, Forming a first semiconductor layer, an active layer, a second semiconductor layer, and a buffer layer; forming a window layer on the buffer layer by epitaxial growth on a material that is an amorphous matching system for the starting substrate And supporting the substrate; removing the starting substrate; forming a first ohmic electrode on the first semiconductor layer; and partially forming a removing portion for exposing the second semiconductor layer, the buffer layer or the window layer and the supporting substrate Providing a step difference; forming a second ohmic electrode in the removing portion; separating the light emitting element formed by the first and second ohmic electrodes to form a light emitting element wafer; and mounting the light emitting element wafer on the mounting substrate The side of the light-emitting element wafer on which the first and second ohmic electrodes are formed is set to the mounting substrate side.

如此一來,藉由以磊晶成長形成窗層兼支承基板而於窗層兼支承基板插入大量的差排的緣故,在超音波安裝時,受到對晶片施加壓力的應力時,藉由窗層兼支承基板會沿著差排面而變形,而能抑制晶片的應力破壞。再者,在利用共晶金屬的覆晶安裝之中,在由於加熱的膨脹,回到室溫時的收縮之中,藉由窗層兼支承基板會沿著差排面而變形,而能抑制晶片的應力破壞。更進一步,即使有第一歐姆電極與第二歐姆電極的段差為大的情況,也能防止覆晶安裝時的發光元件的破損,並且容易地進行發光元件晶片的安裝。In this way, by forming the window layer and supporting the substrate by epitaxial growth, a large number of rows are inserted into the window layer and the supporting substrate, and when the stress is applied to the wafer during ultrasonic mounting, the window layer is used. The supporting substrate is deformed along the difference surface, and stress cracking of the wafer can be suppressed. Further, in the flip chip mounting using the eutectic metal, in the shrinkage at the time of returning to the room temperature due to the expansion of the heating, the substrate supported by the window layer is deformed along the difference surface, and can be suppressed. Stress damage of the wafer. Further, even when the step difference between the first ohmic electrode and the second ohmic electrode is large, breakage of the light-emitting element at the time of flip chip mounting can be prevented, and mounting of the light-emitting element wafer can be easily performed.

此時,該第一半導體層、該活性層及該第二半導體層為AlGaInP或是AlGaAs為佳。In this case, the first semiconductor layer, the active layer, and the second semiconductor layer are preferably AlGaInP or AlGaAs.

如此一來,作為第一半導體層、活性層及第二半導體層,能合適地使用如同上述的材料。As such, as the first semiconductor layer, the active layer, and the second semiconductor layer, materials similar to those described above can be suitably used.

再者此時,該窗層兼支承基板為GaP或是GaAsP為佳。Furthermore, at this time, it is preferable that the window layer and the supporting substrate are GaP or GaAsP.

如此一來,作為窗層兼支承基板,使用如同上述的材料,作為窗層係為合適的同時,能確實地於覆晶安裝時抑制晶片的應力破壞。In this way, as the window layer and the support substrate, the above-described material is used, and the window layer is suitable, and the stress crack of the wafer can be surely suppressed at the time of flip chip mounting.

再者此時,該第一歐姆電極與該第二歐姆電極的段差能為3μm以上11μm以下。Further, at this time, the step difference between the first ohmic electrode and the second ohmic electrode may be 3 μm or more and 11 μm or less.

如此一來,第一歐姆電極與第二歐姆電極的段差即使如上述般大,也能充分地發揮效果。 〔對照先前技術之功效〕As a result, even if the step difference between the first ohmic electrode and the second ohmic electrode is as large as described above, the effect can be sufficiently exerted. [Compared with the efficacy of prior art]

本發明的發光元件的安裝方法,藉由以磊晶成長形成窗層兼支承基板而於窗層兼支承基板插入大量的差排的緣故,在超音波安裝時,受到對晶片施加壓力的應力時,藉由窗層兼支承基板會沿著差排面而變形,而能抑制晶片的應力破壞,在利用共晶金屬的覆晶安裝之中,在由於加熱的膨脹,回到室溫時的收縮之中,藉由窗層兼支承基板會沿著差排面而變形,而能抑制晶片的應力破壞。更進一步,即使有第一歐姆電極與第二歐姆電極的段差為大的情況,也能防止覆晶安裝時的發光元件的破損,並且容易地進行發光元件晶片的安裝。In the method of mounting a light-emitting device of the present invention, a window layer and a support substrate are formed by epitaxial growth, and a large number of rows are inserted into the window layer and the support substrate, and when stress is applied to the wafer during ultrasonic mounting, By the window layer and the supporting substrate, the substrate is deformed along the difference surface, and the stress damage of the wafer can be suppressed. In the flip chip mounting using the eutectic metal, the shrinkage is returned to the room temperature due to the expansion of the heating. Among them, the substrate supported by the window layer is deformed along the difference surface, and stress cracking of the wafer can be suppressed. Further, even when the step difference between the first ohmic electrode and the second ohmic electrode is large, breakage of the light-emitting element at the time of flip chip mounting can be prevented, and mounting of the light-emitting element wafer can be easily performed.

以下,對本發明的實施例進行說明,但是本發明並非限定於此。 如同上述,於覆晶安裝時,存在引起發光元件晶片的破壞的問題。於此,本發明人們為了解決如此的問題而努力地研究。結果發現,藉由對於起始基板以非晶格匹配系的材料磊晶成長窗層兼支承基板,而發現於窗層兼支承基板插入有許多的差排。藉此發現,能抑制在超音波安裝時以及利用共晶金屬的覆晶安裝之中晶片的破壞,更進一步,即使在第一歐姆電極與第二歐姆電極的段差大的情況下,也能在防止覆晶安裝時的發光元件的破損的同時,容易地進行發光元件晶片的安裝。Hereinafter, embodiments of the invention will be described, but the invention is not limited thereto. As described above, there is a problem in that the wafer of the light-emitting element is broken at the time of flip chip mounting. Here, the inventors of the present invention have diligently studied in order to solve such problems. As a result, it was found that by epitaxially growing the window layer and supporting the substrate with the amorphous lattice matching material of the starting substrate, it was found that a large number of rows were inserted into the window layer and the supporting substrate. Accordingly, it has been found that it is possible to suppress the destruction of the wafer during the ultrasonic mounting and the flip-chip mounting using the eutectic metal, and further, even in the case where the step difference between the first ohmic electrode and the second ohmic electrode is large, It is easy to mount the light-emitting element wafer while preventing breakage of the light-emitting element at the time of flip chip mounting.

以下,關於本發明的發光元件的安裝方法,參考第1圖至第8圖而進行說明。Hereinafter, a method of attaching the light-emitting element of the present invention will be described with reference to Figs. 1 to 8 .

首先,準備如第2圖所示的起始基板101(第1圖的SP1)。 作為起始基板101,使用結晶軸為[001]方向往[110]方向傾斜的起始基板101為佳。再者,作為起始基板101,能合適地使用GaAs或是Ge。如此一來,由於能將後述的活性層104的材料以晶格匹配系進行磊晶成長的緣故,而能易於提升活性層104的品質,得到亮度上升或壽命特性的提升。First, the starting substrate 101 (SP1 of Fig. 1) as shown in Fig. 2 is prepared. As the starting substrate 101, it is preferable to use the starting substrate 101 whose crystal axis is inclined in the [001] direction toward the [110] direction. Further, as the starting substrate 101, GaAs or Ge can be suitably used. In this manner, since the material of the active layer 104 to be described later can be epitaxially grown by the lattice matching system, the quality of the active layer 104 can be easily improved, and the luminance can be improved or the life characteristics can be improved.

接下來,亦可於起始基板101之上形成選擇蝕刻層102(第1圖的SP2)。選擇蝕刻層102係於起始基板101之上,能藉由例如MOVPE法(有機金屬氣相成長法)、MBE(分子線磊晶法)或CBE(化學線磊晶法)而成長。Next, a selective etching layer 102 (SP2 of FIG. 1) may be formed on the starting substrate 101. The selective etching layer 102 is formed on the starting substrate 101 and can be grown by, for example, MOVPE method (organic metal vapor phase growth method), MBE (molecular line epitaxy method), or CBE (chemical line epitaxy method).

選擇蝕刻層102係自二層以上的層構造構成,至少具有相接於起始基板101的第二選擇蝕刻層102A及相接於後述的第一半導體層103的第一選擇蝕刻層102B為佳。第二選擇蝕刻層102A及第一選擇蝕刻層102B係自相異的材料或是組成所構成為佳。The selective etching layer 102 is formed of a layer structure of two or more layers, and at least the second selective etching layer 102A that is in contact with the starting substrate 101 and the first selective etching layer 102B that is in contact with the first semiconductor layer 103 to be described later are preferable. . The second selective etch layer 102A and the first selective etch layer 102B are preferably formed from different materials or compositions.

接下來,於起始基板101,藉由磊晶成長而成長,依序形成由第一導電型的第一半導體層103、活性層104及第二導電型的第二半導體層105所構成的發光部108以及緩衝層106(第1圖的SP3)。Next, the starting substrate 101 is grown by epitaxial growth, and the light emitted by the first semiconductor layer 103 of the first conductivity type, the active layer 104, and the second semiconductor layer 105 of the second conductivity type is sequentially formed. Portion 108 and buffer layer 106 (SP3 in Fig. 1).

第一半導體層103、活性層104以及第二半導體層105為AlGaInP或是AlGaAs為佳。如此,能合適地使用如同上述的材料而作為第一半導體層、活性層以及第二半導體層。The first semiconductor layer 103, the active layer 104, and the second semiconductor layer 105 are preferably AlGaInP or AlGaAs. Thus, the material as described above can be suitably used as the first semiconductor layer, the active layer, and the second semiconductor layer.

再者,以InGaP形成緩衝層106為佳。Further, it is preferable to form the buffer layer 106 with InGaP.

為了提升第一半導體層103或是第二半導體層105的特性,而於各層內包含有複數層係為一般,自不待言,第一半導體層103或是第二半導體層105也並非限定於單一層。In order to improve the characteristics of the first semiconductor layer 103 or the second semiconductor layer 105, it is common to include a plurality of layers in each layer. Needless to say, the first semiconductor layer 103 or the second semiconductor layer 105 is not limited to a single one. layer.

此時,第一半導體層103可為二層以上的構造所構成。第一半導體層103的後述的實施表面粗糙化處理之側的低Al組成層103A,相比於活性層側的高Al組成層103B,能藉由Al組成較少的材料所構成者而形成。At this time, the first semiconductor layer 103 may be composed of a structure of two or more layers. The low Al composition layer 103A on the side of the first semiconductor layer 103 to be subjected to the surface roughening treatment described later can be formed by a material having a small Al composition as compared with the high Al composition layer 103B on the active layer side.

如此一來,維持包覆層的載體侷限效果的同時,抑制由於過度蝕刻所導致的焊墊電極的機械強度的下降以及在引線接合時發生的晶片破損,而能製造得到所求凹凸大小的粗糙面的發光元件。In this way, while maintaining the effect of the carrier of the cladding layer, the mechanical strength of the pad electrode due to over-etching and the wafer breakage occurring during wire bonding are suppressed, and the roughness of the desired roughness can be manufactured. Surface light-emitting elements.

接下來,於緩衝層106之上,對於起始基板101,以非晶格匹配系的材料,藉由磊晶成長而形成窗層兼支承基板107,而製作磊晶基板109(第1圖的SP4)。 作為窗層兼支承基板107,以GaP或者是GaAsP為佳。Next, on the buffer layer 106, a window layer and a support substrate 107 are formed by epitaxial growth on the starting substrate 101 by an amorphous matching system, thereby forming an epitaxial substrate 109 (Fig. 1). SP4). As the window layer and supporting substrate 107, GaP or GaAsP is preferred.

接下來,自磊晶基板109去除起始基板101以及第二選擇蝕刻層102A,如同第3圖所示,於發光元件基板110的第一半導體層103的表面僅殘留第一選擇蝕刻層102B(第1圖的SP5)。 具體而言,自磊晶基板109,透過使用第二選擇蝕刻層102A並且藉由濕式蝕刻法而去除起始基板101,而能於第一半導體層103的表面僅殘留第一選擇蝕刻層102B。Next, the starting substrate 101 and the second selective etching layer 102A are removed from the epitaxial substrate 109. As shown in FIG. 3, only the first selective etching layer 102B remains on the surface of the first semiconductor layer 103 of the light emitting element substrate 110 ( SP5 of Fig. 1). Specifically, the first selective etching layer 102B remains on the surface of the first semiconductor layer 103 from the epitaxial substrate 109 by using the second selective etching layer 102A and removing the starting substrate 101 by wet etching. .

接下來,如第4圖所示,於第一半導體層103上的第一選擇蝕刻層102B的表面,將為了對發光元件供給電位的第一歐姆電極121予以形成(第1圖的SP6)。Next, as shown in FIG. 4, the first ohmic electrode 121 for supplying a potential to the light-emitting element is formed on the surface of the first selective etching layer 102B on the first semiconductor layer 103 (SP6 of Fig. 1).

接下來,如第4圖所示,去除第一歐姆電極121的底部以外的範圍的第一選擇蝕刻層102B(第1圖的SP7)。 具體而言,將第一歐姆電極121作為蝕刻遮罩,而能藉由蝕刻去除第一歐姆電極121的底部以外的範圍的第一選擇蝕刻層102B。Next, as shown in FIG. 4, the first selective etching layer 102B (SP7 of FIG. 1) in a range other than the bottom of the first ohmic electrode 121 is removed. Specifically, by using the first ohmic electrode 121 as an etch mask, the first selective etch layer 102B in a range other than the bottom of the first ohmic electrode 121 can be removed by etching.

接下來,如第5圖所示,能進行第一表面粗糙化處理步驟,而將第一半導體層103的表面上的第一歐姆電極121的形成部以外的至少一部份予以表面粗糙化(第1圖的SP8)。Next, as shown in FIG. 5, the first surface roughening treatment step can be performed, and at least a portion other than the formation portion of the first ohmic electrode 121 on the surface of the first semiconductor layer 103 is surface roughened ( SP8 of Fig. 1).

具體而言,例如能藉由無機酸與有機酸的混合液所構成的第一表面粗糙液,而於除了第一半導體層103的表面上的第一歐姆電極121的形成部的部分進行第一表面粗糙化處理。Specifically, for example, a first surface roughening liquid composed of a mixed solution of a mineral acid and an organic acid can be used, and the first portion of the first ohmic electrode 121 on the surface of the first semiconductor layer 103 is first formed. Surface roughening treatment.

接下來,如第6圖所示,進行於部分形成使第二半導體層、緩衝層或是窗層兼支承基板露出的除去部170而設置段差的步驟(除去部、段差形成步驟,第1圖的SP9)。如第6圖所示,於除去部170及其以外的非除去部180之間設置段差。Next, as shown in FIG. 6, a step of partially forming a removal portion 170 for exposing the second semiconductor layer, the buffer layer, or the window layer-supporting substrate is performed (the removal portion and the step difference forming step, FIG. 1) SP9). As shown in Fig. 6, a step is provided between the removal portion 170 and the non-removed portion 180 other than the removal portion 170.

具體而言,例如能藉由材料選擇性低的ICP乾式蝕刻法,而自範圍140的第一半導體層至窗層兼支承基板的一部份進行蝕刻。如此一來,能形成如第6圖所示的已露出窗層兼支承基板107的部分(除去部170)。除去部170係繼承以第一表面粗糙化處理步驟所形成的表面粗糙圖案的緣故,而具有表面粗糙圖案。Specifically, for example, etching can be performed from the first semiconductor layer of the range 140 to a portion of the window layer supporting substrate by the ICP dry etching method having low material selectivity. As a result, a portion (removed portion 170) in which the window layer and the support substrate 107 are exposed as shown in Fig. 6 can be formed. The removing portion 170 inherits the surface rough pattern formed by the first surface roughening treatment step and has a surface roughness pattern.

接下來,如第7圖所示,於除去部170的窗層兼支承基板107的表面上形成第二歐姆電極122(第1圖的SP10)。 如此一來,第一歐姆電極121與第二歐姆電極122之間係具有段差而被形成。在本發明之中,例如,第一歐姆電極121與第二歐姆電極122的段差能為3μm以上且11μm以下。如此一來,即使第一歐姆電極與第二歐姆電極的段差大,亦如同後述,能在防止覆晶安裝時的發光元件的破損的同時,容易地進行發光元件晶片的安裝。Next, as shown in FIG. 7, the second ohmic electrode 122 (SP10 of the first drawing) is formed on the surface of the window layer-supporting substrate 107 of the removing portion 170. As a result, the first ohmic electrode 121 and the second ohmic electrode 122 are formed with a step difference. In the present invention, for example, the step difference between the first ohmic electrode 121 and the second ohmic electrode 122 can be 3 μm or more and 11 μm or less. As described above, even if the step difference between the first ohmic electrode and the second ohmic electrode is large, as described later, it is possible to easily mount the light-emitting element wafer while preventing breakage of the light-emitting element at the time of flip chip mounting.

接下來,如第7圖所示,能藉由絕緣保護膜150而覆蓋第一半導體層103的表面以及發光部108的側面的至少一部份(第1圖的SP11)。 若為透明並且具有絕緣性的材料,絕緣保護膜150可為任一種材料。作為絕緣保護膜150,使用例如SiO­ 或是SiNx 係為合適。若為如此者,藉由光微影法及含有氟酸的蝕刻液,而能容易地於第一歐姆電極121以及第二歐姆電極122的頂部進行開口的加工。Next, as shown in FIG. 7, the surface of the first semiconductor layer 103 and at least a part of the side surface of the light-emitting portion 108 can be covered by the insulating protective film 150 (SP11 of Fig. 1). The insulating protective film 150 may be any material if it is transparent and has an insulating property. As the insulating protective film 150, for example, SiO is used. ­ Or SiN x is suitable. In this case, the opening processing can be easily performed on the tops of the first ohmic electrode 121 and the second ohmic electrode 122 by the photolithography method and the etching solution containing the hydrofluoric acid.

接下來,進行將形成有第一以及第二歐姆電極121、122的發光元件予以分離而製作發光元件晶片的步驟(第1圖的SP12)。 具體而言,能沿著刻劃範圍142(參考第7圖)而刻劃刻劃線,藉由進行裂片(breaking)而分離發光元件,而製作發光元件晶片1(晶粒)。Next, a step of separating the light-emitting elements in which the first and second ohmic electrodes 121 and 122 are formed to form a light-emitting element wafer is performed (SP12 in FIG. 1). Specifically, the scribe line can be scribed along the scribed range 142 (refer to FIG. 7), and the light-emitting element can be separated by performing a breaking to produce the light-emitting element wafer 1 (die).

接下來,如第8圖所示,能藉由第二表面粗糙液進行第二表面粗糙化處理步驟,而將窗層兼支承基板107的側面以及反面予以表面粗糙化。 另外,由於藉由第二表面粗糙化處理而使發光角度擴大的緣故,在不想讓發光角度擴大的情況下不進行處理亦可。Next, as shown in Fig. 8, the second surface roughening treatment step can be performed by the second surface roughening liquid, and the side surface and the reverse surface of the window layer and the support substrate 107 can be roughened. Further, since the light-emitting angle is enlarged by the second surface roughening treatment, the processing may not be performed when the light-emitting angle is not desired to be enlarged.

接下來,進行於該安裝基板覆晶安裝該發光元件晶片的步驟(第1圖的SP14),而使該發光元件晶片1的經形成有該第一及第二歐姆電極之側成為安裝基板(未圖示)之側。Next, a step of flip-chip mounting the light-emitting device wafer on the mounting substrate (SP14 in FIG. 1) is performed, and a side on which the first and second ohmic electrodes are formed on the light-emitting element wafer 1 is a mounting substrate ( Side not shown).

[第一實施方式] 在上述的覆晶安裝步驟(SP14)之中,在第一實施方式之中,對安裝基板(安裝板)的晶固後,能藉由超音波接合而進行覆晶安裝。此時,第一歐姆電極的安裝接合部係設置於晶片邊緣部。[First Embodiment] In the above-described flip chip mounting step (SP14), in the first embodiment, after the crystal substrate of the mounting substrate (mounting plate) is mounted, the flip chip bonding can be performed by ultrasonic bonding. . At this time, the mounting joint portion of the first ohmic electrode is provided at the edge portion of the wafer.

在第一實施方式之中,在超音波安裝時,由於超音波傳播係在滑動面(貫穿差排面)以外的單結晶部傳播的緣故,有效率地進行之外,一方面也在自頂部壓住晶片時,窗層兼支承基板部會容易沿著滑動面變形的緣故,而不易破損。In the first embodiment, in the case of ultrasonic installation, since the ultrasonic wave propagates in a single crystal portion other than the sliding surface (through the differential surface), it is efficiently performed, and on the other hand, from the top. When the wafer is pressed, the window layer and the supporting substrate portion are easily deformed along the sliding surface, and are not easily broken.

[第二實施方式] 在上述的覆晶安裝步驟(SP14)之中,在第二實施方式之中,作為於第一歐姆電極上以及第二歐姆電極上更進一步積層共晶金屬的構造,晶粒接合後,能藉由透過加熱、冷卻處理而進行覆晶安裝。[Second Embodiment] Among the above-described flip chip mounting step (SP14), in the second embodiment, as a structure in which a eutectic metal is further laminated on the first ohmic electrode and the second ohmic electrode, crystal After the grain bonding, the flip chip can be mounted by transmission heating and cooling treatment.

於第一歐姆電極上以及第二歐姆電極上具有低熔點的AuSn等的共晶焊接層,窗層兼支承基板為具有高密度的貫穿差排的覆晶晶片構造。在第二實施方式之中,共晶焊接的熱收縮時,雖然於窗層兼支承基板施加拉扯應力,但是由於具有滑動面(貫穿差排面),而比單結晶變形更大的緣故,應力並未集中,而能迴避晶片破損。The eutectic solder layer of AuSn or the like having a low melting point on the first ohmic electrode and the second ohmic electrode, and the window layer and the supporting substrate are a flip chip structure having a high density of the through-difference. In the second embodiment, in the heat shrinkage of the eutectic soldering, although the pulling stress is applied to the window layer and the supporting substrate, the sliding surface (through the differential surface) has a larger deformation than the single crystal, and the stress is greater. Not concentrated, but can avoid wafer damage.

如此一來,藉由以對於起始基板之非晶格整合系的材料而磊晶成長窗層兼支承基板,而於窗層兼支承基板插入大量的差排(差排密度10個/cm2以上)。藉由使窗層兼支承基板具有高密度的差排,在利用超音波的覆晶安裝時(第一實施方式),受到對晶片施加壓力的應力時,藉由窗層兼支承基板會沿著差排面變形,而能抑制晶片的破損。再者,在利用共晶金屬的覆晶安裝(第二實施方式)之中,在由於加熱的膨脹,回復至室溫時的收縮之中,藉由窗層兼支承基板會沿著差排面變形,而能抑制晶片的破損。In this way, the window layer and the supporting substrate are epitaxially grown by the material of the amorphous integrated layer of the starting substrate, and a large number of rows are inserted into the window layer and the supporting substrate (the difference density is 10 pieces/cm 2 or more). ). When the window layer and the support substrate have a high density difference, when the flip chip is mounted by ultrasonic waves (the first embodiment), when the stress is applied to the wafer, the substrate is supported by the window layer. The differential surface is deformed, and the damage of the wafer can be suppressed. Further, in the flip chip mounting using the eutectic metal (second embodiment), in the shrinkage at the time of returning to room temperature due to the expansion of the heating, the substrate is supported by the window layer along the difference surface. The deformation can suppress the breakage of the wafer.

更進一步,如同本發明形成除去部而設置段差的緣故,即使在第一歐姆電極與第二歐姆電極的段差大的情況下,於覆晶安裝時的發光元件晶片壓迫時,由於發光元件晶片會變形的緣故,而能防止覆晶安裝時的發光元件的破損。特別是窗層兼支承基板具有滑動面的緣故,而對於發光元件晶片壓迫會容易變形,而於第一歐姆電極121接觸於安裝面的同時,第二歐姆電極122也接觸於安裝面的緣故,在覆晶安裝中不一定需要凸塊。藉此,能容易地進行發光元件晶片的安裝。Further, as in the case where the removal portion is formed in the present invention and the step is set, even when the step difference between the first ohmic electrode and the second ohmic electrode is large, when the light-emitting element wafer is pressed during the flip-chip mounting, the light-emitting element wafer is Due to the deformation, it is possible to prevent breakage of the light-emitting element during flip chip mounting. In particular, the window layer and the support substrate have a sliding surface, and the light-emitting element wafer is easily deformed by pressing, and the second ohmic electrode 122 is in contact with the mounting surface while the second ohmic electrode 122 is in contact with the mounting surface. Bumps are not necessarily required in flip chip mounting. Thereby, the mounting of the light-emitting element wafer can be easily performed.

具體而言,第一歐姆電極與第二歐姆電極的段差如同上述,能為3μm以上11μm以下。如此一來,即使第一歐姆電極與第二歐姆電極的段差大,本發明也能充分地發揮功效。Specifically, the step difference between the first ohmic electrode and the second ohmic electrode is as described above, and can be 3 μm or more and 11 μm or less. In this way, even if the step difference between the first ohmic electrode and the second ohmic electrode is large, the present invention can sufficiently exert its effects.

以下表示本發明的實施例以及比較例而更具體地說明本發明,但是本發明並非限定於此。The present invention will be more specifically described below with reference to examples and comparative examples of the invention, but the invention is not limited thereto.

[實施例] 於自結晶軸[001]方向向[110]方向傾斜15°的厚度280μm的n型GaAs所構成的起始基板101上,藉由MOVPE法(有機金屬氣相成長法)將n型GaAs緩衝層(未圖示)成長為0.5μm、由n型AlInP層所構成的第二選擇蝕刻層102A成長為1μm,以及由n型GaAs層所構成的第一選擇蝕刻層102B成長為1μm後,將以AlGaInP所構成的n型包覆層(第一半導體層103)、活性層104及p型包覆層(第二半導體層105)所構成的發光部108予以形成出5.5μm,於其之上,將由p型GaInP所構成的緩衝層106形成出0.3μm,將由p型Gap所構成的窗層兼支承基板107的一部分予以成長1.0μm。接下來,移送至HVPE爐,將自p型GaP所構成的窗層兼支承基板107成長120μm,而得到磊晶基板109(參考第2圖)。[Examples] On the starting substrate 101 made of n-type GaAs having a thickness of 280 μm which was inclined by 15° from the [001] direction to the [110] direction, the MOVPE method (organic metal vapor phase growth method) was used. The GaAs buffer layer (not shown) is grown to 0.5 μm, the second selective etch layer 102A composed of the n-type AlInP layer is grown to 1 μm, and the first selective etch layer 102B composed of the n-type GaAs layer is grown to 1 μm. Thereafter, the light-emitting portion 108 composed of the n-type cladding layer (first semiconductor layer 103) composed of AlGaInP, the active layer 104, and the p-type cladding layer (second semiconductor layer 105) is formed to have a thickness of 5.5 μm. On the other hand, the buffer layer 106 made of p-type GaInP was formed to be 0.3 μm, and a part of the window layer and the support substrate 107 made of p-type Gap was grown by 1.0 μm. Then, it is transferred to the HVPE furnace, and the window layer-support substrate 107 composed of the p-type GaP is grown by 120 μm to obtain an epitaxial substrate 109 (see FIG. 2).

接下來,自磊晶基板109,將起始基板101、GaAs緩衝層及第二選擇蝕刻層102A予以蝕刻去除,而製作僅殘留第一選擇蝕刻層102B的發光元件基板110(參考第3圖)。具體而言,自磊晶基板109,將第二選擇蝕刻層102A作為選擇蝕刻層,利用濕式蝕刻法去除起始基板101,而成為發光元件基板110。Next, the starting substrate 101, the GaAs buffer layer, and the second selective etching layer 102A are etched away from the epitaxial substrate 109, and the light-emitting element substrate 110 in which only the first selective etching layer 102B remains is produced (refer to FIG. 3). . Specifically, from the epitaxial substrate 109, the second selective etching layer 102A is used as a selective etching layer, and the starting substrate 101 is removed by wet etching to form the light-emitting element substrate 110.

接下來,將係為對發光元件的電位供給用電極的第一歐姆電極121予以形成。具體而言,如第4圖所示,於發光元件基板110的第一選擇蝕刻層102B上形成第一歐姆電極121。然後,將第一歐姆電極121作為遮罩,藉由蝕刻而將第一歐姆電極121以外的範圍的第一選擇蝕刻層102B予以去除。Next, the first ohmic electrode 121 for the potential supply electrode of the light-emitting element is formed. Specifically, as shown in FIG. 4, the first ohmic electrode 121 is formed on the first selective etching layer 102B of the light-emitting element substrate 110. Then, the first ohmic electrode 121 is used as a mask, and the first selective etching layer 102B in the range other than the first ohmic electrode 121 is removed by etching.

接下來,如第9圖所示,藉由光微影法,於第二歐姆電極形成預定範圍122a設置光阻遮罩123,藉由第一表面粗糙液,進行第一表面粗糙化處理。第一表面粗糙液係以醋酸及鹽酸的混合液製作,藉由在常溫下蝕刻1分鐘而進行表面粗糙化。Next, as shown in FIG. 9, the photoresist mask 123 is provided in the second ohmic electrode formation predetermined range 122a by the photolithography method, and the first surface roughening treatment is performed by the first surface roughening liquid. The first surface roughening liquid was prepared by mixing a mixture of acetic acid and hydrochloric acid, and was roughened by etching at room temperature for 1 minute.

接下來,藉由光微影法,在範圍140(參考第9圖)形成已開口的圖案,藉由含有鹽酸氣體的ICP電漿蝕刻法而實施除去部、段差形成步驟,去除發光部108以及緩衝層106,而形成露出窗層兼支承基板107的去除部170以及其外的非除去部180(參考第10圖)。此時,雖然除去部170繼承有在第一表面粗糙化處理步驟中所形成的表面粗糙圖案,第二歐姆電極的形成部141的部分,並未在第一表面粗糙化處理步驟中形成粗糙面,並未成為表面粗糙圖案而形成為平坦的表面。Next, an open pattern is formed in the range 140 (refer to FIG. 9) by the photolithography method, and the removing portion and the step forming step are performed by the ICP plasma etching method containing hydrochloric acid gas, and the light emitting portion 108 is removed. The buffer layer 106 forms a removal portion 170 that exposes the window layer and the support substrate 107, and a non-removed portion 180 (refer to FIG. 10). At this time, although the removal portion 170 inherits the surface roughness pattern formed in the first surface roughening treatment step, the portion of the second ohmic electrode forming portion 141 does not form a rough surface in the first surface roughening treatment step. It does not become a surface rough pattern and is formed into a flat surface.

接下來,於第10圖的第二歐姆電極的形成部141形成第二歐姆電極122(參考第11圖)。接下來,積層由SiO2 所構成的絕緣保護膜150,而將覆蓋第一半導體層103表面以及發光部108的側面的由SiO2 所構成的絕緣保護膜150予以形成。Next, the second ohmic electrode 122 is formed in the forming portion 141 of the second ohmic electrode of FIG. 10 (refer to FIG. 11). Next, the laminate formed by the SiO 2 insulating protective film 150, and the cover is protected by the SiO 2 insulating film composed of the side surface of the first semiconductor layer 103 and the surface 150 of the light emitting portion 108 to be formed.

接下來,沿著刻劃範圍142刻劃刻劃線,沿著刻劃線將裂紋線予以延伸,之後藉由進行裂片而分離元件,而形成發光元件晶片11。Next, the scribe line is scribed along the scribed range 142, the crack line is extended along the scribe line, and then the element is separated by performing the cleavage to form the light-emitting element wafer 11.

發光元件晶片11形成後,於支承膠帶轉印發光元件晶片11而使設置有第一歐姆電極121的表面為膠帶面之側,之後,藉由第二表面粗糙液,而實施表面粗糙化窗層兼支承基板107的側面以及背面的第二表面粗糙化處理步驟(參考第12圖)。作為第二表面粗糙液,製作醋酸、氟酸及碘的混合液。然後,藉由在常溫下1分鐘的蝕刻而進行第二表面粗糙化處理。After the light-emitting element wafer 11 is formed, the light-emitting element wafer 11 is transferred onto the support tape so that the surface on which the first ohmic electrode 121 is provided is the side of the tape surface, and then the surface roughening window layer is formed by the second surface roughening liquid. The second surface roughening treatment step of the side surface and the back surface of the support substrate 107 (refer to Fig. 12). As the second surface roughening liquid, a mixed liquid of acetic acid, hydrofluoric acid, and iodine was produced. Then, the second surface roughening treatment was performed by etching at room temperature for 1 minute.

[比較例] 於自結晶軸[001]方向向[110]方向傾斜15°的厚度280μm的n型GaAs所構成的起始基板301上,藉由MOVPE法將n型GaAs緩衝層(未圖示)成長為0.5μm、由n型AlInP層所構成的第二選擇蝕刻層302A成長為1μm,以及由n型GaAs層所構成的第一選擇蝕刻層302B成長為1μm後,於此具有第二選擇蝕刻層302A及第一選擇蝕刻層302B的選擇蝕刻層302上,將以AlGaInP所構成的n型包覆層(第一半導體層303)、活性層304及p型包覆層(第二半導體層305)所構成的發光部308予以形成出5.5μm,於其之上,將由p型GaInP所構成的緩衝層306形成出0.3μm,藉由將電流擴散層307予以磊晶成長1.0μm,而製作磊晶基板309(參考第13圖)。[Comparative Example] An n-type GaAs buffer layer was not formed by the MOVPE method on a starting substrate 301 made of n-type GaAs having a thickness of 280 μm which was inclined by 15° from the [001] direction to the [110] direction. The second selective etching layer 302A composed of the n-type AlInP layer is grown to 1 μm, and the first selective etching layer 302B composed of the n-type GaAs layer is grown to 1 μm, and has a second option. On the selective etching layer 302 of the etching layer 302A and the first selective etching layer 302B, an n-type cladding layer (first semiconductor layer 303) composed of AlGaInP, an active layer 304, and a p-type cladding layer (second semiconductor layer) 305) The light-emitting portion 308 is formed to have a thickness of 5.5 μm, and a buffer layer 306 made of p-type GaInP is formed to be 0.3 μm, and the current diffusion layer 307 is epitaxially grown by 1.0 μm. Epitaxial substrate 309 (refer to Fig. 13).

接下來,如第14圖所示,於磊晶基板309接合厚度為300μm的GaP單結晶基板310。於磊晶晶版309與GaP單結晶基板310的接合,以鹼系的溶液洗淨磊晶基板309及GaP單結晶基板310兩者,利用BCB黏著劑而接合。Next, as shown in Fig. 14, a GaP single crystal substrate 310 having a thickness of 300 μm is bonded to the epitaxial substrate 309. The epitaxial wafer 309 is bonded to the GaP single crystal substrate 310, and both the epitaxial substrate 309 and the GaP single crystal substrate 310 are washed with an alkali solution, and bonded by a BCB adhesive.

接下來,自磊晶基板309,將起始基板301、GaAs緩衝層及第二選擇蝕刻層302A予以蝕刻去除,而製作僅殘留第一選擇蝕刻層302B的發光元件基板311(參考第15圖)。具體而言,自磊晶基板309,將第二選擇蝕刻層302A作為選擇蝕刻層,利用濕式蝕刻法去除起始基板301,而成為發光元件基板311。Next, the starting substrate 301, the GaAs buffer layer, and the second selective etching layer 302A are etched away from the epitaxial substrate 309, and the light-emitting element substrate 311 in which only the first selective etching layer 302B remains is produced (refer to Fig. 15). . Specifically, from the epitaxial substrate 309, the second selective etching layer 302A is used as a selective etching layer, and the starting substrate 301 is removed by wet etching to form the light-emitting element substrate 311.

接下來,將係為對發光元件的電位供給用電極的第一歐姆電極321予以形成。具體而言,如第16圖所示,於接合基板311的第一選擇蝕刻層302B上形成第一歐姆電極321。然後,將第一歐姆電極321作為遮罩,藉由蝕刻而將第一歐姆電極321以外的範圍的第一選擇蝕刻層302B予以去除。Next, the first ohmic electrode 321 for the potential supply electrode of the light-emitting element is formed. Specifically, as shown in FIG. 16, the first ohmic electrode 321 is formed on the first selective etching layer 302B of the bonding substrate 311. Then, the first ohmic electrode 321 is used as a mask, and the first selective etching layer 302B in a range other than the first ohmic electrode 321 is removed by etching.

接下來,如第17圖所示,藉由第一表面粗糙液,進行第一表面粗糙化處理。第一表面粗糙液係以醋酸及鹽酸的混合液製作,藉由在常溫下蝕刻1分鐘而進行表面粗糙化。Next, as shown in Fig. 17, the first surface roughening treatment is performed by the first surface roughening liquid. The first surface roughening liquid was prepared by mixing a mixture of acetic acid and hydrochloric acid, and was roughened by etching at room temperature for 1 minute.

接下來,藉由光微影法,在範圍340(參考第17圖)形成已開口的圖案,藉由含有鹽酸氣體的ICP電漿蝕刻法而實施除去部、段差形成步驟,蝕刻範圍340,而形成露出電流擴散層307以及其外的非除去部380(參考第18圖)。Next, by the photolithography method, an open pattern is formed in the range 340 (refer to FIG. 17), and the removing portion and the step forming step are performed by the ICP plasma etching method containing hydrochloric acid gas, and the etching range 340 is performed. A non-removed portion 380 is formed which exposes the current diffusion layer 307 and the outside thereof (refer to FIG. 18).

接下來,如第18圖所示,形成第二歐姆電極322。接下來,如第19圖所示,積層由SiO2 所構成的絕緣保護膜350,而形成覆蓋第一半導體層303表面以及發光部308的側面的由SiO2 所構成的絕緣保護膜350。Next, as shown in Fig. 18, a second ohmic electrode 322 is formed. Next, as shown in FIG. 19, the protective laminate of an insulating film 350 composed of SiO 2, to form a protective insulating film is formed of SiO 2 covers the surface 350 and the light emitting portion 308 of the side surface of the first semiconductor layer 303.

接下來,沿著刻劃範圍342(參考第19圖)刻劃刻劃線,沿著刻劃線將裂紋線予以延伸,之後藉由進行裂片而分離元件,如第20圖所示,形成發光元件晶片201。Next, the scribe line is scribed along the scribed range 342 (refer to FIG. 19), the crack line is extended along the scribe line, and then the element is separated by performing the cleavage, as shown in FIG. 20, to form a luminescence Component wafer 201.

發光元件晶片201形成後,於支承膠帶轉印發光元件晶片201而使設置有第一歐姆電極321的表面為膠帶面之側,之後,藉由第二表面粗糙液,而實施表面粗糙化GaP單結晶基板310的側面以及背面的第二表面粗糙化處理步驟(參考第20圖)。作為第二表面粗糙液,製作醋酸、氟酸及碘的混合液。然後,藉由在常溫下1分鐘的蝕刻而進行第二表面粗糙化處理。After the light-emitting element wafer 201 is formed, the light-emitting element wafer 201 is transferred onto the support tape so that the surface on which the first ohmic electrode 321 is provided is the side of the tape surface, and then the surface roughening GaP is performed by the second surface roughening liquid. A second surface roughening treatment step of the side surface and the back surface of the crystal substrate 310 (refer to Fig. 20). As the second surface roughening liquid, a mixed liquid of acetic acid, hydrofluoric acid, and iodine was produced. Then, the second surface roughening treatment was performed by etching at room temperature for 1 minute.

將實施例以及比較例所製造的發光元件晶片,各100個分別進行Au-Au超音波安裝,並且將進行比較的結果表示於第21圖。在比較例之中,被認為是原因的晶片壓黏或是超音波印加時的震動所導致的破損會發生,不良率上升。另一方面,在實施例之中,相比於比較例,起因於同樣原因的晶片破損的發生率較少。Each of the light-emitting element wafers produced in the examples and the comparative examples was subjected to Au-Au ultrasonic mounting, and the results of comparison were shown in Fig. 21. In the comparative example, damage caused by vibration of the wafer which is considered to be the cause or vibration at the time of ultrasonic printing occurs, and the defective ratio increases. On the other hand, in the examples, the incidence of wafer breakage due to the same reason was small compared to the comparative example.

接下來,將實施例以及比較例所製造的發光元件晶片,各100個分別於電極上以及安裝基板上設置AuSn層,進行熱熔融(220℃以上)而進行安裝,並且將進行比較的結果表示於第22圖。在比較例以及實施例之中,被認為是起因為熱熔融後的AuSn的熱收縮的破損雖然會發生,但是如第22圖所示,相比於比較例,實施例的破損率為少。Next, the light-emitting element wafers produced in the examples and the comparative examples were each provided with an AuSn layer on the electrode and the mounting substrate, and were thermally melted (220 ° C or higher), and the results of the comparison were shown. In Figure 22. In the comparative examples and the examples, it is considered that the breakage of the heat shrinkage of AuSn after the heat fusion occurred, but as shown in Fig. 22, the breakage rate of the examples was small as compared with the comparative example.

在實施例之中,由於窗層兼支承基板107係藉由磊晶成長而形成的緣故,在600~800℃程度的溫度範圍形成。線膨脹係數,相較於GaP,AlGaInP為更大,於成長後降溫至室溫時,由於膨脹係數差異,對於基板除去面,會發生凹形狀的翹曲。再者,於AlGaInP/GaP之間,晶格定數差存在3.7%,此晶格定數差也會使翹曲增大。另一方面,由於晶格定數差,而於窗層兼支承基板存在高密度的差排。如此一來,於實施例的窗層兼支承基板具有高密度的貫穿差排。由於差排面具有在施加外力於結晶時發生滑動的特性的緣故,振動或壓黏時的應力施加於結晶時,於破壞結晶前,藉由結晶沿著滑動面滑動,而避開安裝時的應力,其結果,能想到晶片破損率會低下。In the embodiment, the window layer and the supporting substrate 107 are formed by epitaxial growth, and are formed in a temperature range of about 600 to 800 °C. The coefficient of linear expansion is larger than that of GaP, and AlGaInP is larger. When the temperature is lowered to room temperature after growth, due to the difference in expansion coefficient, warpage of the concave shape occurs on the substrate removal surface. Furthermore, between AlGaInP/GaP, the lattice difference is 3.7%, and this lattice difference also increases the warpage. On the other hand, due to the difference in lattice number, there is a high density difference between the window layer and the support substrate. As a result, the window layer-supporting substrate of the embodiment has a high-density through-dissipation row. Since the difference surface has the property of slipping when an external force is applied to the crystal, when the stress at the time of vibration or pressure bonding is applied to the crystal, the crystal slides along the sliding surface before the crystal is broken, thereby avoiding the mounting. As a result of the stress, it is conceivable that the wafer breakage rate is lowered.

另一方面,在比較例之中,雖然線膨脹差異所導致的與實施例相同的翹曲會發生,但是接合溫度為350℃,相較於實施例的情況係較低溫的緣故,相較於實施例,翹曲為1/10以下。On the other hand, in the comparative example, the same warpage as in the embodiment caused by the difference in linear expansion occurred, but the joining temperature was 350 ° C, which was lower than that in the case of the example, as compared with the case of the example. In the examples, the warpage was 1/10 or less.

接下來,在實施例以及比較例之中,將第一歐姆電極與第二歐姆電極的段差予以變化而製造發光元件晶片,在製造的發光元件晶片並未設置凸塊,而進行覆晶安裝時的生產率的測定。於第23圖表示此結果。在第23圖之中,橫軸作為實施例以及比較例的第一歐姆電極與第二歐姆電極的段差,縱軸則表示為在安裝時能安裝完成的晶片數的生產率。Next, in the examples and the comparative examples, the step of the first ohmic electrode and the second ohmic electrode was changed to produce a light-emitting element wafer, and the bump was not provided in the manufactured light-emitting element wafer, and the flip chip was mounted. Determination of productivity. This result is shown in Figure 23. In Fig. 23, the horizontal axis represents the step difference between the first ohmic electrode and the second ohmic electrode of the embodiment and the comparative example, and the vertical axis represents the productivity of the number of wafers that can be mounted at the time of mounting.

覆晶安裝時,發光元件晶片會對安裝面壓迫。由於發光元件晶片的壓迫,安裝面之側的金屬部會變形的緣故,雖然發光元件晶片會沉入安裝面之側,但是此變形不大。因此,在比較例之中,如第23圖所示,若設置於安裝面的發光元件晶片上的第一歐姆電極321與第二歐姆電極322的段差為3μm以上,接觸於安裝面的第一歐姆電極321的金屬的變形量不足,雖然第一歐姆電極321表面充分地接觸安裝面,但是第二歐姆電極322會發生未接觸安裝面的現象。此結果會導致短路,而無法安裝。因此,為了使在電極的變形量變大,一般而言,會於第一歐姆電極321以及第二歐姆電極322上設置凸塊。但是,凸塊必須使用鍍金法等將Au(金)等有厚厚地形成,材料費會變得非常地高昂。When the flip chip is mounted, the light-emitting element wafer is pressed against the mounting surface. Due to the pressing of the light-emitting element wafer, the metal portion on the side of the mounting surface is deformed, and although the light-emitting element wafer sinks to the side of the mounting surface, the deformation is not large. Therefore, in the comparative example, as shown in FIG. 23, if the step difference between the first ohmic electrode 321 and the second ohmic electrode 322 provided on the light-emitting element wafer of the mounting surface is 3 μm or more, the first contact with the mounting surface The amount of deformation of the metal of the ohmic electrode 321 is insufficient, and although the surface of the first ohmic electrode 321 sufficiently contacts the mounting surface, the second ohmic electrode 322 may not contact the mounting surface. This result can cause a short circuit and cannot be installed. Therefore, in order to increase the amount of deformation of the electrode, in general, bumps are provided on the first ohmic electrode 321 and the second ohmic electrode 322. However, the bumps must be formed thickly by Au (gold) or the like using a gold plating method or the like, and the material cost becomes extremely high.

另一方面,在實施例之中,窗層兼支承基板具有滑動面,作為其結果,形狀係為可變而發揮另外的功效。具體而言,於覆晶安裝時的發光元件晶片壓迫時,由於發光元件晶片會變形的緣故,在覆晶安裝之中不一定必須要凸塊。亦即,由於窗層兼支承基板具有滑動面的緣故,對於發光元件晶片壓迫會容易變形,第一歐姆電極121接觸於安裝面的同時,第二歐姆電極122也接觸於安裝面。由於第一歐姆電極121以及第二歐姆電極122兩者會接觸於安裝面的緣故,而能藉由超音波接合法等,在安裝面與電極之間形成堅固的接合。因此,如第23圖所示,實施例的第一歐姆電極與第二歐姆電極的段差即使在3μm以上11μm以下的範圍之中,也能不使用高價的凸塊,進行生產率良好的覆晶安裝。On the other hand, in the embodiment, the window layer-supporting substrate has a sliding surface, and as a result, the shape is variable and exerts another effect. Specifically, when the light-emitting element wafer is pressed during the flip chip mounting, the light-emitting element wafer is deformed, and the bump is not necessarily required in the flip chip mounting. That is, since the window layer and the support substrate have a sliding surface, the light-emitting element wafer is easily deformed by pressing, and the first ohmic electrode 121 is in contact with the mounting surface, and the second ohmic electrode 122 is also in contact with the mounting surface. Since both the first ohmic electrode 121 and the second ohmic electrode 122 are in contact with the mounting surface, a strong bonding can be formed between the mounting surface and the electrode by ultrasonic bonding or the like. Therefore, as shown in Fig. 23, even if the step difference between the first ohmic electrode and the second ohmic electrode of the embodiment is in the range of 3 μm or more and 11 μm or less, it is possible to perform the flip chip mounting with good productivity without using expensive bumps. .

此外,本發明並不限定於上述的實施例。上述實施例為舉例說明,凡具有與本發明的申請專利範圍所記載之技術思想實質上同樣之構成,產生相同的功效者,不論為何物皆包含在本發明的技術範圍內。Further, the present invention is not limited to the above embodiments. The above-described embodiments are exemplified, and those having substantially the same technical concept as those described in the claims of the present invention have the same effects, and are included in the technical scope of the present invention.

1‧‧‧發光元件晶片
11‧‧‧發光元件晶片
101‧‧‧起始基板
102‧‧‧選擇蝕刻層
102A‧‧‧第二選擇蝕刻層
102B‧‧‧第一選擇蝕刻層
103‧‧‧第一半導體層
103A‧‧‧低Al組成層
103B‧‧‧高Al組成層
104‧‧‧活性層
105‧‧‧第二半導體層
106‧‧‧緩衝層
107‧‧‧窗層兼支承基板
108‧‧‧發光部
109‧‧‧磊晶基板
110‧‧‧發光元件基板
121‧‧‧第一歐姆電極
122‧‧‧第二歐姆電極
122a‧‧‧預定範圍
123‧‧‧光阻遮罩
140‧‧‧範圍
141‧‧‧形成部
142‧‧‧刻劃範圍
150‧‧‧絕緣保護膜
170‧‧‧除去部
180‧‧‧非除去部
201‧‧‧發光元件晶片
301‧‧‧起始基板
302‧‧‧選擇蝕刻層
302A‧‧‧第二選擇蝕刻層
302B‧‧‧第一選擇蝕刻層
303‧‧‧第一半導體層
304‧‧‧活性層
305‧‧‧第二半導體層
306‧‧‧緩衝層
307‧‧‧電流擴散層
308‧‧‧發光部
309‧‧‧磊晶基板
310‧‧‧GaP單結晶基板
311‧‧‧發光元件基板
321‧‧‧第一歐姆電極
322‧‧‧第二歐姆電極
340‧‧‧範圍
342‧‧‧刻劃範圍
350‧‧‧絕緣保護膜
380‧‧‧非除去部
1‧‧‧Lighting element chip
11‧‧‧Lighting element chip
101‧‧‧Starting substrate
102‧‧‧Select etching layer
102A‧‧‧Second selective etching layer
102B‧‧‧First choice etching layer
103‧‧‧First semiconductor layer
103A‧‧‧Low Al composition
103B‧‧‧High Al layer
104‧‧‧Active layer
105‧‧‧Second semiconductor layer
106‧‧‧buffer layer
107‧‧‧Window layer and support substrate
108‧‧‧Lighting Department
109‧‧‧ epitaxial substrate
110‧‧‧Light-emitting element substrate
121‧‧‧First ohmic electrode
122‧‧‧Second ohmic electrode
122a‧‧‧Predetermined range
123‧‧‧Light-shielding mask
140‧‧‧Scope
141‧‧‧ Formation Department
142‧‧‧scribed range
150‧‧‧Insulation protective film
170‧‧‧Removal
180‧‧‧Non-removal department
201‧‧‧Lighting element chip
301‧‧‧Starting substrate
302‧‧‧Select etching layer
302A‧‧‧Second selective etching layer
302B‧‧‧First choice etching layer
303‧‧‧First semiconductor layer
304‧‧‧Active layer
305‧‧‧Second semiconductor layer
306‧‧‧buffer layer
307‧‧‧current diffusion layer
308‧‧‧Lighting Department
309‧‧‧ epitaxial substrate
310‧‧‧GaP single crystal substrate
311‧‧‧Light-emitting element substrate
321‧‧‧First ohmic electrode
322‧‧‧second ohmic electrode
340‧‧‧Scope
342‧‧‧scribed range
350‧‧‧Insulation protective film
380‧‧‧ Non-removal department

第1圖係顯示本發明的發光元件的安裝方法的一範例的步驟圖。 第2圖係顯示本發明的發光元件的安裝方法的於起始基板上成長有選擇蝕刻層、發光部及窗層兼支承基板的磊晶基板的概略圖。 第3圖係顯示本發明的發光元件的安裝方法的自磊晶基板去除起始基板以及第二選擇蝕刻層的發光元件基板的概略圖。 第4圖係顯示本發明的發光元件的安裝方法的形成有第一歐姆電極的發光元件基板的概略圖。 第5圖係顯示本發明的發光元件的安裝方法的已進行第一表面粗糙化處理的發光元件基板的概略圖。 第6圖係顯示本發明的發光元件的安裝方法的已進行除去部、段差形成步驟的發光元件基板的概略圖。 第7圖係顯示本發明的發光元件的安裝方法的形成有第二歐姆電極並且形成有絕緣保護膜的發光元件基板的概略圖。 第8圖係顯示本發明的發光元件的安裝方法的分離發光元件而製作的發光元件晶片的概略圖。 第9圖係實施例的已進行第一表面粗糙化處理的發光元件基板的概略圖。 第10圖係顯示實施例的已進行除去部、段差形成步驟的發光元件基板的概略圖。 第11圖係顯示實施例的形成有第二歐姆電極並且形成有絕緣保護膜的發光元件基板的概略圖。 第12圖係顯示實施例的分離發光元件而製作的發光元件晶片的概略圖。 第13圖係顯示比較例的於起始基板上成長有選擇蝕刻層、發光部及窗層兼支承基板的磊晶基板的概略圖。 第14圖係顯示比較例的於磊晶基板接合GaP單結晶基板的基板的概略圖。 第15圖係顯示比較例的自磊晶基板去除起始基板以及第二選擇蝕刻層的接合基板的概略圖。 第16圖係顯示比較例的形成有第一歐姆電極的接合基板的概略圖。 第17圖係顯示比較例的已進行第一表面粗糙化處理的接合基板的概略圖。 第18圖係顯示比較例的已進行除去部、段差形成步驟、形成有第二歐姆電極的接合基板的概略圖。 第19圖係顯示比較例的形成有絕緣保護膜的接合基板的概略圖。 第20圖係顯示比較例的分離發光元件而製作的發光元件晶片的概略圖。 第21圖係顯示實施例以及比較例的使用超音波進行安裝時的不良發生率的圖。 第22圖係顯示實施例以及比較例的使用共晶金屬層進行安裝時的不良發生率的圖。 第23圖係顯示實施例以及比較例的第一歐姆電極與第二歐姆電極的段差變化時的與直通率的關係的圖。Fig. 1 is a step diagram showing an example of a method of mounting a light-emitting element of the present invention. Fig. 2 is a schematic view showing an epitaxial substrate in which a selective etching layer, a light-emitting portion, and a window layer-supporting substrate are grown on a starting substrate in the method of mounting a light-emitting device of the present invention. Fig. 3 is a schematic view showing a light-emitting element substrate from an epitaxial substrate removal start substrate and a second selective etching layer in the method of mounting a light-emitting element of the present invention. Fig. 4 is a schematic view showing a light-emitting element substrate on which a first ohmic electrode is formed in a method of mounting a light-emitting element of the present invention. Fig. 5 is a schematic view showing a light-emitting element substrate on which the first surface roughening treatment has been performed in the method of mounting a light-emitting element of the present invention. Fig. 6 is a schematic view showing a light-emitting element substrate in which a removal portion and a step forming step are performed in the method of mounting a light-emitting element of the present invention. Fig. 7 is a schematic view showing a light-emitting element substrate in which a second ohmic electrode is formed and an insulating protective film is formed, in a method of mounting a light-emitting element of the present invention. Fig. 8 is a schematic view showing a light-emitting element wafer produced by separating a light-emitting element of a method of mounting a light-emitting element of the present invention. Fig. 9 is a schematic view showing a light-emitting element substrate on which the first surface roughening treatment has been performed in the embodiment. Fig. 10 is a schematic view showing a light-emitting element substrate in which the removal portion and the step difference forming step of the embodiment are shown. Fig. 11 is a schematic view showing a light-emitting element substrate of the embodiment in which a second ohmic electrode is formed and an insulating protective film is formed. Fig. 12 is a schematic view showing a light-emitting element wafer produced by separating the light-emitting elements of the embodiment. Fig. 13 is a schematic view showing an epitaxial substrate in which a selective etching layer, a light-emitting portion, and a window layer-supporting substrate are grown on a starting substrate in a comparative example. Fig. 14 is a schematic view showing a substrate of a comparative example in which a GaP single crystal substrate is bonded to an epitaxial substrate. Fig. 15 is a schematic view showing a bonded substrate from the epitaxial substrate removal starting substrate and the second selective etching layer of the comparative example. Fig. 16 is a schematic view showing a bonded substrate on which a first ohmic electrode is formed in a comparative example. Fig. 17 is a schematic view showing a bonded substrate on which the first surface roughening treatment of the comparative example is performed. Fig. 18 is a schematic view showing a removed portion, a step forming step, and a bonded substrate on which a second ohmic electrode is formed in a comparative example. Fig. 19 is a schematic view showing a bonded substrate on which an insulating protective film is formed in a comparative example. Fig. 20 is a schematic view showing a light-emitting element wafer produced by separating a light-emitting element of a comparative example. Fig. 21 is a view showing the occurrence rate of failure in the case of mounting using ultrasonic waves in the examples and the comparative examples. Fig. 22 is a graph showing the occurrence rate of defects in the case of mounting using a eutectic metal layer of the examples and the comparative examples. Fig. 23 is a graph showing the relationship with the through rate when the step difference between the first ohmic electrode and the second ohmic electrode of the examples and the comparative examples was changed.

Claims (5)

一種發光元件的安裝方法,包含下列步驟: 於起始基板上,以與該起始基板相晶格匹配系的材料,藉由磊晶成長而成長,依序形成第一半導體層、活性層、第二半導體層以及緩衝層; 於該緩衝層之上,以對於該起始基板為非晶格匹配系的材料,藉由磊晶成長而形成窗層兼支承基板; 去除該起始基板; 於該第一半導體層之上形成第一歐姆電極; 部分地形成使該第二半導體層、該緩衝層或是該窗層兼支承基板露出的除去部,而設置段差; 於該除去部形成第二歐姆電極; 將經形成有該第一及第二歐姆電極的發光元件予以分離而製作發光元件晶片,以及 於該安裝基板覆晶安裝該發光元件晶片,而使該發光元件晶片的經形成有該第一及第二歐姆電極之側成為安裝基板側。A method for mounting a light-emitting element, comprising the steps of: growing a material that is lattice-matched with the starting substrate on a starting substrate, growing by epitaxial growth, sequentially forming a first semiconductor layer, an active layer, a second semiconductor layer and a buffer layer; on the buffer layer, a material for the amorphous matrix matching system of the starting substrate is formed by epitaxial growth to form a window layer and a supporting substrate; removing the starting substrate; Forming a first ohmic electrode on the first semiconductor layer; partially forming a removal portion for exposing the second semiconductor layer, the buffer layer or the window layer and supporting substrate, and providing a step; forming a second portion in the removing portion An ohmic electrode; separating a light-emitting element formed with the first and second ohmic electrodes to form a light-emitting element wafer; and mounting the light-emitting element wafer on the mounting substrate, and forming the light-emitting element wafer The side of the first and second ohmic electrodes becomes the mounting substrate side. 如請求項1所述的發光元件的安裝方法,其中該第一半導體層、該活性層及該第二半導體層為AlGaInP或是AlGaAs。The method of mounting a light-emitting element according to claim 1, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are AlGaInP or AlGaAs. 如請求項1所述的發光元件的安裝方法,其中該窗層兼支承基板為GaP或是GaAsP。The method of mounting a light-emitting element according to claim 1, wherein the window layer and the support substrate are GaP or GaAsP. 如請求項2所述的發光元件的安裝方法,其中該窗層兼支承基板為GaP或是GaAsP。The method of mounting a light-emitting element according to claim 2, wherein the window layer and the support substrate are GaP or GaAsP. 如請求項1至4中任一項所述的發光元件的安裝方法,其中該第一歐姆電極與該第二歐姆電極的段差為3μm以上11μm以下。The method of mounting a light-emitting element according to any one of claims 1 to 4, wherein a step difference between the first ohmic electrode and the second ohmic electrode is 3 μm or more and 11 μm or less.
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