CN112993138B - Chip substrate and manufacturing method thereof - Google Patents
Chip substrate and manufacturing method thereof Download PDFInfo
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- CN112993138B CN112993138B CN202011140930.9A CN202011140930A CN112993138B CN 112993138 B CN112993138 B CN 112993138B CN 202011140930 A CN202011140930 A CN 202011140930A CN 112993138 B CN112993138 B CN 112993138B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 title claims abstract description 57
- 239000002184 metal Substances 0.000 claims abstract description 174
- 229910052751 metal Inorganic materials 0.000 claims abstract description 174
- 238000000034 method Methods 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 50
- 238000002161 passivation Methods 0.000 claims description 38
- 230000001154 acute effect Effects 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
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- 230000036544 posture Effects 0.000 description 25
- 239000004065 semiconductor Substances 0.000 description 16
- 239000000084 colloidal system Substances 0.000 description 13
- 230000000694 effects Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
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- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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Abstract
The application provides a chip substrate manufacturing method, an epitaxial structure containing a metal layer is bonded with a display back plate, and then the part of the bonded epitaxial structure except the metal layer is etched to form a plurality of mutually separated epitaxial layers. And forming a mask layer on the epitaxial layer, and etching the metal layer under the shielding of the mask layer to obtain a plurality of mutually independent metal layers. After the etching is finished, a metal film layer can be formed on the side edge of the mask layer, and the display back plate after the etching is finished is placed on an inclined base, so that the metal film layer can be removed by etching. The method removes the residues of the metal film layer in the manufacturing process of the chip substrate, and can avoid the short circuit phenomenon caused by the metal film layer. The application also relates to a chip substrate prepared by the method.
Description
Technical Field
The invention relates to the technical field of chip manufacturing, in particular to a manufacturing method of a chip substrate and the chip substrate manufactured by the method.
Background
In the manufacturing process of the chip substrate with the vertical structure, the display back plate and the epitaxial structure are bonded in a metal bonding mode, and then the epitaxial structure is etched. In this process, the bonded epitaxial structure is usually etched to form a plurality of mutually separated epitaxial layers, and the metal layer is divided by using an ion beam dry etching technique (IBE) to obtain a plurality of P electrodes. In the dividing process, the sputtered metal debris can accumulate along the mask layer and form a metal film layer attached to the side surface of the mask layer. The accumulated metal film layer cannot be removed by a photoresist stripping process.
Due to the defects, when the display back plate is coated at a later stage, the position of the accumulated metal film layer is not easy to be coated with the passivation layer, or the coated passivation layer is easy to break at the position, so that the short circuit possibly occurs in the subsequent chip manufacturing process.
Disclosure of Invention
The application aims to overcome the defects in the prior art, and provides a manufacturing method of a chip substrate, so as to remove a metal film layer possibly appearing in the process of manufacturing the chip substrate and avoid the phenomenon of short circuit, and the manufacturing method specifically comprises the following technical scheme:
a chip substrate manufacturing method comprises the following steps:
providing an epitaxial structure; the epitaxial structure comprises a metal layer;
bonding one surface of the epitaxial structure, which is provided with the metal layer, with a display back plate;
etching the bonded epitaxial structure to form a plurality of mutually separated epitaxial layers;
respectively forming a mask layer on each epitaxial layer, and etching the bonded metal layer under the shielding of the mask layer; a metal film layer is formed on the side surface of the mask layer in the process of etching the metal layer;
placing the etched display back plate on a base to etch the metal film layer on the side face of the mask layer; wherein, the one side that base and display backplate contacted is relative horizontal plane slope.
According to the chip substrate manufacturing method, one surface of the epitaxial structure, which is provided with the metal layer, is bonded with the display back plate, and the epitaxial structure is etched, so that a plurality of mutually separated epitaxial layers can be obtained. And then, respectively forming the mask layer on each epitaxial layer, etching the metal layer, and forming the metal film layer on the side surface of the mask layer after etching. According to the method, the display back plate is placed on the inclined base, and the metal film layer is etched, so that the purpose of removing the metal film layer accumulated on the side face of the mask layer is achieved. According to the chip substrate manufacturing method, in the subsequent manufacturing process, the subsequent layer structure damage caused by the metal film layer can be prevented, and therefore the phenomenon of short circuit in the chip manufacturing process is avoided.
Optionally, the pedestal is controlled to rotate or swing in the process of etching the metal film layer on the side of the mask layer.
The base is controlled and the posture of the base is adjusted in a rotating or swinging mode, so that the metal film layer accumulated on each side surface of the mask layer can be exposed to etching beams.
Optionally, an included angle β between the surface of the base, which is in contact with the display back plate, and the horizontal plane satisfies the condition: beta is more than or equal to 15 degrees and less than or equal to 32 degrees.
The limitation of the angle between the base and the horizontal plane is convenient for etching and removing the metal film layer accumulated on the edge of the mask layer, and the stability of the display back plate placed on the base can be ensured.
Optionally, an included angle α between the side on which the metal film layer is formed and the horizontal plane is an acute angle.
An included angle alpha is formed between the side face where the metal film layer is formed and the horizontal plane, so that the sputtered metal film layer can be relatively concentrated in accumulation.
Optionally, the included angle α satisfies the condition: alpha is more than or equal to 50 degrees and less than or equal to 75 degrees.
The limitation of the included angle alpha can lead the metal film layers to be accumulated in a concentrated mode, and all the metal film layers can be removed conveniently in the later period.
Optionally, the thickness h of the mask layer satisfies the condition: h is more than or equal to 1 mu m and less than or equal to 3 mu m.
The mask layer has enough thickness to better protect the epitaxial layer and avoid the damage of the epitaxial layer caused by the synchronous etching of the mask layer.
Optionally, the method further includes:
removing the mask layer, and manufacturing a passivation layer to cover the display back plate;
and manufacturing an electrode at the position of the passivation layer corresponding to the epitaxial layer.
Because the accumulated metal film layer is eliminated, the metal layer and the electrode are not easy to generate short circuit in the bonding process, so that the metal layer and the electrode which are mutually insulated can be manufactured, and the effect of driving the epitaxial layer to emit light is achieved.
Optionally, the passivation layer covers the epitaxial layer, the metal layer, and the display backplane at the same time.
And manufacturing the passivation layer to cover the display back plate and ensure the insulation of the epitaxial layer and the metal layer. So as to facilitate the subsequent fabrication of the electrode.
Optionally, the manufacturing of the electrode at the position of the passivation layer corresponding to the epitaxial layer includes:
patterning the passivation layer to expose a portion of the epitaxial layer;
and depositing a conductive material on the exposed epitaxial layer to manufacture and form the electrode.
And the conductive material is filled, so that the conduction between the electrode and the metal layer can be realized, and the effect of enabling the epitaxial structure to emit light is achieved.
The application also provides a chip substrate which is manufactured by the manufacturing method of the chip substrate.
According to the chip substrate, the accumulation of the metal film layer is avoided, the passivation layer fracture caused by the accumulation of the metal film layer can be prevented in the subsequent manufacturing process of the passivation layer and the electrode, and the phenomenon of short circuit in the manufacturing process of the chip substrate is avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic view of a chip substrate provided by the present invention;
FIG. 2 is a flow chart of a method for fabricating a chip substrate according to the present invention;
FIG. 3 is a schematic structural diagram of steps S10 and S20 in the method for manufacturing a chip substrate according to the present invention;
FIG. 4 is a schematic structural diagram of step S30 in the method for manufacturing a chip substrate according to the present invention;
FIG. 5 is a schematic structural diagram of step S40 in the method for manufacturing a chip substrate according to the present invention;
FIG. 6 is a schematic structural diagram of step S50 in the method for manufacturing a chip substrate according to the present invention;
FIG. 7 is a schematic structural diagram of step S50 in the method for manufacturing a chip substrate according to the present invention;
FIGS. 8-10 are schematic views of structures in a prior art etching process;
FIGS. 11-16 are flow diagrams of other embodiments of methods for fabricating a chip substrate according to the present invention;
fig. 17 is a schematic diagram of another embodiment of a chip substrate provided by the present invention.
Description of reference numerals:
01-a chip substrate; 1-a display backplane; 2-an epitaxial structure; 21-a metal layer; 22-an epitaxial layer; 3-a mask layer; 4-a metal film layer; 5-a passivation layer; 51-via holes; 6-a base; 7-an electrode; 8-a device; 221-a first semiconductor layer; 222-a second semiconductor layer; 223-a light emitting layer;
-a first rotating shaft;
-a second rotational axis; 001-first direction; 010-a first end; 020-second end; 601-first pose; 602-a second pose; 301-a first side; 302-a second side; 303-upper surface; 31-a first colloid; 32-second colloid.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without any inventive step, are within the scope of the present invention.
Furthermore, the following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. Directional phrases used in this disclosure, such as, for example, "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer only to the orientation of the appended drawings and are, therefore, used herein for better and clearer illustration and understanding of the invention, and do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Please refer to fig. 1, which illustrates a chip substrate 01 according to the present application. The chip substrate 01 includes a display backplane 1 and at least one device 8 disposed on the display backplane 1. The device 8 is typically a plurality, and the plurality of devices 8 is typically arranged in an array on the chip substrate 01. Each device 8 comprises a metal layer 21, an electrode 7 arranged in correspondence of the metal layer 21, and an epitaxial layer 22 arranged between the metal layer 21 and the electrode 7. The electrode 7 is usually made of a transparent material, and a voltage difference formed after the metal layer 21 and the electrode 7 are conducted can drive the epitaxial layer 22 to emit light, so that the chip substrate 01 can achieve a display effect. In other embodiments, the chip substrate 01 may also be used to specially manufacture a single color device, such as a green (G) light emitting device or a blue (B) light emitting device, and the single color light emitting device on the chip substrate 01 may be transferred onto the display panel by bulk transfer, so as to realize the light emitting function of the display panel.
Referring to fig. 2, a flow chart of a method for manufacturing a chip substrate provided by the present invention specifically includes the following steps:
s10, providing an epitaxial structure 2; the epitaxial structure 2 comprises a metal layer 21;
specifically, referring to fig. 3, the epitaxial structure 2 includes a metal layer 21 and each individual epitaxial layer 22 that is formed by etching in the subsequent process, the epitaxial layer 22 includes a first semiconductor layer 221, a light emitting layer 223 and a second semiconductor layer 222, and the metal layer 21 may be made of a tin-copper alloy or other materials. The epitaxial structure 2 is arranged on the display back plate 1, and the epitaxial structure 2 is connected with the display back plate 1 in a metal bonding mode. And the epitaxial structure is a composite layer structure, and specifically includes a metal layer 21, a first semiconductor layer 221, a light emitting layer 223, and a second semiconductor layer 222. The first semiconductor layer 221 is located between the metal layer 21 and the light emitting layer 223, and the light emitting layer 223 is located between the first semiconductor layer 221 and the second semiconductor layer 222. The first semiconductor layer 221 and the metal layer 21 are electrically connected, and after the two layers are respectively conducted and form a voltage difference, a corresponding light is formed in the light emitting layer 223 to be emitted, so as to achieve a display function.
S20, bonding the side of the epitaxial structure 2 with the metal layer 21 with a display backboard 1;
specifically, with reference to fig. 3, the epitaxial structure 2 includes a metal layer 21, a first semiconductor layer 221, a light emitting layer 223, and a second semiconductor layer 222, and one side of the epitaxial structure 2 having the metal layer 21 is bonded to the display backplane 1 to form a layer structure of the display backplane 1, the metal layer 21, the first semiconductor layer 221, the light emitting layer 223, and the second semiconductor layer 222, which are sequentially arranged, so that in a manufacturing process of the chip substrate 01, after the independent epitaxial layers 22 are formed, the metal layer 21 on the display backplane 1 is etched, and thus the independent metal layers 21 can be obtained.
S30, etching the bonded epitaxial structure 2 to form a plurality of mutually separated epitaxial layers 22;
specifically, referring to fig. 4, before etching the metal layer 21, the first semiconductor layer 221, the light emitting layer 223, and the second semiconductor layer 222 in the epitaxial structure 2 need to be etched to obtain a plurality of epitaxial layers 22 arranged at intervals. A part of the metal layer 21 is exposed between any two adjacent epitaxial layers 22, and a plurality of epitaxial layers 22 arranged at intervals are arranged on the metal layer 21 in a matrix shape.
S40, respectively forming a mask layer 3 on each epitaxial layer 22, and etching the bonded metal layer 21 under the shielding of the mask layer 3; wherein, a metal film layer 4 is formed on the side surface of the mask layer 3 in the process of etching the metal layer 21;
specifically, referring to fig. 5, the mask layer 3 is fabricated to cover each epitaxial layer 22, and since the back plate 1 is shown to have a plurality of epitaxial layers 22 spaced from each other, each mask layer 3 can cover a plurality of epitaxial layers 22, that is, one mask layer 3 and one epitaxial layer 22 are matched with each other to form an independent structure. Defining an upper surface 303 on which the epitaxial layer 22 is formed after etching, and a first side 301 and a second side 302 connected to the upper surface 303 from both sides of the epitaxial layer 22, respectively. Alternatively described, the epitaxial layer 22 includes first and second sides 301 and 302 opposite to each other on both sides, and an upper surface 303 on the top, and the upper surface 303 is connected between the top of the first side 301 and the top of the second side 302. At this time, each individual mask layer 3 covers the upper surface 303, the first side 301, and the second side 302 of each individual epitaxial layer 22, respectively. And the mask layer 3 comprises a first colloid 31 covering the upper surface 303 of each epitaxial layer 22 and a second colloid 32 covering the first side 301 and the second side 302 of the epitaxial layer 22. The exposed metal layer 21 is dry-etched under the mask of the mask layer 3, to obtain a plurality of metal layers 21 spaced apart from each other. At this time, there is no metal connection between two adjacent metal layers 21, and mutually independent structures are formed. The positions of the metal layers 21 correspond to the positions of the epitaxial layers 22 one by one, and because the mask layer 3 shields the epitaxial layers 22, part of light which would be irradiated onto the metal layers 21 in the etching process can be blocked by the mask layer 3 coated on the epitaxial layers 22, so that the width between the metal layers 21 is greater than the width of the corresponding epitaxial layers 22.
After the step, a mask layer covering the epitaxial layer 22 is reserved near the position corresponding to each epitaxial layer 22 on the chip substrate 01, and the accumulation of the metal film layer 4 is formed on the side surface of the mask layer 3 in the process of etching the metal layer 21. According to the method, the epitaxial layer 22 and a part of the metal layer 21 are coated by arranging the mask layer 3, and meanwhile, the epitaxial layer 22 and a part of the metal layer 21 are protected. The metal film layer 4 formed in the step can be attached to the mask layer 3, and the metal film layer 4 is separated from the epitaxial layer 22 and a part of the metal layer 21, so that direct lap joint between the metal film layer 4 and the epitaxial layer 22 or the metal layer 21 is avoided.
S50, placing the etched display back plate 1 on a base 6 to etch the metal film layer 4 on the side surface of the mask layer 3; wherein, the surface of the base 6 contacted with the display back plate 1 is inclined relative to the horizontal plane.
Specifically, please refer to fig. 6 and 7 in combination, the display back plate 1, the epitaxial layer 22 disposed on the display back plate 1, and the mask layer 3 attached with the metal film layer 4 are disposed on the base 6, and the base 6 is successively in a first posture 601 and a second posture 602, where fig. 6 and 7 are two different postures of the base 6, respectively, where fig. 6 is the first posture 601 of the base 6, and fig. 7 is the second posture 602 of the base 6. Because the edge of the mask layer 3 is attached to the accumulated metal film layer 4, the base 6 can expose the metal film layers 4 at two sides of the split mask layer 3 in two postures, which is beneficial to further etching the accumulated metal film layer 4 in the step, and thus the mask layer 3 without the attachment of the metal film layer 4 is obtained.
The application provides a manufacturing method of a chip substrate 01, which comprises the steps of providing an epitaxial structure 2 comprising a metal layer 21, bonding one surface, provided with the metal layer 21, of the epitaxial structure 2 with a display back plate 1, etching the part, except the metal layer 21, of the bonded epitaxial structure 2 to form a plurality of mutually separated epitaxial layers 22, forming each mask layer 3 on each epitaxial layer 22, and etching the metal layer 21 under the shielding of the mask layer 3. Wherein, the side of mask layer 3 can form a metal film layer 4 in the etching process, and this application is placed on a base 6 through the demonstration backplate 1 after accomplishing the sculpture, and the slope of placing through base 6 drives the slope of showing backplate 1 and places and make metal film layer 4 can be got rid of by the sculpture. Compared with the situation that the metal film layer 4 cannot be removed in the prior art, the method and the device avoid the phenomenon that the metal film layer 4 is accumulated on the metal layer 21, so that the poor insulating covering effect of the subsequent passivation layer 5 is caused.
Referring to fig. 8, in the prior art, the epitaxial layer 22 is coated with the mask layer 3, and after the metal layer 21 is dry-etched, the metal film layer 4 is accumulated along the side surface of the mask layer 3. When the mask layer 3 is removed, the formed metal film layer 4 cannot be removed by a photoresist stripping method, and thus each metal layer 21 with the metal film layer 4 remaining is obtained as shown in fig. 8.
Referring to fig. 9 and fig. 10, the metal layer 4 formed on the metal layer 21 may cause the passivation layer 5 at the metal layer 4 to be not easily plated and/or the passivation layer 5 plated at the metal layer 4 to be easily broken in the subsequent manufacturing process of the passivation layer 5. Both cases shown in fig. 9 and 10 result in a short circuit phenomenon due to the metal film layer 4. Compared with the prior art, the display back plate 1, the epitaxial layer 22 and the mask layer 3 are driven by the base 6 to be in different postures respectively and are subjected to dry etching to remove the metal film layer 4 formed in the chip manufacturing process, so that no metal film layer 4 is left in the manufacturing process of the chip substrate, and the short circuit phenomenon caused by the metal film layer 4 can be avoided.
Referring to fig. 11, in an etching method provided in the present application, step S50 "placing the etched display back panel 1 on a base 6 to etch the metal film 4 on the side of the mask layer 3" may further include:
s50b, controlling the pedestal 6 to rotate or swing in the process of etching the metal film layer 4 on the side surface of the mask layer 3.
Specifically, in the present embodiment, please refer to fig. 6 and 7, the direction perpendicular to the inclined plane of the base 6 is defined to have a first rotation axis Φ1The base 6 drives the epitaxial layer 22 and the mask layer 3 covering the epitaxial layer 22 to be in the first posture 601 or the second posture 602 in sequence, wherein the first posture 601 is a state that the first end 010 is higher than the second end 020, and at this time, the metal film layer 4 close to one side of the first end 010 is exposed in a range irradiated by the etching beam; the second attitude 602 is a state in which the second end 020 is higher than the first end 010, and the metal film layer 4 on the side close to the second end 020 is exposed to the range irradiated by the etching beam. In the first posture 601, the base 6 drives the epitaxial layer 22 and the mask layer 3 coated on the epitaxial layer 22 to rotate around the first rotation axis phi1Rotating and synchronously carrying out dry etching on the metal film layer 4 attached to the side surface of the mask layer 3. Or, when the base 6 is in the first posture 601, the metal film 4 near the first end 010 is more exposed to the range irradiated by the etching beam and is removed by dry etching, and at this time, the base 6 drives the epitaxial layer 22 and the mask layer 3 covering the epitaxial layer 22 to rotate around the first rotation axis phi1When the base 6 is rotated to the second posture 602, the metal film layer 4 near the second end 020 side is more exposed to the irradiation range of the etching beam and is also removed by the dry etching when the base is rotated to the second posture 602.
It can also be defined in this step to have a second direction parallel to the bottom surface of the base 6 and perpendicular to said first direction 001Axis of rotation phi2(not shown, second axis of rotation phi)2In a direction perpendicular to the paper). The base 6 passes around a second axis of rotation phi2The heights of the first end 010 and the second end 020 are adjusted by swinging, and the base 6 drives the epitaxial layer 22 and the mask layer 3 coated on the epitaxial layer 22 to be in the first posture 601 and the second posture 602 in sequence, so that the effect of removing the metal film layers 4 attached to the two opposite edges of the mask layer 3 by dry etching is achieved.
It should be noted that, in this embodiment, only the scheme of two postures that the base 6 needs to be in is provided, and a method of respectively placing the base in the two postures by rotating and swinging is synchronously provided. However, the posture of the base 6 in the chip substrate manufacturing method in the present application does not only include the above two movement modes, but also includes all postures and all posture adjustment methods capable of adjusting the posture of the base 6 to perform etching to remove the metal film layer 4 attached to the edge of the mask layer 3.
Referring to fig. 12, in an embodiment of the present invention, in step S50, "a surface of the base 6 contacting the display backplane 1 is inclined with respect to a horizontal plane", the method may further include:
s50a, an included angle beta between the surface of the base 6 contacted with the display back plate 1 and the horizontal plane satisfies the condition: beta is more than or equal to 15 degrees and less than or equal to 32 degrees.
Specifically, in this embodiment, the display back plate 1, the metal layer 21, the epitaxial layer 22, the mask layer 3 coated on the epitaxial layer 22, and the metal film layer 4 attached to the side of the mask layer 3 are placed on the base 6, and the base 6 is successively in the first posture 601 and the second posture 602, so that the etching of the metal film layer 4 by the etching light beam can be realized, and after the included angle β between the contact surface of the base 6 and the display back plate 1 and the horizontal plane meets the condition that β is not less than 15 ° and not more than 32 °, it can be ensured that all the metal film layers 4 attached to the mask layer 3 can be exposed in the irradiation range of the etching light beam, and the etching of the metal film layers can achieve the purpose of removing all the metal film layers 4.
In an embodiment, referring to fig. 13, in step S40, "a metal film layer 4 is formed on a side surface of a mask layer 3 during etching a metal layer 21" in an etching method provided in the present application, which may further include:
s41a, the side on which the metal film layer 4 is formed and the horizontal plane form an acute angle α.
Specifically, in this embodiment, the manufactured mask layer 3 is made of a positive photoresist material, the mask layer 3 formed by the positive photoresist is usually easy to be manufactured into a trapezoid structure, and an included angle α between a side surface of the mask layer 3 on which the metal film layer 4 is formed and a horizontal plane is an acute angle, that is, the mask layer 3 manufactured into the trapezoid structure wraps the epitaxial layer 22. Further, the mask layer 3 includes a first colloid 31 covering the upper surface 303 of each epitaxial layer 22 and a second colloid 32 formed on the first side 301 and the second side 302 of the epitaxial layer 22. In order to etch the metal layer 21, a gap is formed between the adjacent second colloids 32, so that an etching beam can directly irradiate the metal layer 21 and etch the metal layer 21. And because the shape of the mask layer 3 is limited, the distance of the bottom of the second colloid 32 is greater than the distance of the top of the second colloid 32, and the distance of the bottom of the second colloid 32 can affect the size of the interval between the metal layers 21, and if the distance of the bottom of the second colloid 32 is greater, the distance between the etched metal layers 21 is also greater.
Referring to fig. 13, for the step S40a "the included angle α between the side surface where the metal film layer 4 is formed and the horizontal plane is an acute angle", the following embodiments may be further included:
s42a, the included angle alpha satisfies the condition: alpha is more than or equal to 50 degrees and less than or equal to 75 degrees.
Specifically, in the present embodiment, based on the current state of the art at the present stage, it is usually easy to prepare the mask layer 3 having a trapezoid structure to wrap the epitaxial layer 22 during the manufacturing process of the mask layer 3. Further, due to the limitation of the process technology, when the epitaxial layer 22 is coated by the mask layer 3, a certain included angle is formed between the bevel edge of the mask layer 3 and the horizontal direction, and the included angle α satisfies the condition: alpha is more than or equal to 50 degrees and less than or equal to 75 degrees. At this moment, the accumulation of the metal film layer 4 can be conveniently realized in the process of etching the metal layer 21, the metal film layer can be well attached to the side edge of the mask layer 3, and the mask layer 3 is used for preventing the lap joint between the metal film layer 4 and the metal layer 21 from causing short circuit.
In an embodiment, referring to fig. 11 again, the step S40 "of forming a mask layer 3 on each epitaxial layer 22" may further include:
s40b, the thickness h of the mask layer 3 satisfies the condition: h is more than or equal to 1 mu m and less than or equal to 3 mu m.
Specifically, in the present embodiment, due to the limitation of industrial technology, the mask layer 3 has a trapezoidal shape, and the mask layer 3 covering the epitaxial layer 22 has a layer thickness, and when the layer thickness of the mask layer 3 satisfies the condition: when h is more than or equal to 1 μm and less than or equal to 3 μm, the mask layer 3 can be ensured to form better protection on the epitaxial layer 22, and the epitaxial layer 22 is ensured not to be damaged in the manufacturing process of etching the metal layer 21. In addition, in the process of etching the metal layer 21, the light may also have a certain etching effect on the mask layer 3, and if the thickness of the layer between the top of the mask layer 3 having the trapezoid structure and the upper surface 303 of the epitaxial layer 22 is too low, the top of the mask layer 3 may be completely etched, thereby damaging the upper surface 303 of the epitaxial layer 22. However, if the layer thickness is too large, process waste may result, resulting in too high a cost in the actual etching process of the metal layer 21. It should be noted that the thickness of the mask layer 3 provided in this step is the thickness of the first colloid 31 and the second colloid 32.
Referring to fig. 14, in step S50 of the method for manufacturing a chip substrate provided in the present application, after the display backplane 1 after etching is placed on a base 6 to etch a metal film layer 4 on a side of a mask layer 3, the following embodiments are further included:
s60, removing the mask layer 3, and manufacturing a passivation layer 5 to cover the display back plate 1;
and S70, manufacturing an electrode 7 at the position of the passivation layer 5 corresponding to the epitaxial layer 22.
Specifically, in this embodiment, the metal layer 21 without the metal film layer 4 accumulated can be obtained through steps S10 to S50, so that the metal film layer 4 does not exist on the formed chip substrate 01, at this time, the next step may be performed, that is, all the mask layers 3 are removed, the passivation layer 5 is manufactured to cover the display back plate 1, and the electrodes 7 are manufactured at positions corresponding to the respective epitaxial layers 22, so that the respective metal layers 21 can be electrically connected to the respective electrodes 7 through the passivation layer 5. The electrode 7 can also be used for making a lead wire on the side of the passivation layer 5 far away from the display back plate 1 to realize circuit conduction with an external signal, and in cooperation with the metal layers 21 which are formed in the above step in a patterning mode and are spaced from each other, a voltage difference is formed, and the epitaxial layer 22 is driven to realize a light emitting effect.
In an embodiment, referring to fig. 15, regarding step S60 "removing the mask layer 3 and manufacturing the passivation layer 5 to cover the display back plate 1", the method may further include:
s60a, removing the mask layer 3, and fabricating a passivation layer 5 simultaneously covering the epitaxial layer 22, the metal layer 21 and the display back plate 1.
Specifically, in this embodiment, before the passivation layer 5 is fabricated, all the mask layers 3 need to be removed, that is, all the mask layers 3 coated on the epitaxial layer 22 need to be removed, at this time, a plurality of epitaxial layers 22 arranged at intervals are retained on the display back plate 1, an independent metal layer 21 is formed between each epitaxial layer 22 and the display back plate 1, and a gap is formed between any two metal layers 21, so that a part of the display back plate 1 is exposed. That is, the display back plate 1 has a plurality of structures formed thereon and spaced apart from each other, each structure including the metal layer 21 and the epitaxial layer 22. At this time, the passivation layer 5 is formed on the exposed portions of the epitaxial layer 22, the metal layer 21 and the display back plate 1 to cover the epitaxial layer 22, the metal layer 21 and the display back plate 1. Alternatively, the passivation layer 5 is formed to cover the upper surface 303, the first side surface 301 and the second side surface 302 of the plurality of epitaxial layers 22, and the exposed portions of the metal layer 21 and the display backplane 1. The passivation layer 5 is provided so that each structure on the display back plate 1 is in an insulating state.
Referring to fig. 16, for the step S70 "forming the electrode 7 at the position of the passivation layer 5 corresponding to the epitaxial layer 22", the method may further include:
s71, patterning the passivation layer 5 to expose part of the epitaxial layer 22;
s72, depositing a conductive material on the exposed epitaxial layer 22 to form the electrode 7.
Specifically, in the present embodiment, the passivation layer 5 is provided to achieve insulation between the metal layer 21 and the epitaxial layer 22 and the electrode 7, respectively, and achieve the light emitting effect of the epitaxial layer 22 through cooperation of the electrode 7 and the metal layer 21. The process of patterning the passivation layer 5 includes the steps of manufacturing via holes 51 at positions, corresponding to the epitaxial layer 22, of the passivation layer 5, and conducting all the leads through the via hole 51 structure, so that the electrodes 7 and the epitaxial layer 22 are conducted, and the electrodes 7 and a circuit of an external signal are conducted, and the via holes 51 provide paths for the leads, and therefore, the display effect of the epitaxial layer 22 can be achieved.
The application also provides a chip substrate 01, please refer to the chip substrate 01 shown in fig. 17, which is prepared by the above chip substrate manufacturing method. Chip substrate 01 includes that display backplate 1 and the at least one device 8 on the display backplate 1, device 8 include metal level 21, epitaxial layer 22 and electrode 7, and epitaxial layer 22 sets up between metal level 21 and electrode 7, and the voltage difference that forms after metal level 21 and electrode 7 switched on can drive epitaxial layer 22 and give out light, reaches the display effect of this application chip substrate 01. It can be understood that, the chip substrate 01 prepared by the above method can prevent the passivation layer 5 from being broken due to the metal film layer 4 in the later coating process of the passivation layer 5 because the metal film layer 4 is prevented from being formed cumulatively, and can effectively prevent the chip substrate 01 from being short-circuited. It should be noted that, the specific structures of the chip substrate 01 of the present application can be obtained by one-to-one correspondence based on the above method embodiments, and the present application is not further described herein.
The foregoing is illustrative of embodiments of the present invention, and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the embodiments of the present invention and are intended to be within the scope of the present invention.
Claims (9)
1. A chip substrate manufacturing method is characterized by comprising the following steps:
providing an epitaxial structure; the epitaxial structure comprises a metal layer;
bonding one surface of the epitaxial structure, which is provided with the metal layer, with a display back plate;
etching the bonded epitaxial structure to form a plurality of mutually separated epitaxial layers;
respectively forming a mask layer on each epitaxial layer, and etching the bonded metal layer under the shielding of the mask layer; a metal film layer is formed on the side surface of the mask layer in the process of etching the metal layer;
placing the etched display back plate on a base to etch the metal film layer on the side face of the mask layer; wherein, the one side that base and display backplate contacted is relative horizontal plane slope.
2. The method of claim 1, wherein the pedestal is controlled to rotate or swing during the etching of the metal film layer on the side of the mask layer.
3. The method for manufacturing a chip substrate according to claim 1, wherein an included angle between a surface of the base, which is in contact with the display back plate, and a horizontal plane is
The conditions are satisfied: 15 degrees is less than or equal to
≤32°。
4. The method for manufacturing a chip substrate according to claim 1, wherein an included angle α between the side surface on which the metal film layer is formed and a horizontal plane is an acute angle.
5. The method for manufacturing a chip substrate according to claim 4, wherein the included angle α satisfies a condition: alpha is more than or equal to 50 degrees and less than or equal to 75 degrees.
6. The method for manufacturing a chip substrate according to claim 1, wherein a layer thickness h of the mask layer satisfies a condition: h is more than or equal to 1 mu m and less than or equal to 3 mu m.
7. The method for fabricating a chip substrate according to claim 1, further comprising:
removing the mask layer, and manufacturing a passivation layer to cover the display back plate;
and manufacturing an electrode at the position of the passivation layer corresponding to the epitaxial layer.
8. The method for manufacturing a chip substrate according to claim 7, wherein the passivation layer covers the epitaxial layer, the metal layer and the display back plate at the same time.
9. The method for manufacturing a chip substrate according to claim 7, wherein the manufacturing of the electrode at the position of the passivation layer corresponding to the epitaxial layer comprises:
patterning the passivation layer to expose a portion of the epitaxial layer;
and depositing a conductive material on the exposed epitaxial layer to manufacture and form the electrode.
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| WO2019226788A1 (en) * | 2018-05-24 | 2019-11-28 | Lumiode, Inc. | Led display structures and fabrication of same |
| JP6570702B1 (en) * | 2018-05-29 | 2019-09-04 | 日機装株式会社 | Semiconductor light emitting device and method for manufacturing semiconductor light emitting device |
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| CN101728314A (en) * | 2008-10-24 | 2010-06-09 | 和舰科技(苏州)有限公司 | Novel metal etching method |
| CN101814455A (en) * | 2009-02-19 | 2010-08-25 | 乐金显示有限公司 | Method of fabricating array substrate |
| WO2017047011A1 (en) * | 2015-09-15 | 2017-03-23 | 信越半導体株式会社 | Method of mounting light-emitting element |
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