TWI796504B - Manufacturing method of semiconductor element and semiconductor substrate - Google Patents

Manufacturing method of semiconductor element and semiconductor substrate Download PDF

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TWI796504B
TWI796504B TW108125348A TW108125348A TWI796504B TW I796504 B TWI796504 B TW I796504B TW 108125348 A TW108125348 A TW 108125348A TW 108125348 A TW108125348 A TW 108125348A TW I796504 B TWI796504 B TW I796504B
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substrate
thin film
semiconductor thin
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island
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TW201941270A (en
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荻原光彦
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日商菲爾尼克斯股份有限公司
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Abstract

本發明的半導體元件的製造方法包括:形成作為薄膜的 固定層的步驟,所述固定層將半導體薄膜層的與母材基板一側為相反側的主面的至少一部分與母材基板中的半導體薄膜層一側的面的至少一部分結合;藉由將半導體薄膜層或母材基板的一部分區域去除而形成空隙的步驟;於形成空隙後,於半導體薄膜層的主面將形成於拾取基板的有機材料層與固定層結合的步驟;於有機材料層結合於固定層的狀態下將拾取基板沿與母材基板相離的方向移動,藉此將半導體薄膜層自第1基板分離的步驟;以及將自母材基板分離後的半導體薄膜層接合於第2基板的步驟。 The manufacturing method of the semiconductor element of the present invention comprises: forming as thin film A step of fixing the layer, the fixing layer combines at least a part of the main surface of the semiconductor thin film layer on the side opposite to the base substrate side with at least a part of the surface of the semiconductor thin film layer in the base substrate; The step of removing a part of the semiconductor thin film layer or the base substrate to form a void; after forming the void, the step of combining the organic material layer formed on the pick-up substrate with the fixed layer on the main surface of the semiconductor thin film layer; combining the organic material layer A step of separating the semiconductor thin film layer from the first substrate by moving the pick-up substrate in a direction away from the base substrate while the layer is fixed; and bonding the semiconductor thin film layer separated from the base substrate to the second substrate. Substrate steps.

Description

半導體元件的製造方法與半導體基板 Manufacturing method of semiconductor element and semiconductor substrate

本發明是有關於一種半導體元件的製造方法。 The present invention relates to a manufacturing method of a semiconductor element.

先前已知有一種將半導體磊晶層自母材基板拆下並移至其他基板的技術(例如參照專利文獻1)。 Conventionally, there is known a technique for removing a semiconductor epitaxial layer from a base substrate and moving it to another substrate (for example, refer to Patent Document 1).

[現有技術文獻] [Prior art literature]

[專利文獻] [Patent Document]

[專利文獻1]日本專利第3813123號公報 [Patent Document 1] Japanese Patent No. 3813123

圖22是用以說明現有技術的圖。圖22示出了包括母材基板3001、犧牲層3002、半導體磊晶層3003、以及支持體3004的半導體結構。犧牲層3002設置於半導體磊晶層3003與母材基板3001之間,且因蝕刻而變得小於半導體磊晶層3003。3010示出了犧牲層3002受到蝕刻的區域。 Fig. 22 is a diagram for explaining the prior art. FIG. 22 shows a semiconductor structure including a parent substrate 3001 , a sacrificial layer 3002 , a semiconductor epitaxial layer 3003 , and a support 3004 . The sacrificial layer 3002 is provided between the semiconductor epitaxial layer 3003 and the base substrate 3001, and becomes smaller than the semiconductor epitaxial layer 3003 by etching. 3010 shows the etched region of the sacrificial layer 3002.

支持體3004的水平方向的剖面與半導體磊晶層3003為同一形狀,且設置於半導體磊晶層3003之上。支持體3004是將半導體磊晶層3003自母材基板3001拆下時用以支持半導體磊晶層3003的構件。於圖22所示的現有技術中,藉由利用蝕刻將犧牲層3002去除而將半導體磊晶層3003自母材基板3001上剝離。 The support body 3004 has the same shape as the semiconductor epitaxial layer 3003 in cross section in the horizontal direction, and is provided on the semiconductor epitaxial layer 3003 . The support 3004 is a member for supporting the semiconductor epitaxial layer 3003 when the semiconductor epitaxial layer 3003 is removed from the base substrate 3001 . In the prior art shown in FIG. 22 , the semiconductor epitaxial layer 3003 is peeled off from the base substrate 3001 by removing the sacrificial layer 3002 by etching.

於圖22所示的現有技術中,半導體磊晶層3003及支持體3004於犧牲層3002的蝕刻結束的時間點自母材基板3001剝離。因此存在如下課題:於犧牲層3002被完全去除而母材基板3001與半導體磊晶層3003相離的時間點,需要將半導體磊晶層3003移動並載置於與母材基板3001不同的暫時位置。In the conventional technique shown in FIG. 22 , the semiconductor epitaxial layer 3003 and the support body 3004 are peeled off from the base substrate 3001 when the etching of the sacrificial layer 3002 is completed. Therefore, there is a problem that at the time when the sacrificial layer 3002 is completely removed and the base substrate 3001 is separated from the semiconductor epitaxial layer 3003, the semiconductor epitaxial layer 3003 needs to be moved and placed in a temporary position different from that of the base substrate 3001. .

因此,本發明是鑒於所述方面而成,其目的在於藉由將半導體磊晶層接合於其他基板而使製造半導體元件的方法效率化。Therefore, this invention was made in view of the said point, and it aims at improving the efficiency of the method of manufacturing a semiconductor element by joining a semiconductor epitaxial layer to another board|substrate.

本發明的半導體元件的製造方法是將形成於第1基板的上方的半導體薄膜層自所述第1基板分離並接合於與所述第1基板不同的第2基板上的半導體元件的製造方法,且包括:形成作為薄膜的固定層的步驟,所述固定層將所述半導體薄膜層的與所述第1基板一側為相反側的主面的至少一部分與所述第1基板中的所述半導體薄膜層一側的面的至少一部分結合;藉由將所述半導體薄膜層或所述第1基板的一部分區域、或者所述半導體薄膜層與所述第1基板之間的層的一部分區域去除而形成空隙的步驟;於形成所述空隙後,於所述半導體薄膜層的所述主面將形成於第3基板的有機材料層與所述固定層及所述半導體薄膜層的至少一部分結合區域結合的步驟;於所述有機材料層結合於所述結合區域的狀態下將所述第3基板沿與所述第1基板相離的方向移動,藉此將所述半導體薄膜層自所述第1基板分離的步驟;以及將自所述第1基板分離後的所述半導體薄膜層接合於所述第2基板的步驟。The method for manufacturing a semiconductor element of the present invention is a method for manufacturing a semiconductor element in which a semiconductor thin film layer formed on a first substrate is separated from the first substrate and bonded to a second substrate different from the first substrate, And including: the step of forming a fixed layer as a thin film, the fixed layer connects at least a part of the main surface of the semiconductor thin film layer on the side opposite to the side of the first substrate and the first substrate. At least a part of the surface on one side of the semiconductor thin film layer is combined; by removing a part of the semiconductor thin film layer or the first substrate, or a part of the layer between the semiconductor thin film layer and the first substrate And the step of forming a void; after forming the void, on the main surface of the semiconductor thin film layer, the organic material layer formed on the third substrate and at least a part of the bonding area of the fixed layer and the semiconductor thin film layer a step of combining: moving the third substrate in a direction away from the first substrate in a state where the organic material layer is bonded to the bonding region, thereby moving the semiconductor thin film layer from the first substrate a step of separating the substrate; and a step of bonding the semiconductor thin film layer separated from the first substrate to the second substrate.

根據本發明,起到可使將所移動的半導體磊晶層接合於其他基板的步驟效率化的效果。According to the present invention, there is an effect that the efficiency of the step of bonding the moved semiconductor epitaxial layer to another substrate can be achieved.

[半導體元件的製造方法的概要] 於本實施形態的半導體元件的製造方法中,使作為第1基板的母材基板上的半導體薄膜層的島移動至作為第2基板的移動目的地基板,從而製造具有移動目的地基板及半導體薄膜層的半導體元件。「半導體薄膜層的島」是與母材基板相同大小的半導體薄膜層的區域、或較母材基板小的半導體薄膜層的區域。於一塊母材基板上可形成有一個半導體薄膜層的島,亦可形成有多個半導體薄膜層的島。[Summary of Manufacturing Method of Semiconductor Element] In the method of manufacturing a semiconductor element according to this embodiment, the island of the semiconductor thin film layer on the base substrate as the first substrate is moved to the destination substrate as the second substrate, thereby manufacturing the substrate having the destination substrate and the semiconductor thin film. layers of semiconductor components. The "island of the semiconductor thin film layer" is a region of the semiconductor thin film layer having the same size as the base substrate, or a region of the semiconductor thin film layer smaller than the base substrate. An island of one semiconductor thin film layer may be formed on one base material substrate, and islands of a plurality of semiconductor thin film layers may also be formed.

本實施形態的半導體元件的製造方法的特徵在於:形成在半導體薄膜層的島自母材基板分離的狀態下對半導體薄膜層的島進行支持的固定層,以使得在為了將半導體薄膜層的島自母材基板移動至移動目的地基板而將半導體薄膜層的島自母材基板分離的狀態下,半導體薄膜層的島能夠於母材基板上維持穩定的狀態。藉由所述方式,可在使半導體薄膜層的島連結於作為第3基板的拾取基板上所形成的有機物層之後,將半導體薄膜層的島自母材基板分離,並使分離後的半導體薄膜層的島移動至第2基板。The method for manufacturing a semiconductor element according to this embodiment is characterized in that a pinning layer is formed to support the islands of the semiconductor thin film layer in a state where the islands of the semiconductor thin film layer are separated from the base substrate, so that in order to hold the islands of the semiconductor thin film layer In a state where the islands of the semiconductor thin film layer are separated from the base substrate by moving from the base substrate to the destination substrate, the islands of the semiconductor thin film layer can be maintained in a stable state on the base substrate. In this manner, after connecting the islands of the semiconductor thin film layer to the organic layer formed on the pick-up substrate as the third substrate, the islands of the semiconductor thin film layer can be separated from the base substrate, and the separated semiconductor thin film layer Layer islands are moved to the second substrate.

[將半導體薄膜層的島自母材基板拆下的步驟] 圖1A~圖1E是用以說明將半導體薄膜層的島自母材基板拆下的方法的圖。以下,參照圖1A~圖1E來說明將半導體薄膜層的島自母材基板拆下的方法的概要。[Procedure for removing the island of the semiconductor thin film layer from the base substrate] 1A to 1E are diagrams for explaining a method of detaching an island of a semiconductor thin film layer from a base substrate. Hereinafter, an outline of a method for detaching an island of a semiconductor thin film layer from a base substrate will be described with reference to FIGS. 1A to 1E .

首先,如圖1A所示,於作為第1基板的母材基板101上形成預定去除層102,並於預定去除層102上形成作為半導體磊晶層的半導體薄膜層104。預定去除層102是於之後的步驟中藉由蝕刻而去除的區域。First, as shown in FIG. 1A , a removal plan layer 102 is formed on a base substrate 101 as a first substrate, and a semiconductor thin film layer 104 as a semiconductor epitaxial layer is formed on the removal plan layer 102 . The intended removal layer 102 is a region to be removed by etching in a subsequent step.

預定去除層102例如是由當使用既定的蝕刻方法(使用既定的蝕刻液的濕式蝕刻或使用既定的氣體的乾式蝕刻)進行蝕刻時的蝕刻速度與母材基板101及半導體薄膜層104不同的材料而形成。預定去除層102亦可由與母材基板101相同的材料形成。例如,預定去除層102可為母材基板101的表面附近的一部分區域。For example, the planned removal layer 102 is etched by a predetermined etching method (wet etching using a predetermined etching solution or dry etching using a predetermined gas) at a rate different from that of the base substrate 101 and the semiconductor thin film layer 104. material formed. The removal plan layer 102 may also be formed of the same material as the base substrate 101 . For example, the layer to be removed 102 may be a part of the area near the surface of the base substrate 101 .

半導體薄膜層104例如為藉由磊晶成長而形成的半導體薄膜層或藉由晶圓接合(wafer bonding)而形成的半導體薄膜層。半導體薄膜層104亦可為藉由其他方法而形成的半導體薄膜層。The semiconductor thin film layer 104 is, for example, a semiconductor thin film layer formed by epitaxial growth or a semiconductor thin film layer formed by wafer bonding. The semiconductor thin film layer 104 can also be a semiconductor thin film layer formed by other methods.

半導體薄膜層104例如為III-V族化合物半導體材料(例如GaAs、AlGaAs、InGaAs、InP、InAlGaP等)、III族氮化物半導體材料(例如GaN、InN、AlGaN、InGaN、AlN等)、氧化物半導體材料(例如ZnO、Ga2 O3 等)、IV族化合物半導體材料(SiC等)、金剛石、Si或SiGe等。母材基板101例如為III-V族化合物半導體材料基板(例如GaAs基板、InP基板等)、III族氮化物半導體材料基板(例如GaN基板)、氧化物半導體材料基板(例如ZnO基板、Ga2 O3 基板等)、IV族化合物半導體基板(例如SiC等)、金剛石基板、或Si、SiGe等。The semiconductor thin film layer 104 is, for example, a III-V compound semiconductor material (such as GaAs, AlGaAs, InGaAs, InP, InAlGaP, etc.), a III-group nitride semiconductor material (such as GaN, InN, AlGaN, InGaN, AlN, etc.), an oxide semiconductor Materials (such as ZnO, Ga 2 O 3, etc.), Group IV compound semiconductor materials (SiC, etc.), diamond, Si or SiGe, etc. The base material substrate 101 is, for example, a III-V compound semiconductor material substrate (such as a GaAs substrate, an InP substrate, etc.), a III-group nitride semiconductor material substrate (such as a GaN substrate), an oxide semiconductor material substrate (such as a ZnO substrate, Ga 2 O 3 substrates, etc.), group IV compound semiconductor substrates (such as SiC, etc.), diamond substrates, or Si, SiGe, etc.

繼而,如圖1B所示,將半導體薄膜層104分割成多個島區域而形成半導體薄膜層的島108(以下有時將「半導體薄膜層的島108」稱為「島108」)。島108的形狀並無限定,於以下的說明中例示島108為長方形的情況。島108例如可為正方形或六角形。再者,亦可代替將半導體薄膜層104分割成多個島區域而藉由於母材基板101的上方使半導體薄膜層104選擇成長來形成單獨的或多個島108。Next, as shown in FIG. 1B , the semiconductor thin film layer 104 is divided into a plurality of island regions to form semiconductor thin film layer islands 108 (hereinafter, the “semiconductor thin film layer islands 108 ” are sometimes referred to as “islands 108 ”). The shape of the island 108 is not limited, and a case where the island 108 is a rectangle will be exemplified in the following description. The island 108 may be, for example, square or hexagonal. Furthermore, instead of dividing the semiconductor thin film layer 104 into a plurality of island regions, single or plural islands 108 may be formed by selectively growing the semiconductor thin film layer 104 on the base substrate 101 .

另外,形成島108的方法為任意的,可例示以下的方法。 1)藉由光微影/蝕刻步驟對半導體薄膜層104進行加工而形成島108的方法 2)於母材基板101的上方使半導體薄膜層104選擇成長的方法 3)沿母材基板101上的橫向(水平方向)使半導體薄膜層104橫向成長的方法In addition, the method of forming the island 108 is arbitrary, and the following methods can be exemplified. 1) Method of forming island 108 by processing semiconductor thin film layer 104 through photolithography/etching steps 2) A method of selectively growing the semiconductor thin film layer 104 on the base substrate 101 3) A method of laterally growing the semiconductor thin film layer 104 along the lateral direction (horizontal direction) on the base substrate 101

以下,對多個半導體薄膜層的島108中的一個半導體薄膜層的島108進行說明。於該步驟中,如圖1B所示,包括預定去除層102在內亦可形成為島108。預定去除層102中包含於島108的區域為圖1B所示的預定去除區域106。Hereinafter, the island 108 of one semiconductor thin film layer among the plurality of semiconductor thin film layer islands 108 will be described. In this step, as shown in FIG. 1B , islands 108 including the layer 102 to be removed may also be formed. The area included in the island 108 in the intended removal layer 102 is the intended removal area 106 shown in FIG. 1B .

繼而,如圖1C及圖1D所示,形成作為薄膜的固定層110,所述固定層110將島108中的與母材基板101一側為相反側的主面的至少一部分與母材基板101中的島108側的面的至少一部分結合。固定層110例如是在島108的上表面至母材基板101之間延伸存在的形狀,但固定層110只要可將島108與母材基板101結合,則亦可為其他形狀。例如,固定層110亦可由將島108的包含長度方向上的兩側面的區域與母材基板101結合的兩個薄膜構成。另外,固定層110亦可為在島108的短邊方向上以將母材基板101作為起點及終點而跨越島108的方式延伸存在的薄膜。另外,固定層110可與島108的邊平行,亦可形成為在與島108的邊的方向不同的方向上延伸。Next, as shown in FIGS. 1C and 1D , a fixed layer 110 is formed as a thin film, and the fixed layer 110 connects at least a part of the main surface of the island 108 on the side opposite to the base material substrate 101 with the base material substrate 101 . At least a part of the surface on the side of the island 108 is bonded. The fixing layer 110 has, for example, a shape extending between the upper surface of the island 108 and the base substrate 101 , but the fixing layer 110 may have other shapes as long as it can bond the island 108 and the base substrate 101 . For example, the pinning layer 110 may be composed of two thin films that bond regions including both side surfaces in the longitudinal direction of the island 108 to the base substrate 101 . In addition, the fixed layer 110 may be a thin film extending across the island 108 in the short side direction of the island 108 with the base substrate 101 as the starting point and the ending point. In addition, the fixed layer 110 may be parallel to the sides of the island 108 or may be formed to extend in a direction different from the direction of the sides of the island 108 .

於形成在島108的長度方向上延伸存在的固定層110的情況下,於形成固定層110的步驟中,以在半導體薄膜層104的主面上的第1方向(該方向例如是將半導體薄膜層104的被覆率高的兩側面連結的方向)上於半導體薄膜層104的兩端間延伸存在,且在與第1方向正交的第2方向上的半導體薄膜層104的兩側面中的至少一部分區域中半導體薄膜層104露出的方式形成固定層110。於島108為長方形的情況下,固定層110對島108的長邊的側面的被覆率小於對短邊的側面的被覆率。藉由所述方式,當實施後述的蝕刻時,可縮短為了將島108與母材基板101分離而將島108或母材基板101的一部分區域、或者將島108與母材基板101之間的層的一部分區域去除為止的時間。In the case of forming the fixed layer 110 extending in the length direction of the island 108, in the step of forming the fixed layer 110, the first direction on the main surface of the semiconductor thin film layer 104 (this direction is, for example, the semiconductor thin film Layer 104 has a high coverage ratio on both sides of the connection direction) extending between the two ends of the semiconductor thin film layer 104, and at least one of the two sides of the semiconductor thin film layer 104 in the second direction perpendicular to the first direction The fixed layer 110 is formed in such a manner that the semiconductor thin film layer 104 is exposed in a part of the region. When the island 108 is rectangular, the coverage rate of the fixed layer 110 on the long sides of the island 108 is smaller than the coverage on the short sides of the island 108 . In this manner, when performing etching described later, it is possible to shorten the distance between the island 108 and a part of the base substrate 101 or between the island 108 and the base substrate 101 to separate the island 108 from the base substrate 101 . The time until a portion of the layer is removed.

圖1D為與圖1C對應的頂視圖。固定層110發揮如下功能:以島108的於至少正下方的母材基板101上的位置不變的方式,將島108留存於母材基板101的上方。固定層110為包含如下材料的薄膜層:所述材料相對於用以對預定去除區域106進行蝕刻的蝕刻手段而具備耐蝕刻性能。Figure ID is a top view corresponding to Figure 1C. The fixed layer 110 functions to leave the island 108 above the base material substrate 101 so that the position of the island 108 on at least the base material substrate 101 immediately below does not change. The fixed layer 110 is a thin film layer including a material having etching resistance with respect to an etching means used to etch the region 106 to be removed.

作為固定層110的材料,例如可使用氧化膜(例如Six Oy 、Six Oy Nz 、Alx Oy 、Alx Oy Nz 等)、或氮化膜(例如Six Ny 、Alx Ny 等)等無機絕緣膜。無機絕緣膜可為單層或不同材料的積層。例如使用化學氣相沈積(Chemical Vapor Deposition,CVD)法形成無機絕緣膜,並藉由標準的光微影及蝕刻的製程將無機絕緣膜的一部分去除,藉此可形成所期望的固定層110。當形成固定層110時,若具有相對於用以對預定去除區域106進行蝕刻的既定的蝕刻手段的耐性,則作為固定層110的材料,亦可使用有機膜(例如感光性塗佈膜、感光性有機片材等)。As the material of the fixed layer 110, for example, an oxide film (such as SixOy , SixOyNz , AlxOy , AlxOyNz , etc. ) , or a nitride film (such as SixNy , Al x N y, etc.) and other inorganic insulating films. The inorganic insulating film may be a single layer or a laminate of different materials. For example, chemical vapor deposition (Chemical Vapor Deposition, CVD) is used to form an inorganic insulating film, and a part of the inorganic insulating film is removed by standard photolithography and etching processes, thereby forming the desired fixed layer 110 . When forming the fixed layer 110, as long as it has resistance to a predetermined etching method for etching the intended removal region 106, as the material of the fixed layer 110, an organic film (such as a photosensitive coating film, a photosensitive coating film, etc.) can also be used. Sexual organic sheets, etc.).

固定層110的厚度可根據半導體薄膜層的島108的尺寸及厚度而選擇最適合的厚度。固定層110的薄膜厚度例如為較半導體薄膜層的島108的厚度(即形成於母材基板101上的半導體薄膜層104的厚度)薄的厚度。固定層110的厚度較佳為如下厚度:藉由在將後述的作為第3基板的拾取基板200結合於固定層110及半導體薄膜層104的至少一部分結合區域的狀態下沿與母材基板101相離的方向移動拾取基板200的力,將形成於母材基板101上的固定層110與形成於半導體薄膜層的側面的固定層110之間切斷的厚度。The thickness of the fixed layer 110 can be selected according to the size and thickness of the island 108 of the semiconductor thin film layer. The film thickness of the fixed layer 110 is, for example, thinner than the thickness of the island 108 of the semiconductor thin film layer (that is, the thickness of the semiconductor thin film layer 104 formed on the base substrate 101 ). The thickness of the fixed layer 110 is preferably a thickness obtained by bonding the pick-up substrate 200 as a third substrate described later to at least a part of the bonding region of the fixed layer 110 and the semiconductor thin film layer 104 along the surface of the base substrate 101. The force of moving the pick-up substrate 200 in the away direction cuts the thickness between the fixed layer 110 formed on the base substrate 101 and the fixed layer 110 formed on the side surface of the semiconductor thin film layer.

圖1D所示的半導體薄膜層的島108具有長度為L1與L2的邊,且L1>L2。固定層110具有被覆島108的上表面的第1區域、被覆島108的右側面的第2區域、以及被覆島108的左側面的第3區域。固定層110在具有第2區域及第3區域之前更具有被覆母材基板101的區域。於圖1D所示的例子中,固定層110未被覆島108的四個側面中的長邊的側面(即長度為L1的邊的側面),且被覆短邊的側面(即長度為L2的邊的側面)的一部分。The island 108 of the semiconductor thin film layer shown in FIG. 1D has sides with lengths L1 and L2, and L1>L2. The fixed layer 110 has a first region covering the upper surface of the island 108 , a second region covering the right side of the island 108 , and a third region covering the left side of the island 108 . The fixed layer 110 further has a region covering the base substrate 101 before having the second region and the third region. In the example shown in FIG. 1D , the fixed layer 110 does not cover the side of the long side (that is, the side of the side whose length is L1) among the four sides of the island 108, and covers the side of the short side (that is, the side whose length is L2). part of the side).

繼而,如圖1E所示,藉由將島108或母材基板101的一部分區域、或者島108與母材基板101之間的預定去除區域層的一部分區域去除而形成空隙103。例如,將島108的與至少正下方的母材基板101連接的區域蝕刻去除,從而於島108與母材基板101之間的至少島108的正下方區域中形成空隙103。當形成空隙103時,理想的是使用島108相對於所使用的蝕刻液或蝕刻氣體的蝕刻速度至少小於預定去除區域106的蝕刻速度的蝕刻液或蝕刻氣體。Next, as shown in FIG. 1E , the void 103 is formed by removing a part of the island 108 or the base substrate 101 , or a part of the layer to be removed between the island 108 and the base substrate 101 . For example, the region of the island 108 connected to at least the base substrate 101 directly below is etched away to form the void 103 between the island 108 and the base substrate 101 at least in the region directly below the island 108 . When forming the void 103 , it is desirable to use an etching liquid or an etching gas whose etching rate of the island 108 is at least lower than that of the region 106 to be removed with respect to the etching liquid or etching gas used.

於所述蝕刻步驟中,例如於預定去除區域層的蝕刻等向性地進行且蝕刻速度不受方向影響的情況下,因垂直於島108的長邊的方向上的蝕刻距離短,故相較於垂直於短邊的方向上的蝕刻而蝕刻結束得早。因此,藉由開放長邊的側面,或者藉由以相較於短邊上的固定層110的被覆率而長邊上的固定層110的被覆率變小的方式形成固定層110,可更快地結束蝕刻而形成空隙103。藉由所述方式,於用以去除預定去除區域106的蝕刻步驟中,可降低於島108中產生蝕刻損傷的風險。In the etching step, for example, in the case where the etching of the region layer to be removed isotropically proceeds and the etching rate is not affected by the direction, the etching distance in the direction perpendicular to the long side of the island 108 is short compared to Etching in the direction perpendicular to the short side ends early. Therefore, by opening the sides of the long sides, or by forming the fixed layer 110 in such a manner that the coverage of the fixed layer 110 on the long side becomes smaller compared with the coverage of the fixed layer 110 on the short sides, faster The etch ends to form voids 103 . In this way, the risk of etching damage in the island 108 can be reduced during the etching step for removing the intended removal region 106 .

再者,於以上的說明中,例示了藉由利用蝕刻而去除預定去除層102來形成空隙103的情況,但亦可藉由於不形成預定去除層102的情況下利用異向性蝕刻而將母材基板101的表面區域去除來形成空隙。Furthermore, in the above description, the case where the void 103 is formed by removing the intended removal layer 102 by etching has been exemplified, but it is also possible to use anisotropic etching without forming the intended removal layer 102 to form the void 103 . The surface area of the substrate 101 is removed to form voids.

於藉由利用異向性蝕刻而將母材基板101的表面的區域去除來形成空隙的情況下,於形成固定層的步驟中,較佳為將蝕刻速度大的方向上的兩側面設為第2方向。第2方向上的兩側面可整體完全露出,亦可由固定層110被覆一部分區域。而且,較佳為以相較於在第1方向上延伸存在的固定層110對半導體薄膜層104中的第1方向上的兩側面的被覆率,在第2方向上延伸存在的固定層110對半導體薄膜層104中的第2方向上的兩側面的被覆率變小的方式形成固定層110。藉由所述方式,可藉由實施蝕刻而容易地形成空隙103。In the case where the void is formed by removing a region of the surface of the base material substrate 101 by anisotropic etching, in the step of forming the pinned layer, it is preferable to set the two sides in the direction in which the etching rate is high as the second. 2 directions. Both side surfaces in the second direction may be entirely exposed, or a part of the area may be covered by the fixing layer 110 . Furthermore, it is preferable that the fixed layer 110 extending in the second direction has a higher coverage rate on both sides of the semiconductor thin film layer 104 in the first direction than the fixed layer 110 extending in the first direction. The fixed layer 110 is formed so that the coverage of both side surfaces in the second direction of the semiconductor thin film layer 104 becomes small. In this manner, the void 103 can be easily formed by performing etching.

另外,於以上的說明中,例示了半導體薄膜層的島108為長方形的情況,但於如下情況下島108亦可為正方形。 1)藉由利用蝕刻將預定去除層102去除而將半導體薄膜層自母材基板分離的情況 2)使用用以將母材基板101的表面區域去除的異向性蝕刻的情況 3)島108的尺寸非常小的情況(例如為20 μm以下的情況)In addition, in the above description, the case where the island 108 of the semiconductor thin film layer is a rectangle was exemplified, but the island 108 may be a square in the following cases. 1) The case where the semiconductor thin film layer is separated from the base substrate by removing the planned removal layer 102 by etching 2) When using anisotropic etching for removing the surface area of the base substrate 101 3) When the size of the island 108 is very small (eg, 20 μm or less)

[將半導體薄膜層的島108分離的步驟] 圖2A是表示用以將半導體薄膜層的島108自母材基板101分離的作為第3基板的拾取基板200的圖。圖2B是圖2A的A-A剖面。如圖2B所示,拾取基板200具有基底基板201、以及形成於基底基板201上的包含有機材料的拾取凸塊202。作為基底基板201,例如可選擇石英、藍寶石、玻璃等的透明基板;Si等的半導體基板;陶瓷基板;或金屬基板等。基底基板201可為單一材料,亦可為積層材料。另外,基底基板201亦可為利用其他材料對表面進行了塗敷的基板。[Step of separating the islands 108 of the semiconductor thin film layer] FIG. 2A is a diagram showing a pick-up substrate 200 as a third substrate for separating the islands 108 of the semiconductor thin film layer from the base substrate 101 . Fig. 2B is the section A-A of Fig. 2A. As shown in FIG. 2B , the pick-up substrate 200 has a base substrate 201 and pick-up bumps 202 formed on the base substrate 201 including an organic material. As the base substrate 201 , for example, a transparent substrate such as quartz, sapphire, or glass; a semiconductor substrate such as Si; a ceramic substrate; or a metal substrate can be selected. The base substrate 201 can be a single material or a laminated material. In addition, the base substrate 201 may also be a substrate whose surface is coated with other materials.

拾取凸塊202例如為有機材料層,且可藉由於基底基板201上塗佈感光性有機材料並利用標準的光微影製程而形成。有機材料層例如可藉由利用旋塗法、浸漬法等而於拾取基底基板上進行塗敷來形成,亦可藉由將有機材料膜貼附於拾取基底基板上來形成。The pickup bump 202 is, for example, an organic material layer, and can be formed by coating a photosensitive organic material on the base substrate 201 and using standard photolithography processes. The organic material layer can be formed, for example, by coating on the pick-up base substrate by spin coating or dipping, or by attaching an organic material film to the pick-up base substrate.

拾取基板的結構可根據所拾取的島108的形狀或尺寸而進行各種變形。例如,拾取基板可具有插入至基底基板201與拾取凸塊202之間的其他結構。另外,拾取基板亦可如圖2C所示的拾取基板200'般,不具有與作為自母材基板101分離的對象的島108的形狀相對應的拾取凸塊202,而具有面積較島108大且平坦的拾取層204。The structure of the picked-up substrate can be variously modified depending on the shape or size of the picked-up island 108 . For example, the pick-up substrate may have other structures interposed between the base substrate 201 and the pick-up bump 202 . In addition, the pickup substrate may not have the pickup bump 202 corresponding to the shape of the island 108 to be separated from the base substrate 101 like the pickup substrate 200' shown in FIG. 2C , but may have a larger area than the island 108. And the pickup layer 204 is flat.

圖3A~圖3C是示意性地表示使用拾取基板200而將島108自母材基板101分離的步驟的圖。3A to 3C are diagrams schematically showing steps of separating the island 108 from the base substrate 101 using the pick-up substrate 200 .

首先,如圖3A所示,使拾取基板200的拾取凸塊202的位置對準島108。具體而言,將拾取基板200配置於固定層110及島108的至少一部分區域與拾取凸塊202的至少一部分區域重合的位置。First, as shown in FIG. 3A , the position of the pickup bump 202 of the pickup substrate 200 is aligned with the island 108 . Specifically, the pick-up substrate 200 is arranged at a position where at least a partial area of the fixed layer 110 and the island 108 overlaps with at least a partial area of the pick-up bump 202 .

接著,如圖3B所示,使拾取凸塊202接觸或壓接於固定層110及島108的至少一部分區域。藉此,將拾取凸塊202連結於固定層110及島108的至少一部分區域。若於島108與母材基板101之間形成有空隙103的狀態下,使拾取基板200接觸固定層110及島108並向下施力,則於島108與空隙103的邊界線的附近(圖3B的虛線部分),固定層110中產生龜裂或固定層110斷裂。Next, as shown in FIG. 3B , the pick-up bump 202 is contacted or pressed against at least a part of the fixed layer 110 and the island 108 . Thereby, the pick-up bump 202 is connected to at least a part of the fixed layer 110 and the island 108 . When the pick-up substrate 200 is brought into contact with the fixed layer 110 and the island 108 in the state where the gap 103 is formed between the island 108 and the base substrate 101, and a force is applied downward, the area near the boundary line between the island 108 and the gap 103 (Fig. 3B), a crack occurs in the fixed layer 110 or the fixed layer 110 breaks.

於固定層110中產生了龜裂的狀態或固定層110斷裂的狀態下,如圖3C所示,藉由將與固定層110的一部分區域連結的狀態下的拾取基板200提起,固定層110分離成與島108相接的固定層114、以及與母材基板101相接的固定層112,從而可將半導體薄膜層的島108及作為固定層110的一部分區域的固定層114自母材基板101分離。In the state where a crack is generated in the fixed layer 110 or the fixed layer 110 is broken, as shown in FIG. 3C , the fixed layer 110 is separated by lifting the pick-up substrate 200 in the state of being connected to a part of the fixed layer 110. A fixed layer 114 in contact with the island 108 and a fixed layer 112 in contact with the base substrate 101 are formed, so that the island 108 of the semiconductor thin film layer and the fixed layer 114 as a part of the fixed layer 110 can be separated from the base substrate 101. separate.

再者,亦可於自母材基板101分離後的島108的母材基板101側的面上伴有與半導體薄膜層104不同材料的半導體層的狀態下,將島108自母材基板101分離。例如,自母材基板101分離後的島108亦可伴有設置於母材基板101上的、用以使半導體薄膜層104選擇成長或橫向成長的遮罩膜或介電體層。Furthermore, the island 108 may be separated from the base substrate 101 in a state where the surface of the island 108 separated from the base substrate 101 is accompanied by a semiconductor layer of a material different from that of the semiconductor thin film layer 104 on the base substrate 101 side. . For example, the island 108 separated from the base substrate 101 may be accompanied by a mask film or a dielectric layer provided on the base substrate 101 for selectively growing or laterally growing the semiconductor thin film layer 104 .

[將半導體薄膜層的島108接合於其他基板的步驟] 圖3D~圖3F是示意性地表示將分離後的島108接合於移動目的地基板301為止的步驟的圖。如圖3D所示,將於拾取基板200上連結有島108及固定層114的狀態的結構210定位於作為第2基板的移動目的地基板301的上方的既定位置。[Step of bonding the island 108 of the semiconductor thin film layer to another substrate] 3D to 3F are diagrams schematically showing steps up to bonding the separated islands 108 to the transfer destination substrate 301 . As shown in FIG. 3D , the structure 210 in which the island 108 and the fixed layer 114 are connected to the pick-up substrate 200 is positioned at a predetermined position above the moving destination substrate 301 which is the second substrate.

其後,如圖3E所示,將結構210中的固定層114下方的島108的面308壓接於移動目的地基板301,從而將島108接合於移動目的地基板301。亦可於將島108壓接於移動目的地基板301的步驟之前,對所接合的面(半導體薄膜層的島108的面308與移動目的地基板301的表面302)適當進行表面處理。Thereafter, as shown in FIG. 3E , the surface 308 of the island 108 under the fixed layer 114 in the structure 210 is pressure-bonded to the destination substrate 301 , thereby bonding the island 108 to the destination substrate 301 . Before the step of pressure-bonding the island 108 to the destination substrate 301 , surface treatment may be appropriately performed on the bonded surfaces (the surface 308 of the island 108 of the semiconductor thin film layer and the surface 302 of the destination substrate 301 ).

接著,如圖3F所示,自固定層114將拾取凸塊202及基底基板201去除。例如,可藉由浸漬於溶解構成拾取凸塊202的有機材料的有機溶劑等藥液中以使拾取凸塊202溶解,而將固定層114與基底基板201分離。Next, as shown in FIG. 3F , the pick-up bump 202 and the base substrate 201 are removed from the fixed layer 114 . For example, the fixed layer 114 can be separated from the base substrate 201 by immersing in a chemical solution such as an organic solvent that dissolves the organic material constituting the pickup bump 202 to dissolve the pickup bump 202 .

再者,於將島108壓接於移動目的地基板301上的步驟中,於移動目的地基板301與島108的接合牢固的情況下,可於利用有機溶劑等藥液使拾取凸塊202溶解之前將拾取基板200提起。該情況下,於將拾取基板200提起後,可追加利用有機溶劑等藥液對接合有島108的移動目的地基板301上進行清潔的步驟。Furthermore, in the step of press-bonding the island 108 to the transfer destination substrate 301, if the bond between the transfer destination substrate 301 and the island 108 is firm, the pick-up bump 202 may be dissolved with a chemical solution such as an organic solvent. The pick substrate 200 was previously lifted. In this case, after lifting up the pick-up substrate 200, a step of cleaning the destination substrate 301 to which the island 108 is bonded with a chemical solution such as an organic solvent may be added.

再者,於接合於所述移動目的地基板301的島108中,亦可於形成固定層110的步驟之前形成既定的元件結構或元件結構的一部分。另外,於將島108接合於所述移動目的地基板301上之後,可對固定層110進行加工,或者於半導體薄膜層上形成層間絕緣膜或形成與外部結構的電性連接的配線結構等。Furthermore, in the island 108 bonded to the moving destination substrate 301 , a predetermined device structure or a part of the device structure may also be formed before the step of forming the fixed layer 110 . In addition, after the island 108 is bonded to the moving destination substrate 301 , the fixed layer 110 can be processed, or an interlayer insulating film can be formed on the semiconductor thin film layer, or a wiring structure for electrical connection with external structures can be formed.

另外,於以上的說明中,將島108接合於移動目的地基板301的表面,但亦可於移動目的地基板301與島108之間設置其他層(無機材料薄膜層或有機材料薄膜層等)。另外,亦可於接合步驟之後設置熱處理步驟。In addition, in the above description, the island 108 is bonded to the surface of the destination substrate 301, but other layers (inorganic material thin film layer or organic material thin film layer, etc.) may be provided between the destination substrate 301 and the island 108. . In addition, a heat treatment step may be provided after the bonding step.

另外,於將自母材基板101分離後的島108接合於移動目的地基板301的情況下,亦可於島108中的接合於移動目的地基板301一側的面上伴有與半導體薄膜層104不同材料的半導體層的狀態下接合於移動目的地基板301。例如,亦可將伴有設置於母材基板101上的、用於半導體薄膜層104的選擇成長或橫向成長的遮罩膜或介電體層的狀態下的島108接合於移動目的地基板301。In addition, when the island 108 separated from the base substrate 101 is bonded to the transfer destination substrate 301, the surface of the island 108 bonded to the transfer destination substrate 301 may be accompanied by a semiconductor thin film layer. 104 The semiconductor layers of different materials are bonded to the transfer destination substrate 301 in the state. For example, the island 108 may be bonded to the transfer destination substrate 301 with a mask film or dielectric layer provided on the base substrate 101 for selective growth or lateral growth of the semiconductor thin film layer 104 .

[移動多個島108的方法] 於以上的說明中,對移動一個半導體薄膜層的島108的方法進行了說明,但於本實施形態的半導體元件的製造方法中,亦可如圖4A~圖4E所示移動多個半導體薄膜層的島408a、408b、408c。於將多個島408a、408b、408c成批地自母材基板401分離的情況下,準備包括與多個島408a、408b、408c對應的多個拾取凸塊422a、422b、422c的拾取基板420。然後,藉由與所述步驟相同的步驟而使拾取基板420接觸或壓接於固定層410a、410b、410c及島408a、408b、408c,將多個島408a、408b、408c自母材基板401分離,並將多個島408a、408b、408c接合於移動目的地基板451上。[Method of moving a plurality of islands 108] In the above description, the method of moving the island 108 of one semiconductor thin film layer has been described, but in the manufacturing method of the semiconductor element of this embodiment, it is also possible to move a plurality of semiconductor thin film layers as shown in FIGS. 4A to 4E . islands 408a, 408b, 408c. In the case of separating a plurality of islands 408a, 408b, 408c from the base substrate 401 in batches, a pickup substrate 420 including a plurality of pickup bumps 422a, 422b, 422c corresponding to the plurality of islands 408a, 408b, 408c is prepared. . Then, the pick-up substrate 420 is brought into contact or pressure-bonded to the fixed layers 410a, 410b, 410c and the islands 408a, 408b, 408c by the same steps as those described above, and the plurality of islands 408a, 408b, 408c are removed from the base substrate 401. The islands 408 a , 408 b , and 408 c are separated and bonded to the destination substrate 451 .

圖4A~圖4E是示意性地表示使多個島408a、408b、408c移動的步驟的圖。於圖4A~圖4E中,母材基板401、多個空隙403a、403b、403c、多個島408a、408b、408c、多個固定層410a、410b、410c、多個固定層414a、414b、414c、多個固定層416a、416b、416c、拾取基板420、基底基板421、多個拾取凸塊422a、422b、422c、結構430以及移動目的地基板451分別與圖3A~圖3F中的母材基板101、空隙103、島108、固定層110、固定層114、固定層112、拾取基板200、基底基板201、拾取凸塊202、結構210以及移動目的地基板301對應。於將多個島408a、408b、408c自母材基板401分離的情況下,亦可使用如圖2C所示的、不具有拾取凸塊且包括包含有機材料的拾取層的拾取基板。4A to 4E are diagrams schematically showing steps of moving the plurality of islands 408a, 408b, and 408c. In FIGS. 4A to 4E , a base substrate 401, a plurality of voids 403a, 403b, 403c, a plurality of islands 408a, 408b, 408c, a plurality of fixed layers 410a, 410b, 410c, a plurality of fixed layers 414a, 414b, 414c , a plurality of fixed layers 416a, 416b, 416c, a pick-up substrate 420, a base substrate 421, a plurality of pick-up bumps 422a, 422b, 422c, a structure 430, and a moving destination substrate 451 are respectively the same as the parent substrate in FIGS. 3A-3F 101 , void 103 , island 108 , pinned layer 110 , pinned layer 114 , pinned layer 112 , pick up substrate 200 , base substrate 201 , pick up bump 202 , structure 210 and move destination substrate 301 correspond. In the case of separating the plurality of islands 408a, 408b, 408c from the parent substrate 401, a pick-up substrate without pick-up bumps and including a pick-up layer comprising an organic material as shown in FIG. 2C may also be used.

[多個半導體薄膜層的移動] 圖5A~圖5E是用以說明使多個半導體薄膜層的島移動的方法的圖。於圖5A~圖5E中,母材基板501、多個空隙503a、503b、503c、多個島508a、508b、508c、多個固定層510a、510b、510c、多個固定層514a、514c、多個固定層516a、516c、拾取基板520、基底基板521、多個拾取凸塊522a、522c、結構530、移動目的地基板531以及表面551分別與圖3A~圖3F中的母材基板101、空隙103、島108、固定層110、固定層114、固定層112、拾取基板200、基底基板201、拾取凸塊202、結構210、移動目的地基板301以及表面302對應。以下,對選擇母材基板上所形成的多個半導體薄膜層的島中的一部分島並移動至移動目的地基板的方法進行說明。[Movement of Multiple Semiconductor Thin Film Layers] 5A to 5E are diagrams for explaining a method of moving islands of a plurality of semiconductor thin film layers. In FIGS. 5A to 5E , a base substrate 501, a plurality of voids 503a, 503b, 503c, a plurality of islands 508a, 508b, 508c, a plurality of fixed layers 510a, 510b, 510c, a plurality of fixed layers 514a, 514c, multiple A fixed layer 516a, 516c, a pick-up substrate 520, a base substrate 521, a plurality of pick-up bumps 522a, 522c, a structure 530, a moving destination substrate 531, and a surface 551 are respectively related to the parent substrate 101, the gap in FIGS. 103 , island 108 , fixed layer 110 , fixed layer 114 , fixed layer 112 , pick substrate 200 , base substrate 201 , pick bump 202 , structure 210 , move destination substrate 301 , and surface 302 correspond. Hereinafter, a method of selecting some of the islands of the plurality of semiconductor thin film layers formed on the base substrate and moving them to the destination substrate will be described.

如圖5A所示,於半導體薄膜層的島的至少正下方形成空隙503a~空隙503c後,僅於與所選擇的半導體薄膜層的島508a及島508c對應的位置,於拾取基板520的基底基板521上設置有機材料的拾取凸塊522a、拾取凸塊522c。繼而,使拾取凸塊522a與拾取凸塊522c接觸或壓接於島508a與島508c,從而將拾取基板520連結於所選擇的島508a及島508c。圖5B為圖5A的俯視圖,圖5B的A-A剖面相當於圖5A。As shown in FIG. 5A , after forming voids 503a to 503c at least directly below the islands of the semiconductor thin film layer, the base substrate of the pick-up substrate 520 is picked up only at positions corresponding to the islands 508a and 508c of the selected semiconductor thin film layer. Pick-up bumps 522 a and pick-up bumps 522 c of organic materials are disposed on 521 . Then, the pick-up bump 522a and the pick-up bump 522c are brought into contact with or pressed against the islands 508a and 508c, thereby connecting the pick-up substrate 520 to the selected islands 508a and 508c. Fig. 5B is a top view of Fig. 5A, and the section A-A of Fig. 5B corresponds to Fig. 5A.

接著,如圖5C所示,將連結有所選擇的島508a及島508c的拾取基板520提起,從而僅將所選擇的島508a及島508c自母材基板501分離。圖5C是表示藉由拾取基板520而將所選擇的島508a及島508c提起的狀態的圖。如圖5C所示,未選擇的島508b殘留於母材基板501上。Next, as shown in FIG. 5C , only the selected islands 508 a and 508 c are separated from the base substrate 501 by lifting the pick-up substrate 520 connecting the selected islands 508 a and 508 c . FIG. 5C is a diagram showing a state where the selected islands 508 a and 508 c are lifted up by picking up the substrate 520 . As shown in FIG. 5C , unselected islands 508 b remain on the base substrate 501 .

接著,如圖5D所示,將於拾取基板520上連結有島508a、島508c、固定層514a及固定層514c的結構(圖5C所示的結構530)配置於移動目的地基板531上的既定位置。繼而,將島508a及島508c中的與固定層514a及固定層514c為相反側的面558a及面558c壓接於移動目的地基板531的表面551,從而將所選擇的島508a及島508c接合於移動目的地基板531。Next, as shown in FIG. 5D , the structure (the structure 530 shown in FIG. 5C ) in which the island 508a, the island 508c, the fixed layer 514a, and the fixed layer 514c are connected on the pick-up substrate 520 is arranged at a predetermined position on the moving destination substrate 531. . Next, the surfaces 558a and 558c of the islands 508a and 508c that are opposite to the fixed layer 514a and the fixed layer 514c are pressure-bonded to the surface 551 of the moving destination substrate 531, thereby joining the selected islands 508a and 508c. on the moving destination substrate 531 .

接著,自移動目的地基板531將拾取凸塊522a、拾取凸塊522c及基底基板521去除,藉此可製造如圖5E所示般於移動目的地基板531上接合有半導體薄膜層的島508a及島508c的半導體元件。Next, the pick-up bump 522a, the pick-up bump 522c, and the base substrate 521 are removed from the moving destination substrate 531, whereby the island 508a and the island 508a to which the semiconductor thin film layer is bonded on the moving destination substrate 531 as shown in FIG. 5E can be manufactured. The semiconductor elements of island 508c.

[半導體元件的製造方法的步驟流程] 圖6是表示本實施形態的半導體元件的製造方法的步驟流程的圖。如圖6所示,於本實施形態的半導體元件的製造方法中,可使用包括與母材基板501上的既定的所選擇的半導體薄膜層的島508a、508c對應的、有機材料的拾取凸塊522的拾取基板520,將所選擇的島508a、508c自母材基板501分離並接合於移動目的地基板531。藉由所述方式,起到可自母材基板501上的多個島508a、508b、508c中選擇所期望的島508a、508c而接合於移動目的地基板531的效果。[Flow of Steps of Manufacturing Method of Semiconductor Element] FIG. 6 is a diagram showing a flow of steps in the method of manufacturing a semiconductor element according to the present embodiment. As shown in FIG. 6, in the method of manufacturing a semiconductor device according to this embodiment, it is possible to use pick-up bumps made of organic materials corresponding to islands 508a and 508c of predetermined selected semiconductor thin film layers on the base substrate 501. 522 picks up the substrate 520, separates the selected islands 508a and 508c from the parent substrate 501, and bonds them to the destination substrate 531. In this manner, desired islands 508 a , 508 c can be selected from among the plurality of islands 508 a , 508 b , 508 c on the base substrate 501 and bonded to the destination substrate 531 .

關於用以將母材基板501上的多個島508a、508b、508c中的所期望的島508a、508c自母材基板501分離的分離圖案,顯然可進行各種變形。It is obvious that various modifications can be made regarding the separation pattern for separating desired islands 508 a , 508 c from among the plurality of islands 508 a , 508 b , 508 c on the base substrate 501 from the base substrate 501 .

[本實施形態的半導體元件的製造方法所帶來的效果] 根據以上所說明的半導體元件的製造方法,使用包括在基底基板201上藉由光微影並利用有機材料而形成的拾取凸塊202的拾取基板200,將藉由固定層110而固定於母材基板101上的半導體薄膜層的島108自母材基板101分離,並將連結於拾取基板200的半導體薄膜層的島108壓接並接合於移動目的地基板301。藉由所述方式,可將自母材基板101分離的半導體薄膜層104容易地移動至其他基板。[Effects brought about by the method of manufacturing a semiconductor device according to the present embodiment] According to the manufacturing method of the semiconductor device described above, using the pick-up substrate 200 including the pick-up bumps 202 formed on the base substrate 201 by photolithography and using an organic material, the bumps fixed to the base material by the fixing layer 110 are used. The island 108 of the semiconductor thin film layer on the substrate 101 is separated from the base substrate 101 , and the island 108 of the semiconductor thin film layer connected to the pickup substrate 200 is pressure-bonded to the transfer destination substrate 301 . In this manner, the semiconductor thin film layer 104 separated from the base substrate 101 can be easily moved to another substrate.

另外,對本領域技術人員而言顯而易見的是,可對應於自母材基板101分離的半導體薄膜層的島108而容易地製作包括最適合的形狀與尺寸的拾取凸塊202的拾取基板200。根據本實施形態的半導體元件的製造方法,能夠使用可容易地製作的拾取基板200來將半導體薄膜層的島108自母材基板101分離並接合於移動目的地基板301,因此可以低成本來實現半導體薄膜層的島108的移動。In addition, it is obvious to those skilled in the art that the pick-up substrate 200 including pick-up bumps 202 having an optimum shape and size corresponding to the islands 108 of the semiconductor thin film layer separated from the base substrate 101 can be easily fabricated. According to the manufacturing method of the semiconductor element of this embodiment, the island 108 of the semiconductor thin film layer can be separated from the base material substrate 101 and bonded to the destination substrate 301 using the pick-up substrate 200 that can be easily fabricated, so it can be realized at low cost. Movement of the island 108 of the semiconductor thin film layer.

進而,於將半導體薄膜層的島108接合於移動目的地基板301後,自移動目的地基板301上將包含有機材料的拾取凸塊202及拾取基板200的基底基板201去除,因此亦起到可對基底基板201進行重覆再利用的效果。Furthermore, after the island 108 of the semiconductor thin film layer is bonded to the destination substrate 301, the pick-up bump 202 comprising an organic material and the base substrate 201 of the pick-up substrate 200 are removed from the destination substrate 301. The effect of repeatedly reusing the base substrate 201 .

另外,如上所述,於形成在島108的長度方向上延伸存在的固定層110的情況下,產生如下所述的效果。In addition, as described above, when the fixed layer 110 extending in the longitudinal direction of the island 108 is formed, the following effects are produced.

(1)於在半導體薄膜層的島108與母材基板101之間形成空隙的步驟中使用蝕刻液或蝕刻氣體的情況下,可保護半導體薄膜表面、形成於半導體薄膜層的島108的電極、配線等元件結構。(1) When an etching solution or an etching gas is used in the step of forming a gap between the island 108 of the semiconductor thin film layer and the base substrate 101, the surface of the semiconductor thin film, the electrodes formed on the island 108 of the semiconductor thin film layer, and the Component structure such as wiring.

(2)於形成半導體薄膜層的島108與母材基板101之間的空隙之後接合於移動目的地基板301上為止的步驟中,可減少因施加於半導體薄膜層的島108的應力而造成的半導體薄膜層的島108的翹曲量。若如此般藉由以減少應力的方式進行調整而半導體薄膜層的島108的翹曲得到減少,則例如於形成有空隙的狀態下,亦容易藉由固定層110而於母材基板101上保持半導體薄膜層的島108。其結果,容易進行藉由拾取基板200的對半導體薄膜層的島108的分離,並且於在移動目的地基板301上的接合步驟中,容易使半導體薄膜層的島108保持於移動目的地基板301上。(2) In the step of forming the gap between the island 108 of the semiconductor thin film layer and the base substrate 101 and then bonding to the destination substrate 301, the stress applied to the island 108 of the semiconductor thin film layer can be reduced. The warpage amount of the island 108 of the semiconductor thin film layer. If the warpage of the islands 108 of the semiconductor thin film layer is reduced by adjusting so as to reduce the stress in this way, it will be easy to hold on the base substrate 101 by the fixing layer 110 even in the state where a void is formed. The island 108 of the semiconductor thin film layer. As a result, separation of the islands 108 of the semiconductor thin film layer by the pick-up substrate 200 is easily performed, and in the bonding step on the transfer destination substrate 301, it is easy to hold the islands 108 of the semiconductor thin film layer on the transfer destination substrate 301 superior.

(3)於接合於移動目的地基板301上之後的元件形成步驟中,可將固定層110用作配線層與半導體薄膜層之間的層間絕緣膜層等。(3) In the element forming step after bonding on the moving destination substrate 301 , the fixed layer 110 can be used as an interlayer insulating film layer between the wiring layer and the semiconductor thin film layer, or the like.

(4)於接合於移動目的地基板301上之後的元件形成步驟中於固定層110上形成配線層的情況下,可防止當固定層110不連續時所存在的階差處的配線層的斷線。(4) In the case where a wiring layer is formed on the fixed layer 110 in the element forming step after being bonded to the moving destination substrate 301, it is possible to prevent the disconnection of the wiring layer at the level difference that exists when the fixed layer 110 is discontinuous. Wire.

(5)容易確保使用接合於移動目的地基板301上的半導體薄膜層的島108而形成的半導體元件的特性的均一性。藉由半導體薄膜層的島108的表面經連續的固定層110被覆,例如自發光元件上表面出射的光的強度分佈變得均一。於由不連續的固定層110被覆的情況下,於固定層110的不連續區域中光強度發生變化。(5) It is easy to ensure the uniformity of the characteristics of the semiconductor element formed using the island 108 bonded to the semiconductor thin film layer on the movement destination substrate 301 . Since the surface of the island 108 of the semiconductor thin film layer is covered by the continuous fixed layer 110, for example, the intensity distribution of the light emitted from the upper surface of the light-emitting element becomes uniform. In the case of covering with a discontinuous fixed layer 110 , the light intensity changes in the discontinuous region of the fixed layer 110 .

再者,於以上的說明中,以矩形形狀對半導體薄膜層的形狀進行了說明,但除矩形形狀以外,亦可為圓形或具有複雜的形狀的形狀。另外,於以上的說明中,例示(圖示)了不具有元件結構的單純的半導體薄膜層,但半導體薄膜層亦可具有元件結構。另外,半導體薄膜層表面亦可不平坦而包括與元件結構對應的介電體材料或金屬材料的薄膜結構。In addition, in the above description, the shape of the semiconductor thin film layer has been described as a rectangular shape, but other than the rectangular shape, it may be circular or have a complicated shape. In addition, in the above description, a simple semiconductor thin film layer not having an element structure was exemplified (illustrated), but the semiconductor thin film layer may also have an element structure. In addition, the surface of the semiconductor thin film layer can also be uneven and include a thin film structure of dielectric material or metal material corresponding to the device structure.

[半導體元件的製造方法的變形例] 圖7A~圖7D為半導體元件的製造方法的變形例的一例。於圖7A~圖7D中,母材基板701、多個空隙703a、703b、703c、703d、多個島708a、708b、708c、708d、718a、718b、多個固定層705a、705b、705c、705d、多個固定層714a、714b、拾取基板710、基底基板711、拾取層712以及移動目的地基板731分別與圖2C、圖3A~圖3F中的母材基板101、空隙103、島108、固定層110、固定層114、拾取基板200、基底基板201、拾取層204以及移動目的地基板301對應。如圖7A及圖7B(圖7B為圖7A的A-A剖面圖)所示,亦可將母材基板701上的多個半導體薄膜層的島(例如島708a、島708b、島708c、島708d、島718a、島718b)中的、既定的一部分多個島自母材基板分離。另外,如圖7C及圖7D(圖7D為圖7C的A-A剖面圖)所示,可將自母材基板701分離後的島(圖7C的708a、708b、718a、718b)良好地接合於在一部分區域(圖7C中的元件等搭載區域742、元件等搭載區域744)中搭載有其他元件的移動目的地基板731上的既定位置。[Modification of the method of manufacturing a semiconductor element] 7A to 7D are examples of modifications of the method of manufacturing a semiconductor element. In FIGS. 7A to 7D , base material substrate 701, multiple voids 703a, 703b, 703c, 703d, multiple islands 708a, 708b, 708c, 708d, 718a, 718b, multiple fixed layers 705a, 705b, 705c, 705d , a plurality of fixed layers 714a, 714b, a pick-up substrate 710, a base substrate 711, a pick-up layer 712, and a destination substrate 731 are respectively fixed to the parent substrate 101, the void 103, the island 108, The layer 110, the fixed layer 114, the pickup substrate 200, the base substrate 201, the pickup layer 204, and the movement destination substrate 301 correspond. As shown in FIGS. 7A and 7B (FIG. 7B is a cross-sectional view of A-A of FIG. 7A), islands of multiple semiconductor thin film layers on the base substrate 701 (such as island 708a, island 708b, island 708c, island 708d, Among the islands 718 a and 718 b ), a predetermined part of the islands is separated from the base material substrate. In addition, as shown in FIG. 7C and FIG. 7D (FIG. 7D is a cross-sectional view of A-A in FIG. 7C), the islands (708a, 708b, 718a, and 718b in FIG. 7C) separated from the base substrate 701 can be well bonded to the Predetermined positions on the moving destination substrate 731 where other components are mounted in a part of the area (the component etc. mounting area 742 and the component etc. mounting area 744 in FIG. 7C ).

[複合材料元件的製作順序] 圖8A~圖8C是表示使用所述半導體元件的製造方法而製造的半導體元件800的結構的圖。半導體元件800是藉由所述製造方法而製造的複合材料元件。半導體元件800可藉由如下方式製造:將於母材基板上形成了元件結構的半導體薄膜層的島808自母材基板801分離而接合於移動目的地基板831,並形成連接至半導體薄膜層外的配線。此處所示的例子為一例,可適用於各種種類、材料、結構的半導體元件。[Sequence of making composite material components] 8A to 8C are diagrams showing the structure of a semiconductor element 800 manufactured using the above semiconductor element manufacturing method. The semiconductor element 800 is a composite material element manufactured by the manufacturing method. The semiconductor element 800 can be manufactured by separating the island 808 of the semiconductor thin film layer on which the device structure is formed on the base substrate 801 from the base substrate 801, bonding it to the moving destination substrate 831, and forming an island 808 connected to the outside of the semiconductor thin film layer. wiring. The example shown here is an example, and it is applicable to semiconductor elements of various types, materials, and structures.

圖8A示出了半導體元件800的剖面結構。於圖8A中示出了半導體薄膜層的島808;形成於島808的電極822、電極824;於電極位置處包括開口部816a、816b的固定層814;層間絕緣膜842、配線層854及配線層856。FIG. 8A shows a cross-sectional structure of a semiconductor element 800 . In FIG. 8A, an island 808 of a semiconductor thin film layer; an electrode 822 and an electrode 824 formed on the island 808; a fixed layer 814 including openings 816a, 816b at electrode positions; an interlayer insulating film 842, a wiring layer 854, and wiring Layer 856.

當製造半導體元件800時,於母材基板上形成用以形成既定的元件的半導體薄膜層後,形成電極822及電極824、或者進行向半導體薄膜層的島808的分割(元件分離),藉此形成元件結構。其後如圖8B所示般形成固定層814。進而,至少於母材基板801與島808之間形成空隙803。於空隙803的形成中,藉由將預定去除區域蝕刻去除來形成。When manufacturing the semiconductor element 800, after forming the semiconductor thin film layer for forming a predetermined element on the base substrate, the electrode 822 and the electrode 824 are formed, or the island 808 of the semiconductor thin film layer is divided (element separation), whereby Form the element structure. Thereafter, a fixed layer 814 is formed as shown in FIG. 8B. Furthermore, a gap 803 is formed at least between the base substrate 801 and the island 808 . In forming the void 803, it is formed by etching and removing the region to be removed.

其後,將包括包含有機材料的拾取凸塊或拾取層的拾取基板連結於島808及固定層814的一部分區域後,將島808自母材基板801分離。其後,接合於移動目的地基板831上的既定的位置。移動目的地基板831例如亦可設為與母材基板801或島808不同的材料。於接合之前,視需要亦可進行所接合的面(島的接合面及移動目的地基板表面)的用於接合的表面處理。雖未圖示,但亦可於移動目的地基板831與島808之間設置其他薄膜層。Thereafter, the island 808 is separated from the base substrate 801 after a pickup substrate including a pickup bump or a pickup layer made of an organic material is bonded to a part of the island 808 and the fixed layer 814 . Thereafter, bonding is performed at a predetermined position on the moving destination substrate 831 . For example, the destination substrate 831 may be made of a material different from that of the base substrate 801 or the island 808 . Before bonding, surface treatment for bonding may be performed on the surfaces to be bonded (the bonding surface of the island and the surface of the moving destination substrate) as needed. Although not shown, other thin film layers may be provided between the destination substrate 831 and the island 808 .

於將島808接合於移動目的地基板831之後,如圖8C所示,於用作絕緣膜的固定層814中的、島808上的電極822及電極824的位置處形成開口部。其後,形成用於配線形成的層間絕緣膜842,並如圖8A所示般形成配線層854及配線層856,將配線層854及配線層856分別結合於電極822及電極824。如此般,固定層814於島808的上表面、以及於島808的第1方向上的兩側面延伸存在的半導體元件800的製作結束。After the island 808 is bonded to the movement destination substrate 831 , as shown in FIG. 8C , openings are formed at the positions of the electrodes 822 and 824 on the island 808 in the fixed layer 814 serving as an insulating film. Thereafter, interlayer insulating film 842 for wiring formation is formed, and wiring layer 854 and wiring layer 856 are formed as shown in FIG. 8A, and wiring layer 854 and wiring layer 856 are bonded to electrode 822 and electrode 824, respectively. In this way, the fabrication of the semiconductor element 800 in which the fixed layer 814 extends on the upper surface of the island 808 and on both side surfaces of the island 808 in the first direction is completed.

如上所述,根據本實施形態的半導體元件的製造方法,可將形成於母材基板上的包括元件的半導體薄膜層的島良好地自母材基板分離,並可良好地接合於移動目的地基板,從而可獲得具有高性能、高可靠性的複合材料元件。所述製造方法中可適用半導體元件所包括的半導體薄膜層的尺寸、結構等的各種形態。拾取基板所包括的包含有機材料的拾取凸塊例如藉由標準的光微影而製作,因此可與元件結構及半導體薄膜層的形態的各種變更、以及移動目的地基板的形態的各種變更對應地且容易地準備最適合的拾取基板。如此,根據本實施形態的半導體元件的製造方法,可容易地實現最適合的半導體薄膜層的自母材基板的分離及於移動目的地基板上的接合。As described above, according to the method of manufacturing a semiconductor element of this embodiment, the islands formed on the base substrate including the semiconductor thin film layer of the element can be separated from the base substrate satisfactorily and bonded to the transfer destination substrate satisfactorily. , so that composite material components with high performance and high reliability can be obtained. Various forms such as the size and structure of the semiconductor thin film layer included in the semiconductor element can be applied to the above-described manufacturing method. The pick-up bumps containing organic materials included in the pick-up substrate are produced by, for example, standard photolithography, so it can correspond to various changes in the device structure and the shape of the semiconductor thin film layer, as well as various changes in the shape of the moving destination substrate. And it is easy to prepare the most suitable pick-up substrate. Thus, according to the method of manufacturing a semiconductor element of this embodiment, separation of an optimum semiconductor thin film layer from a base substrate and bonding to a transfer destination substrate can be easily realized.

[固定層110的形狀的變形例] 圖9A~圖9D是表示固定層110的形狀的變形例的圖。 如圖9A所示,可使設置於母材基板101的固定層110的寬度L2b及被覆半導體薄膜層的島108的側面的固定層110的寬度L2b較被覆島108的上表面的固定層的寬度L2a窄。藉由所述方式,當藉由拾取基板200將島108自母材基板101拆下時,設置於母材基板101的固定層110與設置於島108的固定層110容易分離。[Modification of the shape of the fixed layer 110] 9A to 9D are diagrams showing modified examples of the shape of the fixing layer 110 . As shown in FIG. 9A, the width L2b of the fixed layer 110 provided on the base substrate 101 and the side surface of the island 108 covering the semiconductor thin film layer can be made wider than the width L2b of the fixed layer covering the upper surface of the island 108. L2a is narrow. In this manner, when the island 108 is detached from the base substrate 101 by picking up the substrate 200 , the fixing layer 110 provided on the base substrate 101 and the fixing layer 110 provided on the island 108 are easily separated.

該情況下,如圖9B所示,於接合於移動目的地基板301的複合材料元件的形態中,被覆半導體薄膜層的島108的短邊的側面的固定層114的寬度L2b亦較被覆半導體薄膜層的島108的上表面的固定層114的寬度L2a窄。In this case, as shown in FIG. 9B , in the form of the composite material element bonded to the moving destination substrate 301, the width L2b of the fixing layer 114 on the short side of the island 108 covering the semiconductor thin film layer is also larger than that of the semiconductor thin film covering layer. The width L2a of the fixed layer 114 on the upper surface of the island of layers 108 is narrow.

另外,如圖9C所示,亦可於被覆半導體薄膜層的島108的固定層110的長邊區域中,設置被覆半導體薄膜層的島108的長邊的側面的一部分且向母材基板101延伸存在的區域130。此時,較佳設為固定層110對長邊的側面的被覆率小於對短邊的被覆率。該情況下,如圖9D所示,於將半導體薄膜層的島108接合於移動目的地基板301的形態下,成為形成有對半導體薄膜層的島108的長邊的側面的一部分進行被覆的固定層110的區域131的狀態。該狀態下,固定層110對長邊的側面的被覆率小於對短邊的被覆率。In addition, as shown in FIG. 9C , in the long side region of the fixed layer 110 of the island 108 covered with the semiconductor thin film layer, a part of the side surface of the long side of the island 108 covered with the semiconductor thin film layer may be provided and extend toward the base substrate 101. area 130 of existence. At this time, it is preferable that the coverage rate of the fixed layer 110 on the side surfaces of the long sides is smaller than the coverage rate of the short sides. In this case, as shown in FIG. 9D , in a state in which the island 108 of the semiconductor thin film layer is bonded to the destination substrate 301 , a fixing member is formed to cover a part of the long sides of the island 108 of the semiconductor thin film layer. The state of region 131 of layer 110. In this state, the coverage rate of the fixed layer 110 on the side surfaces of the long sides is smaller than the coverage rate of the short sides.

[半導體薄膜層104的晶格缺陷的減少] 於Si晶圓上形成GaN磊晶層的過程中,有時會因母材基板101的材料與半導體薄膜層的材料的晶格不匹配、及母材基板101的材料與半導體薄膜層的材料的熱膨脹係數的不匹配(熱膨脹係數的差異)而於半導體薄膜層104中導入結晶缺陷。[Reduction of Lattice Defects in Semiconductor Thin Film Layer 104] In the process of forming a GaN epitaxial layer on a Si wafer, sometimes due to the lattice mismatch between the material of the base substrate 101 and the material of the semiconductor thin film layer, and the difference between the material of the base substrate 101 and the material of the semiconductor thin film layer, The mismatch of thermal expansion coefficients (difference in thermal expansion coefficients) introduces crystal defects into the semiconductor thin film layer 104 .

為解決此種課題,作為母材基板101,可使用與半導體薄膜層相同系統的材料。該情況下,難以利用蝕刻來將半導體薄膜層自母材基板101分離,因此,可將於母材基板101與半導體薄膜層104之間設置有與母材基板101及半導體薄膜層104的材料的蝕刻速度的差大的異種材料層的半導體晶圓用作第1基板。另外,亦可將於母材基板101與半導體薄膜層104之間設置有由晶格常數及熱膨脹係數不同的材料構成的異種材料層的半導體晶圓用作第1基板。作為異種材料層的材料,例如可使用Si。該情況下,較佳為將設置於母材基板101與半導體薄膜層104之間的異種材料層的厚度的上限設為與半導體薄膜層104的厚度相同。In order to solve such a problem, a material of the same system as that of the semiconductor thin film layer can be used as the base substrate 101 . In this case, it is difficult to separate the semiconductor thin film layer from the base substrate 101 by etching. Therefore, a layer that is compatible with the materials of the base substrate 101 and the semiconductor thin film layer 104 may be provided between the base substrate 101 and the semiconductor thin film layer 104. A semiconductor wafer having a dissimilar material layer with a large difference in etching rate is used as the first substrate. In addition, a semiconductor wafer in which a dissimilar material layer made of a material having a different lattice constant and a thermal expansion coefficient is provided between the base substrate 101 and the semiconductor thin film layer 104 may be used as the first substrate. As a material of the dissimilar material layer, for example, Si can be used. In this case, it is preferable to set the upper limit of the thickness of the dissimilar material layer provided between the base substrate 101 and the semiconductor thin film layer 104 to be the same as the thickness of the semiconductor thin film layer 104 .

母材基板101與半導體薄膜層104的晶格常數的差例如小於半導體薄膜層104與異種材料層的晶格常數的差。另外,母材基板101與半導體薄膜層104的熱膨脹係數的差例如小於半導體薄膜層104與異種材料層的熱膨脹係數的差。The difference in lattice constant between the base substrate 101 and the semiconductor thin film layer 104 is, for example, smaller than the difference in lattice constant between the semiconductor thin film layer 104 and the dissimilar material layer. In addition, the difference in thermal expansion coefficient between the base material substrate 101 and the semiconductor thin film layer 104 is, for example, smaller than the difference in thermal expansion coefficient between the semiconductor thin film layer 104 and the dissimilar material layer.

於母材基板101例如為GaN基板,異種材料層例如由Si(111)形成,半導體薄膜層104例如由GaN形成的情況下,GaN的熱膨脹係數2.59 ppm小於Si(111)的熱膨脹係數5.59 ppm,因此有時於母材基板101中產生在下側翹曲的應力(凸出至上側的方向的應力),於半導體薄膜層104中,與母材基板101相反地,產生在上側翹曲的應力(凸出至下側的方向的應力)。如此,藉由於母材基板101及半導體薄膜層104中分別產生相反方向的應力,可使得母材基板101及半導體薄膜層104不易翹曲。When the base substrate 101 is, for example, a GaN substrate, the dissimilar material layer is formed of, for example, Si(111), and the semiconductor thin film layer 104 is formed of, for example, GaN, the thermal expansion coefficient of GaN is 2.59 ppm smaller than that of Si(111) which is 5.59 ppm. Therefore, the stress of warping on the lower side (stress in the direction projecting to the upper side) may be generated in the base material substrate 101, and the stress of warping on the upper side may be generated in the semiconductor thin film layer 104 contrary to the base material substrate 101 ( Stress in the direction of protrusion to the lower side). In this way, by generating stress in opposite directions in the base substrate 101 and the semiconductor thin film layer 104 , the base substrate 101 and the semiconductor thin film layer 104 are less likely to warp.

進而,藉由將設置於母材基板101與半導體薄膜層104之間的異種材料層的厚度的上限設為與半導體薄膜層104相同,即便設置於母材基板101與半導體薄膜層104之間的異種材料層的熱膨脹係數與半導體薄膜層104的熱膨脹係數不同,但基板(母材基板101與薄的異種材料層的積層結構)的熱應力對半導體薄膜層104的影響中,與半導體薄膜層104的熱膨脹係數差小的母材基板101的影響為支配性的。因此,可將異種材料層對半導體薄膜層104帶來的熱應力的影響抑制得小。其結果,可減少半導體薄膜層104的晶格缺陷。Furthermore, by setting the upper limit of the thickness of the dissimilar material layer provided between the base substrate 101 and the semiconductor thin film layer 104 to be the same as that of the semiconductor thin film layer 104, even the dissimilar material layer provided between the base substrate 101 and the semiconductor thin film layer 104 The thermal expansion coefficient of the dissimilar material layer is different from that of the semiconductor thin film layer 104, but the thermal stress of the substrate (laminated structure of the base substrate 101 and the thin dissimilar material layer) affects the semiconductor thin film layer 104 differently from that of the semiconductor thin film layer 104. The influence of the base substrate 101 with a small difference in thermal expansion coefficient is dominant. Therefore, the influence of the thermal stress on the semiconductor thin film layer 104 by the foreign material layer can be suppressed to be small. As a result, lattice defects in the semiconductor thin film layer 104 can be reduced.

另外,異種材料層相對於既定的蝕刻方法的蝕刻速度大於母材基板101及半導體薄膜層104相對於既定的蝕刻方法的蝕刻速度。藉由所述方式,可形成晶格缺陷少的半導體薄膜層104,並且藉由利用異種材料層來形成圖1C所示的預定去除區域106,可有效率地形成空隙103。In addition, the etching rate of the dissimilar material layer by a predetermined etching method is higher than the etching rate of the base substrate 101 and the semiconductor thin film layer 104 by a predetermined etching method. In this way, the semiconductor thin film layer 104 with few lattice defects can be formed, and the void 103 can be efficiently formed by using a different material layer to form the planned removal region 106 shown in FIG. 1C.

[移動目的地基板301的材料的變形例] 於半導體元件的晶片尺寸大的情況下會產生如下課題:因作為半導體元件晶片的基底的基板材料的熱傳導特性而於晶片內產生熱分佈,當半導體元件晶片動作時,於晶片的中央區域,晶片的溫度上昇大。尤其於作為半導體元件晶片的基底的基板的熱傳導率小的情況下,會產生該溫度分佈大的課題。[Modification of the material of the moving destination substrate 301 ] When the wafer size of the semiconductor element is large, the following problems will arise: due to the heat conduction characteristics of the substrate material that is the base of the semiconductor element wafer, heat distribution occurs in the wafer. When the semiconductor element wafer operates, in the central area of the wafer, the wafer temperature rise is large. In particular, when the thermal conductivity of the substrate serving as the base of the semiconductor element wafer is low, the problem of large temperature distribution arises.

因此,作為移動目的地基板301的材料,可選擇具有較母材基板101的熱傳導率高的熱傳導率的材料。作為移動目的地基板301,例如可使用:SiC、AlN、SiN等的陶瓷基板;Cu或Al等的金屬基板;包含由W、Cr、Cu、Mo等多種金屬構成的複合金屬材料、金屬材料層與陶瓷材料的複合材料基板或積層材料基板;包含碳的材料的基板等。藉由使移動目的地基板301的熱傳導率大於母材基板101的熱傳導率,可製造容易散熱的半導體元件。Therefore, as the material of the moving destination substrate 301 , a material having a thermal conductivity higher than that of the base substrate 101 can be selected. As the destination substrate 301, for example, ceramic substrates such as SiC, AlN, and SiN; metal substrates such as Cu or Al; composite metal materials or metal material layers composed of various metals such as W, Cr, Cu, and Mo, etc. can be used. Composite material substrates or laminated material substrates with ceramic materials; substrates of materials containing carbon, etc. By making the thermal conductivity of the moving destination substrate 301 higher than that of the base substrate 101 , it is possible to manufacture a semiconductor element that can easily dissipate heat.

藉由將半導體薄膜層分割成多個島,並將分別形成於分割後的多個島上的多個要素元件相互連接,可使要素元件的散熱性提高,因此可抑制由多個要素元件構成的半導體元件的溫度上昇。尤其藉由作為移動目的地基板301而使用熱傳導率高的材料,即便於流動大電流的動作中亦可抑制各要素元件的溫度上昇。By dividing the semiconductor thin film layer into a plurality of islands and connecting the plurality of element elements formed on the divided islands to each other, the heat dissipation of the element elements can be improved, so that the heat dissipation of the element elements can be suppressed. The temperature of the semiconductor element rises. In particular, by using a material with high thermal conductivity as the moving destination substrate 301 , it is possible to suppress the temperature rise of each element element even during an operation in which a large current flows.

當製造由多個要素元件構成的集合半導體元件時,可使形成於母材基板101的半導體薄膜層的多個島108同時移動至移動目的地基板301。藉由於移動至移動目的地基板301的多個島108上形成電極,或者形成將多個島108的至少任一個之間加以連接的配線圖案,可製造多個要素元件聯合動作的集合半導體元件。When manufacturing an aggregated semiconductor element composed of a plurality of element elements, a plurality of islands 108 formed in the semiconductor thin film layer of the base substrate 101 can be simultaneously moved to the transfer destination substrate 301 . By forming electrodes on the plurality of islands 108 moved to the moving destination substrate 301 or forming a wiring pattern connecting at least any one of the plurality of islands 108 , it is possible to manufacture a collective semiconductor element in which a plurality of element elements operate in conjunction.

[結晶方向的最佳化] 圖10是示意性地例示用作母材基板101的半導體磊晶晶圓的圖。於圖10中,示出了形成於作為母材基板101的Si基板上的多個III族氮化物半導體薄膜層的島108。為以良好的狀態將III族氮化物半導體薄膜層的島108自母材基板101拆下,島108的邊的方向較佳為相對於作為母材基板101的Si(111)基板的<112>方向而為±45°以下的角度範圍。島108的長邊的方向較佳為作為母材基板101的Si(111)基板的<112>方向。[Optimization of crystal orientation] FIG. 10 is a diagram schematically illustrating a semiconductor epitaxial wafer used as a base substrate 101 . In FIG. 10 , islands 108 of a plurality of group III nitride semiconductor thin film layers formed on a Si substrate as a base substrate 101 are shown. In order to remove the island 108 of the Group III nitride semiconductor thin film layer from the base substrate 101 in a good state, the direction of the side of the island 108 is preferably <112> relative to the Si (111) substrate serving as the base substrate 101 The direction is an angle range of ±45° or less. The direction of the long side of the island 108 is preferably the <112> direction of the Si (111) substrate as the base substrate 101 .

Si(111)相對於特定的蝕刻液而顯示出異向性蝕刻特性。藉由利用Si(111)的異向性蝕刻特性,無需對晶圓整體進行蝕刻去除,藉由利用蝕刻而將Si(111)的表面區域去除,便可將於Si(111)上進行磊晶成長而得的半導體薄膜層自Si(111)分離。以前,於使用Si(111)作為母材基板101的情況下,並不知曉於母材基板101上進行磊晶成長而形成的半導體薄膜層的島108的方向的較佳方向。相對於此,發明者發現,較佳為將島108的一條邊(例如較長的邊)的方向設為相對於Si基板的<112>方向而為±45°以下的角度範圍。尤其發明者發現,進而較佳為將島108的長邊的方向設為與Si基板的<112>方向大致平行。Si(111) exhibits anisotropic etching properties with respect to a specific etchant. By using the anisotropic etching characteristics of Si (111), it is not necessary to etch and remove the entire wafer, and by removing the surface area of Si (111) by etching, epitaxy can be performed on Si (111) The grown semiconductor thin film layer is separated from Si(111). Conventionally, when Si (111) was used as the base substrate 101 , the preferred direction of the direction of the islands 108 of the semiconductor thin film layer formed by epitaxial growth on the base substrate 101 was not known. On the other hand, the inventors found that it is preferable to set the direction of one side (for example, the longer side) of the island 108 within an angle range of ±45° or less with respect to the <112> direction of the Si substrate. In particular, the inventors found that it is more preferable to make the direction of the long side of the island 108 substantially parallel to the <112> direction of the Si substrate.

另外,發明者發現,於由六方晶形成半導體薄膜層的島108的情況下,較佳為將半導體薄膜層的島108的長邊的方向設為相對於如GaN等III族氮化物半導體單結晶般的六方晶材料的<1-100>方向而成為±45°以下的角度範圍。尤其發明者發現,進而較佳為將半導體薄膜層的島108的長邊的方向設為與六方晶材料的<1-100>方向大致平行。In addition, the inventors have found that, in the case where the island 108 of the semiconductor thin film layer is formed from a hexagonal crystal, it is preferable to set the direction of the long side of the island 108 of the semiconductor thin film layer relative to the single crystal of a group III nitride semiconductor such as GaN. The <1-100> direction of the general hexagonal crystal material becomes the angle range of ±45° or less. In particular, the inventors found that it is more preferable to set the direction of the long side of the island 108 of the semiconductor thin film layer approximately parallel to the <1-100> direction of the hexagonal crystal material.

如圖10所示,島108具有長度為L3的邊與長度為L4的邊。於以下的說明中,例示為邊的長度L3較邊的長度L4長的長方形的情況,但於L3=L4的情況下(即島108為正方形的情況下),將任一邊設為長邊而亦可適用本發明。As shown in FIG. 10, island 108 has sides of length L3 and sides of length L4. In the following description, the case of a rectangle whose side length L3 is longer than the side length L4 is exemplified, but in the case of L3=L4 (that is, when the island 108 is a square), any side is set as the long side and The present invention is also applicable.

於島108為長方形的情況下,較佳為以使具有L3的長度的邊(較長的邊)與Si(111)基板的<112>方向大致平行的方式形成島108。此處,所謂大致平行,是指於某一定的誤差或偏差的範圍內平行,且不會極端大幅地偏離平行(例如相對於平行而不會超過±10°)。When the island 108 is a rectangle, it is preferable to form the island 108 so that the side (the longer side) having the length of L3 is substantially parallel to the <112> direction of the Si (111) substrate. Here, the term “approximately parallel” means parallel within a certain range of error or deviation, and does not deviate extremely greatly from parallel (for example, within ±10° relative to parallel).

若於Si(111)基板上使C面((0001)面)的III族氮化物半導體薄膜層進行結晶成長,則Si的<112>方向與III族氮化物半導體薄膜層的結晶方向<1-100>方向平行。該情況下,較佳為以使島108的長度為L3的邊與III族氮化物半導體磊晶層的結晶的<1-100>方向大致平行的方式形成島108。If the group III nitride semiconductor thin film layer on the C plane ((0001) plane) is crystallized and grown on a Si (111) substrate, the <112> direction of Si and the crystallographic direction of the group III nitride semiconductor thin film layer <1- 100 > direction parallel. In this case, it is preferable to form the island 108 so that the side of the island 108 whose length is L3 is substantially parallel to the <1-100> direction of the crystallization of the Group III nitride semiconductor epitaxial layer.

如已述般,作為形成島108的方法而可採用多種方法,例如,藉由對結晶成長而得的半導體薄膜層實施蝕刻,可形成一條邊的方向與III族氮化物半導體磊晶層的結晶的<1-100>方向大致平行的半導體薄膜層的島108。As already mentioned, various methods can be used as a method for forming the island 108. For example, by etching the semiconductor thin film layer obtained by crystal growth, the crystallization of the group III nitride semiconductor epitaxial layer in the direction of one side can be formed. The <1-100> direction is substantially parallel to the island 108 of the semiconductor thin film layer.

另外,亦可藉由於母材基板101上由SiO2 、Six Ny 等的無機絕緣膜形成具有開口的遮罩層,並於開口區域中使半導體薄膜層選擇成長,從而形成島108的最長的邊的方向與Si(111)的<112>方向或六方晶的<1-100>方向大致平行的半導體薄膜層的島108。另外,亦可藉由自選擇成長而得的半導體薄膜層沿橫向於遮罩層上進行結晶成長,而形成島108的最長的邊的方向與Si(111)的<112>方向或六方晶的<1-100>方向大致平行的半導體薄膜層的島108。於遮罩層上進行結晶成長而得的半導體薄膜層的島108與在遮罩層之外的區域進行結晶成長而得的半導體薄膜層相比,缺陷少,可獲得高品質的結晶成長區域。In addition, a mask layer with openings can also be formed on the base substrate 101 by an inorganic insulating film such as SiO 2 , Six N y , etc., and the semiconductor thin film layer is selectively grown in the opening area, thereby forming the longest part of the island 108 The island 108 of the semiconductor thin film layer whose edge direction is approximately parallel to the <112> direction of Si (111) or the <1-100> direction of the hexagonal crystal. In addition, the direction of the longest side of the island 108 and the <112> direction of Si (111) or the direction of the hexagonal crystal can also be formed by self-selectively growing the semiconductor thin film layer to carry out crystal growth on the mask layer in the lateral direction. The <1-100> direction is substantially parallel to the island 108 of the semiconductor thin film layer. The island 108 of the semiconductor thin film layer obtained by crystal growth on the mask layer has fewer defects than the semiconductor thin film layer obtained by crystal growth in a region other than the mask layer, and a high-quality crystal growth region can be obtained.

根據發明者進行的驗證實驗,於使半導體薄膜層的島108的長邊(L3的長度的邊)大致平行於Si(111)基板的<110>方向的情況下(將圖10所示的矩形的島108旋轉90°後的情況),元件區域的正下方的Si(111)基板表面的蝕刻未進行,無法進行遍及島108的正下方整個面的、Si基板表面的蝕刻去除。其結果,無法自用作母材基板101的Si(111)基板以良好的狀態將島108拆下。According to the verification experiment conducted by the inventors, in the case where the long side (the side of the length of L3) of the island 108 of the semiconductor thin film layer is approximately parallel to the <110> direction of the Si (111) substrate (the rectangle shown in FIG. 10 When the island 108 is rotated by 90°), the etching of the Si (111) substrate surface directly below the element region does not proceed, and the etching removal of the Si substrate surface over the entire surface directly below the island 108 cannot be performed. As a result, the island 108 cannot be detached from the Si (111) substrate serving as the base substrate 101 in a good state.

圖11A、圖11B是發明者藉由實驗調查而得的、表示半導體薄膜層的島108的長邊的方向與Si(111)的<112>方向或六方晶的<1-100>方向所成的角度θ、與垂直於半導體薄膜層的島108的長邊的方向上的Si(111)基板表面區域的蝕刻速度之間的關係的圖。圖11A的縱軸示出了設為θ=0°、45°、90°的情況下的蝕刻速度除以0°的情況下的蝕刻速度而得的值。圖11B是用以說明角度θ的圖。Figures 11A and 11B are obtained by the inventors through experimental investigations, showing the relationship between the direction of the long side of the island 108 of the semiconductor thin film layer and the <112> direction of Si (111) or the <1-100> direction of the hexagonal crystal. The graph of the relationship between the angle θ of , and the etching rate of the Si (111) substrate surface region in the direction perpendicular to the long side of the island 108 of the semiconductor thin film layer. The vertical axis of FIG. 11A shows the value obtained by dividing the etching rate when θ=0°, 45°, and 90° by the etching rate when 0°. FIG. 11B is a diagram for explaining the angle θ.

如圖11A所示,若θ超過45°而趨向90°,則相對於與長邊垂直的方向而言的蝕刻速度大幅降低。如圖11A、圖11B所示,為使島108與Si(111)基板之間的蝕刻良好地進行而於島108與Si(111)基板之間的、島108的正下方區域整體中形成空隙,理想的是島108的長邊的方向與Si(111)的<112>方向或六方晶的<1-100>方向所成的角度θ至少不超過45°。As shown in FIG. 11A , when θ exceeds 45° and tends to 90°, the etching rate with respect to the direction perpendicular to the long side decreases significantly. As shown in FIG. 11A and FIG. 11B , in order to allow the etching between the island 108 and the Si (111) substrate to progress favorably, a void is formed between the island 108 and the Si (111) substrate in the entire area directly under the island 108 Ideally, the angle θ formed by the direction of the long side of the island 108 and the <112> direction of Si (111) or the <1-100> direction of the hexagonal crystal does not exceed at least 45°.

根據該結果可確認,當遍及島108的正下方的整個面而將Si(111)基板的表面區域蝕刻去除時,為進行遍及島108的正下方整個面的、Si基板表面的蝕刻去除而以良好的狀態將島108自Si(111)基板拆下,理想的是將矩形形狀的島108的長邊(長度為L1的邊)的方向與Si(111)基板的<112>方向的角度設定成±45°以下的角度範圍。From this result, it can be confirmed that when the surface region of the Si (111) substrate is etched and removed over the entire surface immediately below the island 108, the Si substrate surface is etched and removed over the entire surface immediately below the island 108. Good condition Remove the island 108 from the Si(111) substrate, ideally set the angle between the direction of the long side (the side with length L1) of the rectangular shaped island 108 and the <112> direction of the Si(111) substrate Angle range below ±45°.

於半導體薄膜層為III族氮化物或SiC般的六方晶系的結晶的情況下,理想的是使矩形的半導體薄膜層的島108的長邊(圖10的L3)的方向與六方晶的<1-100>的方向所成的角度θ為±45°以下的角度範圍。再者,半導體薄膜層的島108亦可為具有III族氮化物半導體或SiC以外的六方晶系的材料,例如為ZnO。In the case where the semiconductor thin film layer is a hexagonal crystal like Group III nitride or SiC, it is desirable to make the direction of the long side (L3 in FIG. The angle θ formed by the directions of 1-100> is within an angle range of ±45° or less. Furthermore, the island 108 of the semiconductor thin film layer can also be a hexagonal material other than Group III nitride semiconductor or SiC, such as ZnO.

於以上的說明中,以半導體薄膜層的島108為矩形形狀的情況為例進行了說明,於半導體薄膜層的島108為其他形狀的情況下,可將半導體薄膜層的島108中最長的邊設為與Si(111)基板的<112>方向大致平行的方向(使最長的邊的方向與半導體磊晶層的結晶的<1-100>方向大致平行)。In the above description, the case where the island 108 of the semiconductor thin film layer is a rectangular shape has been described as an example. The direction is substantially parallel to the <112> direction of the Si (111) substrate (the direction of the longest side is substantially parallel to the <1-100> direction of the crystal of the semiconductor epitaxial layer).

圖12是表示Si(111)基板的母材基板101上所設置的六角形狀的半導體薄膜層的島109的圖。島109具有長度為L1、L2、L3的邊,且滿足L1>L2、L3的關係。即,長度為L1的邊為最長的邊。如圖12所示,使半導體薄膜層的島109的L1長度的邊與Si(111)的<112>方向大致平行。該情況下,於將由六方晶構成的半導體薄膜層的島109接合於移動目的地基板301上的形態下,半導體薄膜層的島109的L1長度的邊(即最長的邊)與六方晶的<1-100>方向大致平行。FIG. 12 is a diagram showing islands 109 of hexagonal semiconductor thin film layers provided on a base material substrate 101 of a Si (111) substrate. The island 109 has sides with lengths L1, L2, and L3, and satisfies the relationship of L1>L2, L3. That is, the side with length L1 is the longest side. As shown in FIG. 12 , the side of the island 109 of the semiconductor thin film layer having the L1 length is substantially parallel to the <112> direction of Si (111). In this case, in the state where the island 109 of the semiconductor thin film layer made of hexagonal crystal is bonded to the destination substrate 301, the side (i.e. the longest side) of the L1 length of the island 109 of the semiconductor thin film layer and the < 1-100 > Directions roughly parallel.

再者,母材基板101亦可為絕緣體上矽(Silicon on Insulator,SOI)基板。另外,亦可為將母材基板101與半導體薄膜層設為同種材料的基板。例如,於半導體薄膜層為III族氮化物半導體的情況下,母材基板101可為例如於GaN基板上設置有Si(111)層的基板。在將於GaN基板上設置有Si(111)的基板設為母材基板101的情況下,GaN可為絕緣基板(半絕緣性基板或高電阻基板),亦可為導電性基板(摻雜有不純物的基板)。Furthermore, the base substrate 101 may also be a silicon-on-insulator (SOI) substrate. In addition, it may be a substrate in which the base material substrate 101 and the semiconductor thin film layer are made of the same material. For example, when the semiconductor thin film layer is a III-nitride semiconductor, the base substrate 101 may be, for example, a GaN substrate provided with a Si(111) layer. In the case where the substrate provided with Si (111) on the GaN substrate is used as the base substrate 101, GaN may be an insulating substrate (semi-insulating substrate or high-resistance substrate), or a conductive substrate (doped with Substrates of impurities).

作為其他例子,母材基板101可為例如將Si(111)層晶圓接合於石英基板或藍寶石基板等包含氧化物材料、SiN或AlN等氮化物材料、或者半導體材料的基板上而成的基板。As another example, the base substrate 101 may be, for example, a substrate obtained by bonding an Si (111) layer wafer to a substrate containing an oxide material such as a quartz substrate or a sapphire substrate, a nitride material such as SiN or AlN, or a semiconductor material. .

(實驗例) 圖13A是作為母材基板101的Si(111)基板上所形成的GaN半導體薄膜層的島的顯微鏡相片。圖13A是將半導體薄膜層的島的至少正下方的Si(111)基板的表面區域蝕刻去除後的狀態的顯微鏡相片,所述半導體薄膜層的島在與Si(111)的<112>方向大致平行或者與GaN半導體薄膜層的<1-100>方向大致平行的方向上具有長邊。於半導體薄膜層的島的至少正下方區域中,在半導體薄膜層的島與Si(111)基板之間形成有空隙。(experimental example) 13A is a microscope photograph of islands of a GaN semiconductor thin film layer formed on a Si (111) substrate serving as a base substrate 101 . Fig. 13A is a microscope photo of the state after at least the surface region of the Si (111) substrate directly below the island of the semiconductor thin film layer is etched and removed, and the island of the semiconductor thin film layer is approximately in the <112> direction of the Si (111) There are long sides in a direction parallel or approximately parallel to the <1-100> direction of the GaN semiconductor thin film layer. A gap is formed between the island of the semiconductor thin film layer and the Si (111) substrate in at least a region directly below the island of the semiconductor thin film layer.

圖13B是相對於母材基板101的結晶方向的半導體薄膜層的島的長邊的方向與圖13A不同的、GaN半導體薄膜層的島的顯微鏡相片。圖13B示出了經過對半導體薄膜層的島的至少正下方的Si(111)基板的表面區域進行蝕刻的步驟之後的狀態,所述半導體薄膜層的島在與Si(111)的<112>方向大致垂直或者與GaN半導體薄膜層的<1-100>方向大致垂直的方向上具有長邊。如圖13B所示,於半導體薄膜層的島的至少正下方區域中,殘存有在半導體薄膜層的島與Si(111)基板之間未形成空隙的區域。FIG. 13B is a microscope photograph of the islands of the GaN semiconductor thin film layer in which the direction of the long sides of the islands of the semiconductor thin film layer with respect to the crystallographic direction of the base substrate 101 is different from FIG. 13A . FIG. 13B shows the state after the step of etching at least the surface region of the Si(111) substrate immediately below the island of the semiconductor thin film layer at <112> with the Si(111) The direction is substantially vertical or has a long side in a direction substantially perpendicular to the <1-100> direction of the GaN semiconductor thin film layer. As shown in FIG. 13B , in at least the region immediately below the island of the semiconductor thin film layer, a region where no gap is formed between the island of the semiconductor thin film layer and the Si (111) substrate remains.

再者,圖13B所示的樣本的蝕刻時間為圖13A所示的樣本的蝕刻時間的約3倍。圖13B的由(1)表示的區域的顏色看起來深,該顏色看起來深的區域為未形成空隙的區域。如圖13B所示,即便對圖13B所示的樣本進行相當長時間的蝕刻,於半導體薄膜層的島的正下方區域中,亦殘存有在半導體薄膜層的島與Si(111)基板之間未形成空隙的區域。Furthermore, the etching time of the sample shown in FIG. 13B was about three times that of the sample shown in FIG. 13A . The color of the region indicated by (1) in FIG. 13B appears dark, and the region where the color appears dark is a region where voids are not formed. As shown in FIG. 13B, even if the sample shown in FIG. 13B is etched for a relatively long time, in the region directly below the island of the semiconductor thin film layer, there remains a gap between the island of the semiconductor thin film layer and the Si (111) substrate. Areas where voids are not formed.

圖13B的由(2)表示的區域為固定層。圖13B的由(3)表示的區域為半導體薄膜層。於圖13B的由(4)表示的區域中,可確認到於半導體薄膜層的島中產生了蝕刻損傷。The region indicated by (2) in FIG. 13B is the fixed layer. The region indicated by (3) in FIG. 13B is a semiconductor thin film layer. In the region indicated by (4) in FIG. 13B , it was confirmed that etching damage occurred in the islands of the semiconductor thin film layer.

如以上所說明般,藉由發明者的實驗可確認到,為了將六方晶的半導體薄膜層(例如GaN、InN、AlN、GaN/Alx Ga1-x N/Inx Ga1-x N等的積層;SiC、ZnO等的半導體薄膜層)的島自第1基板(Si(111)基板)分離而於六方晶的半導體薄膜層的島的正下方的整個區域中,在半導體薄膜層的島與第1基板之間形成空隙,為此,理想的是使半導體薄膜層的島的長邊的方向至少與Si(111)的<112>的方向大致平行,或者與六方晶(GaN磊晶層)的<1-100>的方向大致平行。As explained above, it has been confirmed by the experiment of the inventors that in order to form a hexagonal semiconductor thin film layer (such as GaN, InN, AlN, GaN/ AlxGa1 -xN / InxGa1 -xN , etc. stacked layer; the island of the semiconductor thin film layer of SiC, ZnO, etc.) is separated from the first substrate (Si (111) substrate) and in the entire area directly below the island of the hexagonal semiconductor thin film layer, the island of the semiconductor thin film layer To form a gap with the first substrate, it is ideal to make the direction of the long side of the island of the semiconductor thin film layer at least roughly parallel to the <112> direction of Si (111), or to align with the hexagonal (GaN epitaxial layer ) The direction of <1-100> is roughly parallel.

圖14是在發明者所進行的實驗中,將長邊與<1-100>方向大致平行的半導體薄膜層的島接合於移動目的地基板301的狀態的顯微鏡相片。如圖14所示,於半導體薄膜層的島上殘留有固定層114的一部分(被覆半導體薄膜層的島的上表面及短邊的側面的一部分區域的固定層)。14 is a microscope photograph of a state where islands of semiconductor thin film layers whose long sides are substantially parallel to the <1-100> direction are bonded to a moving destination substrate 301 in an experiment conducted by the inventors. As shown in FIG. 14 , a part of the fixed layer 114 (the fixed layer covering the upper surface of the island of the semiconductor thin film layer and a part of the side surface of the short side) remains on the island of the semiconductor thin film layer.

於圖14所示的顯微鏡相片中,接合於移動目的地基板301的半導體薄膜層的島中未觀察到干涉條紋或色不均,能夠確認半導體薄膜層的島可良好地接合於移動目的地基板301。認為如此般半導體薄膜層的島可以良好的狀態接合於移動目的地基板301的理由在於:可形成<1-100>方向與半導體薄膜層的島的長邊的方向大致平行的半導體薄膜層的島,且可於半導體薄膜層的島與母材基板101之間,至少在半導體薄膜層的島的正下方區域中形成空隙,並且於面向空隙的半導體薄膜層的表面未產生由蝕刻步驟造成的損傷。且認為原因在於:藉由於半導體薄膜層的島的正下方區域中形成有空隙的狀態下將半導體薄膜層的島自母材基板101分離,可以良好的狀態將半導體薄膜層的島自母材基板101分離。In the microscope photograph shown in FIG. 14 , no interference fringe or color unevenness was observed in the islands of the semiconductor thin film layer bonded to the destination substrate 301, and it was confirmed that the islands of the semiconductor thin film layer were well bonded to the destination substrate. 301. It is considered that the reason why the islands of the semiconductor thin film layer can be bonded to the destination substrate 301 in a good state is that the islands of the semiconductor thin film layer whose <1-100> direction is substantially parallel to the direction of the long side of the island of the semiconductor thin film layer can be formed. , and between the island of the semiconductor thin film layer and the base material substrate 101, a void can be formed at least in the area directly below the island of the semiconductor thin film layer, and the surface of the semiconductor thin film layer facing the void is not damaged by the etching step. . The reason is considered to be that by separating the islands of the semiconductor thin film layer from the base substrate 101 in a state where a void is formed in the region directly below the islands of the semiconductor thin film layer, the islands of the semiconductor thin film layer can be separated from the base substrate 101 in a good state. 101 separation.

[使固定層110容易斷裂的方法] 圖15A、圖15B是用以說明使固定層110容易斷裂的方法的圖。如圖15A所示,於半導體薄膜層的島108與母材基板101之間形成空隙的蝕刻步驟中,亦可形成遍及較圖1E所示的空隙103更廣的區域而形成的空隙117。於圖15A所示的例子中,於母材基板101上形成有固定層110的區域的一部分中,在固定層110與母材基板101之間形成有空隙117。[Method of making the fixing layer 110 easy to break] 15A and 15B are diagrams for explaining a method of making the fixing layer 110 easy to break. As shown in FIG. 15A , in the etching step for forming a space between the island 108 of the semiconductor thin film layer and the base substrate 101 , the space 117 may be formed over a wider area than the space 103 shown in FIG. 1E . In the example shown in FIG. 15A , a gap 117 is formed between the fixing layer 110 and the base substrate 101 in a part of the region where the fixing layer 110 is formed on the base substrate 101 .

若於該狀態下對固定層110施加向下的力,則會對固定層110中的、與母材基板101之間存在空隙117的區域的角部(圖15A的虛線的橢圓部分)附加大的應力,從而於圖15B所示的虛線的部分容易產生龜裂或斷裂。If a downward force is applied to the fixed layer 110 in this state, a large force will be added to the corner of the fixed layer 110 in the area where the gap 117 exists between the base material substrate 101 (the elliptical portion of the dotted line in FIG. 15A ). Stress, so cracks or fractures are likely to occur at the portion shown by the dotted line in FIG. 15B.

圖16是表示實際的實驗中對固定層110的分離狀態進行觀察而得的結果的顯微鏡相片。圖16是對自母材基板101分離後的半導體薄膜層的島108自背面(預定接合面)進行觀察而得的顯微鏡相片。於圖16的由A表示的部位具有被覆半導體薄膜層的島108的側面的一部分區域的固定層110。圖16是自半導體薄膜層的島的背面進行觀察,因此難以觀察到固定層110的上表面部分,但圖16的由A附近的括號表示的寬度的固定層110是自半導體薄膜層的島108的側面a經由半導體薄膜層的島108的上表面(與圖16中所觀察到的面為相反側的面)而到達側面b。FIG. 16 is a microscope photograph showing the results of observing the separation state of the pinned layer 110 in an actual experiment. FIG. 16 is a microscope photograph obtained by observing the island 108 of the semiconductor thin film layer separated from the base substrate 101 from the back surface (surface to be joined). A portion indicated by A in FIG. 16 has a fixed layer 110 covering a part of the side surface of the island 108 of the semiconductor thin film layer. Fig. 16 is observed from the back side of the island of the semiconductor thin film layer, so it is difficult to observe the upper surface part of the fixed layer 110, but the fixed layer 110 of the width represented by the brackets near A in Fig. 16 is from the island 108 of the semiconductor thin film layer. The side a of the semiconductor thin film layer reaches the side b via the upper surface of the island 108 of the semiconductor thin film layer (the surface opposite to the surface observed in FIG. 16 ).

如圖16所示,未觀察到自半導體薄膜層的島108的側面向半導體薄膜層的島108的外側延伸存在的固定層110。另外,未觀察到超出圖16所示的半導體薄膜層的島108的背面(利用顯微鏡觀察到的面)的高度而延展的固定層110。As shown in FIG. 16 , the fixed layer 110 extending from the side of the island 108 of the semiconductor thin film layer to the outside of the island 108 of the semiconductor thin film layer was not observed. In addition, the fixed layer 110 extending beyond the height of the back surface (the surface observed with a microscope) of the island 108 of the semiconductor thin film layer shown in FIG. 16 was not observed.

圖17是將圖16所示的自母材基板分離後的半導體薄膜層的島108接合於移動目的地基板301的狀態的顯微鏡相片。於圖17所示的半導體薄膜層的島108的上表面及側面中殘留有固定層110的一部分。如圖17所示,自母材基板101分離後的半導體薄膜層的島108可良好地接合於移動目的地基板301。FIG. 17 is a microscope photograph of a state in which the semiconductor thin film layer island 108 separated from the base substrate shown in FIG. 16 is bonded to the destination substrate 301 . A part of the fixed layer 110 remains on the upper surface and side surfaces of the island 108 of the semiconductor thin film layer shown in FIG. 17 . As shown in FIG. 17 , the island 108 of the semiconductor thin film layer separated from the base substrate 101 can be satisfactorily bonded to the destination substrate 301 .

於圖16及圖17所示的顯微鏡觀察相片中,設置於半導體薄膜層的島108的固定層的位置形成於自半導體薄膜層的島108的中心位置稍向上方偏移的位置,但相對於半導體薄膜層的島108而形成固定層110的位置亦可為半導體薄膜層的島108的中心線上,亦可形成於自中心線偏移的位置。另外,形成固定層110的位置亦可為相對於島108的中心線而傾斜的方向。In the microscope observation photographs shown in FIGS. 16 and 17 , the position of the fixed layer provided on the island 108 of the semiconductor thin film layer is formed at a position slightly shifted upward from the center position of the island 108 of the semiconductor thin film layer, but relative to The position where the fixed layer 110 is formed on the island 108 of the semiconductor thin film layer can also be the center line of the island 108 of the semiconductor thin film layer, and can also be formed at a position offset from the center line. In addition, the position where the fixed layer 110 is formed may also be inclined relative to the center line of the island 108 .

另外,固定層110亦可具有自在相當於第1方向的長度方向上延伸存在的區域的至少一部分區域起,在相當於第2方向的短邊方向上延伸的區域。圖18A、圖18B是表示具有在短邊方向上延伸的區域的固定層110的例子的圖。圖18A所示的固定層110具有自固定層110的長度方向中的同一位置起向兩側延伸的區域。圖18B所示的固定層110具有自固定層110的長度方向中的不同位置起向兩側延伸的區域。In addition, the fixed layer 110 may have a region extending in the short-side direction corresponding to the second direction from at least a part of the region extending in the longitudinal direction corresponding to the first direction. 18A and 18B are diagrams showing examples of the fixed layer 110 having regions extending in the short-side direction. The fixed layer 110 shown in FIG. 18A has regions extending to both sides from the same position in the longitudinal direction of the fixed layer 110 . The fixed layer 110 shown in FIG. 18B has regions extending to both sides from different positions in the length direction of the fixed layer 110 .

[半導體薄膜層中的階差結構的形成] 於在半導體薄膜層中形成元件結構的情況下,根據元件結構的功能而於半導體薄膜層中形成階差。圖19A、圖19B是示意性地表示將母材基板1001上所形成的半導體薄膜層分割成各別的半導體薄膜層的島的狀態的圖。圖19A是母材基板1001及半導體薄膜層的島的頂視圖,圖19B是剖面圖。半導體薄膜層的島具有高度各不相同的多個區域(1002a、1002b)。[Formation of Step Structure in Semiconductor Thin Film Layer] In the case of forming the device structure in the semiconductor thin film layer, a step difference is formed in the semiconductor thin film layer according to the function of the device structure. 19A and 19B are diagrams schematically showing a state in which the semiconductor thin film layer formed on the base substrate 1001 is divided into islands of individual semiconductor thin film layers. FIG. 19A is a top view of the base substrate 1001 and islands of the semiconductor thin film layer, and FIG. 19B is a cross-sectional view. The island of the semiconductor thin film layer has a plurality of regions ( 1002 a , 1002 b ) with different heights.

於將形成有此種半導體薄膜層的島的母材基板1001的表面蝕刻去除而將半導體薄膜層的島自母材基板分離的步驟中,因區域1002b的厚度小於區域1002a的厚度,故母材基板1001中的區域1002b的周邊亦因蝕刻而被去除。因於蝕刻前形成抗蝕劑遮罩開口部時的遮罩開口部的對準精度不為±0,故於遮罩開口部與島的外周線之間產生偏移。因此,為確保餘裕(margin),需要使抗蝕劑遮罩開口部的外周線位於島的外周線的外側。其結果,如19B所示般,於區域1002b的周邊的區域中形成槽1003。In the step of etching and removing the surface of the base substrate 1001 on which the islands of the semiconductor thin film layer are formed to separate the islands of the semiconductor thin film layer from the base substrate, since the thickness of the region 1002b is smaller than the thickness of the region 1002a, the base material The periphery of the region 1002b in the substrate 1001 is also removed by etching. Since the alignment accuracy of the mask opening is not ±0 when the resist mask opening is formed before etching, misalignment occurs between the mask opening and the outer peripheral line of the island. Therefore, in order to secure a margin, it is necessary to position the outer circumference of the resist mask opening outside the outer circumference of the island. As a result, as shown in FIG. 19B , a groove 1003 is formed in a region around the region 1002b.

若形成槽1003,則於槽1003的區域中露出的、區域1002b的正下方的母材基板1001的表面區域的側面的面積大於區域1002a正下方的母材基板1001的表面區域的側面的面積。其結果,接觸蝕刻液的側面的面積大的母材基板1001的一部分區域(區域1002b的正下方區域)的藉由蝕刻的去除更快速地進行,藉此於區域1002b的正下方的母材基板1001中產生階差。若於半導體薄膜層的島的正下方具有階差,則當將半導體薄膜層的島壓向下方(母材基板方向)時,可產生因該階差而半導體薄膜層的島呈銳角彎折而發生龜裂的課題。因此,為解決此種課題,於藉由將半導體薄膜層自母材基板分離而製造半導體元件的方法中,較佳為於形成半導體薄膜層的步驟中形成未露出至半導體薄膜層的外周的階差結構。When the groove 1003 is formed, the area of the side surface of the surface region of the base substrate 1001 immediately below the region 1002b exposed in the region of the groove 1003 is larger than the area of the side surface of the surface region of the base substrate 1001 directly below the region 1002a. As a result, a part of the area of the base substrate 1001 (the area immediately below the region 1002 b ) whose side surface is in contact with the etchant is removed more rapidly by etching, and the base substrate directly below the region 1002 b is thus removed by etching. Step difference is generated in 1001. If there is a step directly below the island of the semiconductor thin film layer, when the island of the semiconductor thin film layer is pressed downward (in the direction of the base substrate), the island of the semiconductor thin film layer may be bent at an acute angle due to the step difference. Issues where cracks occur. Therefore, in order to solve such a problem, in the method of manufacturing a semiconductor element by separating the semiconductor thin film layer from the base substrate, it is preferable to form a step not exposed to the outer periphery of the semiconductor thin film layer in the step of forming the semiconductor thin film layer. poor structure.

圖20A~圖20C是表示包括形成有未露出至半導體薄膜層的島的外周的階差結構的半導體薄膜層的島920的半導體元件的圖。圖20A是半導體元件的頂視圖,圖20B是A-A線剖面圖,圖20C是B-B線剖面圖。於圖20A~圖20C中,於移動目的地基板931上接合有半導體薄膜層的島920,所述半導體薄膜層的島920中形成有於表面露出有p型半導體層的區域921、於表面露出有n型半導體層的凹狀的區域922、及於表面露出有p型半導體層的外周壁923。20A to 20C are diagrams showing a semiconductor element including an island 920 of a semiconductor thin film layer having a step structure not exposed to the outer periphery of the island of the semiconductor thin film layer. 20A is a top view of a semiconductor element, FIG. 20B is a sectional view along line A-A, and FIG. 20C is a sectional view along line B-B. In FIGS. 20A to 20C, an island 920 of a semiconductor thin film layer is bonded to a moving destination substrate 931, and a region 921 of a p-type semiconductor layer exposed on the surface is formed in the island 920 of the semiconductor thin film layer. A concave region 922 having an n-type semiconductor layer and an outer peripheral wall 923 having a p-type semiconductor layer exposed on the surface.

圖21A~圖21I是用以說明製造如圖20A~圖20C所示的半導體元件的方法的圖。此處,以發光二極體(Light Emitting Diode,LED)結構為例進行說明,但本製造方法並不限定於製造具有LED結構的半導體元件的方法,可適用於製造包括各種元件結構的半導體元件的方法。21A to 21I are diagrams for explaining a method of manufacturing the semiconductor element shown in FIGS. 20A to 20C . Here, the light emitting diode (Light Emitting Diode, LED) structure is taken as an example for illustration, but this manufacturing method is not limited to the method of manufacturing semiconductor elements with an LED structure, and is applicable to the manufacture of semiconductor elements including various element structures Methods.

圖21A中的母材基板901是用以使LED半導體層(例如GaN等的III族氮化物半導體層的積層結構)進行磊晶成長的母材基板,且例如為Si基板。圖21A中的虛線的區域是預定形成半導體薄膜層的多個島920的區域。The base substrate 901 in FIG. 21A is a base substrate for epitaxially growing an LED semiconductor layer (for example, a stacked structure of Group III nitride semiconductor layers such as GaN), and is, for example, a Si substrate. The dotted line area in FIG. 21A is the area where the plurality of islands 920 of the semiconductor thin film layer are scheduled to be formed.

圖21B是圖21A的A-A線剖面圖。如圖21B所示,半導體薄膜層的島920具有於表面露出有p型半導體層的區域921、將p型半導體層蝕刻去除而於表面露出有n型半導體層的區域922、及於表面露出有p型半導體層的外周壁923。Fig. 21B is a sectional view taken along line A-A of Fig. 21A. As shown in Figure 21B, the island 920 of the semiconductor thin film layer has a region 921 where the p-type semiconductor layer is exposed on the surface, a region 922 where the p-type semiconductor layer is etched away to expose the n-type semiconductor layer on the surface, and a region 922 where the n-type semiconductor layer is exposed on the surface. The outer peripheral wall 923 of the p-type semiconductor layer.

如圖21C所示,於母材基板901上分割成各別的半導體薄膜層的島920。繼而,以將露出有p型半導體層的區域921、露出有n型半導體層的區域922及外周壁923的表面的至少一部分區域與母材基板901結合的方式形成固定層928。圖21D是經分割形成的島920的周邊的剖面圖,且示出了形成有將島920與母材基板901結合的固定層928的狀態。於圖21C中圖示了6個半導體薄膜層的島920,但半導體薄膜層的島920的個數、間距、形狀、尺寸等可適當設計。於露出有n型半導體層的區域922中,以階差未露出至半導體薄膜層的島920的外周的方式設置有外周壁923,因此於半導體薄膜層的島920的周圍的母材基板901的區域中,未形成反映出半導體薄膜層的島920所包括的元件結構的階差。As shown in FIG. 21C , the base substrate 901 is divided into islands 920 of individual semiconductor thin film layers. Next, pinning layer 928 is formed so as to bond at least part of the surface of p-type semiconductor layer exposed region 921 , n-type semiconductor layer exposed region 922 , and outer peripheral wall 923 to base substrate 901 . FIG. 21D is a cross-sectional view of the periphery of the island 920 formed by division, and shows a state where the fixing layer 928 bonding the island 920 and the base substrate 901 is formed. 21C shows six islands 920 of the semiconductor thin film layer, but the number, pitch, shape, size, etc. of the islands 920 of the semiconductor thin film layer can be appropriately designed. In the region 922 where the n-type semiconductor layer is exposed, the peripheral wall 923 is provided in such a manner that the step is not exposed to the outer periphery of the island 920 of the semiconductor thin film layer. In the region, no step reflecting the element structure included in the island 920 of the semiconductor thin film layer is formed.

於對形成半導體薄膜層的島920的預定區域以外的半導體薄膜層進行蝕刻而形成半導體薄膜層的島920的步驟中,可應用標準的光微影及蝕刻步驟。雖未圖示,但於該步驟後,亦可於露出有p型半導體層的區域921的表面的一部分區域及露出有n型半導體層的區域922的表面的一部分區域中形成電極接點。於電極接點的形成中,例如形成可形成歐姆接點(Ohmic contact)的金屬薄膜層,且為了形成低電阻的電極接點,可適當地執行電極接點燒結(sinter)步驟。In the step of forming the island 920 of the semiconductor film layer by etching the semiconductor film layer other than the predetermined region for forming the island 920 of the semiconductor film layer, standard photolithography and etching steps can be applied. Although not shown, after this step, electrode contacts may be formed in part of the surface of the region 921 where the p-type semiconductor layer is exposed and part of the surface of the region 922 where the n-type semiconductor layer is exposed. In the formation of the electrode contact, for example, a metal thin film layer capable of forming an ohmic contact is formed, and in order to form a low-resistance electrode contact, a sintering step of the electrode contact can be performed appropriately.

繼而,如圖21E所示,於母材基板901的表面中,藉由蝕刻而至少將半導體薄膜層的島920的正下方的母材基板901的表面區域去除。於將半導體薄膜層的島920的正下方的母材基板901的表面區域蝕刻去除的步驟中,理想的是使用母材基板901的表面區域的蝕刻速度較半導體薄膜層的蝕刻速度快的蝕刻液或蝕刻氣體。於該蝕刻步驟中,於半導體薄膜層的島920與母材基板901之間形成空隙(圖21E中的斜線區域)。Next, as shown in FIG. 21E , on the surface of the base substrate 901 , at least the surface region of the base substrate 901 directly below the island 920 of the semiconductor thin film layer is removed by etching. In the step of etching and removing the surface region of the base substrate 901 immediately below the island 920 of the semiconductor thin film layer, it is desirable to use an etchant whose etching rate of the surface region of the base substrate 901 is faster than that of the semiconductor thin film layer. or etching gas. In this etching step, a gap (hatched area in FIG. 21E ) is formed between the island 920 of the semiconductor thin film layer and the base substrate 901 .

繼而,如圖21F所示,將半導體薄膜層的島920自第1基板分離。雖省略圖示,但於該步驟中可使用對半導體薄膜層的島進行暫時接著或吸附的結構體(例如所述拾取基板)。於圖21F所示的例子中,將島920分離後,固定層928的一部分殘留於母材基板901。Next, as shown in FIG. 21F , the island 920 of the semiconductor thin film layer is separated from the first substrate. Although not shown, in this step, a structure (for example, the pick-up substrate) that temporarily adheres or adsorbs the islands of the semiconductor thin film layer can be used. In the example shown in FIG. 21F , after the island 920 is separated, a part of the fixed layer 928 remains on the base substrate 901 .

繼而,如圖21G所示,將自母材基板901分離後的半導體薄膜層的島920接合於移動目的地基板931上。於將半導體薄膜層的島920接合於移動目的地基板931上的步驟中,不使用接著劑而將半導體薄膜層的島920壓接於移動目的地基板931上。於將半導體薄膜層的島920接合於移動目的地基板931上的步驟之前,亦可執行對半導體薄膜層的島920的接合面及移動目的地基板931的表面的表面處理步驟。雖未圖示,但亦可於半導體薄膜層的島920與移動目的地基板931之間(至少半導體薄膜層的正下方區域)設置其他材料層。再者,於將半導體薄膜層的島920接合於移動目的地基板931上的步驟中,理想的是不使用接著劑的接合,但亦可使用包含接著劑的膏或片材來進行接合。Next, as shown in FIG. 21G , the island 920 of the semiconductor thin film layer separated from the base substrate 901 is bonded to the transfer destination substrate 931 . In the step of bonding the island 920 of the semiconductor thin film layer to the destination substrate 931, the island 920 of the semiconductor thin film layer is pressure-bonded to the destination substrate 931 without using an adhesive. Before the step of bonding the island 920 of the semiconductor thin film layer to the destination substrate 931, a surface treatment step may be performed on the bonding surface of the island 920 of the semiconductor thin film layer and the surface of the destination substrate 931. Although not shown, other material layers may be provided between the island 920 of the semiconductor thin film layer and the moving destination substrate 931 (at least the area directly under the semiconductor thin film layer). In addition, in the step of bonding the island 920 of the semiconductor thin film layer to the transfer destination substrate 931, it is desirable not to use an adhesive for bonding, but a paste or a sheet containing an adhesive may be used for bonding.

繼而,如圖21H所示,於將半導體薄膜層的島920接合於移動目的地基板931之後,形成層間絕緣膜及配線等半導體元件所必需的結構。例如於不需要用以降低電極與半導體薄膜層的島920的表面的接觸電阻的燒結的情況下、或燒結溫度低的情況下,於將半導體薄膜層的島920接合於移動目的地基板931之後在固定層928中形成開口,於開口內的露出有p型半導體層的區域921中形成電極924,於露出有n型半導體層的區域922中形成電極925,並形成與電極924及電極925連接的配線層927。進而,亦可形成包含所述固定層928的一部分的層間絕緣膜926。例如,亦可於固定層928的一部分上設置層間絕緣膜926。Next, as shown in FIG. 21H , after the island 920 of the semiconductor thin film layer is bonded to the transfer destination substrate 931 , structures necessary for semiconductor elements such as an interlayer insulating film and wiring are formed. For example, when sintering for reducing the contact resistance between the electrode and the surface of the island 920 of the semiconductor thin film layer is not required, or when the sintering temperature is low, after the island 920 of the semiconductor thin film layer is bonded to the destination substrate 931 Form an opening in the fixed layer 928, form an electrode 924 in the region 921 where the p-type semiconductor layer is exposed in the opening, form an electrode 925 in the region 922 where the n-type semiconductor layer is exposed, and form a connection with the electrode 924 and the electrode 925 The wiring layer 927. Furthermore, an interlayer insulating film 926 including a part of the fixed layer 928 may also be formed. For example, an interlayer insulating film 926 may be provided on a part of the fixed layer 928 .

於將多個島920接合於移動目的地基板931的情況下,亦可藉由配線層927而將多個島920上分別所形成的電極924及電極925加以連接。多個島920可為將既定尺寸的一個半導體元件分割成多個小尺寸的要素半導體元件(多個小尺寸的島)而成者。多個小尺寸要素半導體元件可全部包括相同的結構,亦可全部為相同尺寸。藉由所述方式,如下所述般抑制溫度上昇故而較佳。When bonding the plurality of islands 920 to the destination substrate 931 , the electrodes 924 and electrodes 925 respectively formed on the plurality of islands 920 may be connected via the wiring layer 927 . The plurality of islands 920 may be obtained by dividing one semiconductor element of a predetermined size into a plurality of small-sized elemental semiconductor elements (a plurality of small-sized islands). A plurality of small-scale element semiconductor elements may all have the same structure, and may all have the same size. By such means, it is preferable to suppress a temperature rise as described below.

於大尺寸的一個半導體元件中,動作時的發熱大,尤其於中心區域中產生的熱的逸散差,因此中心區域中的元件的溫度上昇大。相對於此,於將一個半導體元件分割成多個小尺寸要素半導體元件的情況下,分割出的要素半導體元件為小尺寸,且各要素半導體元件藉由熱傳導性高的金屬材料的配線層927而經連接,藉此,各要素半導體元件中所產生的熱經由移動目的地基板931及配線層927而效率良好地逸散。其結果,各小尺寸要素半導體元件的溫度上昇得到抑制。In a large-sized semiconductor element, the heat generated during operation is large, and the heat dissipation difference generated in the central region is particularly large, so the temperature rise of the element in the central region is large. In contrast, when one semiconductor element is divided into a plurality of small-sized elemental semiconductor elements, the divided elemental semiconductor elements are small in size, and each elemental semiconductor element is connected by a wiring layer 927 of a metal material having high thermal conductivity. By being connected, the heat generated in each component semiconductor element is efficiently dissipated through the transfer destination substrate 931 and the wiring layer 927 . As a result, the temperature rise of each small-sized element semiconductor element is suppressed.

另外,因將作為半導體薄膜層的多個要素半導體元件接合於移動目的地基板931上,可藉由金屬薄膜配線層而將各小尺寸要素半導體元件加以連接,因此可實現高密度積體。其結果,即便將一個半導體元件分割成多個要素半導體元件,亦可獲得緊湊的半導體元件。此種形態尤其對於流動大電流的半導體元件、例如使用Si、SiC、GaN、Ga2 O3 、金剛石等半導體材料的功率半導體元件而言為較佳的形態。In addition, since a plurality of elemental semiconductor elements as semiconductor thin film layers are bonded to the moving destination substrate 931, each small-sized elemental semiconductor element can be connected through the metal thin film wiring layer, so high-density integration can be realized. As a result, even if one semiconductor element is divided into a plurality of component semiconductor elements, a compact semiconductor element can be obtained. Such a form is particularly preferable for a semiconductor element through which a large current flows, for example, a power semiconductor element using a semiconductor material such as Si, SiC, GaN, Ga 2 O 3 , or diamond.

再者,於參照圖21A~圖21H進行了說明的製造半導體元件的方法中,於圖21D中例示了形成固定層928的情況,但亦可不形成固定層928而執行圖21E及以後的步驟。該情況下,例如亦可如圖21I所示,於將拾取基板930固定於島920的表面(例如露出有p型半導體層的區域921及外周壁923的表面)的狀態下,形成由斜線表示的空隙,並於形成空隙後將拾取基板930提起,藉此將島920自母材基板901分離。於圖21I的狀態中,亦可藉由拾取基板930以外的外部裝置來固定島920。Furthermore, in the method of manufacturing a semiconductor device described with reference to FIGS. 21A to 21H , FIG. 21D exemplifies the case of forming the pinning layer 928 . However, the steps of FIG. 21E and subsequent steps may be performed without forming the pinning layer 928 . In this case, for example, as shown in FIG. 21I , in the state where the pick-up substrate 930 is fixed on the surface of the island 920 (for example, the surface of the region 921 where the p-type semiconductor layer is exposed and the surface of the outer peripheral wall 923 ), an oblique line can be formed. The gap is formed, and the pick-up substrate 930 is lifted after the gap is formed, thereby separating the island 920 from the parent substrate 901 . In the state of FIG. 21I , the island 920 may also be fixed by picking up an external device other than the substrate 930 .

如此,於未形成固定層928的情況下,將半導體薄膜層的島920接合於移動目的地基板931之後,於露出有p型半導體層的區域921中形成電極924,於露出有n型半導體層的區域922中形成電極925。另外,形成對露出有p型半導體層的區域921及露出有n型半導體層的區域922的至少一部分區域進行覆蓋,並且具有使電極924及電極925的一部分露出的開口部的層間絕緣膜926,並形成與電極924及電極925連接的配線層927。In this way, when the fixed layer 928 is not formed, after the island 920 of the semiconductor thin film layer is bonded to the moving destination substrate 931, the electrode 924 is formed in the region 921 where the p-type semiconductor layer is exposed, and the electrode 924 is formed in the region 921 where the n-type semiconductor layer is exposed. Electrode 925 is formed in region 922 of . In addition, an interlayer insulating film 926 is formed to cover at least a part of the region 921 where the p-type semiconductor layer is exposed and the region 922 where the n-type semiconductor layer is exposed, and has an opening for exposing a part of the electrode 924 and the electrode 925, And the wiring layer 927 connected to the electrode 924 and the electrode 925 is formed.

以上,使用實施形態對本發明進行了說明,但本發明的技術範圍並不限定於所述實施形態所記載的範圍,於其主旨的範圍內可進行各種變形及變更。另外,藉由多個實施形態的任意組合而產生的新的實施形態亦包含於本發明的實施形態中。藉由組合而產生的新的實施形態的效果兼具原本的實施形態的效果。As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range described in the said embodiment, Various deformation|transformation and a change are possible within the range of the summary. In addition, new embodiments produced by arbitrary combinations of a plurality of embodiments are also included in the embodiments of the present invention. The effect of the new embodiment produced by combination also has the effect of the original embodiment.

101、401、501、701、801、901、1001、3001‧‧‧母材基板 102‧‧‧預定去除層 103、117、403a、403b、403c、503a~503c、703a、703b、703c、703d、803‧‧‧空隙 104‧‧‧半導體薄膜層 106‧‧‧預定去除區域 108、109、408a、408b、408c、508a、508b、508c、708、708a、708b、708c、708d、718a、718b、808、920‧‧‧半導體薄膜層的島/島 110、112、114、410a、410b、410c、414a、414b、414c、416a、416b、416c、510a、510b、510c、514a、514c、516a、516c、705a、705b、705c、705d、714a、714b、814、928‧‧‧固定層 130、131、921、922、1002a、1002b‧‧‧區域 200、200'、420、520、710、930‧‧‧拾取基板 201、421、521、711‧‧‧基底基板 202、422a、422b、422c、522、522a、522c‧‧‧拾取凸塊 204、712‧‧‧拾取層 210、430、530‧‧‧結構 301、451、531、731、831、931‧‧‧移動目的地基板 302、551‧‧‧表面 308、558a、558c‧‧‧面 742、744‧‧‧元件等搭載區域 800‧‧‧半導體元件 816a、816b‧‧‧開口部 822、824、924、925‧‧‧電極 842、926‧‧‧層間絕緣膜 854、856、927‧‧‧配線層 923‧‧‧外周壁 1003‧‧‧槽 3002‧‧‧犧牲層 3003‧‧‧半導體磊晶層 3004‧‧‧支持體 3010‧‧‧犧牲層受到蝕刻的區域 a、b‧‧‧側面 L1、L2、L3、L4‧‧‧長度 L2a、L2b‧‧‧寬度 θ‧‧‧角度101, 401, 501, 701, 801, 901, 1001, 3001‧‧‧base metal substrate 102‧‧‧planned removal layer 103, 117, 403a, 403b, 403c, 503a~503c, 703a, 703b, 703c, 703d, 803‧‧‧space 104‧‧‧Semiconductor thin film layer 106‧‧‧Scheduled removal area 108, 109, 408a, 408b, 408c, 508a, 508b, 508c, 708, 708a, 708b, 708c, 708d, 718a, 718b, 808, 920‧‧‧island/island of semiconductor film layer 110, 112, 114, 410a, 410b, 410c, 414a, 414b, 414c, 416a, 416b, 416c, 510a, 510b, 510c, 514a, 514c, 516a, 516c, 705a, 705b, 705c, 705d, 714a, 714b, 814, 928‧‧‧fixed layer 130, 131, 921, 922, 1002a, 1002b‧‧‧area 200, 200', 420, 520, 710, 930‧‧‧Pick up substrate 201, 421, 521, 711‧‧‧base substrate 202, 422a, 422b, 422c, 522, 522a, 522c‧‧‧Pick up bumps 204, 712‧‧‧pickup layer 210, 430, 530‧‧‧structure 301, 451, 531, 731, 831, 931‧‧‧moving destination board 302, 551‧‧‧surface 308, 558a, 558c‧‧‧face 742, 744‧‧‧Component loading area 800‧‧‧semiconductor components 816a, 816b‧‧‧opening 822, 824, 924, 925‧‧‧electrodes 842, 926‧‧‧Interlayer insulating film 854, 856, 927‧‧‧wiring layer 923‧‧‧peripheral wall 1003‧‧‧Slot 3002‧‧‧Sacrifice layer 3003‧‧‧Semiconductor epitaxial layer 3004‧‧‧Support 3010‧‧‧Sacrificial layer etched area a, b‧‧‧side L1, L2, L3, L4‧‧‧Length L2a, L2b‧‧‧width θ‧‧‧angle

圖1A是用以說明將半導體薄膜層的島自母材基板拆下的方法的圖。 圖1B是用以說明將半導體薄膜層的島自母材基板拆下的方法的圖。 圖1C是用以說明將半導體薄膜層的島自母材基板拆下的方法的圖。 圖1D是用以說明將半導體薄膜層的島自母材基板拆下的方法的圖。 圖1E是用以說明將半導體薄膜層的島自母材基板拆下的方法的圖。 圖2A是表示作為第3基板的拾取(pick up)基板的圖。 圖2B是圖2A的A-A剖面。 圖2C是表示拾取基板的變形例的圖。 圖3A是示意性地表示自母材基板將半導體薄膜層的島分離的步驟的圖。 圖3B是示意性地表示自母材基板將半導體薄膜層的島分離的步驟的圖。 圖3C是示意性地表示自母材基板將半導體薄膜層的島分離的步驟的圖。 圖3D是示意性地表示將分離後的半導體薄膜層的島接合於移動目的地基板為止的步驟的圖。 圖3E是示意性地表示將分離後的半導體薄膜層的島接合於移動目的地基板為止的步驟的圖。 圖3F是示意性地表示將分離後的半導體薄膜層的島接合於移動目的地基板為止的步驟的圖。 圖4A是示意性地表示使多個半導體薄膜層的島移動的步驟的圖。 圖4B是示意性地表示使多個半導體薄膜層的島移動的步驟的圖。 圖4C是示意性地表示使多個半導體薄膜層的島移動的步驟的圖。 圖4D是示意性地表示使多個半導體薄膜層的島移動的步驟的圖。 圖4E是示意性地表示使多個半導體薄膜層的島移動的步驟的圖。 圖5A是用以說明使多個半導體薄膜層的島移動的方法的圖。 圖5B是用以說明使多個半導體薄膜層的島移動的方法的圖。 圖5C是用以說明使多個半導體薄膜層的島移動的方法的圖。 圖5D是用以說明使多個半導體薄膜層的島移動的方法的圖。 圖5E是用以說明使多個半導體薄膜層的島移動的方法的圖。 圖6是表示本實施形態的半導體元件的製造方法的步驟流程的圖。 圖7A是半導體元件的製造方法的變形例的一例。 圖7B是半導體元件的製造方法的變形例的一例。 圖7C是半導體元件的製造方法的變形例的一例。 圖7D是半導體元件的A-A線剖面圖。 圖8A是表示半導體元件的結構的圖。 圖8B是表示半導體元件的結構的圖。 圖8C是表示半導體元件的結構的圖。 圖9A是表示固定層的形狀的變形例的圖。 圖9B是表示固定層的形狀的變形例的圖。 圖9C是表示固定層的形狀的變形例的圖。 圖9D是表示固定層的形狀的變形例的圖。 圖10是示意性地例示用作母材基板的半導體磊晶晶圓的圖。 圖11A是表示角度θ與垂直於半導體薄膜層的島的長邊的方向上的Si(111)基板表面區域的蝕刻速度的關係的圖。 圖11B是用以說明角度θ的圖。 圖12是表示六角形狀的半導體薄膜層的島的圖。 圖13A是作為母材基板的Si(111)基板上所形成的GaN半導體薄膜層的島的顯微鏡相片。 圖13B是相對於母材基板的結晶方向的半導體薄膜層的島的長邊的方向與圖13A不同的、GaN半導體薄膜層的島的顯微鏡相片。 圖14是將長邊與<1-100>方向大致平行的半導體薄膜層的島接合於移動目的地基板的狀態的顯微鏡相片。 圖15A是用以說明使固定層容易斷裂的方法的圖。 圖15B是用以說明使固定層容易斷裂的方法的圖。 圖16是表示實際的實驗中對固定層的分離狀態進行觀察而得的結果的顯微鏡相片。 圖17是將自母材基板分離後的半導體薄膜層的島接合於移動目的地基板的狀態的顯微鏡相片。 圖18A是表示具有在短邊方向上延伸的區域的固定層的例子的圖。 圖18B是表示具有在短邊方向上延伸的區域的固定層的例子的圖。 圖19A是示意性地表示將母材基板上所形成的半導體薄膜層分割成各別的半導體薄膜層的島的狀態的圖,且是母材基板及半導體薄膜層的島的頂視圖。 圖19B是母材基板及半導體薄膜層的島的剖面圖。 圖20A是半導體元件的頂視圖,所述半導體元件包括形成有未露出至半導體薄膜層的島的外周的階差結構的半導體薄膜層。 圖20B是圖20A所示的半導體元件的A-A線剖面圖。 圖20C是圖20A所示的半導體元件的B-B線剖面圖。 圖21A是用以說明製造半導體元件的方法的圖。 圖21B是用以說明製造半導體元件的方法的圖。 圖21C是用以說明製造半導體元件的方法的圖。 圖21D是用以說明製造半導體元件的方法的圖。 圖21E是用以說明製造半導體元件的方法的圖。 圖21F是用以說明製造半導體元件的方法的圖。 圖21G是用以說明製造半導體元件的方法的圖。 圖21H是用以說明製造半導體元件的方法的圖。 圖21I是用以說明製造半導體元件的方法的圖。 圖22是用以說明現有技術的圖。FIG. 1A is a diagram for explaining a method of detaching an island of a semiconductor thin film layer from a base substrate. FIG. 1B is a diagram for explaining a method of detaching an island of a semiconductor thin film layer from a base substrate. FIG. 1C is a diagram for explaining a method of detaching the islands of the semiconductor thin film layer from the base substrate. FIG. 1D is a diagram illustrating a method of detaching the islands of the semiconductor thin film layer from the base substrate. FIG. 1E is a diagram illustrating a method of detaching an island of a semiconductor thin film layer from a base substrate. FIG. 2A is a diagram showing a pick-up substrate as a third substrate. Fig. 2B is the section A-A of Fig. 2A. FIG. 2C is a diagram showing a modified example of picking up a substrate. 3A is a diagram schematically showing a step of separating islands of a semiconductor thin film layer from a base substrate. 3B is a diagram schematically showing a step of separating islands of the semiconductor thin film layer from the base substrate. 3C is a diagram schematically showing a step of separating islands of the semiconductor thin film layer from the base substrate. FIG. 3D is a diagram schematically showing steps up to bonding the islands of the separated semiconductor thin film layer to the transfer destination substrate. FIG. 3E is a diagram schematically showing steps up to bonding the islands of the separated semiconductor thin film layer to the transfer destination substrate. FIG. 3F is a diagram schematically showing steps up to bonding the islands of the separated semiconductor thin film layer to the transfer destination substrate. 4A is a diagram schematically showing a step of moving islands of a plurality of semiconductor thin film layers. 4B is a diagram schematically showing a step of moving islands of a plurality of semiconductor thin film layers. 4C is a diagram schematically showing a step of moving islands of a plurality of semiconductor thin film layers. FIG. 4D is a diagram schematically showing a step of moving islands of a plurality of semiconductor thin film layers. FIG. 4E is a diagram schematically showing a step of moving islands of a plurality of semiconductor thin film layers. FIG. 5A is a diagram for explaining a method of moving islands of a plurality of semiconductor thin film layers. FIG. 5B is a diagram for explaining a method of moving islands of a plurality of semiconductor thin film layers. FIG. 5C is a diagram for explaining a method of moving islands of a plurality of semiconductor thin film layers. FIG. 5D is a diagram for explaining a method of moving islands of a plurality of semiconductor thin film layers. FIG. 5E is a diagram illustrating a method of moving islands of a plurality of semiconductor thin film layers. FIG. 6 is a diagram showing a flow of steps in the method of manufacturing a semiconductor element according to the present embodiment. FIG. 7A is an example of a modified example of the method of manufacturing a semiconductor element. FIG. 7B is an example of a modified example of the method of manufacturing a semiconductor element. FIG. 7C is an example of a modified example of the method of manufacturing a semiconductor element. Fig. 7D is an A-A sectional view of the semiconductor element. FIG. 8A is a diagram showing the structure of a semiconductor element. FIG. 8B is a diagram showing the structure of a semiconductor element. FIG. 8C is a diagram showing the structure of a semiconductor element. FIG. 9A is a diagram showing a modified example of the shape of the pinned layer. FIG. 9B is a diagram showing a modified example of the shape of the pinned layer. FIG. 9C is a diagram showing a modified example of the shape of the pinned layer. FIG. 9D is a diagram showing a modified example of the shape of the pinned layer. FIG. 10 is a diagram schematically illustrating a semiconductor epitaxial wafer used as a base substrate. 11A is a graph showing the relationship between the angle θ and the etching rate of the Si (111) substrate surface region in the direction perpendicular to the long sides of the islands of the semiconductor thin film layer. FIG. 11B is a diagram for explaining the angle θ. FIG. 12 is a diagram showing islands of hexagonal semiconductor thin film layers. 13A is a microscope photograph of islands of a GaN semiconductor thin film layer formed on a Si (111) substrate as a base substrate. 13B is a microscope photograph of the islands of the GaN semiconductor thin film layer in which the direction of the long sides of the islands of the semiconductor thin film layer with respect to the crystallographic direction of the base substrate is different from that of FIG. 13A . 14 is a microscope photograph of a state in which islands of semiconductor thin film layers whose long sides are substantially parallel to the <1-100> direction are bonded to a moving destination substrate. FIG. 15A is a diagram for explaining a method of making the fixing layer easy to break. FIG. 15B is a diagram for explaining a method of making the fixing layer easy to break. FIG. 16 is a microscope photograph showing the results of observing the separation state of the pinned layer in an actual experiment. FIG. 17 is a microscope photograph of a state in which islands of semiconductor thin film layers separated from a base substrate are bonded to a transfer destination substrate. FIG. 18A is a diagram showing an example of a fixed layer having a region extending in the short-side direction. FIG. 18B is a diagram showing an example of a fixed layer having a region extending in the short-side direction. 19A is a diagram schematically showing a state in which a semiconductor thin film layer formed on a base substrate is divided into individual semiconductor thin film layer islands, and is a top view of the base substrate and the islands of the semiconductor thin film layer. Fig. 19B is a cross-sectional view of the base substrate and the island of the semiconductor thin film layer. 20A is a top view of a semiconductor element including a semiconductor thin film layer formed with a stepped structure not exposed to the outer peripheries of islands of the semiconductor thin film layer. 20B is an A-A sectional view of the semiconductor element shown in FIG. 20A. Fig. 20C is a B-B sectional view of the semiconductor element shown in Fig. 20A. FIG. 21A is a diagram for explaining a method of manufacturing a semiconductor element. FIG. 21B is a diagram for explaining a method of manufacturing a semiconductor element. FIG. 21C is a diagram for explaining a method of manufacturing a semiconductor element. FIG. 21D is a diagram for explaining a method of manufacturing a semiconductor element. FIG. 21E is a diagram for explaining a method of manufacturing a semiconductor element. FIG. 21F is a diagram for explaining a method of manufacturing a semiconductor element. FIG. 21G is a diagram for explaining a method of manufacturing a semiconductor element. FIG. 21H is a diagram for explaining a method of manufacturing a semiconductor element. FIG. 21I is a diagram for explaining a method of manufacturing a semiconductor element. Fig. 22 is a diagram for explaining the prior art.

101:母材基板 101: base material substrate

103:空隙 103: Gap

108:半導體薄膜層的島/島 108: Islands/islands of semiconductor thin film layers

110:固定層 110: fixed layer

200:拾取基板 200: Pick up the substrate

201:基底基板 201: base substrate

202:拾取凸塊 202: Pick up the bump

Claims (9)

一種半導體元件的製造方法,其將形成於第1基板的上方的III族氮化物的半導體薄膜層的島自所述第1基板分離並接合於與所述第1基板不同的第2基板上,所述半導體元件的製造方法的特徵在於包括:在所述第1基板上形成所述半導體薄膜層的島的步驟,所述半導體薄膜層的島是以III族氮化物的所述半導體薄膜層的島的長邊的方向相對於作為所述第1基板的Si(111)基板的<112>方向而為±45°以下的角度範圍的方式形成;形成作為薄膜的固定層的步驟,所述固定層將所述半導體薄膜層的島的與所述第1基板一側為相反側的主面的至少一部分與所述第1基板中的所述半導體薄膜層的島一側的面的至少一部分結合;形成所述固定層的步驟之後,藉由將所述半導體薄膜層的島或所述第1基板的一部分區域、或者所述半導體薄膜層的島與所述第1基板之間的層的一部分區域去除而形成空隙的步驟;將與所述第1基板以及所述第2基板不同的第3基板與所述固定層及所述半導體薄膜層的島的至少一部分的結合區域結合的步驟;於所述第3基板結合於所述結合區域的狀態下將所述第3基板沿與所述第1基板相離的方向移動,藉此將所述半導體薄膜層的島自所述第1基板分離的步驟;以及 將自所述第1基板分離後的所述半導體薄膜層接合於所述第2基板的步驟,於形成所述固定層的步驟之中,形成具有下述厚度的所述固定層:藉由移動所述第3基板的力,將形成於所述第1基板上的所述固定層與形成於所述半導體薄膜層的側面的所述固定層之間產生龜裂的厚度。 A method of manufacturing a semiconductor element, comprising separating an island of a semiconductor thin film layer of group III nitride formed above a first substrate from the first substrate and bonding it to a second substrate different from the first substrate, The manufacturing method of the semiconductor element is characterized in that it includes: a step of forming an island of the semiconductor thin film layer on the first substrate, and the island of the semiconductor thin film layer is formed of the semiconductor thin film layer of group III nitride. The direction of the long side of the island is formed in an angle range of ±45° or less with respect to the <112> direction of the Si (111) substrate as the first substrate; the step of forming a fixed layer as a thin film, the fixed bonding at least a part of the main surface of the island of the semiconductor thin film layer on the side opposite to the side of the first substrate to at least a part of the surface of the island side of the semiconductor thin film layer in the first substrate ; after the step of forming the fixed layer, by placing the island of the semiconductor thin film layer or a part of the first substrate, or a part of the layer between the island of the semiconductor thin film layer and the first substrate a step of removing a region to form a void; a step of combining a third substrate different from the first substrate and the second substrate with a bonding region of at least a part of the fixed layer and the island of the semiconductor thin film layer; moving the third substrate in a direction away from the first substrate in a state where the third substrate is bonded to the bonding region, thereby separating the islands of the semiconductor thin film layer from the first substrate steps; and In the step of bonding the semiconductor thin film layer separated from the first substrate to the second substrate, in the step of forming the fixed layer, the fixed layer is formed to have a thickness as follows: by moving The force of the third substrate is such that a crack occurs between the pinned layer formed on the first substrate and the pinned layer formed on the side surface of the semiconductor thin film layer. 一種半導體元件的製造方法,其將形成於第1基板的上方的六方晶的半導體薄膜層的島自所述第1基板分離並接合於與所述第1基板不同的第2基板上,所述半導體元件的製造方法的特徵在於包括:在所述第1基板上形成所述半導體薄膜層的島的步驟,所述半導體薄膜層的島是以六方晶的所述半導體薄膜層的島的長邊的方向相對於作為所述第1基板的六方晶基板的<1-100>方向而為±45°以下的角度範圍的方式形成;形成作為薄膜的固定層的步驟,所述固定層將所述半導體薄膜層的島的與所述第1基板一側為相反側的主面的至少一部分與所述第1基板中的所述半導體薄膜層的島一側的面的至少一部分結合;形成所述固定層的步驟之後,藉由將所述半導體薄膜層的島或所述第1基板的一部分區域、或者所述半導體薄膜層的島與所述第1基板之間的層的一部分區域去除而形成空隙的步驟;將與所述第1基板以及所述第2基板不同的第3基板與所述 固定層及所述半導體薄膜層的島的至少一部分的結合區域結合的步驟;於所述第3基板結合於所述結合區域的狀態下將所述第3基板沿與所述第1基板相離的方向移動,藉此將所述半導體薄膜層的島自所述第1基板分離的步驟;以及將自所述第1基板分離後的所述半導體薄膜層接合於所述第2基板的步驟,於形成所述固定層的步驟之中,形成具有下述厚度的所述固定層:藉由移動所述第3基板的力,將形成於所述第1基板上的所述固定層與形成於所述半導體薄膜層的側面的所述固定層之間產生龜裂的厚度。 A method of manufacturing a semiconductor element, comprising separating islands of a hexagonal semiconductor thin film layer formed above a first substrate from the first substrate and bonding them to a second substrate different from the first substrate, the The method for manufacturing a semiconductor element is characterized in that it includes: a step of forming an island of the semiconductor thin film layer on the first substrate, and the island of the semiconductor thin film layer is a long side of the island of the semiconductor thin film layer in a hexagonal crystal. The direction of the hexagonal crystal substrate as the first substrate is formed in an angle range of ±45° or less with respect to the <1-100> direction of the hexagonal crystal substrate; the step of forming a fixed layer as a thin film, the fixed layer At least a part of the main surface of the island of the semiconductor thin film layer on the side opposite to the side of the first substrate is combined with at least a part of the surface of the island side of the semiconductor thin film layer in the first substrate; forming the After the step of fixing the layer, it is formed by removing the island of the semiconductor thin film layer or a part of the first substrate, or a part of the layer between the island of the semiconductor thin film layer and the first substrate The step of void; the 3rd substrate different from described 1st substrate and described 2nd substrate and described A step of bonding the fixed layer and at least a part of the bonding region of the island of the semiconductor thin film layer; separating the edge of the third substrate from the first substrate in a state where the third substrate is bonded to the bonding region a step of moving in a direction in which the semiconductor thin film layer is separated from the first substrate; and a step of bonding the semiconductor thin film layer separated from the first substrate to the second substrate, In the step of forming the fixed layer, the fixed layer is formed to have a thickness such that the fixed layer formed on the first substrate and the fixed layer formed on the third substrate are separated by force of moving the third substrate. A thickness at which cracks are formed between the fixed layers on the side surfaces of the semiconductor thin film layer. 如申請專利範圍第1項或第2項所述的半導體元件的製造方法,其中於形成所述固定層的步驟中形成如下厚度的所述固定層,即,藉由沿與所述第1基板相離的方向移動所述第3基板的力而將所述固定層切斷的厚度。 The method for manufacturing a semiconductor device according to claim 1 or 2, wherein in the step of forming the fixed layer, the fixed layer is formed to a thickness such that the fixed layer is formed along the first substrate. The force of moving the third substrate in the direction away from the fixed layer cuts the thickness. 如申請專利範圍第1項或第2項所述的半導體元件的製造方法,其中於形成所述固定層的步驟中形成如下厚度的所述固定層,即,藉由在所述結合的步驟中施加的由所述第3基板朝向所述固定層的力而使所述固定層產生龜裂的厚度。 The method for manufacturing a semiconductor device as described in claim 1 or claim 2, wherein in the step of forming the fixed layer, the fixed layer is formed to a thickness such that, in the step of combining The force applied from the third substrate toward the fixed layer has a thickness such that cracks are generated in the fixed layer. 如申請專利範圍第1項或第2項所述的半導體元件的製 造方法,其中於形成所述固定層的步驟中,以較所述半導體薄膜層的島的厚度薄的方式形成所述固定層。 Manufacturing of semiconductor components as described in item 1 or item 2 of the scope of the patent application In the manufacturing method, in the step of forming the fixed layer, the fixed layer is formed to be thinner than the thickness of the islands of the semiconductor thin film layer. 如申請專利範圍第1項或第2項所述的半導體元件的製造方法,其中於將所述半導體薄膜層的島接合於所述第2基板的步驟後更包括:藉由將具備於所述第3基板,且與所述第2基板結合的有機材料層去除所述半導體薄膜層的島自所述第3基板分離的步驟。 The method for manufacturing a semiconductor element as described in claim 1 or 2 of the scope of the patent application, wherein after the step of bonding the island of the semiconductor thin film layer to the second substrate, it further includes: a third substrate, and the step of separating the organic material layer combined with the second substrate by removing the island of the semiconductor thin film layer from the third substrate. 一種半導體基板,包括:由Si(111)形成的第1基板;III族氮化物的半導體薄膜層的島,以其長邊的方向相對於作為所述第1基板的Si(111)基板的<112>方向而為±45°以下的角度範圍的方式形成在所述第1基板上;以及作為薄膜的固定層,所述固定層將所述半導體薄膜層的島的與所述第1基板一側為相反側的主面的至少一部分與所述第1基板中的所述半導體薄膜層的島一側的面的至少一部分結合,所述半導體薄膜層的島與所述第1基板之間存在空隙,且所述固定層的至少一部分中露出所述空隙,所述固定層具有下述厚度:藉由施加在與所述第1基板不同的第3基板與所述固定層及所述半導體薄膜層的島的至少一部分的結合區域結合的狀態下移動第3基板的力,而產生龜裂的厚度。 A kind of semiconductor substrate, comprises: the 1st substrate that is formed by Si (111); The island of the semiconductor thin film layer of group III nitride, with the direction of its long side relative to the Si (111) substrate as described 1st substrate < The 112> direction is formed on the first substrate in an angle range of ±45° or less; At least a part of the main surface on the opposite side is combined with at least a part of the surface of the island side of the semiconductor thin film layer in the first substrate, and there is a gap between the island of the semiconductor thin film layer and the first substrate. gap, and the gap is exposed in at least a part of the fixed layer, the fixed layer has the following thickness: by applying a third substrate different from the first substrate and the fixed layer and the semiconductor thin film The force of moving the third substrate in the state where at least a part of the bonded region of the islands of the layer is bonded causes cracks in the thickness. 一種半導體基板,包括: 由六方晶形成的第1基板;六方晶的半導體薄膜層的島,以其長邊的方向相對於作為所述第1基板的六方晶基板的<1-100>方向而為±45°以下的角度範圍的方式形成在所述第1基板上;以及作為薄膜的固定層,所述固定層將所述半導體薄膜層的島的與所述第1基板一側為相反側的主面的至少一部分與所述第1基板中的所述半導體薄膜層的島一側的面的至少一部分結合,所述半導體薄膜層的島與所述第1基板之間存在空隙,且所述固定層的至少一部分中露出所述空隙,所述固定層具有下述厚度:藉由施加在與所述第1基板不同的第3基板與所述固定層及所述半導體薄膜層的島的至少一部分的結合區域結合的狀態下移動第3基板的力,而產生龜裂的厚度。 A semiconductor substrate, comprising: The first substrate formed of hexagonal crystal; the island of the hexagonal semiconductor thin film layer, the direction of its long side is ±45° or less with respect to the <1-100> direction of the hexagonal crystal substrate as the first substrate Formed on the first substrate in an angular range; and as a fixed layer of the thin film, the fixed layer holds at least a part of the main surface of the island of the semiconductor thin film layer on the opposite side to the side of the first substrate combined with at least a part of the surface of the island side of the semiconductor thin film layer in the first substrate, there is a gap between the island of the semiconductor thin film layer and the first substrate, and at least a part of the fixed layer The gap is exposed, and the fixed layer has a thickness that is combined with the bonding region of at least a part of the island of the fixed layer and the semiconductor thin film layer by applying a third substrate different from the first substrate. The force of moving the third substrate in the state, and the thickness of the crack. 如申請專利範圍第7項或第8項所述的半導體基板,其中所述固定層的厚度較所述半導體薄膜層的島的厚度薄。 The semiconductor substrate according to claim 7 or claim 8, wherein the thickness of the fixed layer is thinner than the thickness of the islands of the semiconductor thin film layer.
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