JP2009212357A - Nitride-based semiconductor light-emitting element and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride-based semiconductor light-emitting element having a positive electrode at one side of a nitride-based semiconductor laminated structure and a negative electrode at the other side and a method for manufacturing the nitride-based semiconductor light-emitting element. <P>SOLUTION: The nitride-based semiconductor light-emitting element includes: a holding substrate (10) including a metallic layer region (2) and a resin layer region (3); a nitride-based semiconductor laminated structure (30) including p-type nitride-based semiconductor layers (31, 32) successively laminated on the holding substrate, an active layer (33) and an n-type nitride-based semiconductor layer (34); and a p-type ohmic electrode (20) brought into ohmic-contact with the p-type nitride-based semiconductor layer between the holding substrate and the p-type nitride-based semiconductor layer. A metallic layer region included in the holding substrate is electrically conducted through the p-type ohmic electrode to the p-type nitride-based semiconductor layer, and the peripheral edge of the nitride-based semiconductor laminated structure (30) is retreated from the peripheral edge to the inside of the holding substrate (10). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nitride-based semiconductor light-emitting device and a method for manufacturing the same, and in particular, a nitride-based semiconductor light-emitting device having a positive electrode on one side and a negative electrode on the other side of a nitride-based semiconductor multilayer structure, and a method for manufacturing the same. Related to improvements.

  The schematic cross-sectional view of FIG. 20 shows an example of a nitride-based semiconductor light-emitting device disclosed in Japanese Patent Application Laid-Open No. 2001-313422 of Patent Document 1, and this light-emitting device has one side of a nitride-based semiconductor multilayer structure. It has a positive electrode on the side and a negative electrode on the other side. In the drawings of the present application, dimensional relationships such as length, width, and thickness are appropriately changed for clarity and simplification of the drawings, and do not represent actual dimensional relationships. In the drawings of the present application, the same reference numerals represent the same or corresponding parts.

In the nitride-based semiconductor light-emitting device of FIG. 20, at least an n-type nitride-based semiconductor layer 200 and a p-type nitride are formed on a wafer-like crystal growth substrate (not shown) for growing a nitride-based semiconductor layer. A nitride-based semiconductor multilayer structure including the base-based semiconductor layer 201, a first metal layer 202 for obtaining ohmic contact, and a holding substrate 210 are sequentially formed. The holding substrate 210 includes a second metal layer region 205 and a resin layer region 206 as positive electrodes. The second metal layer region 205 is formed by plating. After the holding substrate 210 is formed, at least part of the crystal growth substrate is removed so that at least part of the n-type nitride semiconductor layer 200 is exposed, and the exposed surface of the n-type nitride semiconductor layer 200 is exposed. A negative electrode is provided on the top.
JP 2001-313422 A

  The inventor examined the manufacture of the nitride-based semiconductor light-emitting device shown in FIG. 20 and found that the wafer surface was warped due to the stress of the nitride-based semiconductor multilayer structure after removing at least a part of the crystal growth substrate. The difference in height was as small as several millimeters, and it was found that the wafer processing in the subsequent process is difficult.

  In other words, when the wafer surface is warped, it becomes difficult to focus on a wide area, for example, in photolithography, resulting in performance degradation and quality variations in a plurality of nitride semiconductor light emitting devices obtained from the wafer. obtain.

  In view of such problems in the prior art, the present invention improves a nitride-based semiconductor light-emitting element having a positive electrode on one side of a nitride-based semiconductor multilayer structure and a negative electrode on the other side, and a method for manufacturing the same. The purpose is to do.

  A nitride-based semiconductor light-emitting device according to the present invention includes a holding substrate including a metal layer region and a resin layer region, a p-type nitride-based semiconductor layer, an active layer, and an n-type nitride-based semiconductor sequentially stacked on the holding substrate. A p-type ohmic electrode that is in ohmic contact with the p-type nitride semiconductor layer between the holding substrate and the p-type nitride semiconductor layer. The included metal layer region is electrically connected to the p-type nitride-based semiconductor layer through the p-type ohmic electrode, and the periphery of the nitride-based semiconductor multilayer structure is retreated inward from the periphery of the holding substrate. It is characterized by being.

  The reason why the peripheral edge of the nitride-based semiconductor multilayer structure is recessed inward from the peripheral edge of the holding substrate is that the wafer structure including a plurality of light-emitting element regions is affected by the stress of the nitride-based semiconductor multilayer structure. This is because a groove for reducing warpage is formed in the semiconductor laminated structure, and after dividing the chip through the groove, one side of the groove width remains as a trace.

  In addition, by covering the side surface of the metal layer region included in the holding substrate with the resin layer region, it is possible to prevent metal migration or change with time of the metal layer region. The planar shape of the metal layer region is not particularly limited, and may be, for example, a circular shape, an elliptical shape, or a polygonal shape. The number of metal layer regions in the light emitting element chip is not particularly limited, but the occupied area of the metal layer region is preferably as large as possible to be as close to the chip size as possible from the viewpoint of heat dissipation of the light emitting element chip. However, if the wafer warpage caused by the stress of the metal layer region becomes a problem during the process of the wafer including a plurality of light emitting element regions, the warp of the wafer can be reduced by forming a plurality of metal layer regions of smaller size. Thermal conductivity and electrical conductivity can be maintained while reducing.

  The holding substrate also plays a role of holding the semiconductor laminated structure after the removal of the crystal growth substrate for growing the nitride-based semiconductor layer laminated structure, and handles the wafer including the holding substrate in a later process. It can be stabilized. The thickness of the holding substrate is preferably in the range of 10 μm to 500 μm, and more preferably in the range of 50 μm to 200 μm.

The holding substrate preferably further includes a barrier film interposed between the p-type ohmic electrode and the p-type nitride semiconductor layer. The barrier film is formed to prevent diffusion between the metal layer region and the p-type ohmic electrode, and also to serve as a plating seed layer when the metal layer region is formed by electrolytic plating. . Further, the barrier film also serves as an etching stop layer when a groove is formed in the nitride-based semiconductor multilayer structure after removing the crystal growth substrate from the wafer. An insulating film such as SiO ₂ or SiN may be formed as an additional etching stop layer in the region where the groove is formed, and a barrier film may be formed thereon.

  The metal layer region included in the holding substrate may include one kind of metal selected from the group consisting of Cu, Ag, Au, Ni, Pd, Pt, and Rh, or a stack of these metals. Since this metal layer region also serves as a positive electrode, it is desirable to apply Cu, Ag, or Au in consideration of the viewpoint of improving electric conduction and heat conduction in the light emitting element chip. Note that when a metal that is easily oxidized, such as Cu, is applied to the metal layer region, a metal layer that is not easily oxidized may be formed on the Cu layer.

  The n-type nitride semiconductor layer preferably includes irregularities on at least a part of its surface. As a result, light emitted from the active layer can be efficiently extracted outside the nitride-based semiconductor multilayer structure. It is preferable that an n-type ohmic electrode is further included on the surface of the n-type nitride semiconductor layer. The n-type ohmic electrode may be formed on the surface of the n-type nitride-based semiconductor layer where the unevenness is not formed, or may be formed on the surface where the unevenness is formed. From the viewpoint of improving the light extraction efficiency by the surface uneven structure, the n-type nitride semiconductor layer preferably has unevenness on the surface other than the n-type ohmic electrode formation region.

  In the method for manufacturing a nitride-based semiconductor light-emitting device according to the present invention, an n-type nitride-based semiconductor layer, a nitride-based semiconductor active layer, and a p-type nitride-based semiconductor layer are formed on a wafer-like crystal growth substrate. Growing in order to form a nitride-based semiconductor multilayer structure, forming a p-type ohmic electrode on the p-type nitride-based semiconductor layer, and covering the p-type nitride-based semiconductor layer and the p-type ohmic electrode. A holding substrate is formed, a support member is bonded onto the holding substrate, the crystal growth substrate is removed to expose the surface of the n-type nitride-based semiconductor layer, and the wafer to which the support member is bonded is used in a subsequent process. It is characterized by being provided.

  In forming the holding substrate, a barrier film covering the p-type nitride semiconductor layer and the p-type ohmic electrode is formed, and a metal layer region is formed on the barrier film above the p-type ohmic electrode. And it is preferable to form a resin layer area | region in the remaining area | region. At this time, a resin layer is preferably formed so as to cover the barrier film and the metal layer region, and this resin layer is preferably ground or polished until the surface of the metal layer region is exposed and processed into the resin layer region. In this method, the uniformity and ease of resin embedding can be improved as compared with the case where the resin is embedded only in the region other than the metal layer region, particularly when the metal layer region is thick or the distance between them is narrow.

  The metal layer region included in the holding substrate can be formed by electrolytic plating, electroless plating, vapor deposition, sputtering, printing, or a combination thereof. When a metal layer region having a thickness of 50 μm or more is desired, electrolytic plating is preferably used.

  After the support member is joined and the crystal growth substrate is removed, a first type groove is formed by etching from the exposed surface of the n-type nitride semiconductor layer into the nitride semiconductor multilayer structure. It is preferable. These first-type grooves can greatly reduce the warpage of the wafer after the crystal growth substrate is removed.

  Moreover, it is preferable that an uneven region is formed on the exposed surface of the n-type nitride-based semiconductor layer. In this case, since the warpage of the wafer is reduced by the support member, the uneven region can be formed with good uniformity.

  An n-type ohmic electrode may be formed in a partial region of the exposed surface of the n-type nitride semiconductor layer. Also in this case, since the warpage of the wafer is reduced by the support member, a plurality of n-type ohmic electrodes can be formed with good uniformity.

  The support member can be removed from the holding substrate after the first type groove is formed in the nitride-based semiconductor multilayer structure and after the n-type ohmic electrode is formed. If the support member is removed before the formation of the first type groove, the warp of the wafer becomes about several millimeters due to the stress of the nitride-based semiconductor multilayer structure, and the subsequent wafer process becomes difficult. On the other hand, if the support member is removed after the formation of the first type groove, the stress of the nitride-based semiconductor multilayer structure can be greatly reduced, so that the warpage of the wafer can be suppressed to about several hundred μm. The process can be stabilized. More preferably, the wafer is subjected to the process in a state where the support member is attached until just before the chip division. As a result, the wafer warpage can be suppressed as compared with the state without the support member, and the wafer can be more stably processed in the process. Finally, the support member is removed before the chip division, but since the wafer warpage is reduced by the formation of the first type groove, the warpage of the wafer can be corrected by the dicing sheet used at the time of chip division. The wafer can be attached to the dicing sheet and the chip can be divided easily and accurately.

  Further, after the formation of the nitride-based semiconductor multilayer structure and before the formation of the p-type ohmic electrode, a second type groove is formed in the nitride-based semiconductor multilayer structure from the surface of the p-type nitride-based semiconductor layer. May be. Due to the effect of the second type groove, when removing the crystal growth substrate after attaching the support member, there is a possibility of cracking due to stress in the nitride-based semiconductor multilayer structure (the stress due to the crystal growth substrate is released). The nitride-based semiconductor multilayer structure tries to return to its own form, but since the semiconductor multilayer structure is fixed by the support member, there is no stress escape field, resulting in cracks and release of the stress) Can be avoided. The second type groove is preferably filled with a transparent insulating film in order to protect the pn junction of the nitride-based semiconductor multilayer structure and prevent the light extraction efficiency from being reduced from the side surface (the second type groove is transparent). If the conductive insulating film is not buried, materials such as the p-type ohmic electrode, the barrier film, and the metal layer region are deposited in the second type trench in the subsequent process, resulting in inconvenience).

  According to the present invention as described above, it is possible to improve a nitride-based semiconductor light-emitting element having a positive electrode on one side of a nitride-based semiconductor multilayer structure and a negative electrode on the other side, and a manufacturing method thereof. .

  As a result of studying the nitride-based semiconductor light-emitting device of Patent Document 1 shown in FIG. 20 by the present inventor, the following matters have been found.

  (1) Before removing the substrate for crystal growth, the warpage of the wafer is reduced to about several tens of μm by adjusting the formation conditions (plating conditions, plating solution, resin layer thickness, resin type, etc.) of the holding substrate 210. Even in this case, the warpage of the wafer becomes about mm after removing the crystal growth substrate.

  (2) By forming a groove in the nitride-based semiconductor multilayer structure, it is possible to reduce the stress exerted on the holding substrate by the semiconductor multilayer structure, and as a result, even after removing the crystal growth substrate, the warp of the wafer is reduced. Can be reduced to about several hundred μm.

  That is, in order to employ a holding substrate formed by using plating, the stress of the nitride-based semiconductor multilayer structure is reduced before the removal of the crystal growth substrate, or the nitride after the removal of the crystal growth substrate is removed. A technique for reducing the stress of the semiconductor multilayer structure after receiving the stress of the semiconductor multilayer structure once by some member is indispensable.

  (3) Furthermore, in order to provide a more stable wafer to the process than in the case of (2), a method for further reducing or correcting the warpage of the wafer is required.

  In view of the above-mentioned matters (1) to (3) that have been clarified as a result of examination by the present inventor, the present invention uses the following method.

  (I) A technique is used in which the stress of the nitride-based semiconductor multilayer structure after removing the substrate for crystal growth is temporarily received by the support member, thereby reducing the warpage of the wafer.

  (Ii) By providing the wafer to the process in a state where the influence of the warpage of the wafer is suppressed by the support member, a more stable process becomes possible.

  (Iii) During the process, a groove is formed by etching from the n-type nitride semiconductor layer side exposed by removing the crystal growth substrate into the nitride semiconductor multilayer structure. This groove makes it possible to reduce the stress of the nitride-based semiconductor multilayer structure, and to reduce the warpage of the wafer after the support member is removed.

  (Iv) The support member is removed immediately before dividing the wafer into chips. Although the wafer is slightly warped by the removal of the support member, the warpage is greatly reduced as compared to the case where no groove is formed in the nitride-based semiconductor multilayer structure, so that the wafer is attached to the dicing sheet during chip division. In addition, chip division can be easily performed.

(Embodiment 1)
The schematic cross-sectional view of FIG. 1 shows a nitride-based semiconductor light-emitting device according to Embodiment 1 of the present invention. The nitride-based semiconductor light-emitting device includes a p-type ohmic electrode 20, a p-type nitride-based semiconductor contact layer 31, a p-type nitride-based semiconductor layer 32, a nitride-based semiconductor active layer 33, and a holding substrate 10 below. N-type nitride semiconductor layers 34 are sequentially stacked. That is, these nitride-based semiconductor layers 31-34 constitute the nitride-based semiconductor multilayer structure 30. The n-type nitride semiconductor layer 34 includes irregularities 34a on at least a part of its surface, and an n-type ohmic electrode 40 is formed on the surface.

  The holding substrate 10 includes a barrier film 1 on the lower surface side thereof, and also includes a metal layer region 2 as a positive electrode formed on the barrier film 1 and a resin layer region 3 covering the side surface thereof. Note that the planar shape of the metal layer region 2 is not particularly limited, and may be, for example, a circular shape, an elliptical shape, a polygonal shape, or the like.

  The nitride-based semiconductor light-emitting device of FIG. 1 can be manufactured through the process illustrated in the schematic cross-sectional views of FIGS.

  In FIG. 2, a buffer layer 51, an n-type nitride semiconductor layer 34, a nitride semiconductor MQW (multiple quantum) are formed on a sapphire substrate 50 as a crystal growth substrate using MOCVD (metal organic vapor deposition). Well) A wafer in which an active layer 33, a p-type nitride semiconductor layer 32, and a p-type nitride semiconductor contact layer 31 are sequentially stacked is manufactured. 2 to 13 show only one light emitting element manufacturing region in the wafer, the wafer actually includes a plurality of light emitting element manufacturing regions that spread two-dimensionally in succession.

  In FIG. 3, the wafer on which the nitride-based semiconductor multilayer structure 30 is formed is taken out from the MOCVD apparatus, and the p-type ohmic electrode 20 is formed on the p-type semiconductor contact layer 31. The ohmic electrode 20 is patterned by etching using a photomask. As the p-type ohmic electrode 20, for example, a Pd layer (thickness 1.5 nm), an Ag layer (thickness 300 nm), and a Ni layer (thickness 100 nm) can be sequentially laminated. The thickness is not limited to these examples. For example, a Ni layer, a Pt layer, or the like can be used instead of the Pd layer, and an Ag—Nd layer, an APC (Ag—Pd—Cu) layer, or the like can be used instead of the Ag layer.

  In FIG. 4, the barrier film 1 is formed so as to cover the p-type semiconductor contact layer 31 and the p-type ohmic electrode 20. The barrier film 1 can be formed by sequentially laminating, for example, a Ti layer (thickness 200 nm) as a diffusion preventing layer and a Cu layer (thickness 300 nm) as a plating seed layer. And the thickness is not limited to these examples. For example, a TiN layer, a TiW layer, a TaN layer or the like can be applied instead of the Ti layer, and an Au layer or the like can be applied instead of the Cu layer.

  In FIG. 5, the photomask layer 60 is patterned on the barrier film 1. Then, the metal layer region 2 is formed on the barrier film 1 exposed in the opening region of the photomask layer 60 by electrolytic plating. At this time, the Cu layer contained in the barrier film 1 acts as a plating seed layer. The metal layer region 2 can be, for example, a Cu plating layer, but is not limited thereto, and may be an Au plating layer, an Ag plating layer, or the like.

  The thickness of the photomask layer 60 is preferably larger than the thickness of the metal layer region 2 formed by electrolytic plating. For example, when the thickness of the metal layer region 2 is 100 μm, the photomask layer 60 is desirably thicker than 100 μm. According to a method generally used in the plating process, a liquid resist for thick film, dry film, or the like can be used as a photomask material. By removing the scum from the mask opening after patterning the photomask layer 60, the uniformity and adhesion of the plating layer 2 can be improved. For this scum removal, a technique generally used in the plating process can be used.

  When forming the metal layer region 2 by electrolytic plating, the wafer is immersed in an electrolytic plating bath. This immersion time is not particularly limited, and is appropriately selected according to the properties required for the metal layer region 2 and the uniformity of thickness, and may be, for example, about 30 to 180 minutes. More specifically, for example, when the metal layer region 2 having a thickness of 100 μm is formed, the immersion time can be set to about 90 minutes.

  The metal layer region 2 may be formed including a plurality of types of metal layers. For example, when the metal layer region 2 includes a metal layer such as Cu that easily oxidizes, for example, the Au layer or a laminate of the Ni layer and the Au layer may be plated after the Cu layer plating. By forming the outermost surface of the metal layer region 2 from a material that is difficult to oxidize, its reliability is improved. The thickness of the antioxidant layer in this case is not particularly limited, but a thickness of 1 μm or less is sufficient for the purpose of preventing oxidation.

  In addition, the formation method of the metal layer area | region 2 is not restricted to electrolytic plating, Other methods, such as electroless plating, vapor deposition, sputtering, and printing, can also be used. In addition, after the metal layer region 2 is formed, the plating seed layer as the uppermost layer of the multilayer barrier film 1 may be removed by etching outside the metal layer region 2. Here, when the seed layer and the metal layer region 2 in the multilayer barrier film 1 are the same metal species, the metal layer region 2 is also etched by the same thickness when the seed layer is removed by etching. The thickness of the metal layer region 2 is adjusted to be the thickness of the holding substrate 10.

  In FIG. 6, after the photomask layer 60 is removed using a stripping solution, a resin layer 3 a is formed so as to cover the barrier film 1 and the metal layer region 2. The resin layer 3a can be formed using an epoxy resin or the like, and the epoxy resin can be thermally cured after coating by a printing method, for example. The thickness of the resin layer 3a is desirably equal to or greater than the thickness of the metal layer region 2. For example, when the thickness of the metal layer region 2 is 100 μm, the thickness of the resin layer 3a is preferably 150 μm or more, and is set to 200 μm in this embodiment.

  In FIG. 7, the resin layer 3 a is ground or polished until the metal layer region 2 is exposed, and is processed into the resin layer region 3. Thereby, the formation of the holding substrate 10 is completed.

  In FIG. 8, a support member 70 is attached on the metal layer region 2 and the resin layer region 3. The support member 70 includes an adhesive sheet 71 and a support substrate 72. In this embodiment, a 170 ° C. type thermally foamed sheet is used as the adhesive sheet, but other thermally foamed sheets of a temperature type higher than the subsequent process temperature can also be used. The support substrate 72 may be a sapphire substrate, but other substrates such as a commonly used Si substrate and GaAs substrate may be used.

  In FIG. 9, the crystal growth sapphire substrate 50 is removed, and the surface of the n-type nitride semiconductor layer 34 is exposed. Specifically, after removing the sapphire substrate 50 by laser peeling, the remaining Ga residue on the buffer layer 51 is removed by hydrochloric acid wet etching or the like, and then the surface of the n-type nitride semiconductor layer 34 by dry etching. To expose.

  In FIG. 10, after forming a resist mask pattern (not shown) having a thickness of, for example, 10 μm on the surface of the n-type nitride semiconductor layer 34, a groove 36 is formed in the nitride semiconductor stacked structure 30 by dry etching. By forming the groove 36, the warpage of the wafer after the support member 70 is removed can be reduced. After the grooves 36 are formed by dry etching, the resist pattern is removed with a stripping solution.

  In FIG. 11, a resist mask pattern (not shown) having a thickness of, for example, 10 μm is formed on the surface of the n-type nitride semiconductor layer 34, and the surface uneven structure 34a is formed by dry etching. In the present embodiment, the height difference in the surface uneven structure 34a is set to 1 μm, but the value is not limited to this height difference value. After the surface concavo-convex structure 34a is formed by dry etching, the resist pattern is removed with a stripping solution. The surface uneven structure 34a may be formed by wet etching using KOH or the like.

  In FIG. 12, an n-type ohmic electrode 40 is formed in a partial region on the surface uneven structure 34a. For example, an Hf layer (thickness 5 nm) and an Al layer (thickness 900 nm) can be sequentially stacked as the n-type ohmic electrode 40, but the material and thickness of these layers are not limited to these examples.

  In FIG. 13, the support member 70 is removed from the wafer. Specifically, since the support member 70 can be removed by heating at or above the foaming start temperature of the adhesive sheet 71, the support member 70 was removed by placing the wafer on a hot plate and heating to 170 ° C.

  In FIG. 14, after the support member 70 is removed, a dicing sheet 90 is attached to the n-type nitride-based semiconductor layer 34 side of the wafer, and as shown by the arrows in the drawing, dicing in the resin layer region 3 or The chip is divided by laser scribing. If the chip is divided in the metal layer region 2, the divided side surfaces of the metal layer region 2 are exposed and are not protected, causing deterioration of the metal layer region 2. Further, the total area of the metal layer region 2 per light emitting element chip is reduced, and there is a possibility that the heat dissipation of the light emitting element chip is lowered.

(Embodiment 2)
The schematic cross-sectional view of FIG. 15 shows one stage of the manufacturing process of the nitride-based semiconductor light-emitting device according to Embodiment 2 of the present invention. The process stage in FIG. 15 in the second embodiment corresponds to the process stage in FIG. 5 in the first embodiment.

  However, the wafer of FIG. 5 according to the second embodiment has a plurality of metal layers per light emitting element region, as compared with the case where the wafer of FIG. 5 includes one metal layer region 2 per light emitting element region. It differs in that it includes the region 2a. That is, in FIG. 15, the resist layer 60a includes a plurality of openings in one light emitting element region, and the metal layer region 2a is formed in these openings. The wafer shown in FIG. 15 is subsequently processed into a plurality of light emitting element chips through the same process as in the first embodiment.

(Embodiment 3)
The schematic cross-sectional views of FIGS. 16 and 17 show a middle stage of the manufacturing process of the nitride-based semiconductor light-emitting device according to Embodiment 3 of the present invention. Also in the third embodiment, the wafer shown in FIG. 3 of the first embodiment is formed.

FIG. 16 shows the process steps following FIG. In this process step, the insulating film 4 is formed to a thickness of 1 μm so as to cover the p-type semiconductor contact layer 31 and the p-type ohmic electrode 20. Thereafter, the insulating film 4 is partially removed in the region on the p-type ohmic electrode 20 by etching using a photomask (not shown). Of course, the photomask is removed after the etching is completed. In this way, the wafer of FIG. 16 is obtained. The insulating film 4 can be formed of a single layer film such as SiO ₂ , SiN, SOG (spin on glass), polyimide, or a laminated film thereof, and the thickness of the insulating film 4 is not limited to 1 μm. Can be selected within the range of 0.5 to 5 μm.

  In FIG. 17, the barrier film 1 a is formed so as to cover the p-type ohmic electrode 20 and the insulating film 4. This barrier film 1a can be formed in the same manner as the barrier film 1 in FIG.

  The wafer of FIG. 17 in the third embodiment is also processed into a plurality of light emitting element chips through the same process as that of FIG.

  In addition, the insulating film 4 in the third embodiment can exhibit a barrier effect similarly to the barrier film 1a, and also serves as an etching stop layer when the groove 36 as shown in FIG. 10 is formed by etching. Can also demonstrate.

(Embodiment 4)
18 and 19 show the middle stages of the manufacturing process of the nitride-based semiconductor light-emitting device according to Embodiment 4 of the present invention. Also in the fourth embodiment, the wafer shown in FIG. 2 of the first embodiment is formed.

  FIG. 18 shows the process steps following FIG. In this process step, a photomask 81 is formed on the p-type semiconductor contact layer 31, and a groove 82 is formed by etching so that the remaining thickness of the semiconductor stacked structure 30 becomes 0.5 μm. However, the thickness remaining at the bottom of the groove 82 in the semiconductor multilayer structure 30 is not limited to 0.5 μm, and may be selected within a range of 0.5 to 5 μm.

  In the fourth embodiment, the groove 82 is a crack caused by the stress of the nitride-based semiconductor multilayer structure 30 when the crystal growth substrate 50 is removed in a state where the support member 70 is attached in a later process step similar to FIG. It can act to suppress the occurrence of. The planar position of the groove 82 is preferably formed so as to coincide with the groove 36 formed in a later process step similar to FIG.

In FIG. 19, after removing the photomask 81, the trench 82 is filled with a translucent insulating film 83. Here, the translucent insulating film 82 can be formed of a single layer film such as SiO ₂ , SiN, SOG (spin-on-glass), polyimide, or a laminated film thereof. The reason why the trench 82 is filled with the translucent insulating film 83 is to protect the pn junction of the nitride-based semiconductor multilayer structure 30 and to prevent a decrease in light extraction efficiency from its side surface. If the groove 82 is not filled with the translucent insulating film 83 and the process proceeds to the subsequent process stage, materials such as the ohmic electrode 20, the barrier film 1, and the first metal layer 2 region are deposited in the groove 82, which causes inconvenience. Because it occurs.

  The wafer of FIG. 19 in the fourth embodiment is also processed into a plurality of light emitting element chips through the same process as that of FIG.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  As described above, according to the present invention, in a nitride-based semiconductor light-emitting device having a positive electrode on one side of a nitride-based semiconductor multilayer structure and a negative electrode on the other side, the characteristics and manufacturing method of the device Can be improved.

1 is a schematic cross-sectional view showing a nitride semiconductor light emitting device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing one stage in the manufacturing process of the nitride semiconductor light emitting device of FIG. 1. FIG. 3 is a schematic cross-sectional view showing a process step subsequent to FIG. 2. FIG. 4 is a schematic cross-sectional view showing a process step subsequent to FIG. 3. FIG. 5 is a schematic cross-sectional view showing a process step subsequent to FIG. 4. FIG. 6 is a schematic cross-sectional view showing a process step subsequent to FIG. 5. FIG. 7 is a schematic cross-sectional view showing a process step subsequent to FIG. 6. FIG. 8 is a schematic cross-sectional view showing a process step subsequent to FIG. 7. FIG. 9 is a schematic cross-sectional view showing a process step subsequent to FIG. 8. FIG. 10 is a schematic cross-sectional view showing a process step subsequent to FIG. 9. FIG. 11 is a schematic cross-sectional view showing a process step subsequent to FIG. 10. FIG. 12 is a schematic cross-sectional view showing a process step subsequent to FIG. 11. FIG. 13 is a schematic cross-sectional view showing a process step subsequent to FIG. 12. FIG. 14 is a schematic cross-sectional view showing a process step subsequent to FIG. 13. FIG. 6 is a schematic cross-sectional view showing one stage in a manufacturing process of a nitride semiconductor light emitting device according to another embodiment of the present invention. FIG. 10 is a schematic cross-sectional view showing one stage in a manufacturing process of a nitride semiconductor light emitting device according to still another embodiment of the present invention. FIG. 17 is a schematic cross-sectional view showing a process step subsequent to FIG. 16. FIG. 10 is a schematic cross-sectional view showing one stage in a manufacturing process of a nitride semiconductor light emitting device according to still another embodiment of the present invention. FIG. 19 is a schematic cross-sectional view showing a process step subsequent to FIG. 18. 1 is a schematic cross-sectional view showing a nitride-based semiconductor light-emitting device according to Patent Document 1.

Explanation of symbols

  1, 1a barrier film, 2, 2a metal layer region, 3 resin layer region, 3a resin layer, 4 insulating film, 10 holding substrate, 20 p-type ohmic electrode, 30 nitride-based semiconductor multilayer structure, 31 p-type nitride-based Semiconductor contact layer, 32 p-type nitride semiconductor layer, 33 active layer, 34 n-type nitride semiconductor layer, 34a surface irregularities, 36 grooves, 40 n-type ohmic electrode, 50 crystal growth substrate, 51 buffer layer, 60, 60a Photoresist mask, 70 Support member, 71 Adhesive sheet, 72 Support substrate, 81 Photomask, 82 Groove, 83 Insulating film, 90 Dicing sheet, 200 n-type nitride semiconductor layer, 201 p-type nitride semiconductor Layer, 202 first metal layer, 205 second metal layer, 206 resin region, 210 holding substrate.

Claims (17)

A holding substrate including a metal layer region and a resin layer region;
A nitride-based semiconductor multilayer structure including a p-type nitride-based semiconductor layer, an active layer, and an n-type nitride-based semiconductor layer, which are sequentially stacked on the holding substrate, and the holding substrate and the p-type nitride-based semiconductor layer A p-type ohmic electrode in ohmic contact with the p-type nitride-based semiconductor layer,
The metal layer region included in the holding substrate is electrically connected to the p-type nitride-based semiconductor layer through the p-type ohmic electrode,
A nitride-based semiconductor light-emitting device, wherein a periphery of the nitride-based semiconductor multilayer structure is recessed inward from a periphery of the holding substrate.   2. The nitride-based semiconductor light-emitting element according to claim 1, wherein a side surface of the metal layer region included in the holding substrate is covered with the resin layer region.   The nitride-based semiconductor light-emitting element according to claim 1, wherein the holding substrate further includes a barrier film interposed between the p-type ohmic electrode and the p-type nitride-based semiconductor layer.   The metal layer region included in the holding substrate includes one kind of metal selected from the group consisting of Cu, Ag, Au, Ni, Pd, Pt, and Rh, or a stack of these metals. Item 4. The nitride-based semiconductor light-emitting device according to any one of Items 1 to 3.   5. The nitride-based semiconductor light-emitting element according to claim 1, wherein the holding substrate has a thickness in a range of 10 μm to 500 μm.   6. The nitride-based semiconductor light-emitting element according to claim 1, wherein the n-type nitride-based semiconductor layer includes irregularities on at least a part of a surface thereof.   The nitride-based semiconductor light-emitting element according to claim 1, further comprising an n-type ohmic electrode on a surface of the n-type nitride-based semiconductor layer. On the wafer-like crystal growth substrate, an n-type nitride semiconductor layer, a nitride semiconductor active layer, and a p-type nitride semiconductor layer are sequentially grown to form a nitride semiconductor stacked structure,
Forming a p-type ohmic electrode on the p-type nitride semiconductor layer;
Forming a holding substrate so as to cover the p-type nitride semiconductor layer and the p-type ohmic electrode;
Bonding a support member on the holding substrate,
Removing the crystal growth substrate to expose a surface of the n-type nitride semiconductor layer;
A method for manufacturing a nitride-based semiconductor light-emitting device, wherein the wafer to which the support member is bonded is subjected to a subsequent process.   In the formation of the holding substrate, a barrier film is formed to cover the p-type nitride semiconductor layer and the p-type ohmic electrode, and a metal layer region is formed on the barrier film above the p-type ohmic electrode. And the resin layer area | region is formed in the remaining area | region, The manufacturing method of the nitride type semiconductor light-emitting device of Claim 8 characterized by the above-mentioned.   A resin layer is formed so as to cover the barrier film and the metal layer region, and the resin layer is ground or polished until the surface of the metal layer region is exposed to be processed into the resin layer region. The method for producing a nitride-based semiconductor light-emitting device according to claim 9.   The nitride according to any one of claims 8 to 10, wherein the metal layer region included in the holding substrate is formed by electrolytic plating, electroless plating, vapor deposition, sputtering, printing, or a combination thereof. For manufacturing a semiconductor light emitting device.   12. The first type groove is formed by etching from the exposed surface of the n-type nitride semiconductor layer into the nitride semiconductor multilayer structure. Of manufacturing a nitride-based semiconductor light-emitting device.   The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 8, wherein an uneven region is formed on the exposed surface of the n-type nitride-based semiconductor layer.   14. The nitride-based semiconductor light-emitting element according to claim 8, wherein an n-type ohmic electrode is formed in a partial region of the exposed surface of the n-type nitride-based semiconductor layer. Production method.   The method according to claim 14, wherein the support member is removed from the holding substrate after the n-type ohmic electrode is formed.   A second type groove is formed in the nitride-based semiconductor multilayer structure from the surface of the p-type nitride-based semiconductor layer after the formation of the nitride-based semiconductor multilayer structure and before the formation of the p-type ohmic electrode. The method for producing a nitride-based semiconductor light-emitting device according to claim 8, wherein   The method for manufacturing a nitride-based semiconductor light-emitting element according to any one of the stacked structures 8 to 16, wherein the second type groove is filled with a light-transmitting insulating film.

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