JP2007096090A - Semiconductor light emitting element and method of manufacturing the same - Google Patents

Semiconductor light emitting element and method of manufacturing the same Download PDF

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JP2007096090A
JP2007096090A JP2005285015A JP2005285015A JP2007096090A JP 2007096090 A JP2007096090 A JP 2007096090A JP 2005285015 A JP2005285015 A JP 2005285015A JP 2005285015 A JP2005285015 A JP 2005285015A JP 2007096090 A JP2007096090 A JP 2007096090A
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electrode
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semiconductor light
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Saburo Nakajima
三郎 中島
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Sanyo Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light emitting device which can be prevented from decreasing in light emission intensity and increasing in leak current not by giving damage to a light emission region of a semiconductor light emission layer caused by mechanical stress or a shock during wire bonding. <P>SOLUTION: A conductive substrate 1, a p-side electrode 6, and an insulating layer 5 are joined to one another through a conductive fusion layer 7. A nitride semiconductor layer 2 including the light emission region is formed as the semiconductor light emission layer, and the p-side electrode 6 is formed of metal below the nitride semiconductor layer 2. An n-side electrode comprises an n-side wire bonding electrode 3, and an auxiliary electrode 4. The n-side wire bonding electrode 3 is arranged in a region apart from a region where the nitride semiconductor layer 2 is formed, so that neither a shock nor stress during wire bonding is applied to the nitride semiconductor layer 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、ワイヤボンディング電極を有する半導体発光素子及び半導体発光素子の製造方法に関する。   The present invention relates to a semiconductor light emitting device having a wire bonding electrode and a method for manufacturing the semiconductor light emitting device.

今日、ＧａＮ（窒化ガリウム）、ＡｌＮ（窒化アルミニウム）、ＩｎＮ（窒化インジウム）、ＢＮ（窒化ホウ素）もしくはＴｌＮ（窒化タリウム）またはこれらの混晶等を用いたＩＩＩ−Ｖ族窒化物半導体（以下、窒化物系半導体と呼ぶ）およびこれらの混晶にＡｓ、ＰおよびＳｂの少なくとも１つの元素を含む混晶等のＩＩＩ−Ｖ族窒化物半導体からなる化合物半導体層を有する窒化物系半導体素子を利用した発光ダイオード（以下ＬＥＤ）の開発が盛んに行われている。特に近年、将来の照明代替用途を目指して発光出力の向上と低コスト化の要望が強い。そのためには歩留まり向上が重要となってくる。   Today, III-V group nitride semiconductors using GaN (gallium nitride), AlN (aluminum nitride), InN (indium nitride), BN (boron nitride), TlN (thallium nitride), or a mixed crystal thereof (hereinafter referred to as the following) Nitride-based semiconductor elements having a compound semiconductor layer made of a III-V group nitride semiconductor such as a mixed crystal containing at least one element of As, P, and Sb in these mixed crystals are used. The development of light emitting diodes (hereinafter referred to as LEDs) has been actively conducted. In particular, in recent years, there is a strong demand for improvement in light emission output and cost reduction for future lighting alternative applications. For this purpose, yield improvement is important.

ところで、上記窒化物系半導体素子を利用したＬＥＤ等に限らず、一般に半導体発光素子では、発光領域に電流を流すために、電極にリードワイヤーをワイヤボンディングにより接続することが行われている。このワイヤボンディング時には、キャピラリによる過度の力等が電極に加わることにより電極下の半導体層の発光領域にダメージを与えて破壊してしまうようなことがあり、発光領域へのダメージは、発光強度の低下やリーク電流の増大という問題を引き起こしていた。   By the way, not only the LED using the nitride-based semiconductor element and the like, but generally in a semiconductor light-emitting element, a lead wire is connected to an electrode by wire bonding in order to flow a current in a light-emitting region. At the time of wire bonding, excessive force or the like by the capillary may be applied to the electrode to damage the light emitting region of the semiconductor layer under the electrode, causing damage to the light emitting region. This causes problems such as a decrease and an increase in leakage current.

そこで、上記問題を解決するために、例えば特許文献１に示されるように、ワイヤボンディングする電極を半導体発光素子の発光領域以外の場所に形成する技術が提案されている。この従来技術を用いた半導体発光素子の構造を図４に示す。図４（ａ）は平面図を、（ｂ）は（ａ）のＡ−Ａ’断面図を、（ｃ）は（ａ）のＢ−Ｂ’断面図を示す。サファイア等の絶縁性基板２１上には、ｎ型窒化物半導体層２７、発光層及びｐ型層を含む窒化物半導体層２２が形成されている。ｐ側ワイヤボンディング用電極２３は、窒化物半導体層２２の上に設けられており、ｎ側ワイヤボンディング用電極２４は、ｎ型窒化物半導体層２７に直接形成されている。   In order to solve the above problem, for example, as disclosed in Patent Document 1, a technique for forming an electrode to be wire-bonded in a place other than the light emitting region of the semiconductor light emitting element has been proposed. The structure of a semiconductor light emitting device using this conventional technique is shown in FIG. 4A is a plan view, FIG. 4B is a sectional view taken along the line A-A ′ in FIG. 4A, and FIG. 4C is a sectional view taken along the line B-B ′ in FIG. On an insulating substrate 21 such as sapphire, an n-type nitride semiconductor layer 27, a nitride semiconductor layer 22 including a light emitting layer and a p-type layer are formed. The p-side wire bonding electrode 23 is provided on the nitride semiconductor layer 22, and the n-side wire bonding electrode 24 is formed directly on the n-type nitride semiconductor layer 27.

また、ｐ側ワイヤボンディング用電極２３からは補助電極２５が延出されており、ｎ側ワイヤボンディング用電極２４を取り囲むように環状に形成されている。この補助電極２５が設けられていることで、窒化物半導体層２２に電流がより均一に流れ、発光強度が向上する。   An auxiliary electrode 25 extends from the p-side wire bonding electrode 23 and is formed in an annular shape so as to surround the n-side wire bonding electrode 24. By providing the auxiliary electrode 25, a current flows more uniformly in the nitride semiconductor layer 22 and the light emission intensity is improved.

図４の構成において、仮に、ワイヤボンディング時の機械的ストレスや衝撃により窒化物半導体層２２Ｂが破壊されたとしても、ｐ側ワイヤボンディング用電極２３下の窒化物半導体層２２Ｂと、発光に寄与させる発光領域としての役割を果す窒化物半導体層２２Ａとを絶縁膜２６により電気的に分離しているので、ダメージを受けていない窒化物半導体層２２Ａ側が発光領域として動作し、発光強度の低下やリーク電流の増大を防止することができるというものである。
特開２００３−１７９２３６ In the configuration of FIG. 4, even if the nitride semiconductor layer 22B is destroyed due to mechanical stress or impact during wire bonding, the nitride semiconductor layer 22B under the p-side wire bonding electrode 23 contributes to light emission. Since the nitride semiconductor layer 22A serving as a light emitting region is electrically separated from the nitride semiconductor layer 22 by the insulating film 26, the nitride semiconductor layer 22A side that is not damaged operates as the light emitting region, and the emission intensity is reduced or leaked. The increase in current can be prevented.
JP 2003-179236 A

しかし、上記従来技術は、絶縁性基板に半導体発光層を成長させ、同一面側にｐ側電極とｎ側電極を有する構造を対象としている。したがって、導電性基板に半導体発光層を成長させ、半導体発光層のｐ側とｎ側にそれぞれ電極を対向して形成した半導体発光素子においては、ワイヤボンディング用電極と対向した電極との間で電流を流す構造となるため、上記従来技術を適用できず、ワイヤボンディング用電極下の窒化物半導体層を電気的に分離できないという問題があった。   However, the above prior art is directed to a structure in which a semiconductor light emitting layer is grown on an insulating substrate and a p-side electrode and an n-side electrode are provided on the same surface side. Therefore, in the semiconductor light emitting device in which the semiconductor light emitting layer is grown on the conductive substrate and the electrodes are formed on the p side and the n side of the semiconductor light emitting layer so as to face each other, the current between the wire bonding electrode and the facing electrode is Therefore, there is a problem in that the conventional technology cannot be applied and the nitride semiconductor layer under the wire bonding electrode cannot be electrically separated.

本発明は、上述した課題を解決するために創案されたものであり、ワイヤボンディング時の機械的ストレスや衝撃により半導体発光層の発光領域にダメージを与えないようにして、発光強度の低下やリーク電流の増大を防止することができ、歩留まりを良くすることができる半導体発光素子及び半導体発光素子の製造方法を提供することを目的としている。   The present invention was devised to solve the above-described problems, and reduces the emission intensity and leaks by preventing damage to the light emitting region of the semiconductor light emitting layer due to mechanical stress or impact during wire bonding. An object of the present invention is to provide a semiconductor light emitting device capable of preventing an increase in current and improving yield, and a method for manufacturing the semiconductor light emitting device.

上記目的を達成するために、本発明に係る半導体発光素子は、導電性基板上に、少なくとも、第１電極、発光領域を含む半導体発光層、第２電極が順に積層され、前記第２電極の一部がワイヤボンディング用電極を構成している半導体発光素子において、前記ワイヤボンディング用電極を前記半導体発光層と上下に重ならないように、半導体発光層が形成されている領域から分離した領域に配置したことを特徴とする半導体発光素子である。   In order to achieve the above object, a semiconductor light emitting device according to the present invention includes, on a conductive substrate, at least a first electrode, a semiconductor light emitting layer including a light emitting region, and a second electrode, which are sequentially stacked. In a semiconductor light emitting device, part of which constitutes a wire bonding electrode, the wire bonding electrode is disposed in a region separated from the region where the semiconductor light emitting layer is formed so as not to overlap the semiconductor light emitting layer. This is a semiconductor light emitting device characterized by the above.

また、前記ワイヤボンディング用電極と前記半導体発光層との間には電気的絶縁層が形成されていることを特徴とする請求項１記載の半導体発光素子である。   2. The semiconductor light emitting element according to claim 1, wherein an electrically insulating layer is formed between the wire bonding electrode and the semiconductor light emitting layer.

また、前記電気的絶縁層が、前記半導体発光層の一部に重なるようにして半導体発光層の上側に形成されていることを特徴とする請求項２記載の半導体発光素子である。   3. The semiconductor light emitting element according to claim 2, wherein the electrically insulating layer is formed on an upper side of the semiconductor light emitting layer so as to overlap a part of the semiconductor light emitting layer.

また、前記第１電極と導電性基板とは電気的に接続されており、電気的に接続された面と反対側の面は外部接続端子となっていることを特徴とする請求項１〜請求項３のいずれか１項に記載の半導体発光素子である。   The first electrode and the conductive substrate are electrically connected, and a surface opposite to the electrically connected surface is an external connection terminal. 4. The semiconductor light-emitting device according to any one of items 3.

また、本発明に係る半導体発光素子の製造方法は、成長用基板に発光領域を含む半導体発光層、第１電極の順に成長させ、導電性基板に前記半導体発光層、第１電極を貼り替えた後、前記半導体発光層の上に第２電極が積層されるとともに、該第２電極の一部を構成するワイヤボンディング用電極が前記半導体発光層と上下に重ならないように、半導体発光層が形成されている領域から分離した領域に設けられる半導体発光素子の製造方法において、成長用基板上で前記半導体発光層、第１電極のパターニングを行っておくことを特徴とする半導体発光素子の製造方法である。   Also, in the method for manufacturing a semiconductor light emitting device according to the present invention, a semiconductor light emitting layer including a light emitting region on a growth substrate and a first electrode are grown in this order, and the semiconductor light emitting layer and the first electrode are pasted on a conductive substrate. Thereafter, a second electrode is stacked on the semiconductor light emitting layer, and a semiconductor light emitting layer is formed so that a wire bonding electrode constituting a part of the second electrode does not overlap with the semiconductor light emitting layer. A method for manufacturing a semiconductor light emitting device, comprising: patterning the semiconductor light emitting layer and the first electrode on a growth substrate, wherein the semiconductor light emitting layer and the first electrode are patterned on a growth substrate. is there.

本発明によれば、半導体発光素子のワイヤボンディング電極部が、半導体発光層が形成されている領域とは異なる領域に形成されているので、ワイヤボンディング時に半導体発光層には機械的ストレスや衝撃が伝わらず、ダメージが発生しないので、発光強度の低下やリーク電流の増大を防止することができ、歩留まりを良くすることができる。   According to the present invention, since the wire bonding electrode portion of the semiconductor light emitting device is formed in a region different from the region where the semiconductor light emitting layer is formed, mechanical stress and impact are applied to the semiconductor light emitting layer during wire bonding. Therefore, no damage occurs, so that a decrease in light emission intensity and an increase in leakage current can be prevented, and the yield can be improved.

以下、図面を参照して本発明の一実施形態を説明する。図１は本発明による半導体発光素子の構造を示す。図１（ａ）は、本発明の半導体発光素子の平面図を、同図（ｂ）は（ａ）のＡ−Ａ’断面図を、（ｃ）は（ａ）のＢ−Ｂ’断面図を示す。     Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the structure of a semiconductor light emitting device according to the present invention. 1A is a plan view of a semiconductor light emitting device of the present invention, FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. 1A, and FIG. 1C is a cross-sectional view taken along line BB ′ in FIG. Indicates.

半導体発光層として発光領域を含む窒化物半導体層２が形成されており、窒化物半導体層２の下側には金属からなるｐ側電極６が、上側には金属からなるｎ側電極が形成されており、ｐ側電極とｎ側電極は窒化物半導体層２を挟んで対向して設けられている。ｐ側電極６とｎ側電極は、各々、第１電極又は第２電極のいずれかに相当するものである。   A nitride semiconductor layer 2 including a light emitting region is formed as a semiconductor light emitting layer. A p-side electrode 6 made of metal is formed on the lower side of the nitride semiconductor layer 2 and an n-side electrode made of metal is formed on the upper side. The p-side electrode and the n-side electrode are provided to face each other with the nitride semiconductor layer 2 interposed therebetween. Each of the p-side electrode 6 and the n-side electrode corresponds to either the first electrode or the second electrode.

また、ｎ側電極は、ｎ側ワイヤボンディング用電極３とｎ側ワイヤボンディング用電極３から延出されて環状に形成された補助電極４とで構成されている。この補助電極４は、窒化物半導体層２の上側と絶縁層５の上側に接触するように設けられており、補助電極４により窒化物半導体層２に電流がより均一に流れ、発光強度が向上する。   The n-side electrode includes an n-side wire bonding electrode 3 and an auxiliary electrode 4 that extends from the n-side wire bonding electrode 3 and has an annular shape. The auxiliary electrode 4 is provided so as to be in contact with the upper side of the nitride semiconductor layer 2 and the upper side of the insulating layer 5, and the auxiliary electrode 4 allows the current to flow more uniformly in the nitride semiconductor layer 2, thereby improving the light emission intensity. To do.

ｎ側ワイヤボンディング用電極３は、導電性基板１の片隅に配置されており、絶縁層５上に形成されているもので、窒化物半導体層２とは接触しておらず、また、窒化物半導体層２が形成されている領域と離れた領域に配置され、窒化物半導体層２とは上下に重ならない位置に設けられている。一方、導電性基板１とｐ側電極６及び絶縁層５とは導電性融着層７を介して接合されており、この接合面と反対側にはｐ側電極端子８が形成されている。   The n-side wire bonding electrode 3 is disposed at one corner of the conductive substrate 1 and is formed on the insulating layer 5 and is not in contact with the nitride semiconductor layer 2. The semiconductor layer 2 is disposed in a region away from the region where the semiconductor layer 2 is formed, and is provided at a position where the nitride semiconductor layer 2 does not overlap vertically. On the other hand, the conductive substrate 1, the p-side electrode 6 and the insulating layer 5 are joined via a conductive fusion layer 7, and a p-side electrode terminal 8 is formed on the side opposite to the joined surface.

半導体発光層としての窒化物半導体層２は、ｎ側電極から近い順に、例えば、ｎ型コンタクト層、ｎ型クラッド層、活性層、ｐ型クラッド層、ｐ型コンタクト層等から構成される。この場合、活性層が発光領域に相当する。   The nitride semiconductor layer 2 as the semiconductor light emitting layer includes, for example, an n-type contact layer, an n-type cladding layer, an active layer, a p-type cladding layer, and a p-type contact layer in order from the n-side electrode. In this case, the active layer corresponds to the light emitting region.

導電性基板１は、電気を導通させるものであれば何でも良いが、本実施例では、窒化物半導体層２を用いているので、導電性基板１は、窒化物半導体層２の熱膨張率と近い材料が良く、例えば、熱膨張率が近いものから順に、ＧａＮ、シリコン、ＳｉＣの導電性材料が望ましく、その他に酸化銅と銅粒子の焼成基板（Ｃｕ２Ｏ ５０ｗｔ％）やＣｕＷ合金等が適切である。 The conductive substrate 1 may be anything as long as it conducts electricity. However, in this embodiment, the nitride semiconductor layer 2 is used, so the conductive substrate 1 has a coefficient of thermal expansion of the nitride semiconductor layer 2. Close materials are good. For example, conductive materials of GaN, silicon, and SiC are desirable in order of decreasing thermal expansion coefficient. In addition, copper oxide and copper particle fired substrates (Cu 2 O 50 wt%), CuW alloys, etc. Is appropriate.

また、絶縁層５は、電気的絶縁材料で構成されており、塗布型の絶縁物としてポリイミド樹脂等を、ＣＶＤ、スパッタ、蒸着型の絶縁物としてＳｉＯ２、ＴｉＯ２、Ａｌ２Ｏ３等を用いる。ＳｉＯ２、ＴｉＯ２、Ａｌ２Ｏ３等を用いた場合、これらの材料は、無機材料で耐熱性に優れているので、絶縁層の上にｎ側電極材料を蒸着やスパッタで形成する温度（基板温度は約２００℃になる）に耐えることができ、電極材料の蒸着やスパッタ時の収縮がない。また、硬度が大きく、パターニング時の薬品に耐えることができ、組み立て工程での機械的ストレスでの変形がない。 The insulating layer 5 is made of an electrically insulating material, and polyimide resin or the like is used as a coating type insulator, and SiO 2 , TiO 2 , Al 2 O 3 or the like is used as a CVD, sputter, or vapor deposition type insulator. Use. When SiO 2 , TiO 2 , Al 2 O 3 or the like is used, these materials are inorganic materials and have excellent heat resistance. Therefore, the temperature at which the n-side electrode material is formed on the insulating layer by vapor deposition or sputtering ( The substrate temperature is about 200 ° C.), and there is no shrinkage during electrode material deposition or sputtering. Further, it has a high hardness, can withstand chemicals during patterning, and is not deformed by mechanical stress in the assembly process.

ｐ側電極６は、例えば、金属の多層膜により構成されており、窒化物半導体層２側から近い順に、Ｔｉ（膜厚１００Å）、Ａｌ（膜厚１０００Å）、Ｔｉ（膜厚１０００Å）、Ｐｔ（膜厚２０００Å）、Ａｕ（膜厚３０００Å）の多層構造となっている。一方、ｎ側ワイヤボンディング用電極３と補助電極４とで構成されたｎ側電極は、ｐ側電極６と同様、金属の多層膜により構成されており、例えば、窒化物半導体層２側から近い順に、Ｎｉ（膜厚１００Å）、Ａｌ（膜厚１０００Å）、Ｔｉ（膜厚１０００Å）、Ｐｔ（膜厚２０００Å）、Ａｕ（膜厚３０００Å）の多層構造となっている。導電性基板１の両側に設けられた導電性融着層７とｐ側電極端子８は、例えば膜厚２〜８μｍのＡｕ（７０〜８０％）とＳｎ（２０〜３０％）の合金により構成される。   The p-side electrode 6 is composed of, for example, a metal multilayer film, and in order from the nitride semiconductor layer 2 side, Ti (film thickness 100 mm), Al (film thickness 1000 mm), Ti (film thickness 1000 mm), Pt It has a multilayer structure of (film thickness 2000 mm) and Au (film thickness 3000 mm). On the other hand, the n-side electrode composed of the n-side wire bonding electrode 3 and the auxiliary electrode 4 is composed of a metal multilayer film like the p-side electrode 6, and is, for example, close to the nitride semiconductor layer 2 side. In order, it has a multilayer structure of Ni (film thickness 100 mm), Al (film thickness 1000 mm), Ti (film thickness 1000 mm), Pt (film thickness 2000 mm), and Au (film thickness 3000 mm). The conductive fusion layer 7 and the p-side electrode terminal 8 provided on both sides of the conductive substrate 1 are made of, for example, an alloy of Au (70 to 80%) and Sn (20 to 30%) having a film thickness of 2 to 8 μm. Is done.

ｎ側ワイヤボンディング用電極３に、電源の負電極からのリードワイヤーをワイヤボンディングにより接続し、ｐ側電極端子８を放熱体等に接続するとともに電源の正電極に接続して、窒化物半導体層２に電流を流し、発光させる。ｎ側ワイヤボンディング用電極３は、窒化物半導体層２と上下に重ならないように、かつ窒化物半導体層２が形成されている領域と離れた領域に位置しているので、上記ワイヤボンディング時の機械的ストレスや衝撃は、ワイヤボンディング領域下の絶縁層５や導電性基板１に加わるのみで、窒化物半導体層２には加わらず、窒化物半導体層２にはダメージが発生しない。   A lead wire from the negative electrode of the power source is connected to the n-side wire bonding electrode 3 by wire bonding, and the p-side electrode terminal 8 is connected to a radiator or the like and also connected to the positive electrode of the power source, and the nitride semiconductor layer A current is passed through 2 to emit light. The n-side wire bonding electrode 3 is positioned so as not to overlap the nitride semiconductor layer 2 in the vertical direction and away from the region where the nitride semiconductor layer 2 is formed. Mechanical stress and impact are only applied to the insulating layer 5 and the conductive substrate 1 under the wire bonding region, and not applied to the nitride semiconductor layer 2, and no damage is caused to the nitride semiconductor layer 2.

図２は図１の半導体発光素子の製造方法を示す。また、図１と同じ番号を付しているものは、同じ構成を示す。図２（ａ）に示すように、まず、サファイア、ＳｉＣ、ＧａＮ等の成長用基板１０上に、エピタキシャル成長によって分離層９、活性層を含む窒化物半導体層２の順に成長させ、その上にｐ側電極６を全面に形成する。   FIG. 2 shows a method for manufacturing the semiconductor light emitting device of FIG. Moreover, what attaches | subjects the same number as FIG. 1 shows the same structure. As shown in FIG. 2A, first, on the growth substrate 10 made of sapphire, SiC, GaN or the like, a separation layer 9 and a nitride semiconductor layer 2 including an active layer are grown in this order by epitaxial growth, and p is formed thereon. The side electrode 6 is formed on the entire surface.

次に、図２（ｂ）に示すように、接着面にＡｕ−Ｓｎ合金等の導電性融着層７、対面にｐ側電極端子８を形成した導電性基板１と図２（ａ）において形成した多層基板とを融着する。図２（ｃ）に示すように、例えばレーザリフトオフ（ＬＬＯ）の方法を用い、分離層９で吸収されるレーザ光を分離層９全体にスキャンして分離層９を溶かして成長用基板１０を分離する。   Next, as shown in FIG. 2 (b), in FIG. 2 (a), the conductive substrate 1 in which a conductive fusion layer 7 such as an Au-Sn alloy is formed on the bonding surface and the p-side electrode terminal 8 is formed on the opposite surface. The formed multilayer substrate is fused. As shown in FIG. 2C, for example, a laser lift-off (LLO) method is used to scan the entire separation layer 9 with the laser light absorbed by the separation layer 9 to melt the separation layer 9 to thereby form the growth substrate 10. To separate.

次に、図２（ｄ）のように、窒化物半導体層２をパターニングしてｐ側電極６が露出する領域を形成する。その後、図２（ｅ）のように、ｐ側電極６が露出しているワイヤボンディング領域から窒化物半導体層２の一部に絶縁層５をパターン形成する。絶縁層５をパターン形成するときには、図のように、窒化物半導体層２の端部に絶縁層５が一部上下に重なるように形成しておく。仮に、窒化物半導体層２と絶縁層５を並べるようにして敷き詰めた場合には、窒化物半導体層２と絶縁層５との間に隙間が生じる場合があり、この隙間にｎ側電極材料が入り込んでｐ側電極と短絡することがあるので、このようなトラブルを防止するためである。最後にｎ側ワイヤボンディング用電極３及び補助電極４を形成する。そしてワイヤボンディング接続を行った状態を示すのが、Ａｕワイヤボンド１１である。   Next, as shown in FIG. 2D, the nitride semiconductor layer 2 is patterned to form a region where the p-side electrode 6 is exposed. Thereafter, as shown in FIG. 2E, the insulating layer 5 is patterned on a part of the nitride semiconductor layer 2 from the wire bonding region where the p-side electrode 6 is exposed. When patterning the insulating layer 5, the insulating layer 5 is formed so as to partially overlap the end of the nitride semiconductor layer 2 as shown in the figure. If the nitride semiconductor layer 2 and the insulating layer 5 are laid side by side, a gap may be formed between the nitride semiconductor layer 2 and the insulating layer 5, and the n-side electrode material is formed in this gap. This is to prevent such trouble because it may enter and short-circuit with the p-side electrode. Finally, the n-side wire bonding electrode 3 and the auxiliary electrode 4 are formed. And it is Au wire bond 11 which shows the state which performed wire bonding connection.

次に、図３に図２とは別の製造方法を示す。また、図１、２と同じ番号を付しているものは、同じ構成を示す。図３（ａ）に示すように、まず、サファイア、ＳｉＣ、ＧａＮ等の成長用基板１０上に、エピタキシャル成長によって分離層９、活性層を含む窒化物半導体層２の順に成長させ、その上にｐ側電極６を全面に形成する。その後、図３（ｂ）に示すように、ｐ側電極６と窒化物半導体層２をパターニングして分離層９が露出する領域を形成する。   Next, FIG. 3 shows a manufacturing method different from FIG. Moreover, what attached | subjected the same number as FIG.1, 2 shows the same structure. As shown in FIG. 3A, first, on the growth substrate 10 made of sapphire, SiC, GaN or the like, a separation layer 9 and a nitride semiconductor layer 2 including an active layer are grown in this order by epitaxial growth, and p is formed thereon. The side electrode 6 is formed on the entire surface. Thereafter, as shown in FIG. 3B, the p-side electrode 6 and the nitride semiconductor layer 2 are patterned to form a region where the separation layer 9 is exposed.

次に図３（ｃ）に示すように、接着面にＡｕ−Ｓｎ合金等の導電性融着層７、対面にｐ側端子８を形成した導電性基板１と図３（ｂ）において形成した多層基板とを融着する。そして図３（ｄ）に示すように、例えば分離層９で吸収されるレーザ光を分離層９全体にスキャンして分離層９を溶かして成長基板を分離する。   Next, as shown in FIG. 3 (c), the conductive substrate 1 in which a conductive fusion layer 7 such as an Au—Sn alloy is formed on the bonding surface and the p-side terminal 8 is formed on the opposite surface is formed in FIG. 3 (b). A multilayer substrate is fused. Then, as shown in FIG. 3D, for example, laser light absorbed by the separation layer 9 is scanned over the entire separation layer 9 to melt the separation layer 9 and separate the growth substrate.

図３（ｅ）に示すように、導電性融着層７が露出しているワイヤボンディング領域から窒化物半導体層２の一部に絶縁層５をパターン形成する。最後にｎ側ワイヤボンディング用電極３及び補助電極４をパターン形成する。そしてワイヤボンディング接続を行った状態を示すのが、Ａｕワイヤボンド１１である。   As shown in FIG. 3E, the insulating layer 5 is patterned on a part of the nitride semiconductor layer 2 from the wire bonding region where the conductive fusion layer 7 is exposed. Finally, the n-side wire bonding electrode 3 and the auxiliary electrode 4 are patterned. And it is Au wire bond 11 which shows the state which performed wire bonding connection.

図３の製造方法は、図２の製造方法と異なり、成長用基板１０上に半導体層を堆積させた状態でエッチングによるパターニングを行っている。この成長用基板１０は半導体発光素子には用いられない部分なので、エッチングの際に、耐腐食性や堅さを考慮する必要がないが、図２では導電性基板１にこの制約が発生する。   The manufacturing method of FIG. 3 is different from the manufacturing method of FIG. 2 in that patterning is performed by etching in a state where a semiconductor layer is deposited on the growth substrate 10. Since this growth substrate 10 is a portion that is not used in a semiconductor light emitting device, it is not necessary to consider corrosion resistance and rigidity during etching, but this restriction occurs in the conductive substrate 1 in FIG.

また、エッチングによって窒化物半導体層２をパターニングした場合、ｐ側電極６の露出している領域には、エッチングの影響で表面に凹凸が生じるが、図３では、エッチングによるパターニングを、成長用基板１０上で済ませておき、その後窒化物半導体層２とｐ側電極６とを導電性基板１に貼り替えるようにしているので、導電性融着層７表面の平坦性に影響を与える工程がなくなり、導電性融着層７表面の平坦性が良好になるとともに、その後形成する絶縁層５とｎ側ワイヤボンディング用電極３及び補助電極４の表面の平坦性も向上する。   In addition, when the nitride semiconductor layer 2 is patterned by etching, the surface of the exposed region of the p-side electrode 6 is uneven due to the etching. In FIG. 10, and the nitride semiconductor layer 2 and the p-side electrode 6 are then attached to the conductive substrate 1, so there is no step affecting the flatness of the surface of the conductive fusion layer 7. The flatness of the surface of the conductive fusion layer 7 is improved, and the flatness of the surfaces of the insulating layer 5, the n-side wire bonding electrode 3 and the auxiliary electrode 4 to be formed thereafter is also improved.

次に、図２、図３以外の製造方法について以下に説明する。成長基板の分離をレーザリフトオフ等により行わないのが特徴である。絶縁性の成長用基板１０上に、エピタキシャル成長によって、活性層を含む窒化物半導体層２を成長させ、その上にｐ側電極６を全面に形成する。これは図２（ａ）で分離層９がない構成に相当する。その後、図２（ｂ）と同様に形成する。次に、成長用基板１０を研磨して厚み１０μｍ以下の薄膜化した成長用基板にする。   Next, manufacturing methods other than those shown in FIGS. 2 and 3 will be described below. The growth substrate is not separated by laser lift-off or the like. A nitride semiconductor layer 2 including an active layer is grown on the insulating growth substrate 10 by epitaxial growth, and a p-side electrode 6 is formed on the entire surface thereof. This corresponds to a configuration without the separation layer 9 in FIG. Then, it forms similarly to FIG.2 (b). Next, the growth substrate 10 is polished to form a growth substrate having a thickness of 10 μm or less.

さらに、図１に示すような補助電極４のパターンと窒化物半導体層２とのコンタクト形成のため、補助電極４の下に該当する領域について薄膜化した成長用基板をパターニングで除去する。そしてｐ側電極６が露出しているワイヤボンディング領域から窒化物半導体層２の一部に絶縁層５をパターン形成する。最後にｎ側ワイヤボンディング用電極３及び補助電極４をパターン形成する。   Further, in order to form a contact between the pattern of the auxiliary electrode 4 and the nitride semiconductor layer 2 as shown in FIG. 1, the growth substrate thinned in a corresponding region under the auxiliary electrode 4 is removed by patterning. Then, the insulating layer 5 is patterned on a part of the nitride semiconductor layer 2 from the wire bonding region where the p-side electrode 6 is exposed. Finally, the n-side wire bonding electrode 3 and the auxiliary electrode 4 are patterned.

上記実施例では、成長用基板のレーザ分離を行わないため、分離層のエピタキシャル成長が不要となり、高品質な窒化物半導体層を成長できる効果がある。また必要に応じて薄膜化した成長用基板表面を凹凸加工して光取り出し効率を向上させることもできる。
In the above embodiment, since the growth substrate is not subjected to laser separation, there is no need for epitaxial growth of the separation layer, and it is possible to grow a high-quality nitride semiconductor layer. Further, if necessary, the surface of the growth substrate that has been thinned can be processed to be uneven, thereby improving the light extraction efficiency.

本発明の半導体発光素子の構造を示す図である。It is a figure which shows the structure of the semiconductor light-emitting device of this invention. 本発明の半導体発光素子における製造方法を示す図である。It is a figure which shows the manufacturing method in the semiconductor light-emitting device of this invention. 本発明の半導体発光素子における他の製造方法を示す図である。It is a figure which shows the other manufacturing method in the semiconductor light-emitting device of this invention. 従来の半導体発光素子の構造を示す図である。It is a figure which shows the structure of the conventional semiconductor light-emitting device.

符号の説明Explanation of symbols

１ 導電性基板
２ 窒化物半導体層
３ ｎ側ワイヤボンディング用電極
４ 補助電極
５ 絶縁層
６ ｐ側電極
７ 導電性融着層
８ ｐ側電極端子
９ 分離層
１０ 成長用基板
DESCRIPTION OF SYMBOLS 1 Conductive substrate 2 Nitride semiconductor layer 3 N side wire bonding electrode 4 Auxiliary electrode 5 Insulating layer 6 P side electrode 7 Conductive fusion layer 8 P side electrode terminal 9 Separation layer 10 Growth substrate

Claims (5)

導電性基板上に、少なくとも、第１電極、発光領域を含む半導体発光層、第２電極が順に積層され、前記第２電極の一部がワイヤボンディング用電極を構成している半導体発光素子において、前記ワイヤボンディング用電極を前記半導体発光層と上下に重ならないように、半導体発光層が形成されている領域から分離した領域に配置したことを特徴とする半導体発光素子。   In a semiconductor light emitting device in which at least a first electrode, a semiconductor light emitting layer including a light emitting region, and a second electrode are sequentially stacked on a conductive substrate, and a part of the second electrode constitutes a wire bonding electrode. A semiconductor light emitting element, wherein the wire bonding electrode is disposed in a region separated from a region where a semiconductor light emitting layer is formed so as not to overlap the semiconductor light emitting layer. 前記ワイヤボンディング用電極と前記半導体発光層との間には電気的絶縁層が形成されていることを特徴とする請求項１記載の半導体発光素子。   2. The semiconductor light emitting device according to claim 1, wherein an electrically insulating layer is formed between the wire bonding electrode and the semiconductor light emitting layer. 前記電気的絶縁層は、前記半導体発光層の一部に重なるようにして半導体発光層の上側に形成されていることを特徴とする請求項２記載の半導体発光素子。   3. The semiconductor light emitting element according to claim 2, wherein the electrically insulating layer is formed above the semiconductor light emitting layer so as to overlap a part of the semiconductor light emitting layer. 前記第１電極と導電性基板とは電気的に接続されており、電気的に接続された面と反対側の面は外部接続端子となっていることを特徴とする請求項１〜請求項３のいずれか１項に記載の半導体発光素子。   4. The first electrode and the conductive substrate are electrically connected, and a surface opposite to the electrically connected surface is an external connection terminal. The semiconductor light-emitting device according to any one of the above. 成長用基板に発光領域を含む半導体発光層、第１電極の順に成長させ、導電性基板に前記半導体発光層、第１電極を貼り替えた後、前記半導体発光層の上に第２電極が積層されるとともに、該第２電極の一部を構成するワイヤボンディング用電極が前記半導体発光層と上下に重ならないように、半導体発光層が形成されている領域から分離した領域に設けられる半導体発光素子の製造方法において、成長用基板上で前記半導体発光層、第１電極のパターニングを行っておくことを特徴とする半導体発光素子の製造方法。
A semiconductor light-emitting layer including a light-emitting region is grown on a growth substrate and a first electrode in this order. After the semiconductor light-emitting layer and the first electrode are pasted on a conductive substrate, a second electrode is stacked on the semiconductor light-emitting layer. And a semiconductor light emitting device provided in a region separated from the region where the semiconductor light emitting layer is formed so that a wire bonding electrode constituting a part of the second electrode does not overlap the semiconductor light emitting layer vertically In the method of manufacturing a semiconductor light emitting device, the semiconductor light emitting layer and the first electrode are patterned on a growth substrate.
JP2005285015A 2005-09-29 2005-09-29 Semiconductor light emitting element and method of manufacturing the same Pending JP2007096090A (en)

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