JP4799041B2 - Nitride semiconductor device manufacturing method - Google Patents

Nitride semiconductor device manufacturing method Download PDF

Info

Publication number
JP4799041B2
JP4799041B2 JP2005133462A JP2005133462A JP4799041B2 JP 4799041 B2 JP4799041 B2 JP 4799041B2 JP 2005133462 A JP2005133462 A JP 2005133462A JP 2005133462 A JP2005133462 A JP 2005133462A JP 4799041 B2 JP4799041 B2 JP 4799041B2
Authority
JP
Japan
Prior art keywords
nitride
layer
based semiconductor
substrate
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2005133462A
Other languages
Japanese (ja)
Other versions
JP2006310657A (en
Inventor
三郎 中島
康光 久納
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2005133462A priority Critical patent/JP4799041B2/en
Publication of JP2006310657A publication Critical patent/JP2006310657A/en
Application granted granted Critical
Publication of JP4799041B2 publication Critical patent/JP4799041B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

本発明は、窒化物系半導体素子の製造方法に関する。 The present invention relates to a method for manufacturing a nitride compound-based semiconductor device.

近年、GaN、InN、AlN等の窒化物系半導体素子は、青色や緑色の発光ダイオード(LED)や青紫半導体レーザなどの発光素子、高温動作可能な高速トランジスタなどの電子デバイスの材料として盛んに用いられている。この窒化物系半導体素子は、一般に、バルク単結晶の製造が困難なことから、サファイアやSiCなどの異種基板(成長基板)上に、ヘテロエピキャシタル成長法を用いて形成される(例えば、特許文献1及び特許文献2参照。)。   In recent years, nitride-based semiconductor elements such as GaN, InN, and AlN have been actively used as materials for electronic devices such as light emitting elements such as blue and green light emitting diodes (LEDs) and blue-violet semiconductor lasers, and high-speed transistors that can operate at high temperatures. It has been. Since this nitride-based semiconductor element is generally difficult to manufacture a bulk single crystal, it is formed on a heterogeneous substrate (growth substrate) such as sapphire or SiC by using a hetero-epitaxial growth method (for example, (See Patent Document 1 and Patent Document 2.)

具体的には、窒化物系半導体素子は、以下に示すような工程で製造される。   Specifically, the nitride-based semiconductor element is manufactured by the following process.

まず、成長基板上に、GaNなどからなる窒化物系半導体素子層を順次エピキャシタル成長させ、ついで真空蒸着法により電極を形成する。一方、Au−Sn合金、共晶半田等からなる半田層を形成した支持基板を準備し、半田層を介して窒化物系半導体素子層と支持基板とを接合する。次に、窒化物系半導体素子層界面付近の半導体素子層を溶融することなどによって、支持基板及び窒化物系半導体素子層から成長基板を除去する。   First, a nitride semiconductor element layer made of GaN or the like is sequentially epitaxially grown on a growth substrate, and then an electrode is formed by a vacuum deposition method. On the other hand, a support substrate on which a solder layer made of Au—Sn alloy, eutectic solder or the like is formed is prepared, and the nitride-based semiconductor element layer and the support substrate are bonded via the solder layer. Next, the growth substrate is removed from the support substrate and the nitride-based semiconductor element layer by, for example, melting the semiconductor element layer near the nitride-based semiconductor element layer interface.

このようにして、図9に示すように、n側GaN層2、p側GaN層3上に、p側電極4、p側パッド電極5が形成され、n側GaN層2上に、n側パッド電極9が形成され、半田層7を介して支持基板6と接合された窒化物系半導体素子が得られる。
特開平11−30780号公報 特開2000−277804号公報
In this way, as shown in FIG. 9, the p-side electrode 4 and the p-side pad electrode 5 are formed on the n-side GaN layer 2 and the p-side GaN layer 3, and the n-side GaN layer 2 has the n-side A nitride-based semiconductor element in which the pad electrode 9 is formed and bonded to the support substrate 6 through the solder layer 7 is obtained.
Japanese Patent Laid-Open No. 11-30780 JP 2000-277804 A

上述したような、支持基板の接合、成長基板の分離除去を行った場合、図9に示すように、p側GaN層3のメサエッチ深さ(例えば、1〜3μm)と、p側パッド電極5の厚み(例えば、1〜3μm)により、窒化物系半導体層と半田層7との間に空洞部11が生じる。支持基板6上には、窒化物系半導体素子層からなる複数の発光素子が形成されるが、この空洞部11は、複数の発光素子毎に分割する際のスクライブ位置(図9のP部分)にあたることなる。通常、発光素子を形成する窒化物系半導体素子層(図9のn側GaN層2、p側GaN層3)は、0.3〜10μm程度と薄いため、ダイヤモンドポイントやダイシングソーによるスクライブ時の圧力によって、窒化物系半導体素子層が撓み、スクライブラインから発光領域に向かってクラックが入り、歩留まりを低下させる場合があった。   When the support substrate is bonded and the growth substrate is separated and removed as described above, the mesa etch depth (for example, 1 to 3 μm) of the p-side GaN layer 3 and the p-side pad electrode 5 as shown in FIG. Due to the thickness (for example, 1 to 3 μm), the cavity 11 is generated between the nitride-based semiconductor layer and the solder layer 7. A plurality of light emitting elements composed of nitride-based semiconductor element layers are formed on the support substrate 6, and the cavities 11 are scribed when dividing each of the plurality of light emitting elements (P portion in FIG. 9). It will be hit. Usually, the nitride-based semiconductor element layers (n-side GaN layer 2 and p-side GaN layer 3 in FIG. 9) forming the light-emitting element are as thin as about 0.3 to 10 μm. In some cases, the nitride-based semiconductor element layer is bent by the pressure and cracks are generated from the scribe line toward the light emitting region, thereby reducing the yield.

そこで、本発明は、上記の課題に鑑み、複数の発光素子毎に分割する際、発光領域にまでクラックが入らず、歩留まりの低下を抑制する窒化物系半導体素子の製造方法を提供することを目的とする。 The present invention has been made in view of the above problems, when dividing into each of a plurality of light emitting elements, cracks without entering to the light emitting region, to provide a method for manufacturing a nitride compound-based semiconductor device that to suppress the reduction in yield With the goal.

上記目的を達成するため、本発明の第1の特徴は、成長基板上に少なくとも1層以上の窒化物系半導体素子層からなる複数の発光素子を形成する工程と、窒化物系半導体素子層上に支持基板を接合する工程と、接合された窒化物系半導体素子層及び支持基板から成長基板を除去する工程とを備える窒化物系半導体素子の製造方法であって、複数の発光素子の分割領域にあたる窒化物系半導体素子層と支持基板との間の空洞部に、樹脂充填する工程を有する窒化物系半導体素子の製造方法であることを要旨とする。 In order to achieve the above object, a first feature of the present invention is that a plurality of light-emitting elements comprising at least one nitride-based semiconductor element layer are formed on a growth substrate, and a nitride-based semiconductor element layer is formed. and bonding a supporting substrate, a manufacturing method for a nitride semiconductor device and a step of removing the growth substrate from the bonded nitride-based semiconductor element layer and the support substrate, the divided regions of the plurality of light emitting elements corresponding to the cavity between the supporting substrate a nitride-based semiconductor element layer, and summarized in that a method of manufacturing a nitride-based semiconductor device having a step of filling the resin.

第1の特徴に係る窒化物系半導体素子の製造方法によると、スクライブ位置となる空洞部に樹脂が充填されているため、複数の発光素子毎に分割する際、発光領域にまでクラックが入らず、歩留まりの低下を抑制することができる。 According to the method for manufacturing a nitride-based semiconductor device according to the first feature, since the hollow portion serving as the scribe position is filled with the resin, no cracks are formed in the light emitting region when dividing each light emitting device. , Yield reduction can be suppressed.

又、第1の特徴に係る窒化物系半導体素子の製造方法において、樹脂は、熱硬化性樹脂であることが好ましい。又、樹脂の粘度は、25℃において100cp以下であることが好ましい In the method for manufacturing a nitride semiconductor device according to the first feature, the resin is preferably a thermosetting resin. Further, the viscosity of the resin, preferably not more than 100cp at 25 ° C..

発明によると、複数の発光素子毎に分割する際、発光領域にまでクラックが入らず、歩留まりの低下を抑制する窒化物系半導体素子の製造方法を提供することができる。 According to the present invention, when dividing into each of a plurality of light emitting elements, cracks without entering to the light emitting region, it is possible to provide a manufacturing method of the nitride compound-based semiconductor device that to suppress the decrease in yield.

次に、図面を参照して、本発明の実施の形態を説明する。以下の図面の記載において、同一又は類似の部分には、同一又は類似の符号を付している。ただし、図面は模式的なものであり、各寸法の比率等は現実のものとは異なることに留意すべきである。従って、具体的な寸法等は以下の説明を参酌して判断すべきものである。又、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることは勿論である。 Next, with reference to the accompanying drawings, illustrating the implementation of the embodiment of the present invention. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and ratios of dimensions and the like are different from actual ones. Accordingly, specific dimensions and the like should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

(第1の実施の形態)
第1の実施の形態では、成長基板上に少なくとも1層以上の窒化物系半導体素子層からなる複数の発光素子を形成する工程と、窒化物系半導体素子層上に支持基板を接合する工程と、接合された窒化物系半導体素子層及び支持基板から成長基板を除去する工程とによって製造され、複数の発光素子の分割領域にあたる窒化物系半導体素子層と支持基板との間の空洞部に、樹脂が充填されている窒化物系半導体素子について説明する。
(First embodiment)
In the first embodiment, a step of forming a plurality of light-emitting elements composed of at least one nitride-based semiconductor element layer on a growth substrate, and a step of bonding a support substrate on the nitride-based semiconductor element layer And a step of removing the growth substrate from the bonded nitride-based semiconductor element layer and the support substrate, and in a cavity between the nitride-based semiconductor element layer and the support substrate, which is a divided region of the plurality of light-emitting elements, A nitride semiconductor device filled with resin will be described.

第1の実施の形態に係る窒化物系半導体素子は、図1に示すように、n側GaN層2、p側GaN層3上に、p側電極4、p側パッド電極5が形成され、n側GaN層2上に、n側パッド電極9が形成され、半田層7を介して支持基板6と接合されている。   In the nitride-based semiconductor device according to the first embodiment, as shown in FIG. 1, a p-side electrode 4 and a p-side pad electrode 5 are formed on an n-side GaN layer 2 and a p-side GaN layer 3, An n-side pad electrode 9 is formed on the n-side GaN layer 2 and is joined to the support substrate 6 via the solder layer 7.

又、複数の発光素子の分割領域(図1のP部分)にあたる窒化物系半導体素子層(n側GaN層2)と支持基板6との間の空洞部に、エポキシ樹脂等の熱硬化性樹脂10が充填されている。この熱硬化性樹脂は、作業性に富み、絶縁性のものであればよい。したがって、25℃での粘度が100cp(centi-poise)以下であることが好ましい。又、強度保持のため、ショアー硬度が75以上であることが好ましい。このような熱硬化性樹脂として、例えば、日本ペルノックス社製のME−514/HV−514やME−550/HV−550などを用いることができる。   Further, a thermosetting resin such as an epoxy resin is formed in a cavity between the nitride semiconductor element layer (n-side GaN layer 2) corresponding to the divided region (P portion in FIG. 1) of the plurality of light emitting elements and the support substrate 6. 10 is filled. The thermosetting resin may have any workability and an insulating property. Therefore, the viscosity at 25 ° C. is preferably 100 cp (centi-poise) or less. In order to maintain strength, the Shore hardness is preferably 75 or more. As such a thermosetting resin, for example, ME-514 / HV-514 or ME-550 / HV-550 manufactured by Nippon Pernox may be used.

そして、第1の実施の形態に係る窒化物系半導体素子は、図2に示すように、樹脂10が充填されている領域で、ダイヤモンドポイント14やダイシングソーにより、複数の発光素子毎に分割される。   The nitride semiconductor device according to the first embodiment is divided into a plurality of light emitting devices by a diamond point 14 or a dicing saw in a region filled with the resin 10 as shown in FIG. The

次に、第1の実施の形態に係る窒化物系半導体素子の製造方法について、図3を用いて説明する。   Next, a method for manufacturing the nitride semiconductor device according to the first embodiment will be described with reference to FIG.

まず、図3(a)に示すように、MOCVD(Metal Organic Chemical Vapor Deposition)法を用いて、サファイア基板(成長基板)13上に、n側GaN層2、p側GaN層3を形成する。具体的には、バッファ層、n型コンタクト層、n型クラッド層、光活性層、p型キャップ層、p型クラッド層及びp型コンタクト層を順次成長させる。次に、フォトリソグラフィ技術により、n型クラッド層まで格子状にメサエッチングして溝を形成し、p型コンタクト層から光活性層までを発光素子毎に分離する。ついで、p側電極4を形成し、p側パッド電極5を形成する箇所にコンタクトホールが開いた、SiO2からな
る絶縁膜8を形成し、表面がAuからなるp側パッド電極5を形成する。
First, as shown in FIG. 3A, an n-side GaN layer 2 and a p-side GaN layer 3 are formed on a sapphire substrate (growth substrate) 13 by MOCVD (Metal Organic Chemical Vapor Deposition). Specifically, a buffer layer, an n-type contact layer, an n-type cladding layer, a photoactive layer, a p-type cap layer, a p-type cladding layer, and a p-type contact layer are sequentially grown. Next, a groove is formed by mesa etching in a lattice shape up to the n-type cladding layer by photolithography, and the p-type contact layer to the photoactive layer are separated for each light emitting element. Next, the p-side electrode 4 is formed, the insulating film 8 made of SiO 2 having a contact hole is formed at the place where the p-side pad electrode 5 is to be formed, and the p-side pad electrode 5 whose surface is made of Au is formed. .

一方、支持基板6として、熱膨張率が純銅に比べて小さく、かつ、熱伝導と電気抵抗が小さい材料である、銅と酸化銅粒子の焼結体基板を準備する。支持基板6は、この材質に限らず、タングステン等の金属及び合金や、へき開性を有するSi、SiC、GaAs基板等の半導体基板も使用可能である。支持基板6は、後の樹脂充填工程のために、成長基板13端面よりも1〜5mm程度大きいものを準備することが好ましい。そして、支持基板6上に、Au−Sn合金、共晶半田等からなる半田層7を形成する。   On the other hand, as the support substrate 6, a sintered body substrate of copper and copper oxide particles, which is a material having a thermal expansion coefficient smaller than that of pure copper and having low heat conduction and electrical resistance, is prepared. The support substrate 6 is not limited to this material, and a metal and an alloy such as tungsten, or a semiconductor substrate such as a cleaved Si, SiC, or GaAs substrate can be used. It is preferable to prepare a support substrate 6 that is about 1 to 5 mm larger than the end face of the growth substrate 13 for a subsequent resin filling step. Then, a solder layer 7 made of Au—Sn alloy, eutectic solder or the like is formed on the support substrate 6.

次に、図3(b)に示すように、複数の発光素子が形成された成長基板13の窒化物系半導体素子層面と、支持基板6の半田層7とを熱圧着により、接合する。   Next, as shown in FIG. 3B, the nitride-based semiconductor element layer surface of the growth substrate 13 on which the plurality of light emitting elements are formed and the solder layer 7 of the support substrate 6 are joined by thermocompression bonding.

次に、図3(c)に示すように、成長基板13と窒化物系半導体素子層間で基板分離を行い、窒化物系半導体素子層(n側GaN層2、p側GaN層3)と支持基板6とが半田層7で接着された積層基板を得る。基板分離は、成長基板13の材質に応じて、研磨、ドライエッチ、ウェットエッチ、レーザリフトオフ法等を用いる。   Next, as shown in FIG. 3C, the substrate is separated between the growth substrate 13 and the nitride-based semiconductor element layer, and the nitride-based semiconductor element layer (the n-side GaN layer 2 and the p-side GaN layer 3) is supported. A laminated substrate is obtained in which the substrate 6 is bonded with the solder layer 7. For substrate separation, polishing, dry etching, wet etching, a laser lift-off method, or the like is used according to the material of the growth substrate 13.

次に、接合界面に格子状に発生している空洞部11に、エポキシ樹脂等の熱硬化性樹脂を、毛細管現象を利用して侵入させる。成長基板13よりも一回り大きい面積を有する支持基板6を用いると、窒化物系半導体素子層よりも突出した支持基板6の端面に熱硬化性樹脂を配置することにより、空洞部11に熱硬化性樹脂を侵入させることができる。   Next, a thermosetting resin such as an epoxy resin is made to enter the cavity 11 generated in a lattice shape at the bonding interface by utilizing a capillary phenomenon. When the support substrate 6 having a slightly larger area than the growth substrate 13 is used, a thermosetting resin is disposed on the end surface of the support substrate 6 protruding from the nitride-based semiconductor element layer, thereby thermosetting the cavity 11. A functional resin can be made to enter.

このようにして、図1に示す窒化物系半導体素子を得ることができる。   In this way, the nitride semiconductor device shown in FIG. 1 can be obtained.

第1の実施の形態に係る窒化物系半導体素子によると、空洞部11に樹脂が充填されることにより、ダイヤモンドポイント14やダイシングソーによって、複数の発光素子毎に分割する際、機械的圧力によって発光素子を形成する窒化物系半導体素子層が撓まないので、スクライブラインから発光領域に向かって発生するクラックを防止することができる。この結果、スクライブにおける歩留まりの低下を抑制することができる。本発明は、特に、窒化物系半導体素子層が1〜50μm程度と薄い場合に有効である。   According to the nitride-based semiconductor device according to the first embodiment, when the cavity portion 11 is filled with resin, when divided into a plurality of light emitting devices by the diamond point 14 or the dicing saw, due to the mechanical pressure. Since the nitride-based semiconductor element layer that forms the light-emitting element does not bend, cracks that occur from the scribe line toward the light-emitting region can be prevented. As a result, it is possible to suppress a decrease in yield in scribing. The present invention is particularly effective when the nitride-based semiconductor element layer is as thin as about 1 to 50 μm.

又、数μmの厚さの薄膜窒化物系半導体素子層(図1のn側GaN層2)が浮かずに固定されているため、発光素子のハンドリング時に窒化物系半導体素子層が欠けることを防止することができる。   Further, since the thin film nitride-based semiconductor element layer (n-side GaN layer 2 in FIG. 1) having a thickness of several μm is fixed without being floated, the nitride-based semiconductor element layer is missing when the light-emitting element is handled. Can be prevented.

更に、空洞部に樹脂10が充填されているため、図4に示すように、Au線15などによるワイヤボンディング時の加圧により窒化物系半導体素子層が割れることがなく、n側パッド電極9を発光素子端部に設けることができる。このように、n側パッド電極9を発光素子端部に設けると、表面からの発光が遮断される割合が減少し、光取り出し効率が向上する。   Further, since the cavity 10 is filled with the resin 10, as shown in FIG. 4, the nitride-based semiconductor element layer is not broken by the pressurization at the time of wire bonding with the Au wire 15 or the like, and the n-side pad electrode 9 is not broken. Can be provided at the end of the light emitting element. Thus, when the n-side pad electrode 9 is provided at the end of the light emitting element, the ratio of light emission from the surface is reduced, and the light extraction efficiency is improved.

(第2の参考の形態)
第2の参考の形態では、成長基板上に少なくとも1層以上の窒化物系半導体素子層からなる複数の発光素子を形成する工程と、窒化物系半導体素子層上に支持基板を接合する工程と、接合された窒化物系半導体素子層及び支持基板から成長基板を除去する工程とによって製造され、複数の発光素子の分割領域にあたる窒化物系半導体素子層と支持基板との間の空洞部に、異常成長した窒化物系半導体素子層が配置されている窒化物系半導体素子について、説明する。
(Second reference form)
In the second reference embodiment, a step of forming a plurality of light-emitting elements composed of at least one nitride-based semiconductor element layer on a growth substrate, and a step of bonding a support substrate on the nitride-based semiconductor element layer, And a step of removing the growth substrate from the bonded nitride-based semiconductor element layer and the support substrate, and in a cavity between the nitride-based semiconductor element layer and the support substrate, which is a divided region of the plurality of light-emitting elements, A nitride semiconductor device in which an abnormally grown nitride semiconductor device layer is disposed will be described.

第2の参考の形態に係る窒化物系半導体素子は、図5に示すように、n側GaN層2、p側GaN層3上に、p側電極4、p側パッド電極5が形成され、n側GaN層2上に、n側パッド電極9が形成され、半田層7を介して支持基板6と接合されている。 As shown in FIG. 5, the nitride-based semiconductor device according to the second reference form has a p-side electrode 4 and a p-side pad electrode 5 formed on an n-side GaN layer 2 and a p-side GaN layer 3. An n-side pad electrode 9 is formed on the n-side GaN layer 2 and is joined to the support substrate 6 via the solder layer 7.

又、複数の発光素子の分割領域(図5のP部分)にあたる窒化物系半導体素子層(n側GaN層2)と支持基板6との間の空洞部に、n側GaN層2よりも厚膜化し、異常成長した窒化物系半導体素子層12(以下において、「異常成長エピタキシャル層」という。)が配置されている。異常成長エピタキシャル層12の詳細については、後に詳述する。   In addition, the cavity between the nitride-based semiconductor element layer (n-side GaN layer 2) and the support substrate 6 corresponding to the divided region (P portion in FIG. 5) of the plurality of light-emitting elements is thicker than the n-side GaN layer 2. A nitride-based semiconductor element layer 12 (hereinafter referred to as “abnormally grown epitaxial layer”) that has been formed into a film and abnormally grown is disposed. Details of the abnormally grown epitaxial layer 12 will be described later.

そして、第2の参考の形態に係る窒化物系半導体素子は、図6に示すように、異常成長エピタキシャル層12が配置されている領域で、ダイヤモンドポイント14やダイシングソーにより、複数の発光素子毎に分割される。 Then, as shown in FIG. 6, the nitride-based semiconductor device according to the second reference embodiment is a region where the abnormally grown epitaxial layer 12 is disposed, and each of the plurality of light emitting devices is formed by a diamond point 14 or a dicing saw. It is divided into.

次に、第2の参考の形態に係る窒化物系半導体素子の製造方法について、図7及び図8を用いて説明する。図7は、発光素子が2個並んだ平面図、図8は、異常成長エピタキシャル層12付近の拡大断面図である。 Next, a manufacturing method for a nitride semiconductor device according to the second reference embodiment will be described with reference to FIGS. FIG. 7 is a plan view in which two light emitting elements are arranged, and FIG. 8 is an enlarged cross-sectional view in the vicinity of the abnormally grown epitaxial layer 12.

まず、図7及び図8(a)に示すように、GaN基板(成長基板)13上に、TiO2からなる基板分離用薄膜19を形成する。基板分離用薄膜19は、TiO2の他、Al23、SiO2、Si34、Ta25、W、Ti、Pt、Moなどを用いてもよい。基板分離用薄膜19は、成長基板13と窒化物系半導体素子層とを分離する際の分離領域として機能する。例えば、レーザ照射によって、成長基板13を分離する場合、基板分離用薄膜19は、レーザのエネルギーで瞬時に溶解する領域となる。 First, as shown in FIGS. 7 and 8A, a substrate separating thin film 19 made of TiO 2 is formed on a GaN substrate (growth substrate) 13. The substrate separating thin film 19 may use Al 2 O 3 , SiO 2 , Si 3 N 4 , Ta 2 O 5 , W, Ti, Pt, Mo, or the like in addition to TiO 2 . The substrate separating thin film 19 functions as an isolation region for separating the growth substrate 13 and the nitride-based semiconductor element layer. For example, when the growth substrate 13 is separated by laser irradiation, the substrate separating thin film 19 becomes a region that is instantaneously dissolved by the energy of the laser.

GaN基板(成長基板)13上にこのような基板分離用薄膜19を形成し、その上に、GaN層やInGaN層をエピタキシャル成長させると、基板分離用薄膜19が形成された面の端部に近い、GaN基板(成長基板)露出部での成長速度が異常に大きくなる。この原因は、原料ガスが加熱されてできるラジカル種がTiO2上よりもGaN上に付着しやすいため、TiO2パターン上のラジカル種がマイクレーションにより、基板分離用薄膜19端部で供給過剰な状態になり、成長速度が増大するためである。この現象は、いわゆるマスキング効果と呼ばれている。 When such a substrate separating thin film 19 is formed on a GaN substrate (growth substrate) 13 and a GaN layer or an InGaN layer is epitaxially grown thereon, it is close to the end of the surface on which the substrate separating thin film 19 is formed. The growth rate at the exposed portion of the GaN substrate (growth substrate) becomes abnormally large. This is because the radical species generated by heating the source gas are more likely to adhere on GaN than on TiO 2 , so that radical species on the TiO 2 pattern are excessively supplied at the end of the substrate separation thin film 19 due to the microphone. This is because the growth rate increases. This phenomenon is called a so-called masking effect.

又、異常成長の幅は条件にもよるが、一般的には、基板分離用薄膜19の端部から、10μm程度の距離まで異常成長することが観察される。又、異常成長エピタキシャル層12の成長速度は、正常なエピタキシャル成長の2倍以上になることもある。   Although the width of abnormal growth depends on conditions, it is generally observed that abnormal growth occurs from the end of the substrate separating thin film 19 to a distance of about 10 μm. In addition, the growth rate of the abnormally grown epitaxial layer 12 may be twice or more that of normal epitaxial growth.

基板分離用薄膜19の厚さは、成長基板13のGaN結晶構造を反映する程度にすると、基板分離用薄膜19にもエピタキシャル成長が可能なため、1〜5nm程度(例えば、3nm程度)であることが好ましい。又、基板分離用薄膜19の端部から約10μmの異常成長があるため、基板分離用薄膜19の間隔L4を約20μmとすることが好ましい。約20μmとすることにより、基板分離用薄膜19の間隔L4に渡り、異常成長層を形成することができる。又、図7において、基板分離用薄膜19は、330×330μm四方とする。   If the thickness of the substrate separating thin film 19 reflects the GaN crystal structure of the growth substrate 13, the thickness of the substrate separating thin film 19 can be epitaxially grown on the substrate separating thin film 19. Is preferred. Further, since there is an abnormal growth of about 10 μm from the end portion of the substrate separating thin film 19, it is preferable to set the distance L4 between the substrate separating thin films 19 to about 20 μm. By setting the thickness to about 20 μm, an abnormally grown layer can be formed over the interval L4 of the substrate separating thin film 19. In FIG. 7, the thin film 19 for substrate separation is 330 × 330 μm square.

次に、MOCVD法を用いて、GaN基板(成長基板)13及び基板分離用薄膜19上に、n側GaN層2、p側GaN層3を形成する。具体的には、バッファ層、n型コンタクト層、n型クラッド層、光活性層、p型キャップ層、p型クラッド層及びp型コンタクト層を順次成長させる。図8(a)において、基板分離用薄膜19の厚さA4は3nm、n側GaN層2の厚さA3は、1μm、p側GaN層3の厚さA2は1μm、異常成長エピタキシャル層12の厚さA4は2μm程度となる。このように、異常成長エピタキシャル層12の厚さA1は、正常な成長をするn側GaN層2、又はp側GaN層3の厚さA2、A3の2倍となっている。   Next, the n-side GaN layer 2 and the p-side GaN layer 3 are formed on the GaN substrate (growth substrate) 13 and the substrate separating thin film 19 by MOCVD. Specifically, a buffer layer, an n-type contact layer, an n-type cladding layer, a photoactive layer, a p-type cap layer, a p-type cladding layer, and a p-type contact layer are sequentially grown. In FIG. 8A, the thickness A4 of the substrate separating thin film 19 is 3 nm, the thickness A3 of the n-side GaN layer 2 is 1 μm, the thickness A2 of the p-side GaN layer 3 is 1 μm, and the abnormally grown epitaxial layer 12 The thickness A4 is about 2 μm. Thus, the thickness A1 of the abnormally grown epitaxial layer 12 is twice the thicknesses A2 and A3 of the n-side GaN layer 2 or the p-side GaN layer 3 that normally grows.

次に、図8(b)に示すように、フォトリソグラフィ技術により、n型クラッド層まで格子状にメサエッチングして溝18を形成し、p型コンタクト層から光活性層まで発光素子毎に分離する。このとき、異常成長エピタキシャル層12は、メサエッチングせず、そのままの状態として残す。メサエッチングの深さは、p側GaN層3の厚み以上とすることにより、隣接する発光素子と電気的に分離する。ついで、p側電極4(厚さB1:0.4μm)を形成する。このとき、図7に示すように、1つの発光素子に対する、メサエッチングを行った領域の幅L3は、270μm程度であり、メサエッチングを行った領域の間隔L5は、80μm程度である。   Next, as shown in FIG. 8B, by mesa etching to the n-type cladding layer in a lattice shape by photolithography technology, grooves 18 are formed and separated from the p-type contact layer to the photoactive layer for each light emitting element. To do. At this time, the abnormally grown epitaxial layer 12 is left as it is without being mesa-etched. By making the depth of the mesa etching to be equal to or greater than the thickness of the p-side GaN layer 3, it is electrically separated from the adjacent light emitting element. Next, the p-side electrode 4 (thickness B1: 0.4 μm) is formed. At this time, as shown in FIG. 7, the width L3 of the region subjected to mesa etching with respect to one light emitting element is about 270 μm, and the interval L5 between the regions subjected to mesa etching is about 80 μm.

次に、図8(c)に示すように、p側パッド電極5を形成する箇所にコンタクトホールが開いた、SiO2からなる絶縁膜8を形成し、表面がAuからなるp側パッド電極5(厚さC1:1.6μm)を形成する。 Next, as shown in FIG. 8C, an insulating film 8 made of SiO 2 with a contact hole opened is formed at a location where the p-side pad electrode 5 is formed, and the p-side pad electrode 5 whose surface is made of Au. (Thickness C1: 1.6 μm) is formed.

その後の工程は、第1の実施の形態に係る窒化物系半導体素子と同様である。   Subsequent steps are the same as those of the nitride semiconductor device according to the first embodiment.

即ち、支持基板6として、熱膨張率が純銅に比べて小さく、かつ、熱伝導と電気抵抗が小さい材料である、銅と酸化銅粒子の焼結体基板を準備する。そして、支持基板6上に、Au−Sn合金、共晶半田等からなる半田層7を形成する。   That is, as the support substrate 6, a sintered body substrate of copper and copper oxide particles, which is a material having a smaller coefficient of thermal expansion than pure copper and a small thermal conductivity and electrical resistance, is prepared. Then, a solder layer 7 made of Au—Sn alloy, eutectic solder or the like is formed on the support substrate 6.

次に、複数の発光素子が形成された成長基板13の窒化物系半導体素子層面と、支持基板6の半田層7とを熱圧着により、接合する。   Next, the nitride-based semiconductor element layer surface of the growth substrate 13 on which the plurality of light emitting elements are formed and the solder layer 7 of the support substrate 6 are joined by thermocompression bonding.

次に、成長基板13と窒化物系半導体素子層間で基板分離を行い、窒化物系半導体素子層(n側GaN層2、p側GaN層3)と支持基板6とが半田層7で接着された積層基板を得る。基板分離は、成長基板13の材質に応じて、研磨、ドライエッチ、ウェットエッチ、レーザリフトオフ法等を用いる。   Next, the substrate is separated between the growth substrate 13 and the nitride-based semiconductor element layer, and the nitride-based semiconductor element layers (n-side GaN layer 2 and p-side GaN layer 3) and the support substrate 6 are bonded by the solder layer 7. A laminated substrate is obtained. For substrate separation, polishing, dry etching, wet etching, a laser lift-off method, or the like is used according to the material of the growth substrate 13.

このようにして、図5に示す窒化物系半導体素子を得ることができる。   In this manner, the nitride semiconductor device shown in FIG. 5 can be obtained.

第2の参考の形態に係る窒化物系半導体素子によると、空洞部11に異常成長エピタキシャル層12が配置されることにより、ダイヤモンドポイント14やダイシングソーによって、複数の発光素子毎に分割する際、機械的圧力によって発光素子を形成するエピタキシャル層が撓まないので、スクライブラインから発光領域に向かって発生するクラックを防止することができる。この結果、スクライブにおける歩留まりの低下を抑制することができる。 According to the nitride-based semiconductor device according to the second reference embodiment, when the abnormally grown epitaxial layer 12 is disposed in the cavity portion 11, when divided into a plurality of light emitting devices by the diamond point 14 or the dicing saw, Since the epitaxial layer forming the light emitting element is not bent by the mechanical pressure, it is possible to prevent cracks generated from the scribe line toward the light emitting region. As a result, it is possible to suppress a decrease in yield in scribing.

又、第2の参考の形態では、異常成長エピタキシャル層12の高さを調整することにより、p側パッド電極5表面よりも高い位置に、異常成長エピタキシャル層12を形成することも可能である。この場合、支持基板6との接合時に、p側パッド電極5への圧力を低減することができる。 In the second reference embodiment, the abnormally grown epitaxial layer 12 can be formed at a position higher than the surface of the p-side pad electrode 5 by adjusting the height of the abnormally grown epitaxial layer 12. In this case, the pressure on the p-side pad electrode 5 can be reduced at the time of bonding to the support substrate 6.

(その他の実施形態)
本発明は上記の実施形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
(Other embodiments)
Although the present invention has been described according to the above-described embodiments, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

例えば、上記の実施の形態では、主として、窒化物半導体素子層の活性層から放出される光を利用する発光ダイオードや半導体レーザについて例示したが、本発明はこれに限らず、これら発光素子からの放出光を励起光とする蛍光体とを組み合わせた発光素子の製造にも利用可能である。又、窒化物系半導体素子層を有するHEMT(High Electron Mobility Transistor)などの電子デバイス、SAW(Surface Acoustic Wave)デバイス、受光素子への応用が可能である。 For example, in the above embodiment, the light emitting diode and the semiconductor laser that mainly use light emitted from the active layer of the nitride semiconductor element layer are exemplified. However, the present invention is not limited to this, and the light emitting diodes and the semiconductor lasers are not limited thereto. The present invention can also be used in the manufacture of a light emitting device that combines a phosphor that uses emitted light as excitation light. Further, it can be applied to electronic devices such as HEMT (High Electron Mobility Transistor) having a nitride-based semiconductor element layer, SAW (Surface Acoustic Wave) devices, and light receiving elements.

又、上記の実施の形態では、MOCVD法を用いて、窒化物半導体各層を結晶成長させる説明したが、本発明はこれに限らず、HVPE法やガスソースMBE法などを用いて、窒化物半導体各層を結晶成長させてもよい。 In the above embodiment, the nitride semiconductor layers are crystal-grown using the MOCVD method. However, the present invention is not limited to this, and the nitride semiconductor using the HVPE method, the gas source MBE method, or the like. Each layer may be crystal-grown.

又、上記の実施の形態では、GaN、AlGaN、InGaN及びAlNなどからなる層を含む窒化物系半導体素子層を用いたが、本発明はこれに限らず、GaN、AlGaN、InGaN及びAlNからなる層以外の層を含む窒化物系半導体素子層を用いてもよい。又、半導体素子層の形状は、メサ構造、リッジ構造などの電流狭窄造を有するものでもよい。 In the above embodiment, the nitride-based semiconductor element layer including a layer made of GaN, AlGaN, InGaN, and AlN is used. However, the present invention is not limited to this, and is made of GaN, AlGaN, InGaN, and AlN. A nitride-based semiconductor element layer including layers other than the layers may be used. The semiconductor element layer may have a current confinement structure such as a mesa structure or a ridge structure.

又、上記の実施の形態では、窒化物系半導体素子層の成長用基板として、サファイア基板、GaN基板を用いたが、本発明はこれに限らず、窒化物系半導体の成長の可能な基板、例えば、Si、SiC、GaAs、MgO、ZnO、スピネル等が使用可能である。 In the above embodiment, the sapphire substrate and the GaN substrate are used as the growth substrate for the nitride-based semiconductor element layer. However, the present invention is not limited to this, and a substrate on which a nitride-based semiconductor can be grown. For example, Si, SiC, GaAs, MgO, ZnO, spinel, etc. can be used.

又、支持基板材料は、導電性であることが好ましく、第1〜第2の実施の形態において用いた、金属−金属酸化物の複合材料の他、導電性半導体(Si、SiC、GaAs、ZnO等)や、金属あるいは複合金属(Al、Fe−Ni、Cu−W、CU−Mo等)などを用いることができる。一般に、半導体材料よりも金属系材料が機械特性に優れ、割れにくいために、支持基板材料として適している。   The support substrate material is preferably conductive. In addition to the metal-metal oxide composite material used in the first and second embodiments, a conductive semiconductor (Si, SiC, GaAs, ZnO) is used. Etc.), metal or composite metal (Al, Fe-Ni, Cu-W, CU-Mo, etc.) can be used. In general, a metal-based material is superior to a semiconductor material in terms of mechanical characteristics and is not easily cracked, so that it is suitable as a support substrate material.

このように、本発明はここでは記載していない様々な実施形態等を含むことは勿論である。従って、本発明の技術的範囲は上記の説明から妥当な特許請求の範囲に係る発明特定事項によってのみ定められるものである。   As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

第1の実施の形態に係る窒化物系半導体素子の断面図である。1 is a cross-sectional view of a nitride-based semiconductor device according to a first embodiment. 図1において、複数の発光素子間を分離した際の断面図である。In FIG. 1, it is sectional drawing at the time of isolate | separating between some light emitting elements. 第1の実施の形態に係る窒化物系半導体素子の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the nitride type semiconductor element which concerns on 1st Embodiment. 第1の実施の形態に係る窒化物系半導体素子の素子分離後にワイヤボンディングを行った際の断面図である。It is sectional drawing at the time of performing wire bonding after the element isolation | separation of the nitride type semiconductor element which concerns on 1st Embodiment. 第2の参考の形態に係る窒化物系半導体素子の断面図である。It is sectional drawing of the nitride-type semiconductor element which concerns on a 2nd reference form. 図5において、複数の発光素子間を分離した際の断面図である。In FIG. 5, it is sectional drawing at the time of isolate | separating between some light emitting elements. 第2の参考の形態に係る窒化物系半導体素子の上面図である。It is a top view of the nitride-type semiconductor element which concerns on a 2nd reference form. 第2の参考の形態に係る窒化物系半導体素子の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the nitride type semiconductor element which concerns on a 2nd reference form. 従来の窒化物系半導体素子の断面図である。It is sectional drawing of the conventional nitride semiconductor device.

2…n側GaN層
3…p側GaN層
4…p側電極
5…p側パッド電極
6…支持基板
7…半田層
8…絶縁膜
9…n側パッド電極
10…樹脂
11…空洞部
13…異常成長エピタキシャル層
14…ダイヤモンドポイント
2 ... n-side GaN layer 3 ... p-side GaN layer 4 ... p-side electrode 5 ... p-side pad electrode 6 ... support substrate 7 ... solder layer 8 ... insulating film 9 ... n-side pad electrode 10 ... resin 11 ... cavity 13 ... Abnormally grown epitaxial layer 14 ... Diamond point

Claims (4)

成長基板上に少なくとも1層以上の窒化物系半導体素子層からなる複数の発光素子を形成する工程と、前記窒化物系半導体素子層上に半田層を介して支持基板を接合する工程と、接合された前記窒化物系半導体素子層及び前記支持基板から前記成長基板を除去する工程とを備える窒化物系半導体素子の製造方法であって、
前記複数の発光素子の分割領域にあたる前記窒化物系半導体素子層と前記半田層との間の空洞部に、樹脂を充填する工程と、
前記樹脂を充填する工程の後、前記樹脂が充填されている領域で、前記窒化物系半導体素子層と前記支持基板とを、前記半田層及び前記樹脂層と共に、前記複数の発光素子毎に分割する工程とを有することを特徴とする窒化物系半導体素子の製造方法。
Forming a plurality of light emitting elements comprising at least one nitride-based semiconductor element layer on a growth substrate, bonding a support substrate on the nitride-based semiconductor element layer via a solder layer, and bonding And a step of removing the growth substrate from the nitride-based semiconductor device layer and the support substrate, comprising:
Filling a cavity between the nitride-based semiconductor element layer and the solder layer, which is a divided region of the plurality of light-emitting elements, with a resin ;
After the step of filling the resin, in the region filled with the resin, the nitride-based semiconductor element layer and the support substrate are divided into the plurality of light emitting elements together with the solder layer and the resin layer. And a method of manufacturing a nitride-based semiconductor device.
前記樹脂は、熱硬化性樹脂であることを特徴とする請求項1に記載の窒化物系半導体素子の製造方法。   The method for manufacturing a nitride semiconductor device according to claim 1, wherein the resin is a thermosetting resin. 前記樹脂の粘度は、25℃において100cp以下であることを特徴とする請求項1又は2に記載の窒化物系半導体素子の製造方法。   The method for manufacturing a nitride-based semiconductor element according to claim 1 or 2, wherein the viscosity of the resin is 100 cp or less at 25 ° C. 前記樹脂を充填する工程の後、前記樹脂が充填されている領域上にパッド電極を設ける工程を有することを特徴とする請求項1〜のいずれか1項に記載の窒化物系半導体素子の製造方法。
After the step of filling the resin, the nitride-based semiconductor device according to any one of claims 1 to 3, wherein the resin is characterized by having a step of providing a pad electrode on a region is filled Production method.
JP2005133462A 2005-04-28 2005-04-28 Nitride semiconductor device manufacturing method Active JP4799041B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005133462A JP4799041B2 (en) 2005-04-28 2005-04-28 Nitride semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005133462A JP4799041B2 (en) 2005-04-28 2005-04-28 Nitride semiconductor device manufacturing method

Publications (2)

Publication Number Publication Date
JP2006310657A JP2006310657A (en) 2006-11-09
JP4799041B2 true JP4799041B2 (en) 2011-10-19

Family

ID=37477183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005133462A Active JP4799041B2 (en) 2005-04-28 2005-04-28 Nitride semiconductor device manufacturing method

Country Status (1)

Country Link
JP (1) JP4799041B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080303033A1 (en) * 2007-06-05 2008-12-11 Cree, Inc. Formation of nitride-based optoelectronic and electronic device structures on lattice-matched substrates
KR101371511B1 (en) * 2007-10-04 2014-03-11 엘지이노텍 주식회사 Light emitting device having vertical topology
KR101018179B1 (en) 2008-10-16 2011-02-28 삼성엘이디 주식회사 Method for forming pattern of group ? nitride semiconductor substrate and manufaturing method of group ? nitride semiconductor light emitting device
JP2010267813A (en) 2009-05-14 2010-11-25 Toshiba Corp Light emitting device, and method for manufacturing the same
KR101075721B1 (en) * 2009-06-04 2011-10-21 삼성전기주식회사 Solar cell and method manufacturing the same
US8471282B2 (en) 2010-06-07 2013-06-25 Koninklijke Philips Electronics N.V. Passivation for a semiconductor light emitting device
WO2020235074A1 (en) * 2019-05-23 2020-11-26 三菱電機株式会社 Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0567546A (en) * 1991-09-06 1993-03-19 Hitachi Ltd Semiconductor substrate and its manufacture
JPH0685057A (en) * 1992-09-02 1994-03-25 Nisshin Steel Co Ltd Dicing of semiconductor chip
JPH06112527A (en) * 1992-09-28 1994-04-22 Sanyo Electric Co Ltd Silicon carbide light emitting diode device and its manufacture
JP3474917B2 (en) * 1994-04-08 2003-12-08 日本オプネクスト株式会社 Method for manufacturing semiconductor device
JP2002083753A (en) * 2000-09-08 2002-03-22 Sanyo Electric Co Ltd Substrate for nitride-based semiconductor, and nitride- based semiconductor device, and method of manufacturing the same
JP4360071B2 (en) * 2002-05-24 2009-11-11 日亜化学工業株式会社 Manufacturing method of nitride semiconductor laser device
JP4211329B2 (en) * 2002-09-02 2009-01-21 日亜化学工業株式会社 Nitride semiconductor light emitting device and method of manufacturing light emitting device

Also Published As

Publication number Publication date
JP2006310657A (en) 2006-11-09

Similar Documents

Publication Publication Date Title
JP4624131B2 (en) Nitride semiconductor device manufacturing method
JP4295669B2 (en) Manufacturing method of semiconductor device
US9735327B2 (en) Light emitting device and manufacturing method for same
JP4925726B2 (en) Manufacturing method of light emitting diode
JP4817673B2 (en) Nitride semiconductor device fabrication method
JP5016808B2 (en) Nitride semiconductor light emitting device and method for manufacturing nitride semiconductor light emitting device
KR101457209B1 (en) Light emitting device and method for fabricating the same
US20070194327A1 (en) Semiconductor light-emitting device and method for fabricating the same
JP4799041B2 (en) Nitride semiconductor device manufacturing method
KR20040104232A (en) A METHOD OF PRODUCING VERTICAL GaN LIGHT EMITTING DIODES
JP2007067418A (en) Group iii nitride light emitting device having light emitting region with double hetero-structure
JP2006073619A (en) Nitride based compound semiconductor light emitting diode
US8329481B2 (en) Manufacturing method of nitride semiconductor light emitting elements
JP2006303034A (en) Method of manufacturing nitride-based semiconductor device
KR100986963B1 (en) Light emitting device and method for fabricating the same
JP4731180B2 (en) Nitride semiconductor device manufacturing method
JP2007158100A (en) Manufacturing method of nitride semiconductor light-emitting element
KR100886110B1 (en) Supporting substrates for semiconductor light emitting device and method of manufacturing vertical structured semiconductor light emitting device using the supporting substrates
US8143618B2 (en) ZnO based semiconductor device and its manufacture method
JP2007173369A (en) Semiconductor light-emitting element and manufacturing method thereof
JP2007096090A (en) Semiconductor light emitting element and method of manufacturing the same
JP2007273590A (en) Nitride semiconductor element and its manufacturing method
JP6245791B2 (en) Vertical nitride semiconductor device and manufacturing method thereof
JP4570683B2 (en) Nitride compound semiconductor light emitting device manufacturing method
KR102649711B1 (en) Method for manufacturing ultra-thin type semiconductor die

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071018

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20080118

RD13 Notification of appointment of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7433

Effective date: 20080201

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100527

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100601

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100728

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101026

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101224

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110705

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110802

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140812

Year of fee payment: 3

R151 Written notification of patent or utility model registration

Ref document number: 4799041

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140812

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140812

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250