JP2003110148A - Semiconductor light-emitting device - Google Patents

Semiconductor light-emitting device

Info

Publication number
JP2003110148A
JP2003110148A JP2001301834A JP2001301834A JP2003110148A JP 2003110148 A JP2003110148 A JP 2003110148A JP 2001301834 A JP2001301834 A JP 2001301834A JP 2001301834 A JP2001301834 A JP 2001301834A JP 2003110148 A JP2003110148 A JP 2003110148A
Authority
JP
Japan
Prior art keywords
nitride semiconductor
layer
light emitting
electrode
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001301834A
Other languages
Japanese (ja)
Other versions
JP4045767B2 (en
Inventor
Tsuguhisa Hayashi
嗣久 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichia Chemical Industries Ltd
Original Assignee
Nichia Chemical Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichia Chemical Industries Ltd filed Critical Nichia Chemical Industries Ltd
Priority to JP2001301834A priority Critical patent/JP4045767B2/en
Publication of JP2003110148A publication Critical patent/JP2003110148A/en
Application granted granted Critical
Publication of JP4045767B2 publication Critical patent/JP4045767B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting device which exhibits high heat-dissipating efficiency. SOLUTION: The semiconductor light-emitting device has a light-emitting element which is composed of semiconductor elements on a substrate 11 and is mounted on a mount substrate. First bumps 31 which are connected to the side of the mount substrate with electrical continuity and second bumps 32 which are connected to the mount substrate with electrical insulation are provided. When heat is far from the first bumps 31 and is not sufficiently dissipated to the side of the mount substrate, it is efficiently led via the second bumps 32 to the side of the mount substrate. In this way, high heat-dissipating efficiency can be attained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【従来の技術】近年、窒化物半導体を用いて構成された
半導体素子が、青色発光が可能な発光素子として多様な
用途に使用されるようになってきている。
2. Description of the Related Art In recent years, a semiconductor device made of a nitride semiconductor has been used for various purposes as a light emitting device capable of emitting blue light.

【0002】この窒化物半導体を用いて構成された半導
体素子は、通常、サファイア基板上にn型窒化物半導体
層、窒化物半導体活性層、p型窒化物半導体層が順次積
層され、p側の層および窒化物半導体活性層の一部を除
去して露出させたn型窒化物半導体層上にn側オーミッ
ク電極が形成され、p型窒化物半導体層上にp側オーミ
ック電極が形成されている。
A semiconductor device formed by using this nitride semiconductor is usually formed by sequentially stacking an n-type nitride semiconductor layer, a nitride semiconductor active layer, and a p-type nitride semiconductor layer on a sapphire substrate. An n-side ohmic electrode is formed on the exposed n-type nitride semiconductor layer by removing a part of the layer and the nitride semiconductor active layer, and a p-side ohmic electrode is formed on the p-type nitride semiconductor layer. .

【0003】窒化物半導体を用いた従来の発光素子に
は、p型窒化物半導体側からp型窒化物半導体層上に形
成された透光性を有する正電極を介して発光した光を出
力するいわゆる半導体側発光タイプと、透光性を有する
サファイア基板を介して発光した光を出力する基板側発
光タイプに分けられている。
A conventional light emitting device using a nitride semiconductor outputs light emitted from the p-type nitride semiconductor side through a positive electrode having a light-transmitting property formed on the p-type nitride semiconductor layer. It is classified into a so-called semiconductor-side light emitting type and a substrate-side light emitting type that outputs light emitted through a light-transmitting sapphire substrate.

【0004】窒化物半導体発光素子のなかでもとくに窒
化ガリウム系半導体素子では、通常p型窒化物半導体の
抵抗値が比較的高いという特徴を有するために、p型窒
化物半導体層のほぼ全面に透光性のp側のオーミック電
極を形成することにより窒化物半導体活性層全体に電流
が注入されるように構成している。また窒化物半導体発
光素子では、上述のようにn型窒化物半導体上の一部に
n電極を形成し、窒化物半導体層の成長面側にp側電極
とn側電極の両方を形成する必要があるため、窒化物半
導体活性層全体に電流が注入されにくい。そこで、n型
窒化物半導体層の1つの隅部にn側のオーミック電極を
形成し、その1つの隅部と対角を成すp側オーミック電
極上の他の隅部に、外部と電気的に導通するためのp側
のパッド電極を形成し、n側オーミック電極上には、n
側のパッド電極を形成し、窒化物半導体の活性層全体に
電流が注入されやすいようにしている。
Among the nitride semiconductor light emitting devices, the gallium nitride based semiconductor device, in particular, has a characteristic that the resistance value of the p-type nitride semiconductor is generally relatively high, so that the p-type nitride semiconductor layer is almost entirely transparent. A current is injected into the entire nitride semiconductor active layer by forming an optical p-side ohmic electrode. Further, in the nitride semiconductor light emitting device, it is necessary to form the n electrode on a part of the n-type nitride semiconductor as described above and to form both the p side electrode and the n side electrode on the growth surface side of the nitride semiconductor layer. Therefore, it is difficult to inject current into the entire nitride semiconductor active layer. Therefore, an n-side ohmic electrode is formed at one corner of the n-type nitride semiconductor layer, and the other corner on the p-side ohmic electrode that is diagonal to the one corner is electrically connected to the outside. A p-side pad electrode for conduction is formed, and n is formed on the n-side ohmic electrode.
A pad electrode on the side is formed so that current can be easily injected into the entire active layer of the nitride semiconductor.

【0005】すなわち、窒化ガリウム系半導体素子で
は、絶縁性のサファイア基板を用いて構成されているこ
と、およびp型窒化物半導体の抵抗値が比較的大きいと
いう、例えば、GaAs系等の他の半導体素子とは異な
る事情があるために、p側オーミック電極をp型窒化ガ
リウム系半導体層のほぼ全面に設け、かつn側のオーミ
ック電極とp側のパッド電極とを対角を成す位置に形成
し活性層に効率よく電流が注入されるような、独特の構
成を有している。
That is, the gallium nitride based semiconductor device is constructed by using an insulating sapphire substrate, and the p-type nitride semiconductor has a relatively large resistance value. Since there is a situation different from that of the element, the p-side ohmic electrode is provided on almost the entire surface of the p-type gallium nitride based semiconductor layer, and the n-side ohmic electrode and the p-side pad electrode are formed at diagonal positions. It has a unique structure so that current can be efficiently injected into the active layer.

【0006】さらに、従来の窒化物半導体発光素子で
は、通常、半導体層および電極層を保護するために、n
側パット電極上およびp側パット電極上の外部回路との
接続部分とを除いて、絶縁性保護膜を形成する。以上の
ように構成された従来の窒化物半導体発光素子は、正お
よび負のパット電極の外部回路との接続部分をそれぞ
れ、配線基板に対向させて例えばフリップチップボンデ
ィングにより接続し、発光した光は透光性の基板を介し
て出力される。
Further, in the conventional nitride semiconductor light emitting device, normally, in order to protect the semiconductor layer and the electrode layer, n
An insulating protective film is formed on the side pad electrode and the p-side pad electrode except for the connection portion with the external circuit. In the conventional nitride semiconductor light emitting device configured as described above, the positive and negative pad electrodes are connected to the external circuit by facing the wiring substrate, and are connected by, for example, flip chip bonding, and the emitted light is It is output through the transparent substrate.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上記の
方法により大面積の窒化物半導体発光素子、なかでも窒
化ガリウム系半導体素子を得ようとする場合、以下のよ
うな問題が生じる。上述した、p側オーミック電極をp
型窒化ガリウム系半導体層のほぼ全面に設けかつn側オ
ーミック電極とp側パッド電極を、対角を成す位置に形
成するという独特の構成では、大面積の発光素子を形成
する場合、窒化物半導体活性層に注入される電流は、n
側オーミック電極からある一定の距離の範囲では、ほぼ
一定と見なすことができるが、その範囲を超えると急激
に減少し、均一な発光も難しくなる。
However, when trying to obtain a large area nitride semiconductor light emitting device, especially a gallium nitride based semiconductor device by the above method, the following problems occur. The p-side ohmic electrode described above is p
Type gallium nitride-based semiconductor layer is provided on almost the entire surface and an n-side ohmic electrode and a p-side pad electrode are formed in diagonal positions, a unique structure is required for forming a large-area light emitting device. The current injected into the active layer is n
It can be regarded as almost constant within a certain distance from the side ohmic electrode, but if it exceeds the certain range, it is rapidly reduced and uniform light emission becomes difficult.

【0008】例えば、サファイア基板上にn型窒化物半
導体層、窒化物半導体活性層、p型窒化物半導体層を積
層し、形成された窒化ガリウム系の発光素子では、n側
オーミック電極から250μm以内の距離にある窒化物
半導体活性層に注入される電流はほぼ一定であるが、2
50μm以上離れると急激に減少する。実際には220
μmより離れると窒化物半導体活性層に注入される電流
は徐々に減少しはじめるが、250μmまでは電流値は
実質的に一定と見なすことができる。
For example, in a gallium nitride-based light emitting device formed by stacking an n-type nitride semiconductor layer, a nitride semiconductor active layer, and a p-type nitride semiconductor layer on a sapphire substrate, within 250 μm from the n-side ohmic electrode. The current injected into the nitride semiconductor active layer at a distance of is almost constant.
When the distance is more than 50 μm, it sharply decreases. Actually 220
The current injected into the nitride semiconductor active layer gradually begins to decrease when the distance is more than μm, but the current value can be regarded as substantially constant up to 250 μm.

【0009】またこの現象(窒化物半導体活性層が25
0μm以上離れると注入される電流が急激に減少すると
いう現象)は、n型窒化物半導体層の抵抗値に起因して
生じると考えられるが、通常、用いられるn型窒化物半
導体層の抵抗値の範囲においては、ほとんど変わらない
ことが確認されている。
This phenomenon (the nitride semiconductor active layer is 25
The phenomenon that the injected current sharply decreases when the distance is 0 μm or more) is considered to be caused by the resistance value of the n-type nitride semiconductor layer, but normally, the resistance value of the n-type nitride semiconductor layer is used. It has been confirmed that there is almost no change in the range of.

【0010】上記の知見から、n型窒化物半導体層の上
に、一方向に長い長方形の窒化物半導体活性層およびp
型窒化物半導体層を形成した場合であっても、n側オー
ミック電極からの距離を一定以内の距離、(ある範囲以
内)好ましくは250μm以内とすれば、窒化物半導体
活性層全体にほぼ均一に電流を注入することができる。
From the above knowledge, a rectangular nitride semiconductor active layer which is long in one direction and a p-type nitride semiconductor active layer are formed on the n-type nitride semiconductor layer.
Even when the type nitride semiconductor layer is formed, if the distance from the n-side ohmic electrode is within a certain distance (within a certain range), preferably within 250 μm, the nitride semiconductor active layer is almost evenly formed. Current can be injected.

【0011】大面積の発光素子を得る場合は、上記p側
オーミック電極をp型窒化ガリウム系半導体層のほぼ全
面に設けかつn側のオーミック電極とp側のパッド電極
を、対角を成す位置に形成するという独特の構成を相似
形により、大きくするという構成では、上記の理由によ
り困難であるため、1つの基板上に、望ましいある一定
の距離に窒化物半導体活性層が存在する発光素子を、線
形又はアレイ状に複数個配列することにより構成するの
が好ましい。
To obtain a large-area light emitting device, the p-side ohmic electrode is provided on almost the entire surface of the p-type gallium nitride based semiconductor layer, and the n-side ohmic electrode and the p-side pad electrode are located at diagonal positions. It is difficult to increase the size of the peculiar structure of forming the same by a similar shape for the above reason. Therefore, a light emitting device in which a nitride semiconductor active layer is present at a desired constant distance on one substrate is formed. It is preferable that a plurality of linear or arrayed elements are arranged.

【0012】しかし、上記の方法で、複数の半導体素子
を基板上に並べ、各々の半導体素子を接続した大面積の
発光素子(LEDチップ)を、実装基体に実装した場
合、窒化物半導体活性層にほぼ均一に電流を注入できる
が、面積が広くなるため、活性層から生じる熱に対する
放熱性の問題が生じてくる。従来の面積の素子により基
体に実装し発光装置とした半導体素子は、オーミック電
極上に外部と電気的に導通するために形成されたパッド
電極上に設けられている正負1対のバンプから熱が放熱
され、放熱性を問題とする必要はあまりなかった。しか
し、例えば面積が広くなるなどして、前記正負一対のバ
ンプから離れた部分において、放熱が十分に行われずに
熱が堆積されると、素子の劣化を招き、寿命や一定の発
光出力を保ち続けるなどの発光能力に影響を与える、な
どといった問題が顕在化してくる。
However, in the case where a plurality of semiconductor elements are arranged on a substrate by the above method and a large-area light emitting element (LED chip) in which each semiconductor element is connected is mounted on a mounting substrate, a nitride semiconductor active layer is formed. Although a current can be injected substantially uniformly into the substrate, since the area becomes large, there arises a problem of heat dissipation from heat generated from the active layer. A semiconductor element that is mounted on a substrate with a conventional area and is used as a light emitting device generates heat from a pair of positive and negative bumps provided on a pad electrode formed on the ohmic electrode for electrical conduction with the outside. Heat was dissipated, and there was not much need to consider heat dissipation. However, for example, when the area is widened and heat is accumulated in the portion away from the pair of positive and negative bumps without sufficient heat dissipation, the element is deteriorated, and the life and constant light emission output are maintained. Problems such as continuing to affect the light emitting ability will become apparent.

【0013】そこで本発明は、発光素子の放熱性を高め
た、寿命や一定の発光出力を保ち続けるなどの発光能力
に優れた半導体発光装置を提供することを目的とし、さ
らには、大面積でかつ放熱効率の良い集積型の半導体発
光装置を提供することを目的とする。
Therefore, an object of the present invention is to provide a semiconductor light emitting device having an improved heat dissipation of the light emitting element and having an excellent light emitting ability such as keeping the life and maintaining a constant light emitting output, and further, in a large area. Another object of the present invention is to provide an integrated semiconductor light emitting device having good heat dissipation efficiency.

【0014】[0014]

【課題を解決するための手段】以上の目的を達成するた
めに、本発明による半導体発光装置は、基板上に半導体
素子が形成されてなる発光素子が実装基体に実装されて
なる半導体発光装置において、前記半導体発光装置は、
実装基体側と電気的に導通して接続された第1のバンプ
と、実装基体と電気的に絶縁して接続された第2のバン
プとを有することを特徴とし、前記第1のバンプ以外に
前記第2のバンプを設けることにより、放熱性を高める
ことができる。
To achieve the above object, a semiconductor light emitting device according to the present invention is a semiconductor light emitting device in which a light emitting element having a semiconductor element formed on a substrate is mounted on a mounting base. , The semiconductor light emitting device,
A first bump electrically connected to the mounting substrate side and connected thereto; and a second bump electrically insulated and connected to the mounting substrate side, and other than the first bump. By providing the second bump, heat dissipation can be improved.

【0015】また基板上に複数の半導体素子が形成さ
れ、実装基体に実装されてなる半導体発光装置におい
て、前記半導体発光装置は、実装基体と電気的に導通し
て接続された第1のバンプと、実装基体と電気的に絶縁
して接続された第2のバンプとを有することを特徴とす
る。前記第1のバンプは、半導体素子の正電極および負
電極に、それぞれ接続され、外部と導通されるものであ
り、外部に接続された電極上に形成される前記第1のバ
ンプ以外に、第2のバンプとして、1つ又は複数のバン
プを設けることにより、前記外部に接続された電極上の
第1のバンプから離れた部分すなわち、熱伝導しにくい
部分に堆積した熱においても、第2のバンプを設けるこ
とによって、実装基体に対する接触面積が増加すること
で、実装基体への放熱効率が良好となり、結果的に素子
の劣化を防ぎ、半導体発光装置の寿命を向上させること
ができる。
In a semiconductor light emitting device having a plurality of semiconductor elements formed on a substrate and mounted on a mounting base, the semiconductor light emitting device includes a first bump electrically connected to the mounting base and connected to the first bump. , And a second bump electrically insulated and connected to the mounting substrate. The first bumps are connected to the positive electrode and the negative electrode of the semiconductor element, respectively, and are electrically connected to the outside. In addition to the first bumps formed on the electrodes connected to the outside, By providing one or a plurality of bumps as the second bump, even if the heat deposited on the portion away from the first bump on the electrode connected to the outside, that is, the portion where heat conduction is difficult, By providing the bumps, the contact area with respect to the mounting base increases, so that the efficiency of heat dissipation to the mounting base improves, and as a result, deterioration of the element can be prevented and the life of the semiconductor light emitting device can be improved.

【0016】また第2のバンプは外部に接続された正負
1対の電極間の距離に応じて適宜個数を決めることがで
きる。
The number of the second bumps can be appropriately determined according to the distance between a pair of positive and negative electrodes connected to the outside.

【0017】また、前記第2のバンプは、前記半導体素
子のうち、隣り合った2つの半導体素子を電気的に接続
して大面積の発光素子としている各半導体素子の接続電
極上に設けることで、比較的均一に放熱することができ
好ましい。また第2のバンプは、前記第1のバンプと同
様の金属材料で形成し、絶縁保護膜上などに設けるより
も接続電極上に設けることで、工程上容易に形成でき好
ましい。これらのようにして第2のバンプを設けること
で、各バンプ間の距離が長く熱が堆積しやすい大面積の
発光素子等において、特にその放熱効果が顕著に見込ま
れる。
Further, the second bump is provided on the connection electrode of each semiconductor element, which is a large-area light emitting element by electrically connecting two adjacent semiconductor elements among the semiconductor elements. It is preferable because heat can be dissipated relatively uniformly. It is preferable that the second bump is formed of the same metal material as that of the first bump and is provided on the connection electrode rather than on the insulating protective film because it can be easily formed in the process. By providing the second bumps as described above, the heat radiation effect is particularly expected in a large-area light emitting element or the like in which the distance between the bumps is long and heat is easily accumulated.

【0018】また、前記基板は透光性を有し、光取り出
し面を基板側とするフリップチップで実装した半導体素
子において顕著な効果を示す。またこのようなフリップ
チップ実装方法により、光取り出し面を基板側にすると
発光効率も良くなる。
Further, the substrate has a light-transmitting property, and a remarkable effect is exhibited in a semiconductor element mounted by flip-chip with the light extraction surface on the substrate side. Further, when the light extraction surface is on the substrate side by such a flip chip mounting method, the light emission efficiency is also improved.

【0019】なお、前記半導体素子は、n型窒化物半導
体層、窒化物半導体活性層、p型窒化物半導体層が順次
積層され、前記p型窒化物半導体および、窒化物半導体
活性層の一部を除去して露出されたn型窒化物半導体層
上にn側オーミック電極が形成され、p型窒化物半導体
層上にp型オーミック電極が形成されてなることを特徴
とする構成である。
In the semiconductor device, an n-type nitride semiconductor layer, a nitride semiconductor active layer, and a p-type nitride semiconductor layer are sequentially stacked, and the p-type nitride semiconductor and a part of the nitride semiconductor active layer. Is formed, and an n-side ohmic electrode is formed on the exposed n-type nitride semiconductor layer, and a p-type ohmic electrode is formed on the p-type nitride semiconductor layer.

【0020】[0020]

【発明の実施の形態】実施の形態1.本発明に係わる実
施形態の半導体発光装置は、透光性を有する基板を介し
て発光した光を出力するいわゆる基板側発光タイプの半
導体素子であって、例えば、図1に示すように、サファ
イアからなる基板上に、n型窒化物半導体層、窒化物半
導体活性層、p型窒化物半導体層が積層され、p側、n
側オーミック電極が各層上に形成され、p側のオーミッ
ク電極の一部にp側パッド電極が形成されている半導体
素子において、これらn側オーミック電極およびp側パ
ッド電極上に、金属からなる第1のバンプが設けられ、
さらに第1のバンプと同様の金属材料からなる第2のバ
ンプが設けられており、実装基体にマウントされている
ものである。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. A semiconductor light emitting device according to an embodiment of the present invention is a so-called substrate side light emitting type semiconductor element that outputs light emitted through a substrate having a light-transmitting property. For example, as shown in FIG. On the substrate, an n-type nitride semiconductor layer, a nitride semiconductor active layer, and a p-type nitride semiconductor layer are laminated,
In a semiconductor device in which a side ohmic electrode is formed on each layer and a p-side pad electrode is formed on a part of the p-side ohmic electrode, a first metal layer is formed on the n-side ohmic electrode and the p-side pad electrode. Bumps are provided,
Further, second bumps made of the same metal material as the first bumps are provided and mounted on the mounting substrate.

【0021】通常、バンプは半導体素子をフェイスダウ
ン実装により実装基体に搭載する際、p側、n側の電極
および実装基体の間に設けられ、半導体素子と実装基体
の接合を目的として用いられる。詳細に説明すると、サ
ファイアからなる基板上に順次積層された、n型窒化物
半導体層、活性層、p型窒化物半導体層上にp側オーミ
ック電極は全面に形成され、前記p側オーミック電極の
一部にパッド電極が形成されている。一方、p型半導体
層および活性層を除去し、表面が露出されたn型窒化物
半導体層上には、n側オーミック電極が形成されてい
る。これらp側パッド電極、およびn側オーミック電極
上以外には絶縁保護膜が形成されている。これらのp側
パッド電極上およびn側オーミック電極に例えば錫−銀
−銅合金(Sn−Ag−Cu)または錫−銅−ニッケル
合金(Sn−Cu−Ni)などの低融点金属を用いたは
んだからなる第1のバンプが設けられている。
Usually, the bump is provided between the p-side and n-side electrodes and the mounting base when the semiconductor device is mounted on the mounting base by face-down mounting, and is used for the purpose of joining the semiconductor device and the mounting base. More specifically, the p-side ohmic electrode is formed on the entire surface of the n-type nitride semiconductor layer, the active layer, and the p-type nitride semiconductor layer, which are sequentially stacked on the substrate made of sapphire. A pad electrode is formed in part. On the other hand, the p-type semiconductor layer and the active layer are removed, and an n-side ohmic electrode is formed on the exposed n-type nitride semiconductor layer. An insulating protection film is formed on the p-side pad electrode and the n-side ohmic electrode. Solder using a low melting point metal such as tin-silver-copper alloy (Sn-Ag-Cu) or tin-copper-nickel alloy (Sn-Cu-Ni) on the p-side pad electrode and the n-side ohmic electrode. A first bump consisting of

【0022】本発明で用いられるバンプは、上記材料以
外に、錫(Sn)、金(Au)、インジウム(In)、
金−鉛合金(Au−Pb)、錫−白金合金(Sn−P
t)、インジウム−錫合金(In−Sn)、共晶錫−鉛
(Sn−Pb)などの一般にバンプとして用いられる材
料が挙げられる。特にSn−Ag−CuおよびSn−C
u−Niは実装性の点で優れている。これらの材料から
なる第1のバンプを設けることにより、半導体素子は実
装基体に接合されており、これらn側およびp側の電極
上のバンプは外部と電気的に導通されている。
In addition to the above materials, the bumps used in the present invention include tin (Sn), gold (Au), indium (In),
Gold-lead alloy (Au-Pb), tin-platinum alloy (Sn-P
t), indium-tin alloy (In-Sn), eutectic tin-lead (Sn-Pb), and other materials generally used as bumps. Especially Sn-Ag-Cu and Sn-C
u-Ni is excellent in mountability. By providing the first bumps made of these materials, the semiconductor element is bonded to the mounting substrate, and the bumps on the n-side and p-side electrodes are electrically connected to the outside.

【0023】また、バンプの形成方法としては、はんだ
材料を用いての溶着、めっき、スタッドバンプなどに用
いるボール、スクリーン印刷、または金を用いためっ
き、ボール、さらにはポリマーを用いたスクリーン印刷
などが挙げられ、電極上、電極と対向する実装基体上、
もしくは電極上と電極と対向する実装基体上の両方、の
いずれかの位置に、上記バンプを形成し、実装基体と接
合することで形成されるが、特に金を用いたバンプの場
合は、実装基体側にも、接着する際のバンプに対向する
位置に金を形成しておき、金−金接合による金バンプを
形成するのが好ましい。
The bumps can be formed by welding using solder material, plating, balls used for stud bumps, screen printing, or plating using gold, balls, and screen printing using polymers. , On the mounting substrate facing the electrode,
Alternatively, it is formed by forming the bumps at either position on the electrode or on the mounting substrate facing the electrode and joining the bumps to the mounting substrate. Particularly, in the case of bumps using gold, mounting is performed. It is preferable that gold is formed on the substrate side at a position facing the bump when bonding, and the gold bump is formed by gold-gold bonding.

【0024】本発明の半導体発光装置は、前記n側およ
びp側の電極上以外の部分においても、n側オーミック
電極14およびp側パッド電極16上に形成されている
第1のバンプ31とは別の部分に、1つ或いは複数の第
2のバンプ32が設けられており、前記第2のバンプ3
2は、n側或いはp側の電極上の第1のバンプ31から
実装基体24へ伝わりにくい活性層10から生じた熱
を、実装基体24へ導くために設けられているものであ
り、前記第2のバンプ32は外部と電気的に導通されて
いない。
In the semiconductor light emitting device according to the present invention, the first bumps 31 formed on the n-side ohmic electrode 14 and the p-side pad electrode 16 are formed on the portions other than the n-side and p-side electrodes. One or more second bumps 32 are provided in another portion, and the second bumps 3 are provided.
2 is provided to guide the heat generated from the active layer 10 which is difficult to be transferred from the first bump 31 on the n-side or p-side electrode to the mounting substrate 24 to the mounting substrate 24. The second bump 32 is not electrically connected to the outside.

【0025】尚、前記第2のバンプ32は、前記第1の
バンプ31と同様の材料からなる金属又はそれらの合
金、或いは熱伝導率の良い他の材料からなるものであっ
てもよいし、さらに第2のバンプの形成方法としては、
上記に挙げた第1のバンプの形成方法と同じ方法を用い
ることができる。
The second bump 32 may be made of the same material as the first bump 31 such as metal or alloy thereof, or other material having good thermal conductivity. Further, as a method of forming the second bump,
The same method as the method of forming the first bump described above can be used.

【0026】また、前記第2のバンプ32と窒化物半導
体層上の絶縁保護膜の間には、ボンディングパッド19
が形成されていてもよい。
Further, the bonding pad 19 is provided between the second bump 32 and the insulating protective film on the nitride semiconductor layer.
May be formed.

【0027】バンプと絶縁保護膜との間にボンディング
パッド19が形成されることで、第2のバンプ32を形
成するときの位置あわせが容易となり、バンプを設けや
すくなる。
By forming the bonding pad 19 between the bump and the insulating protective film, the alignment when forming the second bump 32 is facilitated and the bump is easily provided.

【0028】また、前記ボンディングパッド19は絶縁
保護膜17を開口して、オーミック電極15上に形成す
ると、絶縁保護膜17を介さず熱が伝わるので、より効
率的に放熱効果を高めることができるが、前記ボンデイ
ングパッド19上に第2のバンプ32を形成しても素子
に影響を与えない程度の厚さを考慮するものとし、外部
電極と導通されるn側オーミック電極14およびp側パ
ッド電極16と同様の材料からなる金属であっても、そ
れ以外の金属であってもよい。
When the bonding pad 19 is formed on the ohmic electrode 15 by opening the insulating protective film 17, heat is transferred without passing through the insulating protective film 17, so that the heat dissipation effect can be more efficiently enhanced. However, considering the thickness of the second bump 32 on the bonding pad 19 so as not to affect the device, the n-side ohmic electrode 14 and the p-side pad electrode that are electrically connected to the external electrode are taken into consideration. It may be a metal made of the same material as 16 or other metal.

【0029】本実施の形態は、はんだをバンプとして用
いているが、金などのはんだを用いないバンプを形成し
てもよく、その場合、実装基体への実装方法としては、
(1)バンプと実装基体との間に新たにはんだを形成
し、接続させる方法、(2)バンプと実装基体との間に
異方性導電フィルムや異方性導電ペーストを介して接続
させる方法などがある。
In this embodiment, solder is used as the bump. However, bumps not using solder such as gold may be formed. In that case, the mounting method on the mounting substrate is as follows.
(1) A method of newly forming and connecting solder between the bump and the mounting base, and (2) A method of connecting between the bump and the mounting base via an anisotropic conductive film or an anisotropic conductive paste. and so on.

【0030】また、本実施の形態において、p側パッド
電極およびn側パッド電極(n側パッド電極を設けない
場合は、n側オーミック電極)自体を第1のバンプと
し、ボンディングパッド自体を第2のバンプとして実装
基体に実装することも可能である。
Further, in the present embodiment, the p-side pad electrode and the n-side pad electrode (or the n-side ohmic electrode when the n-side pad electrode is not provided) itself is the first bump, and the bonding pad itself is the second bump. It is also possible to mount it as a bump on the mounting substrate.

【0031】尚、本実施の形態は複数個の半導体素子を
並べ、大面積の発光素子とした場合にも適用される。
The present embodiment is also applicable to a case where a plurality of semiconductor elements are arranged to form a large area light emitting element.

【0032】これらの条件を満たすことにより、例えば
大面積の発光素子にみられるように、電極上のバンプか
ら距離が長く放熱が十分に行われない等の問題を有する
半導体素子における放熱性を高め、活性層から生じた熱
が堆積されずに放熱されることにより、半導体発光装置
の劣化を抑制することができる。実施の形態2本実施の
形態2の窒化物半導体発光装置は、例えば図2に示すよ
うな1000μm×1000μmのサファイア基板上に
長方形の3つの半導体素子1、2、3を互いに平行に配
置しかつ、放熱性を高めるために複数のバンプを、各素
子を接続している接続電極上に設け、実装基体24との
接触面積を大きくさせることにより、工程上容易に且つ
均等な放熱が可能となることから、電極からの距離が比
較的遠く熱の放散が不十分である部分での発光素子の温
度上昇を抑え、その結果として、長寿命で、長時間でも
安定した均一な発光能力を持つ半導体発光装置を実現で
きる。
By satisfying these conditions, the heat dissipation property of the semiconductor device having a problem that the distance from the bump on the electrode is long and the heat is not sufficiently dissipated, as seen in, for example, a large-area light emitting device, is improved. Since the heat generated from the active layer is radiated without being accumulated, deterioration of the semiconductor light emitting device can be suppressed. Embodiment 2 A nitride semiconductor light emitting device of Embodiment 2 has three rectangular semiconductor elements 1, 2 and 3 arranged in parallel with each other on a sapphire substrate of 1000 μm × 1000 μm as shown in FIG. By providing a plurality of bumps on the connection electrodes connecting each element to increase the heat dissipation and increasing the contact area with the mounting substrate 24, it is possible to easily and uniformly dissipate the heat in the process. Therefore, the temperature rise of the light emitting element is suppressed in the portion where the distance from the electrode is relatively large and the heat dissipation is insufficient. As a result, the semiconductor has a long life and a stable and uniform light emitting ability even for a long time. A light emitting device can be realized.

【0033】詳細に説明すると、本発明における第2の
形態のように、複数の半導体素子を並べて大面積の発光
素子を得る場合は、n型窒化物半導体上に設けられたn
側オーミック電極と窒化物半導体活性層およびp型窒化
物半導体層の他の長辺との間の距離を好ましい距離と
し、素子を複数個基板上に形成し、大面積にすることが
望ましい。ここで好ましい距離とは、上記記載のよう
に、窒化物半導体活性層に注入される電流がほぼ一定と
なる距離の最大値であり、これは窒化物半導体の抵抗値
により変化するものである。
More specifically, when a plurality of semiconductor elements are arranged to obtain a large-area light emitting element as in the second embodiment of the present invention, n provided on an n-type nitride semiconductor is used.
It is desirable that the distance between the side ohmic electrode and the other long sides of the nitride semiconductor active layer and the p-type nitride semiconductor layer be a preferable distance, and a plurality of devices be formed on the substrate to have a large area. As described above, the preferable distance is the maximum value of the distance at which the current injected into the nitride semiconductor active layer is substantially constant, which changes depending on the resistance value of the nitride semiconductor.

【0034】しかし、このように大面積の発光素子を形
成し、フリップチップ実装する場合、外部に接続されて
いる正負1対の電極上にバンプ(第1のバンプ31)が
形成され、前記第1のバンプ31を介し発光素子は実装
基体24と接続しているが、他の部分はアンダーフィル
などと呼ばれる封止樹脂により充填されており、樹脂は
金属や半導体、絶縁保護膜と比較して熱伝導率が低いの
で、これら他の部分で発生した熱はほとんど放熱されず
に堆積する。
However, when a large-area light emitting device is formed and flip-chip mounted in this way, bumps (first bumps 31) are formed on a pair of positive and negative electrodes connected to the outside, and Although the light emitting element is connected to the mounting substrate 24 via the bump 31 of No. 1, the other portion is filled with a sealing resin called underfill or the like, and the resin is compared with a metal, a semiconductor, or an insulating protective film. Since the thermal conductivity is low, the heat generated in these other parts is deposited with almost no radiation.

【0035】そのため、複数個並んだ状態で形成されて
いる各素子を接続している、接続電極上に、第1のバン
プ31(外部電極と接続され電気的に導通している)と
同様に第2のバンプ32を形成することにより、前記第
2のバンプ32は、電気的に独立した絶縁状態で、実装
時に半導体素子および実装基体24に接触することがで
き、前記バンプ付近に生じた活性層からの熱が実装基体
24へ導かれるので、発光素子の放熱性を高めることが
可能となる。
Therefore, similar to the first bumps 31 (which are connected to the external electrodes and are electrically connected) on the connection electrodes, which connect the respective elements formed in a line. By forming the second bumps 32, the second bumps 32 can be brought into contact with the semiconductor element and the mounting substrate 24 at the time of mounting in an electrically independent insulating state, and the activity generated near the bumps can be achieved. Since the heat from the layers is conducted to the mounting substrate 24, it is possible to improve the heat dissipation of the light emitting element.

【0036】また、接続電極上に第2のバンプ32を設
けることで、第2のバンプを形成するための位置あわせ
が容易であり、第2のバンプの形状および大きさを一定
とした場合、均等に放熱が行われることで、長時間均一
に発光することが可能となり、発光むらを防ぐことがで
きる。
Further, by providing the second bump 32 on the connection electrode, the alignment for forming the second bump is easy, and when the shape and size of the second bump are constant, By uniformly radiating heat, it becomes possible to emit light uniformly for a long time, and it is possible to prevent uneven light emission.

【0037】本実施の形態2の好ましい形態を、以下に
挙げる。図3は本実施の形態における半導体発光装置を
断面から見たときの模式断面図である。
Preferred forms of the second embodiment are listed below. FIG. 3 is a schematic cross-sectional view of the semiconductor light emitting device according to the present embodiment as seen from a cross section.

【0038】サファイア基板上にn型窒化物半導体層1
2、窒化物半導体活性層10、およびp型窒化物半導体
層13が順次積層され、形成された複数個の窒化物半導
体発光素子において、隣りあった2つの半導体素子を接
続電極により電気的に接続し、大面積の発光素子とした
場合、n側オーミック電極14上およびp側パッド電極
16上に形成された外部接続電極22(図中においてn
側を22a、p側を22bとする)に金属材料からなる
第1のバンプ31を設け、さらに、各素子を電気的に接
続している接続電極上21に、第1のバンプ31と同様
の金属材料からなる第2のバンプ32を設ける。
N-type nitride semiconductor layer 1 on sapphire substrate
2. Nitride semiconductor active layer 10 and p-type nitride semiconductor layer 13 are sequentially stacked to form a plurality of nitride semiconductor light emitting devices, and two adjacent semiconductor devices are electrically connected by a connection electrode. However, in the case of a large-area light emitting element, the external connection electrode 22 (in the figure, n is formed on the n-side ohmic electrode 14 and the p-side pad electrode 16).
Side 22a, and p side 22b) is provided with a first bump 31 made of a metal material, and the same as the first bump 31 is provided on the connection electrode 21 electrically connecting each element. A second bump 32 made of a metal material is provided.

【0039】第2のバンプ32を設けることにより、第
1のバンプ31からの放熱が十分行われず堆積した熱
が、第2のバンプ32を介して実装基体24へと導かれ
る。
By providing the second bump 32, the heat radiated from the first bump 31 is not sufficiently radiated, and the accumulated heat is guided to the mounting substrate 24 via the second bump 32.

【0040】好ましくは、複数個の半導体素子の隣りあ
った素子を、互いに電気的に接続しているすべての接続
電極21上の絶縁保護膜18を開口し、第2のバンプ3
2を設けるものであり、金属からなる接続電極21上
に、同様の成分からなる第2のバンプ32を設けること
で、絶縁保護膜上にバンプを設ける場合と比較して、よ
り放熱性が高まる。
Preferably, the insulating protection film 18 on all the connection electrodes 21 electrically connecting mutually adjacent semiconductor elements to each other is opened, and the second bumps 3 are formed.
2 is provided, and by providing the second bumps 32 made of the same component on the connection electrode 21 made of metal, heat dissipation is further enhanced as compared with the case where the bumps are provided on the insulating protective film. .

【0041】前記第2のバンプ32と接続電極21の間
には、パッド電極と同様の金属材料からなるボンディン
グパッドを形成してもよい。
A bonding pad made of the same metal material as the pad electrode may be formed between the second bump 32 and the connection electrode 21.

【0042】また、外部と導通されず、絶縁状態で存在
する第2のバンプ32および第2のバンプが形成される
ボンディングパッドは、複数個形成される方が、実装基
体24と接する面が多くなり、放熱性が増すので好まし
い。
Further, the second bumps 32 which are not electrically connected to the outside and are present in an insulating state, and the bonding pads on which the second bumps are formed are more in contact with the mounting substrate 24 when a plurality of bonding pads are formed. This is preferable because it improves heat dissipation.

【0043】また、前記第2のバンプ32は前記第1の
バンプ31と同様の材料からなる金属又はそれらの合金
或いは、熱伝導率の良い他の材料からなる金属であって
もよく、好ましくは、前記第2のバンプ32の下に形成
されるボンディングパッドより、熱伝導率のよい金属に
よって形成されるものである。
The second bump 32 may be made of a metal similar to that of the first bump 31 or an alloy thereof, or a metal made of another material having a high thermal conductivity, preferably. The bonding pad formed under the second bump 32 is made of a metal having a higher thermal conductivity.

【0044】さらに実装基体24は、バンプと接続する
部分に、熱伝導率のよい金属が実装基体24の表面上
に、或いは実装基体24を貫通した状態で埋め込まれて
いるなどの形状であると、放熱効果が高まり、より好ま
しい。
Further, the mounting substrate 24 has a shape such that a metal having a high thermal conductivity is embedded on the surface of the mounting substrate 24 or in a state where the mounting substrate 24 penetrates the mounting substrate 24. It is more preferable because the heat dissipation effect is enhanced.

【0045】実施の形態2で用いられる(第1および第
2の)バンプは、実施の形態1と同様に、Sn−Ag−
CuおよびSn−Cu−Ni、Sn、Au、In、Au
−Pb、Sn−Pt、In−Sn、Sn−Pbなどの一
般にバンプとして用いられる材料が挙げられる。特にS
n−Ag−CuおよびSn−Cu−Niは実装性の点で
優れている。
The (first and second) bumps used in the second embodiment are similar to those of the first embodiment in that Sn-Ag- is used.
Cu and Sn-Cu-Ni, Sn, Au, In, Au
Materials commonly used as bumps, such as -Pb, Sn-Pt, In-Sn, and Sn-Pb, may be mentioned. Especially S
n-Ag-Cu and Sn-Cu-Ni are excellent in mountability.

【0046】また、バンプの形成方法としても、実施の
形態1と同様に、はんだ材料を用いての溶着、めっき、
スタッドバンプなどに用いるボール、スクリーン印刷、
または金を用いためっき、ボール、さらにはポリマーを
用いたスクリーン印刷などが挙げられ、電極上、電極と
対向する実装基体上、もしくは電極上と電極と対向する
実装基体上の両方、のいずれかの位置に、上記バンプを
形成し、実装基体と接合することで形成されるが、特に
金を用いたバンプの場合は、実装基体側にも、接着する
際のバンプに対向する位置に金を形成しておき、金−金
接合による金バンプを形成するのが好ましい。
Further, as the method of forming the bumps, similarly to the first embodiment, the welding using the solder material, the plating,
Balls used for stud bumps, screen printing,
Alternatively, plating using gold, balls, screen printing using a polymer, etc. may be mentioned. Either on the electrode, on the mounting substrate facing the electrode, or on both the electrode and the mounting substrate facing the electrode. It is formed by forming the above-mentioned bump at the position of and bonding it to the mounting substrate. Particularly, in the case of a bump using gold, the mounting substrate side is also provided with gold at a position facing the bump when bonding. It is preferable to form the gold bumps by gold-gold bonding.

【0047】本実施の形態は、はんだをバンプとして用
いているが、金などのはんだを用いないバンプを形成し
てもよく、その場合、実装基体への実装方法としては、
(1)バンプと実装基体との間に新たにはんだを形成
し、接続させる方法、(2)バンプと実装基体との間に
異方性導電フィルムや異方性導電ペーストを介して接続
させる方法などがある。
In this embodiment, solder is used as the bump. However, bumps not using solder such as gold may be formed. In that case, the mounting method on the mounting substrate is as follows.
(1) A method of newly forming and connecting solder between the bump and the mounting substrate, and (2) A method of connecting between the bump and the mounting substrate via an anisotropic conductive film or an anisotropic conductive paste. and so on.

【0048】また、本実施の形態において、外部接続電
極は、p側パッド電極およびn側パッド電極(n側パッ
ド電極を設けない場合は、n側オーミック電極)の膜厚
を大きくすることで、省略が可能である。
Further, in the present embodiment, the external connection electrode is formed by increasing the film thickness of the p-side pad electrode and the n-side pad electrode (or the n-side ohmic electrode when the n-side pad electrode is not provided). It can be omitted.

【0049】さらにまた、外部接続電極(外部接続電極
を設けない場合は、p側パッド電極およびn側パッド電
極)自体を第1のバンプとし、接続電極或いはボンディ
ングパッド自体を第2のバンプとして実装基体に実装す
ることも可能である。
Furthermore, the external connection electrode (p-side pad electrode and n-side pad electrode when the external connection electrode is not provided) itself is used as the first bump, and the connection electrode or the bonding pad itself is mounted as the second bump. It can also be mounted on a substrate.

【0050】また実施の形態2において、半導体素子が
3つの場合について説明したが、本発明はこれに限られ
るものではなく、2つの半導体素子を用いて構成した物
であってもよいし、3以上の半導体素子で構成したもの
であってもよい。
In the second embodiment, the case where the number of semiconductor elements is three has been described, but the present invention is not limited to this, and may be one configured by using two semiconductor elements, or three. It may be composed of the above semiconductor elements.

【0051】[0051]

【実施例1】(基板)サファイア(c面)よりなる基板
11をMOVPEの反応容器内にセットし、水素を流し
ながら、基板の温度を1050℃まで上昇させ、基板の
クリーニングを行う。この基板 としては他にR面A面
を主面とするサファイア基板、スピネル(MgAl
)のような絶縁性実装基体24などでもよい。 (n型窒化物半導体)基板をクリーニング後、n型窒化
物半導体層12を次の順序で成長させる。
Example 1 (Substrate) A substrate 11 made of sapphire (c-plane) is set in a MOVPE reaction vessel, the temperature of the substrate is raised to 1050 ° C. while flowing hydrogen, and the substrate is cleaned. Other examples of this substrate include a sapphire substrate whose main surface is the R surface and A surface, and spinel (MgAl 2 O
The insulating mounting substrate 24 such as 4 ) may be used. After cleaning the (n-type nitride semiconductor) substrate, the n-type nitride semiconductor layer 12 is grown in the following order.

【0052】基板の温度を510℃まで下げ、基板11
上にGaNよりなるバッファ層を100Å成長させる。
The substrate temperature is lowered to 510 ° C., and the substrate 11
A 100 Å growth of a GaN buffer layer is grown on top.

【0053】次にバッファ層成長後、温度を1050℃
まで上昇させ、アンドープGaN層を1.5μmの膜厚
で成長させる。
Next, after growing the buffer layer, the temperature is raised to 1050 ° C.
And an undoped GaN layer is grown to a thickness of 1.5 μm.

【0054】続いて1050℃で、Siを4.5×10
18/cmドープしたGaN層を2.2μmの膜厚で
成長させる。
Subsequently, at 1050 ° C., Si was added to 4.5 × 10 5.
A 18 / cm 3 -doped GaN layer is grown to a thickness of 2.2 μm.

【0055】次に1050℃で、アンドープGaN層を
3000Åの膜厚で、さらにSiを4.5×1018
cmドープしたGaN層を300Å、さらにアンドー
プGaN層を50Åの膜厚で成長させる。
Next, at 1050 ° C., an undoped GaN layer having a thickness of 3000 Å and Si of 4.5 × 10 18 /
A cm 3 -doped GaN layer is grown to 300 Å, and an undoped GaN layer is grown to a film thickness of 50 Å.

【0056】続いて同様の温度で、アンドープGaNよ
りなる第1の層を40Å、温度を800℃にして、続い
てアンドープIn0.13Ga0.87Nよりなる第2
の層を20Åの膜厚で成長させ、これらの操作を繰り返
し、第1+第2+の順で交互に10層ずつ積層させ、最
後に第1の層を積層させた、n型多層膜層を成長させ
る。 (窒化物半導体活性層)次にn型窒化物半導体層12を
成長後、アンドープGaNよりなる障壁層を200Åの
膜厚で成長させ、続いて温度を800℃にして、Siを
5×1017/cmドープしたIn0.3Ga0.7
Nよりなる井戸層を30Åの膜厚で成長させる。そして
障壁+井戸+障壁+井戸…の順で障壁層を6層と、井戸
層5層を交互に積層して、総膜厚1350Åの多重量子
井戸よりなる窒化物半導体活性層10を積層させる。 (p型窒化物半導体層)窒化物半導体活性層10成長
後、p型窒化物半導体13を次の構成で成長させる。
Subsequently, at the same temperature, the first layer made of undoped GaN is set to 40 Å and the temperature is set to 800 ° C., and then the second layer made of undoped In 0.13 Ga 0.87 N is formed.
Layer is grown to a film thickness of 20Å, these operations are repeated, and 10 layers are alternately laminated in the order of 1 + 2nd +, and finally the first layer is laminated to grow an n-type multilayer film layer. Let (Nitride Semiconductor Active Layer) Next, after growing the n-type nitride semiconductor layer 12, a barrier layer made of undoped GaN is grown to a film thickness of 200Å, and subsequently the temperature is set to 800 ° C. and Si is set to 5 × 10 17. / Cm 3 Doped In 0.3 Ga 0.7
A well layer made of N is grown to a film thickness of 30Å. Then, six barrier layers and five well layers are alternately laminated in the order of barrier + well + barrier + well to laminate the nitride semiconductor active layer 10 composed of multiple quantum wells with a total film thickness of 1350Å. (P-Type Nitride Semiconductor Layer) After the growth of the nitride semiconductor active layer 10, the p-type nitride semiconductor 13 is grown with the following structure.

【0057】まず1050℃で、Mgを5×1019
cmドープしたp型Al0.1Ga0.9Nよりなる
第3の層を25Åの膜厚で成長させ、続いてアンドープ
GaNよりなる第4の層を25Åの膜厚で成長させ、こ
れらの操作を繰り返し、第3+第4の順で交互に4層ず
つ積層した超格子よりなるp型多層膜層を200Åの膜
厚で成長させる。
First, at 1050 ° C., Mg was added at 5 × 10 19 /
The third layer of p-type Al 0.1 Ga 0.9 N doped with cm 3 was grown to a thickness of 25 Å, and then the fourth layer of undoped GaN was grown to a thickness of 25 Å. The above procedure is repeated to grow a p-type multilayer film layer having a film thickness of 200Å, which is made of a superlattice in which four layers are alternately stacked in the order of 3 + 4.

【0058】続いて1050℃で、Mgを1×1020
/cmドープしたp型GaNよりなる層を2700Å
の膜厚で成長させる。
Subsequently, at 1050 ° C., Mg was added at 1 × 10 20.
/ Cm 3 Doped p-type GaN layer 2700Å
To grow.

【0059】以上のようにして窒化物半導体を成長させ
たウエハを反応容器から取り出し、n型窒化物半導体層
12を露出するために、露出させる部分を除くp型窒化
物半導体13の上にSiOマスクを形成し、RIEに
よって、エッチングを行い、n型窒化物半導体層12
(SiドープGaN層122)の表面を露出させる。
The wafer on which the nitride semiconductor has been grown as described above is taken out of the reaction container, and in order to expose the n-type nitride semiconductor layer 12, the SiO is formed on the p-type nitride semiconductor 13 except the exposed portion. 2 mask is formed, etching is performed by RIE, and the n-type nitride semiconductor layer 12 is formed.
The surface of the (Si-doped GaN layer 122) is exposed.

【0060】次にp型窒化物半導体層13のほぼ全面を
開口させ、他の部分を覆うようにレジストを塗布し、開
口させたp型窒化物半導体層上にNiを100Å、Pt
を500Å積層後、アニールしてp側オーミック電極1
5を形成する。さらにp側オーミック電極15の一部に
外部と接続するための電極用にPtを3000Å、Ni
を60Åからなるp側パッド電極16を形成し、同時に
p側パッド電極16以外のp側オーミック電極上に1つ
のPt/Ni(3000Å/60Å)のボンディングパ
ッド19を形成する。
Next, a resist is applied so that almost the entire surface of the p-type nitride semiconductor layer 13 is opened and the other parts are covered, and 100 Å of Ni and Pt is applied on the opened p-type nitride semiconductor layer.
After laminating 500 Å, anneal and p-side ohmic electrode 1
5 is formed. Further, Pt is 3000 Å and Ni is used as an electrode for connecting to the outside on a part of the p-side ohmic electrode 15.
The p-side pad electrode 16 of 60 Å is formed, and at the same time, one Pt / Ni (3000 Å / 60 Å) bonding pad 19 is formed on the p-side ohmic electrode other than the p-side pad electrode 16.

【0061】次にレジストを除去し、今度はn型窒化物
半導体層上にWを200Å、Alを1000Å、Wを5
00Å、Ptを3000Å、Niを60Åの順で積層し
たn側オーミック電極14を形成する。
Next, the resist was removed, and this time, 200 Å W, 1000 Å Al, and 5 W on the n-type nitride semiconductor layer.
An n-side ohmic electrode 14 is formed by laminating 00Å, Pt of 3000Å, and Ni of 60Å in this order.

【0062】次に全面にSiOよりなる絶縁保護膜1
7を1.5μmの膜厚で形成し、p側パッド電極16と
n側オーミック電極14の一部およびp側オーミック電
極15上のボンディングパッド19をRIEにより露出
させる。最後にダイシングによりチップ化し、窒化物半
導体発光素子を得る。
Next, an insulating protective film 1 made of SiO 2 is formed on the entire surface.
7 is formed to a film thickness of 1.5 μm, and the p-side pad electrode 16 and a part of the n-side ohmic electrode 14 and the bonding pad 19 on the p-side ohmic electrode 15 are exposed by RIE. Finally, dicing is performed to obtain chips, and a nitride semiconductor light emitting device is obtained.

【0063】次に、窒化物半導体素子のn側オーミック
電極14およびp側パッド電極16およびボンディング
パッド19をSn−Ag−Cuからなる溶融はんだの層
に浸漬し、引き上げることでSn−Ag−Cuからなる
バンプを形成する。
Next, the n-side ohmic electrode 14, the p-side pad electrode 16 and the bonding pad 19 of the nitride semiconductor element are immersed in a layer of molten solder made of Sn-Ag-Cu and pulled up to make Sn-Ag-Cu. A bump made of.

【0064】さらに、バンプが形成された半導体素子を
実装基体24へフェイスダウン実装(フリップチップボ
ンディング)にするため、n型およびp型半導体層を下
側にし、第1のバンプ31が実装基体の配線用電極23
に対向する位置で、前記はんだ層からなる第1のバンプ
31および第2のバンプ32と実装基体とを、半田リフ
ローにより溶接させることで接続する。
Further, in order to perform the face-down mounting (flip chip bonding) of the semiconductor element on which the bumps are formed on the mounting substrate 24, the n-type and p-type semiconductor layers are on the lower side, and the first bumps 31 are the mounting substrate. Wiring electrode 23
The first bumps 31 and the second bumps 32 made of the solder layer and the mounting substrate are connected to each other by welding by solder reflow at a position opposed to.

【0065】以上のようにして、図1に示すような窒化
物半導体発光装置を形成する。
As described above, the nitride semiconductor light emitting device as shown in FIG. 1 is formed.

【0066】また、本実施例とは異なるが、p側パッド
電極上にバンプを設け、n側オーミック電極上にn側パ
ッド電極を形成し、その上にバンプを設けるという形態
であってもよい。
Although it is different from the present embodiment, the bumps may be provided on the p-side pad electrode, the n-side pad electrode may be formed on the n-side ohmic electrode, and the bumps may be provided thereon. .

【0067】[0067]

【実施例2】次に、3つの半導体素子を並べ大面積とし
た形態を例として、実施の形態2の実施例を以下に示
す。
[Embodiment 2] Next, an embodiment of the second embodiment will be described below by taking as an example a configuration in which three semiconductor elements are arranged in a large area.

【0068】サファイア基板上にn型窒化物半導体層、
窒化物半導体活性層、p型窒化物半導体層を、実施例1
と同様の方法で積層する。
An n-type nitride semiconductor layer on a sapphire substrate,
The nitride semiconductor active layer and the p-type nitride semiconductor layer were formed as in Example 1.
Laminate in the same manner as.

【0069】次に窒化物半導体を成長させたウエハを反
応容器から取り出し、分離溝を形成する部分を除きウエ
ハ全体にSiOマスクを形成し、RIEによって、サ
ファイア基板に到達するまでエッチングを行うことによ
り分離溝41を設け、半導体素子1、2、3を形成す
る。
Next, the wafer on which the nitride semiconductor has been grown is taken out from the reaction container, a SiO 2 mask is formed on the entire wafer except for the portion where the separation groove is formed, and etching is performed by RIE until the sapphire substrate is reached. The isolation groove 41 is provided by this, and the semiconductor elements 1, 2, and 3 are formed.

【0070】次にn型窒化物半導体層上にnオーミック
電極およびp型窒化物半導体層上にpオーミック電極、
pパッド電極を実施例1と同様の方法で形成する。
Next, an n ohmic electrode on the n-type nitride semiconductor layer and a p ohmic electrode on the p-type nitride semiconductor layer,
The p-pad electrode is formed by the same method as in the first embodiment.

【0071】本実施例2の半導体発光装置の半導体素子
1、2、3において、各半導体層および電極は図3に示
すような構造であり、それぞれは以下のように形成され
る。
In the semiconductor elements 1, 2, and 3 of the semiconductor light emitting device of the second embodiment, each semiconductor layer and electrode have the structure shown in FIG. 3, and each is formed as follows.

【0072】n型窒化物半導体層12は、好ましくはサ
ファイア基板11上に形成された膜厚1.5μmのアン
ドープGaN層、膜厚2.2μmのSiドープGaN
層、膜厚3000ÅのアンドープGaN層、膜厚300
ÅのSiドープGaN層、膜厚50ÅのアンドープGa
N層、多層膜層の積層構造とする。このようにn層12
を上記積層構造とすることにより、順方向電圧を低くで
きかつ発光効率を良くできる。なお、多層膜層126
は、好ましくは、アンドープGaNよりなり膜厚40Å
の第1の層と、アンドープIn0.13Ga0.87
よりなり膜厚20Åの第2の層を交互にそれぞれ10層
になるように積層することにより構成する。
The n-type nitride semiconductor layer 12 is preferably an undoped GaN layer having a thickness of 1.5 μm and a Si-doped GaN having a thickness of 2.2 μm formed on the sapphire substrate 11.
Layer, 3000 Å thickness undoped GaN layer, 300 thickness
Å Si-doped GaN layer, thickness 50 Å undoped Ga
It has a laminated structure of N layers and multilayer films. Thus, the n layer 12
With the above laminated structure, the forward voltage can be lowered and the luminous efficiency can be improved. The multilayer film layer 126
Is preferably made of undoped GaN and has a film thickness of 40 Å
First layer and undoped In 0.13 Ga 0.87 N
The second layer having a film thickness of 20 Å is alternately laminated to form 10 layers.

【0073】また、積層構造のn層全体としての抵抗率
は、実質的には、膜厚2.2μmのSiドープGaN層
により決まり、この層の抵抗率を5.5〜7.2×10
−3Ωcmの範囲でかつ膜厚が2.0μm以上に設定す
ることが好ましく、このようにすると窒化物半導体活性
層10全体により均一に電流を注入することができ、よ
り均一な発光が得られる。
The resistivity of the entire n-layer of the laminated structure is substantially determined by the Si-doped GaN layer having a thickness of 2.2 μm, and the resistivity of this layer is 5.5 to 7.2 × 10.
It is preferable to set the film thickness in the range of −3 Ωcm to 2.0 μm or more. By doing so, it is possible to more uniformly inject current into the entire nitride semiconductor active layer 10 and obtain more uniform light emission. .

【0074】尚、GaN層において、3×1018〜6
×1018cm−3の範囲でSiをドープすることによ
り、抵抗率が5.5〜7.2×10−3Ωcmの範囲の
SiドープGaN膜を構成できる。
In the GaN layer, 3 × 10 18 to 6
A Si-doped GaN film having a resistivity of 5.5 to 7.2 × 10 −3 Ωcm can be formed by doping Si in the range of × 10 18 cm −3 .

【0075】窒化物半導体活性層10は、n層12とほ
ぼ同一の長さとn層12より狭い幅を有する長方形であ
って、その1つの長辺がn層12の1つの長辺に実質的
に一致するようにn層12上に形成される。このように
形成することにより、n層12上に窒化物半導体活性層
10に沿ってn側オーミック電極を形成するための領域
が確保される。
The nitride semiconductor active layer 10 is a rectangle having substantially the same length as the n layer 12 and a width narrower than the n layer 12, and one long side thereof is substantially one long side of the n layer 12. Are formed on the n-layer 12 so as to correspond to. By forming in this way, a region for forming an n-side ohmic electrode is secured on the n layer 12 along the nitride semiconductor active layer 10.

【0076】ここで、本実施例2では、窒化物半導体活
性層10の幅は、n側オーミック電極から離れた側に位
置する長辺とn側オーミック電極との距離が220μm
になるように設定した。
Here, in the second embodiment, the width of the nitride semiconductor active layer 10 is 220 μm such that the distance between the long side located on the side away from the n-side ohmic electrode and the n-side ohmic electrode is 220 μm.
Was set.

【0077】n側オーミック電極14は、窒化物半導体
活性層10とほぼ同一の長さを有し、n層12上に、窒
化物半導体活性層10に沿ってかつ窒化物半導体活性層
10と近接して形成される。更にこのn側オーミック電
極14と窒化物半導体活性層10との間隔は、製造上の
制約により、10〜20μmに設定されるが、本発明に
おいては間隔を10μm以下にすることが好ましく、こ
のようにすると、均一に電流を注入することができる幅
を大きくすることができる。
The n-side ohmic electrode 14 has substantially the same length as the nitride semiconductor active layer 10, and is provided on the n layer 12 along the nitride semiconductor active layer 10 and in the vicinity of the nitride semiconductor active layer 10. Formed. Further, the interval between the n-side ohmic electrode 14 and the nitride semiconductor active layer 10 is set to 10 to 20 μm due to manufacturing restrictions, but in the present invention, the interval is preferably 10 μm or less. With this, the width in which the current can be uniformly injected can be increased.

【0078】また、n側オーミック電極14は、n層1
2とのオーミック接触を良好にするために、WとAlを
含む層とすることが好ましく、更に好ましくは、W層
(200Å)、W層(500Å)、Pt層(3000
Å)、Ni層(60Å)を順次積層することにより形成
する。
The n-side ohmic electrode 14 is composed of the n-layer 1
In order to improve the ohmic contact with 2, it is preferable to use a layer containing W and Al, more preferably a W layer (200Å), a W layer (500Å), a Pt layer (3000).
Å) and Ni layer (60 Å) are sequentially laminated.

【0079】p型窒化物半導体層13は、窒化物半導体
活性層10と同一平面形状を有して窒化物半導体活性層
10上に重ねて形成される。
The p-type nitride semiconductor layer 13 has the same planar shape as the nitride semiconductor active layer 10 and is formed over the nitride semiconductor active layer 10.

【0080】実際には、窒化物半導体活性層10および
p型窒化物半導体層13は、n層12上に窒化物半導体
活性層10およびp型窒化物半導体層13を重ねて形成
した後、n側オーミック電極14を形成するn型窒化物
半導体層12表面を露出させるために一括してエッチン
グすることにより形成する。
In practice, the nitride semiconductor active layer 10 and the p-type nitride semiconductor layer 13 are formed by stacking the nitride semiconductor active layer 10 and the p-type nitride semiconductor layer 13 on the n layer 12 and then n. It is formed by collectively etching to expose the surface of the n-type nitride semiconductor layer 12 forming the side ohmic electrode 14.

【0081】尚、p型窒化物半導体層13は、1500
Åの厚さに形成した。
The p-type nitride semiconductor layer 13 is 1500
Formed to a thickness of Å.

【0082】p側オーミック電極15は、p型窒化物半
導体層13上のほぼ全面に形成され、p型窒化物半導体
層13と良好なオーミック接触を得るために、Ni層と
Pt層とを積層することにより構成することが好まし
く、より好ましくは、Ni層100ÅとPt層500Å
を積層することにより構成する。
The p-side ohmic electrode 15 is formed on almost the entire surface of the p-type nitride semiconductor layer 13, and in order to obtain a good ohmic contact with the p-type nitride semiconductor layer 13, a Ni layer and a Pt layer are laminated. It is preferable that the Ni layer 100 Å and the Pt layer 500 Å
It is configured by stacking.

【0083】そして、p側パッド電極16は、例えば、
膜厚3000ÅのPtからなり、p側オーミック電極1
5上において、n側オーミック電極14とは離れた側に
位置するp側オーミック電極15の長辺に沿って形成さ
れる。
The p-side pad electrode 16 is, for example,
Made of Pt with a film thickness of 3000Å, p-side ohmic electrode 1
5 is formed along the long side of the p-side ohmic electrode 15 located on the side away from the n-side ohmic electrode 14.

【0084】上述のように構成された半導体素子1、
2、3は、絶縁保護膜17により素子間が分離され、接
続電極21により以下のように接続される。
The semiconductor device 1 configured as described above,
The elements 2 and 3 are separated from each other by the insulating protection film 17, and are connected by the connection electrode 21 as follows.

【0085】絶縁保護膜17は、各半導体素子のp側パ
ッド電極16上およびn側オーミック電極14上を除い
て素子全体を覆うように形成される。
The insulating protection film 17 is formed so as to cover the entire element except the p-side pad electrode 16 and the n-side ohmic electrode 14 of each semiconductor element.

【0086】接続電極21は、半導体素子1のn側オー
ミック電極14上、分離溝41に形成された絶縁保護膜
17および半導体素子2のp型オーミック電極16上に
連続して形成され、これにより、半導体素子1のn側オ
ーミック電極14と半導体素子2のp側オーミック電極
16が接続される。
The connection electrode 21 is continuously formed on the n-side ohmic electrode 14 of the semiconductor element 1, the insulating protective film 17 formed in the isolation groove 41, and the p-type ohmic electrode 16 of the semiconductor element 2. The n-side ohmic electrode 14 of the semiconductor element 1 and the p-side ohmic electrode 16 of the semiconductor element 2 are connected.

【0087】また、接続電極21は、半導体素子2と半
導体素子3との間においても同様に形成され、これによ
り、半導体素子2のn側オーミック電極14と半導体素
子3のp側オーミック電極16が接続される。接続電極
21は、Pt又はAu等、種々の金属で構成することが
できるが、pおよびnオーミック電極との密着性を良好
にするために、Ti(例えば400Å)、Pt(例え
ば、6000Å)、Au(例えば、1000Å)、Ni
(例えば、60Å)を順に積層した構造とすることが望
ましい。
The connection electrode 21 is similarly formed between the semiconductor element 2 and the semiconductor element 3, so that the n-side ohmic electrode 14 of the semiconductor element 2 and the p-side ohmic electrode 16 of the semiconductor element 3 are formed. Connected. The connection electrode 21 can be made of various metals such as Pt or Au, but in order to improve the adhesion to the p and n ohmic electrodes, Ti (for example, 400Å), Pt (for example, 6000Å), Au (for example, 1000Å), Ni
It is desirable to have a structure in which (for example, 60Å) are sequentially stacked.

【0088】尚、本実施例ではさらに、半導体素子1の
p側パッド電極16上に接続電極21と同様の材料から
なる外部接続電極22bが形成され、半導体素子3のn
オーミック電極14上に接続電極21と同様の材料から
なる外部接続電極22aが形成される。
Further, in this embodiment, the external connection electrode 22b made of the same material as the connection electrode 21 is further formed on the p-side pad electrode 16 of the semiconductor element 1, and the n of the semiconductor element 3 is formed.
An external connection electrode 22a made of the same material as the connection electrode 21 is formed on the ohmic electrode 14.

【0089】次に、絶縁保護膜18はp側外部接続電極
22b、n側外部接続電極22aおよび各接続電極21
上を除いて、素子全体を覆うように形成される。
Next, the insulating protective film 18 is formed on the p-side external connection electrode 22b, the n-side external connection electrode 22a and each connection electrode 21.
It is formed so as to cover the entire element except the top.

【0090】最後にダイシングによりチップ化し、窒化
物半導体発光素子を得る。
Finally, dicing is performed to form a chip, and a nitride semiconductor light emitting device is obtained.

【0091】次に、窒化物半導体発光素子のn側外部接
続電極22a、p側外部接続電極22bおよび各半導体
素子を互いに接続する接続電極21を、Sn−Ag−C
uからなる溶融はんだの層に浸漬し、引き上げること
で、Sn−Ag−Cuからなるバンプを形成する。
Next, the n-side external connection electrode 22a, the p-side external connection electrode 22b of the nitride semiconductor light emitting device and the connection electrode 21 for connecting the respective semiconductor devices are connected to Sn-Ag-C.
A bump made of Sn-Ag-Cu is formed by immersing in a molten solder layer made of u and pulling it up.

【0092】さらに、バンプが形成された半導体素子
を、実装基体24へフリップチップボンディング(フェ
イスダウン型実装)にするため、n型およびp型半導体
層を下側にし、第1のバンプ31が実装基体の配線用電
極23に対向する位置で、前記はんだ層からなる第1の
バンプ31および第2のバンプ32と実装基体とを、半
田リフローにより溶接させることで接続する。
Further, in order to perform flip-chip bonding (face-down type mounting) on the semiconductor element on which the bumps are formed, to the mounting substrate 24, the n-type and p-type semiconductor layers are placed on the lower side, and the first bumps 31 are mounted. The first bumps 31 and the second bumps 32 made of the solder layer are connected to the mounting substrate by welding by solder reflow at a position facing the wiring electrode 23 of the substrate.

【0093】また、本実施例とは異なるが、p側パッド
電極上にバンプを設け、nオーミック電極上にn側パッ
ド電極を形成し、その上にバンプを設けるという形態で
あってもよい。
Although it is different from the present embodiment, the bump may be provided on the p-side pad electrode, the n-side pad electrode may be formed on the n-ohmic electrode, and the bump may be provided thereon.

【0094】以上のようにして、図3に示すような大面
積で発光する窒化物半導体発光装置を形成する。 [実施例3]実施例3は図3に示すような構造であり、
実施例2とバンプの形成方法、バンプの材料が異なる。
As described above, a nitride semiconductor light emitting device which emits light in a large area as shown in FIG. 3 is formed. [Embodiment 3] Embodiment 3 has a structure as shown in FIG.
The bump forming method and the bump material are different from those of the second embodiment.

【0095】基板上に半導体素子1、2、3を形成し、
外部接続電極22a、22bを形成し、絶縁保護膜18
を形成するまでは実施例2と同様にして形成する。
The semiconductor elements 1, 2, and 3 are formed on the substrate,
The external connection electrodes 22a and 22b are formed, and the insulating protective film 18 is formed.
It is formed in the same manner as in Example 2 until the above is formed.

【0096】次に、Auをn側外部接続電極22a、p
側外部接続電極22bおよび各半導体素子を互いに接続
する接続電極21上に形成する。
Next, Au is added to the n-side external connection electrodes 22a, p.
It is formed on the side external connection electrode 22b and the connection electrode 21 that connects each semiconductor element to each other.

【0097】さらに今度は実装基体側の、半導体素子上
に形成したAuと対向する位置にもAuを形成する。最
後にそれぞれに形成したAuに超音波振動を与えて接合
させ、金からなる第1のバンプ31と第2のバンプ32
を形成する。
Further, this time, Au is also formed on the mounting substrate side at a position facing Au formed on the semiconductor element. Finally, ultrasonic vibration is applied to the Au formed on each of them to bond them, and the first bump 31 and the second bump 32 made of gold are formed.
To form.

【0098】以上のようにして、図3に示すような大面
積で発光する窒化物半導体発光装置を形成する。
As described above, a nitride semiconductor light emitting device which emits light in a large area as shown in FIG. 3 is formed.

【0099】[0099]

【発明の効果】以上詳細に説明したように、本発明に係
わる半導体発光装置は、従来のn側電極およびp側電極
上に形成するバンプと同様のバンプを、前記n側電極お
よびp側電極上以外の部分に設けることにより、放熱効
果を高め、半導体素子に生じる熱の堆積が原因となって
起こる、素子の劣化や寿命、発光能力に関する問題を解
消することができる。
As described in detail above, in the semiconductor light emitting device according to the present invention, the same bumps as the bumps formed on the conventional n-side electrode and p-side electrode are replaced by the n-side electrode and the p-side electrode. By providing it in a portion other than the above, it is possible to enhance the heat dissipation effect and solve the problems relating to the deterioration of the element, the life, and the light emitting ability, which are caused by the accumulation of heat generated in the semiconductor element.

【0100】また、本発明の効果は、実施の形態2で述
べたように、複数個の半導体素子を並べ、発光面積を大
面積とする半導体発光装置において、より効果が顕著と
なる。
Further, as described in the second embodiment, the effect of the present invention becomes more remarkable in the semiconductor light emitting device in which a plurality of semiconductor elements are arranged and the light emitting area is large.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施の形態1を示す半導体発光装置
の模式断面図。
FIG. 1 is a schematic cross-sectional view of a semiconductor light emitting device showing a first embodiment of the present invention.

【図2】 本発明の実施の形態2における、半導体素子
1、2、3を成長方向側からみた模式図。
FIG. 2 is a schematic view of semiconductor elements 1, 2, and 3 according to a second embodiment of the present invention as viewed from a growth direction side.

【図3】 本発明の実施の形態2を示す半導体発光装置
の模式断面図。
FIG. 3 is a schematic cross-sectional view of a semiconductor light emitting device showing a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10・・・活性層、 11・・・基板、 12・・・n層(n型窒化物半導体層)、 13・・・p層(p型窒化物半導体層)、 14・・・n側オーミック電極、 15・・・p側オーミック電極、 16・・・p側パッド電極、 17、18・・・絶縁保護膜、 19・・・ボンディングパッド、 21・・・接続電極、 22・・・外部接続電極(22aはn側、22bはp
側)、 23・・・配線用電極、 24・・・実装基体、 31・・・第1のバンプ、 32・・・第2のバンプ、 41・・・分離溝。
10 ... Active layer, 11 ... Substrate, 12 ... N layer (n-type nitride semiconductor layer), 13 ... P layer (p-type nitride semiconductor layer), 14 ... N-side ohmic contact Electrodes, 15 ... P-side ohmic electrode, 16 ... P-side pad electrode, 17, 18 ... Insulating protective film, 19 ... Bonding pad, 21 ... Connection electrode, 22 ... External connection Electrode (22a is n side, 22b is p
Side), 23 ... Wiring electrode, 24 ... Mounting substrate, 31 ... First bump, 32 ... Second bump, 41 ... Separation groove.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 基板上に半導体素子が形成されてなる発
光素子が実装基体に実装されてなる半導体発光装置にお
いて、前記半導体発光装置は、実装基体と電気的に導通
して接続された正負一対の第1のバンプと、実装基体と
電気的に絶縁して接続された第2のバンプとを有するこ
とを特徴とする半導体発光装置。
1. A semiconductor light emitting device in which a light emitting element having a semiconductor element formed on a substrate is mounted on a mounting base, wherein the semiconductor light emitting device is a pair of positive and negative electrodes electrically connected to the mounting base. And a second bump electrically insulated and connected to the mounting substrate.
【請求項2】 前記半導体発光装置は、基板上に複数の
発光素子を有し、前記第2のバンプは、隣りあった2つ
の半導体素子を電気的に接続する接続電極上に接して形
成されてなることを特徴とする請求項1に記載の半導体
発光装置。
2. The semiconductor light emitting device has a plurality of light emitting elements on a substrate, and the second bump is formed in contact with a connection electrode electrically connecting two adjacent semiconductor elements. The semiconductor light emitting device according to claim 1, wherein:
【請求項3】 前記基板は透光性を有し、光取り出し面
を基板側とする請求項1乃至請求項2のいずれかに記載
の半導体発光装置。
3. The semiconductor light emitting device according to claim 1, wherein the substrate has a light-transmitting property, and the light extraction surface is on the substrate side.
【請求項4】 前記半導体素子は、n型窒化物半導体
層、窒化物半導体活性層、p型窒化物半導体層が順次積
層され、該p型窒化物半導体層および該窒化物半導体活
性層の一部を除去して露出されたn型窒化物半導体層上
にn側オーミック電極が形成され、p型窒化物半導体層
上にp側オーミック電極が形成されてなることを特徴と
する請求項1乃至請求項3のいずれかに記載の半導体発
光装置。
4. The semiconductor device, wherein an n-type nitride semiconductor layer, a nitride semiconductor active layer, and a p-type nitride semiconductor layer are sequentially stacked, and one of the p-type nitride semiconductor layer and the nitride semiconductor active layer is formed. The n-side ohmic electrode is formed on the n-type nitride semiconductor layer exposed by removing the portion, and the p-side ohmic electrode is formed on the p-type nitride semiconductor layer. The semiconductor light emitting device according to claim 3.
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