JP2014199849A - Nitride light-emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a nitride light-emitting element which achieves high light extraction efficiency even in low operation voltage and can be manufactured in a simple process.SOLUTION: A nitride light-emitting element 1 has an n-layer 35, a p-layer 31 and a light emission layer 33 sandwiched between the n-layer 35 and the p-layer 31 on a support substrate 11. The n-layer 35 is constituted of A1GaN(0<x≤1) whose doped Si concentration is 7×10/cmor more.

Description

  The present invention relates to a nitride light emitting device.

  A nitride semiconductor element made of a nitride of a group III element such as Al, Ga, In or the like has an emission layer interposed between an electron supply layer made of an n-type semiconductor and a hole supply layer made of a p-type semiconductor. Used as a light emitting element. More specifically, a voltage is applied between the n-type semiconductor layer and the p-type semiconductor layer, and current flows through the light-emitting layer, so that the region emits light.

  Here, a stacked body of an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer (hereinafter referred to as an “LED layer”) and an electrode (hereinafter referred to as an “layer” above the n-type semiconductor layer). When the resistance value between the electrodes is called “n-side electrode” is high, the voltage necessary for flowing the current necessary for light emission becomes high, and the efficiency is lowered. For this reason, in order to extract a high amount of light with a low operating voltage, it is important to reduce the resistance value between the LED layer and the n-side electrode as much as possible.

  In response to such a problem, Patent Document 1 below discloses that an n-type semiconductor layer includes a high-concentration layer doped with an n-type impurity such as Si at a high concentration, and an n-type impurity at a lower concentration than the high-concentration layer. An LED element formed by sequentially laminating low-concentration layers doped with is disclosed.

JP 2007-258529 A

S. Fritze, et al., “High Si and Ge n-type doping of GaN doping-Limits and impact on stress”, Applied Physics Letters 100, 122104, (2012)

  In order to flow a necessary current to the light emitting layer with an operating voltage as low as possible, it is preferable to reduce the element resistance as much as possible. For this purpose, a method of realizing an ohmic connection between the n layer and the n-side electrode by increasing the doping amount to the n-type semiconductor layer as much as possible can be considered.

Here, when a blue LED is realized as the nitride light emitting element, GaN is generally used as the n-type semiconductor layer. However, it is known that when the concentration of the dopant implanted into the GaN layer is 1 × 10 ¹⁹ / cm ³ or more, film roughness occurs due to the deterioration of the state of atomic bonds. (For example, see Non-Patent Document 1 above). When such a phenomenon occurs, a low-resistance n-layer is not formed, and as a result, the light emission efficiency decreases.

  In Patent Document 1, in order to overcome this problem, a high-concentration n layer and a low-concentration n layer are alternately stacked. According to this document, the surface roughness formed in the high-concentration layer with such a configuration is filled with the low-concentration layer, so that a high-quality n-layer is formed.

  However, when the method described in Patent Document 1 is adopted, it is necessary to sequentially stack a plurality of high-concentration layers and low-concentration layers as n layers, which causes another problem that the process becomes complicated. .

  In view of the above problems, an object of the present invention is to realize a nitride light-emitting element that realizes high light extraction efficiency even at a low operating voltage and can be manufactured by a simple process.

The nitride light emitting device of the present invention is a nitride light emitting device having an n layer, a p layer, and a light emitting layer formed at a position sandwiched between the n layer and the p layer on a support substrate,
The n layer is made of Al _x Ga _1-x N (0 <x ≦ 1) having a doped Si concentration of 7 × 10 ¹⁹ / cm ³ or more.

According to the earnest study of the present inventor, when the n layer is composed of Al _x Ga _1-x N (0 <x ≦ 1) instead of GaN, the doped Si concentration is set to 7 × 10 ¹⁹ / cm ³ or more. It was confirmed that the problem of roughness did not occur. As a result, the resistance value of the n layer can be reduced, so that a current amount necessary for light emission can be passed through the light emitting layer even with a low operating voltage, and the light emission efficiency can be improved.

Furthermore, when realizing the above-described configuration, it is only necessary to form Al _x Ga _1-x N (0 <x ≦ 1) having an Si concentration of 7 × 10 ¹⁹ / cm ³ or more as the n layer. There is no need to alternately stack a plurality of high concentration layers. Therefore, it is possible to manufacture the nitride light emitting device by a simple process without requiring a complicated manufacturing process.

In particular, when the n layer is composed of Al _x Ga _1-x N (0 <x ≦ 1) and the concentration of Si to be doped is 7 × 10 ¹⁹ / cm ³ or more, the n layer is obtained by the inventors' diligent research. It was confirmed that the specific resistance of 1 × 10 ⁻³ Ω · cm or less can be realized. As a result, even if the n layer is about one digit thinner than the conventional one (for example, about 0.1 μm to 0.5 μm), a sufficient amount of current can be passed through the light emitting layer with a low operating voltage.

  In addition, since the n layer can be realized with a low specific resistance value as described above, a metal material (for example, Ti) having a relatively low work function and having a work function of 4.1 eV or less is formed on the upper surface of the n layer. Of course, even if an electrode made of a metal material (for example, Ni) having a work function of 5.0 eV or higher and having a relatively large work function is formed, ohmic connection can be realized by non-annealing.

Conventionally, when the n layer is made of GaN, there is a problem of film roughness, so that a dopant of 1 × 10 ¹⁹ / cm ³ or more cannot be implanted. For this reason, when a metal material having a high work function is formed as an n-side electrode on the upper layer of the n-layer without annealing, the contact resistance between the n-layer and the n-side electrode is derived from a Schottky barrier generated at the interface. Will rise. Therefore, it has been necessary to reduce the contact resistance by performing an annealing process.

  However, in the case of realizing an LED element having a so-called vertical structure in which a voltage is applied to the front and back surfaces of the substrate to supply a current to the light emitting layer, the substrate is bonded through solder such as Au—Sn alloy during the process. Processing is performed. The annealing process usually needs to be performed at a high temperature of 500 ° C. or higher, but this temperature exceeds the melting point of the solder. For this reason, an annealing process cannot be performed in an LED element having a vertical structure. Therefore, the material that can be used as the n-side electrode is limited to a material that can realize ohmic connection without annealing.

  According to this configuration, since a high doping concentration can be realized as the n layer, even a metal material having a relatively high work function can be used as the n-side electrode even when it is realized as a vertical LED element. . For this reason, the range of materials that can be selected as the n-side electrode is widened, and the degree of freedom in element design can be increased.

  According to the nitride light emitting device of the present invention, it becomes possible to reduce the resistance value of the n layer, so that the amount of current necessary for light emission can be passed through the light emitting layer even with a low operating voltage by a simple process. Luminous efficiency can be improved.

It is a schematic sectional drawing of one Embodiment of the nitride light emitting element. The Si concentration is a photograph of the layer surface when a _{^{7 × 10 19 / cm 3 Al}} x Ga 1-x N (0 <x ≦ 1). It is a photograph of the layer surface of GaN when Si concentration is 1.5 × 10 ¹⁹ / cm ³ . Is a graph plotting the Si concentration and the resistivity relationship _Al x _{Ga 1-x} N at room temperature. It is a block diagram of the element for verification for IV characteristic verification. It is a block diagram of the element for verification for IV characteristic verification. It is a graph which shows the IV characteristic when a voltage is applied with respect to each element for verification which varied Si dope density | concentration to n layer. It is a graph which shows the IV characteristic when a voltage is applied with respect to each element for verification in which the thickness of n layer was varied. It is a graph which shows the IV characteristic between n layer and a feed terminal when a feed terminal is directly formed in the verification element which comprised the n layer by GaN. It is a graph which shows the IV characteristic between n layer and a feed terminal when a feed terminal is directly formed in each verification element in which Si dope density | concentration to n layer was varied. It is a graph which shows the IV characteristic between n layer and a feed terminal when a feed terminal is directly formed in each verification element in which Si dope density | concentration to n layer was varied. It is a graph which shows the IV characteristic between n layer and a power supply terminal when a power supply terminal is directly formed in each element for verification which made the metal material which comprises a power supply terminal different. It is a schematic sectional drawing of another one Embodiment of the nitride light emitting element.

  The nitride light emitting device of the present invention will be described with reference to the drawings. In each figure, the dimensional ratio in the drawing does not necessarily match the actual dimensional ratio.

[Construction]
An example of the structure of the nitride light emitting device of the present invention will be described with reference to FIG. FIG. 1 is a schematic cross-sectional view of an embodiment of a nitride light emitting device.

  The nitride light emitting device 1 includes a support substrate 11, a conductive layer 20, an insulating layer 21, an LED layer 30, and a power supply terminal 42. The LED layer 30 is formed by laminating a p layer 31, a light emitting layer 33, and an n layer 35 in this order from the bottom.

(Support substrate 11)
The support substrate 11 is composed of a conductive substrate such as CuW, W, or Mo, or a semiconductor substrate such as Si.

(Conductive layer 20)
A conductive layer 20 having a multilayer structure is formed on the support substrate 11. In the present embodiment, the conductive layer 20 includes a solder layer 15, a protective layer 17, and a reflective electrode 19.

  The solder layer 15 is made of, for example, Au—Sn, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like. The solder layer 15 is used when the sapphire substrate and the support substrate 11 are bonded as described later in the section of the manufacturing method (see step S5).

  The protective layer 17 is made of, for example, a Pt-based metal (an alloy of Ti and Pt), W, Mo, Ni, or the like. As will be described later, when bonding two substrates through a solder layer during the process, the material constituting the solder diffuses to the reflective electrode 19 side, which will be described later, and prevents a decrease in luminous efficiency due to a drop in reflectance. Plays a function.

  The reflective electrode 19 is made of, for example, an Ag-based metal (an alloy of Ni and Ag), Al, Rh, or the like. It is assumed that the nitride light emitting device 1 takes out the light emitted from the light emitting layer 33 of the LED layer 30 in the upward direction (n layer 35 side) of FIG. The light emitted downward is reflected upward to fulfill the function of increasing luminous efficiency.

  The conductive layer 20 is partly in contact with the LED layer 30, more specifically the p layer 31, and when a voltage is applied between the support substrate 11 and the power supply terminal 42, the support substrate 11, the conductive layer 20, a current path that flows to the power supply terminal 42 via the LED layer 30 is formed.

(Insulating layer 21)
Insulating layer 21 is composed for example _{SiO 2, SiN, Zr 2 O} 3, AlN, etc. _Al 2 _{O 3.} The insulating layer 21 has an upper surface in contact with the bottom surface of the p layer 31. As will be described later, the insulating layer 21 has a function as an etching stopper layer at the time of element isolation, and also has a function of spreading current in a direction parallel to the substrate surface of the support substrate 11.

(LED layer 30)
As described above, the LED layer 30 is formed by laminating the p layer 31, the light emitting layer 33, and the n layer 35 in this order from the bottom.

The p layer 31 has a multilayer structure including, for example, a layer (hole supply layer) made of Al _y Ga _1-y N (0 <y ≦ 1) and a layer (protective layer) made of GaN. . Both layers are doped with p-type impurities such as Mg, Be, Zn, and C.

  The light emitting layer 33 is formed of a semiconductor layer having a multiple quantum well structure in which, for example, a well layer made of InGaN and a barrier layer made of AlGaN are repeated. These layers may be undoped or p-type or n-type doped.

The n layer 35 includes a layer (protective layer) made of GaN in a region in contact with the light emitting layer 33, and a layer (electron) made of Al _x Ga _1-x N (0 <x ≦ 1) on the upper layer. Supply layer). At least the protective layer is doped with an n-type impurity such as Si, Ge, S, Se, Sn, or Te, and is preferably doped with Si. Note that the n layer 35 may be composed of only an electron supply layer composed of Al _x Ga _1-x N (0 <x ≦ 1).

Further, the n layer 35 composed of Al _x Ga _1-x N (0 <x ≦ 1) is doped with impurities so that the doped Si concentration is 7 × 10 ¹⁹ / cm ³ or more. . As will be described later based on photographs obtained through experiments, in this configuration, the impurity concentration of the n layer 35 is greater than 1 × 10 ¹⁹ / cm ³ (for example, 7 × 10 ¹⁹ / cm ³ or more). However, film roughening does not occur.

(Power supply terminal 42)
The power supply terminal 42 is formed in the upper layer of the n layer 35 and is made of, for example, Cr—Au. The power supply terminal 42 is connected to a wire made of, for example, Au or Cu (not shown), and the other end of the wire is connected to a power supply pattern on the substrate on which the nitride light emitting element 1 is disposed. (Not shown).

  As will be described later with reference to experimental data, in this configuration, an ohmic connection is formed in the n layer 35 and the power supply terminal 42, and a reduction in resistance between the two is realized.

Although not shown, an insulating layer as a protective film may be formed on the side surface and the upper surface of the LED layer 30. Note that the insulating layer as the protective film is preferably made of a light-transmitting material (eg, SiO ₂ ).

In the above-described embodiment, one material constituting the p layer 31 is described as Al _y Ga _1-y N (0 <y ≦ 1), and one material constituting the n layer 35 is Al _x Ga _1-x N ( Although described as 0 <x ≦ 1), these may be the same material.

[Verification of film roughness]
Next, as in the nitride light-emitting element 1, the n layer 35 is composed of Al _x Ga _1-x N (0 <x ≦ 1), so that the doped Si concentration is 1 × 10 ¹⁹ / cm ³ . The fact that the film roughness does not occur even if it is increased will be described with reference to the experimental data of FIGS. 2A and 2B. Hereinafter, Al _x Ga _1-x N (0 <x ≦ 1) is abbreviated as Al _x Ga _1-x N.

FIG. 2A is a photograph of the Al _x Ga _1-x N layer surface when the Si concentration is 7 × 10 ¹⁹ / cm ³ . FIG. 2B is a photograph of the surface of the GaN layer when the Si concentration is 1.5 × 10 ¹⁹ / cm ³ . 2A is taken with an AFM (Atomic Force Microscopy), and FIG. 2B is taken with an SEM (Scanning Electron Microscope).

As shown in FIG. 2B, when the n layer is composed of GaN, it can be seen that the surface is roughened when the Si concentration is 1.5 × 10 ¹⁹ / cm ³ . In addition, even when the impurity concentration was 1.3 × 10 ¹⁹ / cm ³ and 2.0 × 10 ¹⁹ / cm ³ , surface roughness was confirmed in the same manner. From this, it can be seen that, as described in Non-Patent Document 1, in GaN, if it is larger than 1 × 10 ¹⁹ / cm ³ , the layer surface is roughened.

On the other hand, according to FIG. 2A, when the n layer is composed of Al _x Ga _1-x N, a stepped surface (atomic step) is confirmed even when the Si concentration is 7 × 10 ¹⁹ / cm ³ . It can be seen that the surface of the layer is not rough. Even when the Si concentration was 2 × 10 ²⁰ / cm ³ , a photograph similar to FIG. 2A was obtained. Further, it was confirmed that even when the component ratio of Al and Ga was changed as a constituent material (Al _x Ga _1-x N), the surface of the layer was not similarly roughened.

On the other hand, even when the n layer is made of GaN and the Si concentration is 0.5 × 10 ¹⁹ / cm ³ , that is, when the Si concentration is 1 × 10 ¹⁹ / cm ³ or less, a photograph similar to FIG. 2A was obtained. .

From the above, it can be seen that the problem of film roughness does not occur even if the Si concentration is 7 × 10 ¹⁹ / cm ³ or more by configuring the n layer with Al _x Ga _1-x N. This point is also apparent from the data relating to the specific resistance described later.

[Verification of resistivity]
FIG. 3 is a graph plotting the relationship between the Si concentration of Al _x Ga _1-x N and the specific resistance when the Si concentration of Al _x Ga _1-x N is changed at room temperature. The specific resistance was measured using a commonly used Hall measuring device.

According to FIG. 3, it can be seen that the specific resistance decreases as the concentration of Si doped in Al _x Ga _1-x N increases. When film roughness occurs, the resistance value increases due to the roughness, and therefore it is assumed that the specific resistance increases at the Si doping concentration value where the film roughness occurs. That is, according to this result, it is suggested that even when the Si concentration is increased to 2 × 10 ²⁰ / cm ³ , no film roughness occurs in Al _x Ga _1-x N.

Note that when the Si doping concentration is set to 9 × 10 ¹⁸ / cm ^{3, which} is approximately the upper limit of 1 × 10 ¹⁹ / cm ³ , which does not cause film roughness, the specific resistance of the GaN is 5 × 10 ^−3. It was Ω · cm. In other words, when GaN is used as the n layer, the specific resistance cannot be lowered more than this value.

According to FIG. 3, by using Al _x Ga _1-x N as the n layer 35, the specific resistance is 1 × 10 ⁻³ Ω · cm when the Si doping concentration is 7 × 10 ¹⁹ / cm ^3. Therefore, the lower limit of the specific resistance of the conventional GaN can be greatly reduced. When Al _x Ga _1-x N is used as the n layer 35 and the Si doping concentration is 2 × 10 ²⁰ / cm ³ , the specific resistance may be 4.5 × 10 ⁻⁴ Ω · cm. The specific resistance value is much lower than the lower limit of the conventional configuration.

[Verification of IV characteristics]
Next, Al _x Ga _1-x N is used as the n layer 35, and the Si doping concentration is set to 7 × 10 ¹⁹ / cm ³ or more, whereby a current necessary for light emission is caused to flow through the element at an operating voltage lower than that in the past. The possible points will be described with reference to examples.

  4A and 4B are examples of elements formed for IV characteristic verification. Note that the element 2A shown in FIG. 4A and the element 2B shown in FIG. 4B are for verifying the relationship between the current I flowing in the n layer 35 and the voltage V when the voltage V is applied to the n layer 35. It is an element. For this reason, unlike the nitride light-emitting element 1, the element was configured in a range necessary for verification.

In the verification element 2A shown in FIG. 4A, an n layer 35 is formed on an upper layer of a sapphire substrate 61 via an undoped layer 36, and two feeding terminals 42 are formed on the upper layer. The n layer 35 is composed of Al _x Ga _1-x N, and Example 1, Example 2, and Comparative Example 1 were produced on the assumption that the Si concentration to be doped was changed.

In the verification element 2B shown in FIG. 4B, an n layer 95 is formed on the sapphire substrate 61 via an undoped layer 36, and two feeding terminals 42 are formed on the n layer 95. The n layer 95, Example 1, Example 2, and Comparative Example constituted by a thick film having a thickness GaN than 1, film roughness the Si concentration to be doped is a value in the vicinity of the upper limit value that does not cause 9 × 10 ¹⁸ A conventional example was prepared as / cm ³ .

  7A to 7C, which will be described later, in the verification element 2A, an ohmic connection is formed even if the power supply terminal 42 made of a metal material is directly formed on the upper surface of the n layer 35. The On the other hand, in the verification element 2B, the ohmic connection is not formed only by directly forming the electrode 42 on the upper surface of the n layer 95, and an annealing process is required to form the ohmic connection.

  In FIGS. 5 and 6 described later, the purpose is to measure the relationship between the voltage applied to the n layer 35 and the n layer 95 and the current. For this reason, both graphs are measured in a state where an ohmic connection is formed between the power supply terminal 42 and the n layer 35 and between the power supply terminal 42 and the n layer 95. Specifically, the graphs of FIGS. 5 and 6 show the verification element 2A in which the power supply terminal 42 is formed directly on the upper layer of the n layer 35, and the verification in which the power supply terminal 42 is formed after the n layer 95 is annealed. It was measured using the element 2B for use.

Example 1
A verification element 2A in which the n layer 35 is formed of Al _x Ga _1-x N with a Si doping concentration of 7 × 10 ¹⁹ / cm ³ and a film thickness of 500 nm was taken as Example 1. The specific resistance at this time was 1 × 10 ⁻³ Ω · cm.
(Example 2)
A verification element 2A in which the n layer 35 is formed of Al _x Ga _1-x N with a Si doping concentration of 2 × 10 ²⁰ / cm ³ and a film thickness of 500 nm was taken as Example 2. The specific resistance at this time was 5 × 10 ⁻⁴ Ω · cm.
(Comparative Example 1)
A verification element 2A in which the n layer 35 is formed of Al _x Ga _1-x N having a Si doping concentration of 1.5 × 10 ¹⁹ / cm ³ and a film thickness of 500 nm is referred to as Comparative Example 1. The specific resistance at this time was 5 × 10 ⁻³ Ω · cm.
(Conventional example)
The verification element 2B in which the Si layer concentration is 9 × 10 ¹⁸ / cm ³ , the film thickness is 3 μm, that is, the n-layer 95 is formed of GaN having a thicker film thickness than those of Example 1, Example 2, and Comparative Example 1, did. The specific resistance at this time was 5 × 10 ⁻³ Ω · cm.

  FIG. 5 is a graph showing the relationship of the current I that flows when the voltage V is applied to the power supply terminal 42 for each of the verification elements of Example 1, Example 2, Comparative Example 1, and the conventional example.

According to FIG. 5, even when the n layer 35 is made of Al _x Ga _1-x N, the Si doping concentration is 1.5 × 10 ¹⁹ / cm ³ , which shows a specific resistance equal to that of the conventional example. In Comparative Example 1, it can be seen that the operating voltage is higher than in the conventional example. This result is considered to be caused by the increase in the resistance value of the n layer 35 because the thickness of the n layer 35 is 500 nm and the n layer 35 is formed with a thickness smaller than 3 μm of the conventional n layer 95.

On the other hand, Example 1 in which the n layer 35 is composed of Al _x Ga _1-x N and the Si doping concentration is 7 × 10 ¹⁹ / cm ³ and the Si doping concentration is 2 × 10 ²⁰ / cm ^3. According to the graph, it is understood that the operating voltage is lower than that of the conventional example even though the n layer 35 is realized with a thickness of 500 nm, which is about one digit thinner than the n layer 95 of the conventional example.

As described above, the specific resistance of the verification element 2A of Example 1 is 1 × 10 ⁻³ Ω · cm, and the specific resistance of the verification element 2A of Example 2 is 5 × 10 ⁻⁴ Ω · cm. It was. That is, the n layer 35 is composed of Al _x Ga _1-x N, and the Si layer concentration is set so that the specific resistance is 1 × 10 ⁻³ Ω · cm or less. It can be seen that even if it is realized with a small film thickness, a necessary current can be supplied with an operating voltage equivalent to or lower than that of the conventional n layer 95.

Next, in the above-described verification element 2A, the concentration of Al _x Ga _1-x N constituting the n layer 35 is changed in the same manner as in Example 2 to change the film thickness. Then, an element of Comparative Example 2 was produced.

(Example 3)
A verification element 2A in which the n layer 35 is formed of Al _x Ga _1-x N having a Si doping concentration of 2 × 10 ²⁰ / cm ^3, which is the same as in Example 2, and a film thickness of 300 nm, was taken as Example 3. Since this element had the same Si doping concentration as in Example 2, the specific resistance was 5 × 10 ⁻⁴ Ω · cm as in Example 2.

Example 4
A verification element 2A in which the n layer 35 is formed of Al _x Ga _1-x N having a Si doping concentration of 2 × 10 ²⁰ / cm ^3, which is the same as that of Example 2, and a film thickness of 100 nm was taken as Example 4. Since this element had the same Si doping concentration as in Example 2, the specific resistance was 5 × 10 ⁻⁴ Ω · cm as in Example 2.

(Comparative Example 2)
The verification element 2A in which the n layer 35 is formed of Al _x Ga _1-x N with the Si doping concentration of 2 × 10 ²⁰ / cm ^3, which is the same as that of Example 2, and with a film thickness of 10 nm is referred to as Comparative Example 2. Since this element had the same Si doping concentration as in Example 2, the specific resistance was 5 × 10 ⁻⁴ Ω · cm as in Example 2.

  FIG. 6 is a graph showing the relationship of the current I that flows when the voltage V is applied to the power supply terminal 42 with respect to each verification element of Example 2, Example 3, Example 4, and Comparative Example 2 described above. .

According to FIG. 6, in Comparative Example 2 in which the thickness of the n layer 35 is as thin as 10 nm, Al _x Ga _1-x N in which the Si doping concentration of the n layer 35 is increased to 2 × 10 ²⁰ / cm ^3. Even if it comprises, the operating voltage is quite high. On the other hand, in Example 4 in which the film thickness of the n layer 35 is 100 nm, Example 3 in which the film thickness is 300 nm, and Example 2 in which the film thickness is 500 nm, it is possible to realize an operating voltage that is approximately the same. This shows that the thickness of the n layer 35 is preferably 100 nm or more.

  According to the graph of FIG. 6, referring to Example 3 in which the film thickness of the n layer 35 is 300 nm and Example 2 in which the film thickness of the n layer 35 is 500 nm, as the film thickness of the n layer 35 is increased, It can be seen that the operating voltage can be further reduced. Also in Example 2, the n layer 35 can be realized with a film thickness that is one digit smaller than the n layer 95 of the conventional example, and this can be expected to improve the productivity of the nitride light emitting device 1.

That is, according to FIG. 5 and FIG. 6, by forming the n layer 35 with Al _x Ga _1-x N having a Si doping concentration of 7 × 10 ¹⁹ / cm ³ or more, 1 × 10 ⁻³ Ω · cm or less. The specific resistance can be realized. That is, a specific resistance value much lower than that of a conventional n layer made of GaN is realized. As a result, even if the n-layer 35 is realized with a film thickness value in a range in which the operating voltage is extremely high in the conventional GaN, such as a film thickness of 100 nm to 500 nm, a necessary current flows at a low operating voltage. It becomes possible.

Since the operating voltage decreases as the thickness of the n layer 35 increases, the nitride light-emitting element 1 can be formed of Al _x Ga _1-x N with a thickness of the n layer 35 of 100 nm or more. .

[Verification of ohmic characteristics]
FIG. 7A to FIG. 7C show the power supply directly to the upper layer without annealing the n layer (35/95) for each of the verification elements of the conventional example, the first example, and the second example described above. 6 is a graph obtained by measuring a relationship between a current flowing through an n layer (35/95) and a voltage when a voltage is applied to the power feeding terminal when the terminal is formed.

  Each of the graphs of FIGS. 7A to 7C shows a metal in which Ti having a thickness of 30 nm and Pt having a thickness of 30 nm are stacked as the power supply terminal 42 in any of the verification elements of the conventional example, Example 1 and Example 2. Material was used.

  FIG. 7A shows the IV characteristic of the conventional example. FIG. 7B shows the IV characteristics of the conventional example, Example 1, and Example 2 when the applied voltage is in the range of −0.3V to 0.3V. FIG. 7C shows the IV characteristics of Example 1 and Example 2 when the applied voltage is in the range of −0.001 V or more and 0.001 V or less. In view of the difference in the scale of the applied voltage, it is divided into three diagrams of FIGS.

  According to FIG. 7A, it can be seen that the applied voltage and the current are not in a proportional relationship, and that the ohmic connection is not formed in the conventional verification element. On the other hand, according to FIG. 7B and FIG. 7C, in the verification elements of Example 1 and Example 2, the current value rises steeply when the applied voltage is approximately 0 V, and an ohmic connection is formed. I understand that

That is, by configuring the n layer 35 with Al _x Ga _1-x N, Si can be doped at a high concentration of 7 × 10 ¹⁹ / cm ³ or more. As a result, the upper surface of the n layer 35 is composed of Ti / Pt. It can be seen that an ohmic connection is formed even if the feeding terminal 42 is directly formed.

On the other hand, when the n layer 95 is made of GaN as in the prior art, in order to obtain a Si doping concentration within a range where the problem of film roughness does not occur, a neighborhood value of 1 × 10 ¹⁹ / cm ³ (here, A value of 9 × 10 ¹⁸ / cm ³ is employed)). 7A to 7C, at this Si doping concentration of 9 × 10 ¹⁸ / cm ³ , an ohmic connection can be achieved only by directly forming the power supply terminal 42 made of Ti / Pt on the upper surface of the n layer 95. It can be seen that it is not formed. For this reason, in the conventional configuration, when the power supply terminal 42 is formed of Ti / Pt, an annealing process for forming an ohmic connection is indispensable.

  By the way, when the nitride light emitting device 1 is formed as a so-called vertical LED device as shown in FIG. 1, a substrate bonding process is performed through solder such as an Au—Sn alloy during the process (described later). Step S5). The annealing process usually needs to be performed at a high temperature of 500 ° C. or higher, but this temperature exceeds the melting point of the solder. For this reason, an annealing process cannot be performed in an LED element having a vertical structure.

  In other words, in view of this point, Ti / Pt cannot be used as the power supply terminal 42 when the n layer 95 is made of GaN to achieve a vertical LED element. That is, in the conventional configuration, the power supply terminal 42 is limited to a material that can realize ohmic connection without performing annealing.

On the other hand, the nitride light emitting device 1 includes the n layer 35 made of Al _x Ga _1-x N, so that the n layer 35 can be doped with Si at a high concentration of 7 × 10 ¹⁹ / cm ³ or more. . As a result, a metal material that conventionally requires an annealing process to form an ohmic connection with the n layer can also be used as a material for the power supply terminal 42 without performing the annealing process. Therefore, the range of selection of materials that can be used as the power supply terminal 42 is widened, and the annealing process is not necessary, so that the process can be simplified.

FIG. 8 is a graph showing IV characteristics between the n layer 35 and the power supply terminal 42 when the power supply terminal 42 is directly formed on each verification element in which the metal material constituting the power supply terminal is different. Here, as the verification element, the verification element 2A in which the n layer 35 is configured by Al _x Ga _1-x N having a Si doping concentration of 2.0 × 10 ²⁰ / cm ³ and a film thickness of 500 nm was used. .

(Example 5)
As the power supply terminal 42, a metal material in which Ti with a film thickness of 30 nm and Pt with a film thickness of 30 nm were stacked was used. The work function of Ti is 4.1 eV.
(Example 6)
As the power supply terminal 42, Ag having a film thickness of 100 nm was used. Note that the work function of Ag is 4.3 eV.
(Example 7)
As the power supply terminal 42, a metal material in which Cr having a film thickness of 10 nm and Au having a film thickness of 100 nm were stacked was used. The work function of Cr is 4.5 eV.
(Example 8)
As the power supply terminal 42, a metal material in which Ni having a thickness of 10 nm and Au having a thickness of 10 nm were stacked was used. Note that the work function of Ni is 5.3 eV.

As can be seen from FIG. 8, in all of Examples 5 to 8, an ohmic connection between the power supply terminal 42 and the n layer 35 is formed. In particular, in Example 8, even when a material such as Ni having a relatively high work function is used as the power supply terminal 42, ohmic connection is obtained only by forming the power supply terminal 42 directly on the upper surface of the n layer 35. . This is because, as a result of realizing the n layer 35 with Al _x Ga _1-x N, the Si doping concentration can be made high concentration of 7 × 10 ¹⁹ / cm ³ or more. It is presumed that it was realized.

[Production method]
Next, an example of a method for manufacturing the nitride light emitting device 1 will be described. In addition, dimensions such as manufacturing conditions and film thickness described in the following manufacturing method are merely examples, and are not limited to these numerical values.

(Step S1)
An LED epi layer is formed on the sapphire substrate. This step is performed, for example, according to the following procedure.

<Preparation of sapphire substrate>
First, the c-plane sapphire substrate is cleaned. More specifically, for this cleaning, for example, a c-plane sapphire substrate is placed in a processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and hydrogen gas with a flow rate of 10 slm is placed in the processing furnace. The temperature in the furnace is raised to, for example, 1150 ° C. while flowing.

<Formation of undoped layer>
Next, a low-temperature buffer layer made of GaN is formed on the surface of the c-plane sapphire substrate, and an underlayer made of GaN is further formed thereon. These low-temperature buffer layer and underlayer correspond to the undoped layer.

  A more specific method for forming the undoped layer is, for example, as follows. First, the furnace pressure of the МОCVD apparatus is 100 kPa, and the furnace temperature is 480 ° C. Then, while flowing nitrogen gas and hydrogen gas having a flow rate of 5 slm respectively as carrier gases into the processing furnace, trimethylgallium having a flow rate of 50 μmol / min and ammonia having a flow rate of 250,000 μmol / min are fed into the processing furnace for 68 seconds. Supply. Thereby, a low-temperature buffer layer made of GaN having a thickness of 20 nm is formed on the surface of the c-plane sapphire substrate.

  Next, the furnace temperature of the MOCVD apparatus is raised to 1150 ° C. Then, while flowing nitrogen gas with a flow rate of 20 slm and hydrogen gas with a flow rate of 15 slm as a carrier gas in the processing furnace, trimethylgallium with a flow rate of 100 μmol / min and ammonia with a flow rate of 250,000 μmol / min are supplied into the processing furnace. For 30 minutes. As a result, a base layer made of GaN having a thickness of 1.7 μm is formed on the surface of the low-temperature buffer layer.

<Formation of n layer 35>
Next, an n layer 35 having a composition of Al _x Ga _1-x N (0 <x ≦ 1) is formed on the undoped layer. If necessary, a protective layer made of n-type GaN may be formed thereon.

A more specific method for forming the n layer 35 is, for example, as follows. First, the furnace pressure of the MOCVD apparatus is set to 30 kPa. Then, while a nitrogen gas having a flow rate of 20 slm and a hydrogen gas having a flow rate of 15 slm are allowed to flow into the processing furnace, trimethylgallium having a flow rate of 94 μmol / min, trimethylaluminum having a flow rate of 6 μmol / min, Ammonia of 250,000 μmol / min and tetraethylsilane having a flow rate of 0.08 μmol / min are supplied into the treatment furnace for 30 minutes. Thus, a high concentration electron supply layer having a composition of Al _0.06 Ga _0.94 N, a doped Si concentration of 7 × 10 ¹⁹ / cm ³ and a thickness of 500 nm is formed on the undoped layer.

  In the case of forming a protective layer made of GaN, the supply of trimethylaluminum is then stopped and another source gas is supplied for 6 seconds, so that the upper layer of the electron supply layer is made of n-type GaN having a thickness of 5 nm. A protective layer is formed.

<Formation of the light emitting layer 33>
Next, a light emitting layer 33 having a multiple quantum well structure in which a well layer made of InGaN and a barrier layer made of AlGaN are periodically repeated is formed on the n layer 35.

  A more specific method for forming the light emitting layer 33 is, for example, as follows. First, the furnace pressure of the MOCVD apparatus is 100 kPa, and the furnace temperature is 830 ° C. Then, while a nitrogen gas having a flow rate of 15 slm and a hydrogen gas having a flow rate of 1 slm are allowed to flow into the processing furnace, trimethylgallium having a flow rate of 10 μmol / min, trimethylindium having a flow rate of 12 μmol / min, and a flow rate of A step of supplying 300,000 μmol / min of ammonia into the processing furnace for 48 seconds is performed. Thereafter, a step of supplying trimethylgallium having a flow rate of 10 μmol / min, trimethylaluminum having a flow rate of 1.6 μmol / min, tetraethylsilane having a flow rate of 0.002 μmol / min and ammonia having a flow rate of 300,000 μmol / min into the processing furnace for 120 seconds is performed. . Hereinafter, by repeating these two steps, the light emitting layer 33 having a multi-quantum well structure of 15 periods with a well layer made of InGaN having a thickness of 2 nm and a barrier layer made of AlGaN having a thickness of 7 nm is obtained. Formed on the surface.

<Formation of p layer 31>
Next, a layer (hole supply layer) composed of Al _y Ga _1-y N (0 <y ≦ 1) is formed on the light emitting layer 33, and a layer composed of GaN is further formed on the layer (hole supply layer). Protective layer). These hole supply layer and protective layer correspond to the p layer 31.

A more specific method for forming the p layer 31 is, for example, as follows. First, the furnace pressure of the MOCVD apparatus is maintained at 100 kPa, and the furnace temperature is raised to 1050 ° C. while nitrogen gas with a flow rate of 15 slm and hydrogen gas with a flow rate of 25 slm are allowed to flow into the processing furnace. Thereafter, trimethylgallium having a flow rate of 35 μmol / min, trimethylaluminum having a flow rate of 20 μmol / min, ammonia having a flow rate of 250,000 μmol / min, and biscyclopentadienyl having a flow rate of 0.1 μmol / min as raw material gases in the processing furnace. Supply for 60 seconds. Thereby, a hole supply layer having a composition of Al _0.3 Ga _0.7 N having a thickness of 20 nm is formed on the surface of the light emitting layer 33. Thereafter, by changing the flow rate of trimethylaluminum to 9 μmol / min and supplying a source gas for 360 seconds, a hole supply layer having a composition of Al _0.13 Ga _0.87 N having a thickness of 120 nm is formed.

  Thereafter, the supply of trimethylaluminum is stopped, the flow rate of biscyclopentadienyl is changed to 0.2 μmol / min, and the source gas is supplied for 20 seconds, whereby a contact layer made of p-type GaN having a thickness of 5 nm. Form.

  Note that magnesium (Mg), beryllium (Be), zinc (Zn), carbon (C), or the like can be used as the p-type impurity.

  In this way, an LED epilayer comprising the undoped layer, the n layer 35, the light emitting layer 33, and the p layer 31 is formed on the sapphire substrate.

(Step S2)
Next, an activation process is performed on the wafer obtained in step S1. More specifically, activation is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal) device.

(Step S3)
Next, the insulating layer 21 is formed at a predetermined location on the upper layer of the p layer 31. More specifically, it is preferable to form the insulating layer 21 at a position located below a region where the power supply terminal 42 is formed in a later step. As the insulating layer 21, for example, SiO ₂ is formed to a thickness of about 200 nm. Note that the material for forming the film may be an insulating material, such as SiN or Al ₂ O ₃ .

(Step S4)
Conductive layer 20 is formed so as to cover the upper surfaces of p layer 31 and insulating layer 21. Here, the conductive layer 20 having a multilayer structure including the reflective electrode 19, the protective layer 17, and the solder layer 15 is formed.

  A more specific method for forming the conductive layer 20 is, for example, as follows. First, a reflective electrode 19 is formed by depositing a 0.7 nm-thickness Ni and a 120 nm-thickness Ag on the entire surface so as to cover the upper surfaces of the p-layer 31 and the insulating layer 21 by a sputtering apparatus. Next, contact annealing is performed at 400 ° C. for 2 minutes in a dry air atmosphere using an RTA apparatus.

  Next, the protective layer 17 is formed by depositing 100 nm of Ti and 200 nm of Pt on the upper surface (Ag surface) of the reflective electrode 19 for three periods with an electron beam evaporation apparatus (EB apparatus). . Further, after depositing Ti with a thickness of 10 nm on the upper surface (Pt surface) of the protective layer 17, Au-Sn solder composed of Au 80% Sn 20% is deposited with a thickness of 3 μm, thereby forming the solder layer 15. Form.

  In the step of forming the solder layer 15, a solder layer may be formed on the upper surface of the support substrate 11 prepared separately from the sapphire substrate. This solder layer may be made of the same material as the solder layer 15. For example, CuW is used as the support substrate 11 as described in the section of the structure.

(Step S5)
Next, the sapphire substrate and the support substrate 11 are bonded together. More specifically, the solder layer 15 and the support substrate 11 are bonded together at a temperature of 280 ° C. and a pressure of 0.2 MPa.

(Step S6)
Next, the sapphire substrate is peeled off. More specifically, with the sapphire substrate facing up and the support substrate 11 facing down, the sapphire substrate is irradiated with KrF excimer laser from the sapphire substrate side to decompose the interface between the sapphire substrate and the LED epilayer. Peeling off. While sapphire passes through the laser, GaN (undoped layer) under the sapphire absorbs the laser, and this interface is heated to decompose GaN. As a result, the sapphire substrate is peeled off.

  Thereafter, GaN (undoped layer) remaining on the wafer is removed by wet etching using hydrochloric acid or the like, and dry etching using an ICP apparatus, and the n layer 35 is exposed.

(Step S7)
Next, adjacent elements are separated. Specifically, the LED layer 30 is etched using the ICP device until the upper surface of the insulating layer 21 is exposed in the boundary region with the adjacent element. Thereby, the LED layers 30 in the adjacent regions are separated from each other. At this time, the insulating layer 21 functions as an etching stopper layer.

  In this etching process, it is preferable that the side surface of the element is not vertical but is an inclined surface having a taper angle of 10 ° or more. By doing in this way, when forming an insulating layer at a later step, the insulating layer is likely to adhere to the side surface of the LED layer 30, and current leakage can be prevented.

  In addition, after step S7, an uneven surface may be formed on the upper surface of the LED layer 30 with an alkaline solution such as KOH. Thereby, the light extraction area can be increased and the light extraction efficiency can be improved.

(Step S8)
Next, the power supply terminal 42 is formed on the upper surface of the n-type 35. More specifically, the power supply terminal 42 made of Ni having a thickness of 10 nm and Au having a thickness of 10 nm is formed. As described above, after this step, ohmic connection is formed without performing annealing treatment.

As a subsequent process, the exposed element side surface and the element upper surface other than the power supply terminal 42 are covered with an insulating layer. More specifically, an SiO ₂ film is formed by an EB apparatus. An SiN film may be formed. Then, the elements are separated from each other by, for example, a laser dicing apparatus, the back surface of the support substrate 11 is joined to the package by, for example, Ag paste, and wire bonding is performed to the power supply terminal 42.

[Another embodiment]
Hereinafter, another embodiment will be described.

  <1> Although FIG. 1 has been described assuming a so-called vertical structure LED element as the nitride light-emitting element 1, as shown in FIG. 9, the nitride light-emitting element 1 is realized as a horizontal structure LED element. It doesn't matter.

  The nitride light emitting device 1 shown in FIG. 9 has an undoped layer 13 on a sapphire substrate 61, and an n layer 35, a light emitting layer 33, and a p layer 31 are stacked on the sapphire substrate 61 in this order from the bottom. ing. A part of the upper surface of the n layer 35 is exposed, and a power supply terminal 42 is formed on the upper layer of the exposed surface of the n layer 35 and on the upper surface of the p layer 31.

Also in this configuration, the element resistance is reduced by realizing the doped n layer 35 with Al _x Ga _1-x N (0 <x ≦ 1) in which the Si concentration of the doped n layer 35 is 7 × 10 ¹⁹ / cm ³ or more. Thus, the same effects as those of the vertical nitride light emitting element 1 described above are realized.

  When forming the nitride light emitting device 1 shown in FIG. 9, etching is performed after steps S1 to S2 described above until a partial upper surface of the n layer 35 is exposed from the p layer 31 side. Thereafter, the power supply terminal 42 is formed on the upper surface of the p layer 31 and a partial upper surface of the n layer 35 by performing the same process as in step S8.

  In the nitride light emitting device 1 of FIG. 9, the reflective electrode 19 may be formed on the back side of the sapphire substrate 61. Further, an insulating layer that covers the upper surface of the LED layer 30 excluding the upper surface of the power supply terminal 42 and the side surface of the LED layer 30 may be formed.

  <2> The structure shown in FIG. 1 and the manufacturing method described above are examples of a preferred embodiment and do not have to include all of these configurations and processes.

  For example, the solder layer 15 is formed so as to efficiently bond two substrates, and if the bonding of the two substrates can be realized, the function of the nitride light emitting device 1 is not necessarily realized. It is not necessary.

  The reflective electrode 19 is preferably provided in the sense of further improving the extraction efficiency of light emitted from the light emitting layer 33, but is not necessarily provided. The same applies to the protective layer 17 and the like.

  Further, although the insulating layer 21 is formed to function as an etching stopper layer at the time of element isolation in step S7, it is not necessarily provided. However, the effect of spreading the current in a direction parallel to the substrate surface of the support substrate 11 can be expected by forming the insulating layer 21 at a position facing the power supply terminal 42 in a direction orthogonal to the substrate surface of the support substrate 11. .

However, according to the above configuration, by realizing the n layer 35 with Al _x Ga _1-x N (0 <x ≦ 1) having a Si concentration of 7 × 10 ¹⁹ / cm ³ or more, 1 × 10 ⁻³ Ω Since a specific resistance of cm or less can be realized, the n layer 35 can be formed with a thin film thickness of about 100 nm to 500 nm. Accordingly, since the n layer 35 has a function of spreading the current in a direction parallel to the substrate surface of the support substrate 11 as compared with the conventional configuration, the insulating layer 21 is not necessarily provided in order to obtain a current spreading effect. . However, the insulating layer 21 may be provided for the purpose of further enhancing the current spreading effect.

1: Support substrate 2A: Verification element 2B: Verification element 13: Undoped layer 15: Solder layer 17: Protective layer 19: Reflective electrode 20: Conductive layer 21: Insulating layer 30: LED layer 31: P layer 33: Light emitting layer 35: n layer _{(Al x Ga 1-x n} )
36: Undoped layer 42: Feeding terminal 61: Sapphire substrate 95: N layer (GaN)

Claims (4)

A nitride light-emitting element having an n layer, a p layer, and a light emitting layer formed at a position sandwiched between the n layer and the p layer on a support substrate,
The nitride light-emitting element, wherein the n layer is made of Al _x Ga _1-x N (0 <x ≦ 1) having a doped Si concentration of 7 × 10 ¹⁹ / cm ³ or more. 2. The nitride light emitting device according to claim 1, wherein the n layer has a specific resistance of 1 × 10 ⁻³ Ω · cm or less.   The nitride light-emitting element according to claim 1, wherein the n layer has a thickness of 100 nm or more.   The nitride light emitting device according to claim 3, wherein the n layer has a thickness of 100 nm to 500 nm.

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