WO2015029727A1 - Semiconductor light emitting element - Google Patents

Semiconductor light emitting element Download PDF

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Publication number
WO2015029727A1
WO2015029727A1 PCT/JP2014/070711 JP2014070711W WO2015029727A1 WO 2015029727 A1 WO2015029727 A1 WO 2015029727A1 JP 2014070711 W JP2014070711 W JP 2014070711W WO 2015029727 A1 WO2015029727 A1 WO 2015029727A1
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Prior art keywords
layer
light emitting
type semiconductor
semiconductor layer
insulating layer
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PCT/JP2014/070711
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French (fr)
Japanese (ja)
Inventor
杉山　徹
月原　政志
晃平 三好
紗織 南部
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ウシオ電機株式会社
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Application filed by ウシオ電機株式会社 filed Critical ウシオ電機株式会社
Priority to KR1020167002853A priority Critical patent/KR20160027168A/en
Priority to CN201480047832.7A priority patent/CN105518880A/en
Publication of WO2015029727A1 publication Critical patent/WO2015029727A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Definitions

  • the present invention relates to a semiconductor light emitting device having an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer formed therebetween on a support substrate.
  • GaN is mainly used in light emitting devices using nitride semiconductors.
  • a GaN film having few defects is formed by epitaxial growth on a sapphire substrate to form a light emitting element made of a nitride semiconductor.
  • the sapphire substrate is an insulating material, for feeding power to the GaN-based light-emitting element, a part of the p-type semiconductor layer is removed to expose the n-type semiconductor layer, and the p-type semiconductor layer and the n-type semiconductor are exposed.
  • a power feeding electrode is formed on each semiconductor layer.
  • a light emitting element having a structure in which power feeding electrodes are arranged in the same direction is referred to as a “lateral structure”.
  • Patent Document 1 discloses such a technique.
  • a so-called “vertical structure” light-emitting element in which a p-type semiconductor layer and an n-type semiconductor layer are arranged on the front and back surfaces to supply power It is being advanced.
  • an n-type semiconductor layer, a light-emitting layer (also referred to as an “active layer”), and a p-type semiconductor layer are arranged on a sapphire substrate from the bottom, and the p-type semiconductor is arranged.
  • the sapphire substrate is removed.
  • the element surface is an n-type semiconductor layer, and an electrode (n-side electrode) is provided on the n-type semiconductor side, and a voltage as a power supply line is connected to the n-side electrode.
  • the n-side electrode when a voltage is applied between an electrode on the p-type semiconductor layer side (hereinafter referred to as a “p-side electrode”) and the n-side electrode, the n-side electrode is connected to the n-side electrode via the light-emitting layer. Current flows through the side electrode. When a current flows in the light emitting layer, the light emitting layer emits light.
  • the p-side electrode and the n-side electrode are arranged in a positional relationship facing each other in the vertical direction. For this reason, when a voltage is applied between both electrodes, a current path in the vertical direction is formed that travels from the p-side electrode to the n-side electrode at a substantially shortest distance. At this time, most of the current flows in the light emitting layer located directly under the n-side electrode, and the current does not flow much in the other light emitting layers, so that there is a problem that the light emitting region is limited and the light emitting efficiency is lowered. .
  • Patent Document 2 discloses a configuration in which an insulating layer is provided immediately below the n-side electrode for the purpose of spreading the current in a direction parallel to the substrate surface of the support substrate. .
  • FIG. 9 schematically shows a cross-sectional view of the semiconductor light-emitting element disclosed in Patent Document 2.
  • the conventional semiconductor light emitting device 90 includes a conductive layer 92, a reflective film 93, an insulating layer 94, a reflective electrode 95, a semiconductor layer 99, and an n-side electrode 100 on a support substrate 91.
  • the semiconductor layer 99 is formed by stacking a p-type semiconductor layer 96, a light emitting layer 97, and an n-type semiconductor layer 98 in this order from the bottom.
  • the reflective electrode 95 is an electrode corresponding to the aforementioned “p-side electrode”.
  • the insulating layer 94 is formed in a region including a position immediately below the position where the n-side electrode 100 is formed.
  • a reflective film 93 made of a metal material is formed below the insulating layer 94.
  • the reflective film 93 does not have ohmic properties and does not function as an electrode.
  • the reflective electrode 95 is made of a metal material and functions as an electrode (p-side electrode) by realizing ohmic contact between the p-type semiconductor layers 96.
  • the light emitting layer 97 is provided at a position immediately below the n-side electrode 100. Most of the current is prevented from flowing in the vertical direction. That is, after passing through the reflective electrode 95, the current flows toward the n-side electrode 100 while spreading in a direction parallel to the substrate surface of the support substrate 91 (horizontal direction). Thereby, the effect of expanding the current flowing in the light emitting layer 97 in the horizontal direction is obtained, and the light emitting region in the light emitting layer 97 is expanded in the horizontal direction.
  • the reflective electrode 95 reflects the light emitted in the direction toward the support substrate 91 (downward in the drawing) out of the light emitted from the light emitting layer 97 and extracts the light toward the n-side semiconductor layer 98 (upward in the drawing). It also serves the purpose of increasing the take-out efficiency.
  • the reflective film 93 is also formed for the same purpose, and reflects light that travels downward through a portion where the reflective electrode 95 is not formed, and changes the traveling direction to the n-side semiconductor layer 98 side. The take-out efficiency is increased.
  • Patent Document 2 lists materials such as SiO 2 , Al 2 O 3 , ZrO 2 , and TiO 2 as materials for the insulating film 94.
  • the insulating film 94 is formed of these materials, although the insulating film 94 is configured as a transparent film, several percent of light is absorbed by the insulating film 94 when light passes through the insulating film 94.
  • an object of the present invention is to provide a semiconductor light-emitting device that further improves the light extraction efficiency while ensuring the horizontal spread of the current flowing through the light-emitting layer.
  • the present invention is a semiconductor light emitting device having an n-type semiconductor layer, a p-type semiconductor layer, and a light-emitting layer formed between the n-type semiconductor layer and the p-type semiconductor layer on a support substrate, An n-side electrode formed by contacting the bottom surface with the top surface of the n-type semiconductor layer; A reflective electrode formed in a region that includes a position directly below the formation position of the n-side electrode, the upper surface being in contact with the bottom surface of the p-type semiconductor layer; A first insulating layer formed by contacting an upper surface with a bottom surface of the reflective electrode at a position immediately below the formation position of the n-side electrode is provided.
  • the reflective electrode is formed up to a position immediately below the n-side electrode, the first insulating layer is formed on the bottom surface at that location, so that the reflective electrode is reflected at a position directly below the n-side electrode. No current flows below the bottom surface of the electrode. Since the current path is formed in a region where the first insulating layer is not formed, according to the above configuration, even if the reflective electrode and the n-side electrode face each other in the vertical direction, the reflective electrode and the n-side Most of the current does not flow only in the light emitting layer in the region sandwiched between the electrodes. That is, also in the above configuration, an effect of spreading the current flowing in the light emitting layer in a direction (horizontal direction) parallel to the substrate surface of the support substrate can be obtained.
  • the effect of spreading the current flowing in the light emitting layer 97 in the horizontal direction is realized by the insulating layer 94 formed in the upper layer of the reflective film 93. Since the insulating layer 94 is provided above the reflective film 93, the light emitted from the light emitting layer 97 is reflected twice by the reflective film 93 and extracted twice in the insulating layer 94. The light was forced to pass through, and several percent of light was absorbed in the insulating layer 94.
  • the effect of spreading the current flowing in the light emitting layer in the horizontal direction by the first insulating layer provided below the reflective electrode is realized. For this reason, it is not always necessary to provide an insulating layer above the reflective electrode. As a result, the light radiated from the light emitting layer to the support substrate side is not absorbed by the insulating layer until it is reflected by the reflective electrode and taken out to the outside of the n-type semiconductor layer side. Enhanced.
  • the insulating layer 94 is formed so as to be in contact with a part of the bottom surface of the reflective electrode 95, and the p-type nitride layer 96 is formed on the top surface of the reflective electrode 95. Is formed. For this reason, of the light emitted downward (from the support substrate 91 side) from the light emitting layer 97, the light reflected by the reflective electrode 95 is not absorbed by the insulating layer 94. However, in the configuration of FIG. 9, the reflective electrode 95 is not formed at a position immediately below the n-side electrode 100, and the insulating layer 94 is formed.
  • the reflective film 93 is provided on the surface. However, as described above, a portion of the light reflected by the reflective film 93 is absorbed by the insulating layer 94 before being extracted to the outside.
  • the configuration in which the reflective electrode 95 is not formed immediately below the n-side electrode 100 is that when the n-side electrode 100 and the reflective electrode 95 are opposed to each other in the vertical direction, It is assumed that the current flows mainly only in the region of the light emitting layer 97 to be limited, and that the light emitting region in the light emitting layer 97 is limited.
  • the inventors have intensively studied. It was found that the effect of spreading the current flowing in the light emitting layer in the horizontal direction can be realized by forming an insulating layer (first insulating layer) on the bottom surface of the reflective electrode at the position. The present invention has been made based on this fact.
  • the reflective electrode may be configured such that the entire top surface is in contact with the bottom surface of the p-type semiconductor layer.
  • the light emitted downward from the light emitting layer is not absorbed by the insulating layer until it is reflected by the reflective electrode and taken out above the n-type semiconductor layer. Therefore, the light extraction efficiency can be greatly improved as compared with the conventional configuration.
  • the second insulating layer may have a narrower width in a direction parallel to the substrate surface of the support substrate than the n-side electrode located immediately above the second insulating layer.
  • the second insulating layer is formed on the upper surface of the reflective electrode, part of the light that has passed through the second insulating layer is absorbed by the second insulating layer.
  • the effect of spreading the current flowing in the light emitting layer in the horizontal direction can be realized by the first insulating layer formed on the bottom surface of the reflective electrode. For this reason, when an insulating layer (second insulating layer) is formed on the upper surface of the reflective electrode, the width of the second insulating layer can be reduced.
  • the width of the second insulating layer is narrower than that of the n-side electrode, the current flowing in the light emitting layer is expanded in the horizontal direction by the first insulating layer.
  • variety of a 2nd insulating layer can be made thin in this way, even if this 2nd insulating layer is formed in the upper surface of a reflective electrode, among the lights radiated
  • the reflective electrode may be configured such that the entire top surface is in contact with the bottom surface of the p-type semiconductor layer except for the region where the second insulating layer is formed on the top surface.
  • the semiconductor light emitting device of the present invention can be realized as a nitride semiconductor light emitting device in which all of the n-type semiconductor layer, the p-type semiconductor layer, and the light emitting layer are formed of a nitride semiconductor layer.
  • the semiconductor light emitting device of the present invention it is possible to further improve the light extraction efficiency as compared with the conventional configuration while ensuring the horizontal spread of the current flowing through the light emitting layer.
  • the semiconductor light emitting device of the present invention will be described with reference to the drawings.
  • the dimensional ratio in the drawing does not necessarily match the actual dimensional ratio.
  • “the first layer is located immediately below the second layer” means that the second layer is located below the first layer in the direction perpendicular to the substrate surface of the support substrate. It means to do.
  • FIG. 1A is a cross-sectional view schematically showing the configuration of the semiconductor light emitting device of the first embodiment.
  • the semiconductor light emitting device 1 includes a support substrate 11, a conductive layer 20, an insulating layer 21, a semiconductor layer 30, and n-side electrodes (42, 43).
  • the semiconductor layer 30 is formed by stacking a p-type semiconductor layer (32, 31), a light emitting layer 33, and an n-type semiconductor layer 35 in this order from the bottom.
  • 1B is a schematic plan view of the semiconductor light emitting element 1 as viewed from above, and FIG. 1A corresponds to a cross-sectional view taken along line AA in FIG. 1B.
  • the support substrate 11 is composed of a conductive substrate such as CuW, W, or Mo, or a semiconductor substrate such as Si.
  • a conductive layer 20 having a multilayer structure is formed on the support substrate 11.
  • the conductive layer 20 includes a solder layer 13, a solder layer 15, a protective layer 17, and a reflective electrode 19.
  • the solder layer 13 and the solder layer 15 are made of, for example, Au—Sn, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like. As will be described later, the solder layer 13 and the solder layer 15 make the solder layer 13 formed on the support substrate 11 and the solder layer 15 formed on another substrate (a sapphire substrate 61 described later) face each other. Then, the two are bonded together.
  • the protective layer 17 is made of, for example, a Pt-based metal (an alloy of Ti and Pt), W, Mo, Ni, or the like. As will be described later, when bonding is performed via the solder layer, the material constituting the solder is diffused to the reflective electrode 19 side described later, and the function of preventing a decrease in luminous efficiency due to a drop in reflectance is achieved.
  • the reflective electrode 19 is made of, for example, an Ag-based metal (an alloy of Ni and Ag), Al, Rh, or the like. It is assumed that the semiconductor light emitting element 1 takes out the light emitted from the light emitting layer 33 upward (on the n-type semiconductor layer 35 side) in FIG. 1A, and the reflective electrode 19 emits downward from the light emitting layer 33. The function of improving the luminous efficiency is achieved by reflecting the emitted light upward. In addition, the upward arrow in FIG. 1A represents the light extraction direction.
  • the reflective electrode 19 is formed in the lower layer of the p-type semiconductor layer (31, 32) including the position immediately below the n-side electrode (42, 43).
  • the upper surface of the reflective electrode 19 is formed so as to be in contact with the p-type semiconductor layer 32.
  • Insulating layer 21 is composed for example SiO 2, SiN, Zr 2 O 3, AlN, etc. Al 2 O 3.
  • the insulating layer 21 corresponds to a “first insulating layer”.
  • the insulating layer 21 is formed immediately below the n-side electrodes (42, 43), and the upper surface of the insulating layer 21 is in contact with the bottom surface of the reflective electrode 19.
  • the insulating layer 21 serves to expand the current flowing through the light emitting layer 33 in a direction (horizontal direction) parallel to the substrate surface of the support substrate 11.
  • the insulating layer 21 is also formed at a position outside the semiconductor layer 30 and functions as an etching stopper layer at the time of element isolation, as will be described later in the section of the process.
  • the semiconductor layer 30 is formed by stacking the p-type semiconductor layer 32, the p-type semiconductor layer 31, the light emitting layer 33, and the n-type semiconductor layer 35 in this order from the bottom.
  • the p-type semiconductor layer 32 is made of, for example, GaN.
  • the p-type semiconductor layer 31 is made of, for example, Al m Ga 1-m N (0 ⁇ m ⁇ 1). All layers are doped with p-type impurities such as Mg, Be, Zn, or C. Note that the p-type semiconductor layer 32 has a higher impurity concentration than the p-type semiconductor layer 31 and forms a contact layer.
  • the light emitting layer 33 is formed of a semiconductor layer having a multiple quantum well structure in which, for example, a well layer made of InGaN and a barrier layer made of AlGaN are repeated. These layers may be undoped or p-type or n-type doped.
  • the n-type semiconductor layer 35 has a multilayer structure including, for example, a layer (electron supply layer) made of Al n Ga 1-n N (0 ⁇ n ⁇ 1) and a layer (protective layer) made of GaN.
  • the At least the protective layer is doped with an n-type impurity such as Si, Ge, S, Se, Sn, or Te.
  • n-side electrode 42, n-side electrode 43 The n-side electrodes (42, 43) are the upper layers of the n-type semiconductor layer 35, and are formed in the region near the end and the region near the center of the n-type semiconductor layer 35 in the cross-sectional view shown in FIG. Composed. What is formed in the region near the end corresponds to the n-side electrode 43, and what is formed in the region near the center corresponds to the n-side electrode 42.
  • a wire 45 made of Au, Cu or the like is connected to the n-side electrode 43, for example, in the regions 43a and 43b, and the other of the wires 45 is a substrate on which the semiconductor light emitting element 1 is disposed ( It is connected to a power supply pattern of the support substrate 11) (not shown). That is, the n-side electrode 43 functions as a power supply terminal of the semiconductor light emitting element 1. 1A and 1B, the n-side electrode 42 is formed at one location near the center. However, a plurality of n-side electrodes 42 may be formed and arranged in a lattice pattern. . Furthermore, the n-side electrodes 42 may be crossed and arranged in a mesh shape.
  • the n-side electrode 42 and the n-side electrode 43 are connected on the upper surface of the semiconductor layer 30 and serve to expand the current path on the plane of the semiconductor layer 30. That is, by contacting the upper surface of the n-type semiconductor layer 35 at a location different from the n-side electrode 43 constituting the power supply terminal in the upper surface of the n-type semiconductor layer 35, the n-type semiconductor layer 35 in the horizontal direction when energized. It is formed for the purpose of flowing a current over a wide range of the light-emitting layer 33, thereby causing a current to flow over a wide range of the light emitting layer 33.
  • an insulating layer as a protective film may be formed on the side surface of the semiconductor layer 30.
  • the insulating layer as the protective film is preferably made of a light-transmitting material (eg, SiO 2 ).
  • one material constituting the p-type semiconductor layer 31 is described as Al m Ga 1-m N (0 ⁇ m ⁇ 1), and one material constituting the n-type semiconductor layer 35 is Al n n.
  • Ga 1-n N (0 ⁇ n ⁇ 1) these may be the same material.
  • minute irregularities may be formed on the upper surface of the n-type semiconductor layer 35.
  • the reflective electrode 19 is formed in a region including a position directly below the n-side electrode (42, 43), but is reflected at a position immediately below the n-side electrode (42, 43). Since the insulating layer 21 is formed on the bottom surface of the electrode 19, no current flows below the bottom surface of the reflective electrode 19 at a position immediately below the n-side electrodes (42, 43).
  • the current path is formed in a region where the insulating layer 21 is not formed, according to the above configuration, even if the reflective electrode 19 and the n-side electrode (42, 43) are in a positional relationship facing each other in the vertical direction, Most of the current does not flow only in the light emitting layer 33 in the region sandwiched between the reflective electrode 19 and the n-side electrode (42, 43). That is, according to the semiconductor light emitting device 1 shown in FIG. 1A, the current flowing in the light emitting layer 33 is parallel to the substrate surface of the support substrate 11 (horizontal direction) without providing an insulating layer on the reflective electrode 19. The effect can be obtained.
  • the light radiated from the light emitting layer 33 to the support substrate 11 side is not absorbed by the insulating layer until it is reflected by the reflective electrode 19 and taken out to the n-type semiconductor layer 35 side. Efficiency is increased.
  • the configuration of the second embodiment will be described with respect to the fact that the light extraction efficiency is higher than the conventional configuration while realizing the low voltage driving equivalent to the conventional configuration. After that, it will be shown with reference to the results of the elements of the examples and comparative examples.
  • Step S1 As shown in FIG. 2A, the epi layer 40 is formed on the sapphire substrate 61.
  • This step S1 is performed by the following procedure, for example.
  • the c-plane sapphire substrate 61 is cleaned. More specifically, for this cleaning, for example, a c-plane sapphire substrate 61 is placed in a processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and hydrogen having a flow rate of 10 slm is placed in the processing furnace. While flowing the gas, the temperature in the furnace is raised to, for example, 1150 ° C.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • a low-temperature buffer layer made of GaN is formed on the surface of the c-plane sapphire substrate 61, and a base layer made of GaN is further formed thereon. These low-temperature buffer layer and underlayer correspond to the undoped layer 36.
  • a more specific method for forming the undoped layer 36 is as follows. First, the furnace pressure of the ⁇ CVD apparatus is 100 kPa, and the furnace temperature is 480 ° C. Then, while flowing nitrogen gas and hydrogen gas with a flow rate of 5 slm respectively as carrier gas into the processing furnace, trimethylgallium (TMG) with a flow rate of 50 ⁇ mol / min and ammonia with a flow rate of 250,000 ⁇ mol / min are used as the raw material gas in the processing furnace. For 68 seconds. As a result, a low-temperature buffer layer made of GaN having a thickness of 20 nm is formed on the surface of the c-plane sapphire substrate 61.
  • TMG trimethylgallium
  • the furnace temperature of the MOCVD apparatus is raised to 1150 ° C. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas in the processing furnace, TMG having a flow rate of 100 ⁇ mol / min and ammonia having a flow rate of 250,000 ⁇ mol / min are introduced into the processing furnace as source gases. Feed for 30 minutes. As a result, a base layer made of GaN having a thickness of 1.7 ⁇ m is formed on the surface of the low-temperature buffer layer.
  • n-type semiconductor layer 35 having a composition of Al n Ga 1-n N (0 ⁇ n ⁇ 1) is formed on the undoped layer 36.
  • a more specific method for forming the n-type semiconductor layer 35 is, for example, as follows. First, with the furnace temperature kept at 1150 ° C., the furnace pressure of the MOCVD apparatus is set to 30 kPa. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas into the processing furnace, TMG having a flow rate of 94 ⁇ mol / min, trimethylaluminum (TMA) having a flow rate of 6 ⁇ mol / min, Ammonia with a flow rate of 250,000 ⁇ mol / min and tetraethylsilane with a flow rate of 0.025 ⁇ mol / min are supplied into the treatment furnace for 60 minutes.
  • TMG trimethylaluminum
  • tetraethylsilane with a flow rate of 0.025 ⁇ mol / min are supplied into the treatment
  • an n-type semiconductor layer 35 having a composition of Al 0.06 Ga 0.94 N, a Si concentration of 3 ⁇ 10 19 / cm 3 , and a thickness of 2 ⁇ m is formed in the upper layer of the undoped layer 36. .
  • n-type semiconductor layer having a protective layer made of n-type GaN having a thickness of 5 nm on the n-AlGaN layer. 35 may be realized.
  • Si is used as the n-type impurity contained in the n-type semiconductor layer 35 .
  • Ge, S, Se, Sn, Te, or the like can be used as the n-type impurity in addition to Si. .
  • a light emitting layer 33 having a multiple quantum well structure in which a well layer made of InGaN and a barrier layer made of n-type AlGaN are periodically repeated is formed on the n-type semiconductor layer 35.
  • the furnace pressure of the MOCVD apparatus is set to 100 kPa, and the furnace temperature is set to 830 ° C. Then, while flowing nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 1 slm as a carrier gas in the processing furnace, TMG having a flow rate of 10 ⁇ mol / min, trimethylindium (TMI) having a flow rate of 12 ⁇ mol / min, and A step of supplying ammonia at a flow rate of 300,000 ⁇ mol / min into the processing furnace for 48 seconds is performed.
  • TMG having a flow rate of 10 ⁇ mol / min
  • TMA having a flow rate of 1.6 ⁇ mol / min
  • tetraethylsilane having a flow rate of 0.002 ⁇ mol / min
  • ammonia having a flow rate of 300,000 ⁇ mol / min
  • the light-emitting layer 33 having a multi-quantum well structure of 15 periods with a well layer made of InGaN having a thickness of 2 nm and a barrier layer made of n-type AlGaN having a thickness of 7 nm is formed into an n-type. It is formed in the upper layer of the semiconductor layer 35.
  • a p-type semiconductor layer 31 composed of Al m Ga 1-m N (0 ⁇ m ⁇ 1) is formed on the light emitting layer 33.
  • the furnace pressure of the MOCVD apparatus is maintained at 100 kPa, and the furnace temperature is raised to 1025 ° C. while nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 25 slm are supplied as carrier gases in the processing furnace.
  • nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 25 slm are supplied as carrier gases in the processing furnace.
  • TMG with a flow rate of 35 ⁇ mol / min
  • TMA with a flow rate of 20 ⁇ mol / min
  • ammonia with a flow rate of 250,000 ⁇ mol / min
  • biscyclopentadiene with a flow rate of 0.1 ⁇ mol / min for doping p-type impurities.
  • Enilmagnesium (CP 2 Mg) is fed into the processing furnace for 60 seconds.
  • a hole supply layer having a composition of Al 0.3 Ga 0.7 N having a thickness of 20 nm is formed on the surface of the light emitting layer 33.
  • a hole supply layer having a composition of Al 0.13 Ga 0.87 N having a thickness of 120 nm is formed on the surface of the light emitting layer 33.
  • a p-type semiconductor layer 31 is formed by these hole supply layers.
  • the p-type impurity concentration of the p-type semiconductor layer 31 is, for example, about 3 ⁇ 10 19 / cm 3 .
  • ⁇ Formation of p-type semiconductor layer 32> Thereafter, the supply of TMA is stopped, the flow rate of CP 2 Mg is changed to 0.2 ⁇ mol / min, and the raw material gas is supplied for 20 seconds, whereby the thickness is about 5 nm and the p-type impurity concentration is 1 ⁇ 10.
  • a p-type semiconductor layer 32 made of p + GaN of about 20 / cm 3 is formed.
  • the epi layer 40 including the undoped layer 36, the n-type semiconductor layer 35, the light emitting layer 33, the p-type semiconductor layer 31, and the p-type semiconductor layer 32 is formed on the sapphire substrate 61.
  • Step S2 an activation process is performed on the wafer obtained in step S1. More specifically, activation is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal) device.
  • RTA Rapid Thermal Anneal
  • Step S3 the reflective electrode 19 is formed at a predetermined location on the upper surface of the p-type semiconductor layer 32.
  • the reflective electrode 19 is formed in almost the entire region of the p-type semiconductor layer 32 inside the region where the p-type semiconductor layer 32 is formed. More specifically, the reflective electrode 19 is formed so as to include a portion located immediately below a region where the n-side electrode 42 as a power supply terminal is formed in a later step.
  • the reflective electrode 19 is formed by depositing 0.7 nm-thickness Ni and 150 nm-thick Ag on the upper surface of the p-type semiconductor layer 32 by a sputtering apparatus, and then using an RTA apparatus in a dry air atmosphere at 400 ° C. It is formed by performing contact annealing for 2 minutes.
  • the alloy of Ni and Ag is adopted as the material of the reflective electrode 19, the reflective electrode 19 can also be formed of Al or Rh.
  • Step S4 Next, as shown in FIG. 2C, an insulating layer 21 is formed at a predetermined position on the upper layer of the reflective electrode 19.
  • the insulating layer 21 is formed at a location located below a region where the n-side electrode (42, 43) is formed in a later step.
  • a part of the insulating layer 21 can be formed so as to cover the side surface of the reflective electrode 19.
  • the upper layer of the reflective electrode 19 in the region where the insulating layer 21 is not formed is masked, and, for example, SiO 2 is formed to a thickness of about 200 nm by sputtering.
  • the material for forming the film may be an insulating material, such as SiN or Al 2 O 3 .
  • Step S5 As shown in FIG. 2D, the protective layer 17 and the solder layer 15 are formed so as to cover the upper surfaces of the metal electrode 19 and the insulating layer 21.
  • the protective film is formed by depositing 100-nm-thick Ti and 200-nm-thick Pt for three periods so as to cover the upper surfaces of the metal electrode 19 and the insulating layer 21 with an electron beam evaporation apparatus (EB apparatus).
  • Layer 17 is formed. Further, after depositing Ti with a thickness of 10 nm on the upper surface (Pt surface) of the protective layer 17, Au—Sn solder composed of Au 80% Sn 20% is deposited with a thickness of 3 ⁇ m. Form.
  • the solder layer 13 may be formed on the upper surface of the support substrate 11 prepared separately from the sapphire substrate 61 (see FIG. 2E).
  • the solder layer 13 may be made of the same material as the solder layer 15, and is bonded to the solder layer 13 in the next step, whereby the sapphire substrate 61 and the support substrate 11 are bonded together.
  • CuW is used as the support substrate 11 as described above in the section of the structure.
  • a protective layer for preventing diffusion of the material of the solder layer 13 is formed on the support substrate 11 with the same material as the protective layer 17, and the solder layer 13 is formed on the protective layer. It does n’t matter.
  • Step S6 Next, as shown in FIG. 2F, the sapphire substrate 61 and the support substrate 11 are bonded together. More specifically, the solder layer 15 and the solder layer 13 formed on the support substrate 11 are bonded together at a temperature of 280 ° C. and a pressure of 0.2 MPa.
  • Step S7 Next, as shown in FIG. 2G, the sapphire substrate 61 is peeled off. More specifically, the interface between the sapphire substrate 61 and the epi layer 40 is decomposed by irradiating a KrF excimer laser from the sapphire substrate 61 side with the sapphire substrate 61 facing upward and the support substrate 11 facing downward. Then, the sapphire substrate 61 is peeled off. While the laser passes through the sapphire 61, the underlying GaN (undoped layer 36) absorbs the laser, so that this interface is heated to decompose GaN. As a result, the sapphire substrate 61 is peeled off.
  • GaN (undoped layer 36) remaining on the wafer is removed by wet etching using hydrochloric acid or the like, or dry etching using an ICP apparatus, and the n-type semiconductor layer 35 is removed. Expose.
  • the undoped layer 36 is removed, and the semiconductor layer 30 in which the p-type semiconductor layer 32, the p-type semiconductor layer 31, the light emitting layer 33, and the n-type semiconductor layer 35 are stacked in this order from the bottom remains. To do.
  • Step S8 Next, as shown in FIG. 2I, adjacent elements are separated from each other. Specifically, the semiconductor layer 30 is etched using an ICP device until the upper surface of the insulating layer 21 is exposed in a boundary region with an adjacent element. As described above, at this time, the insulating layer 21 also functions as a stopper during etching.
  • n-side electrodes (42, 43) are formed on the upper surface of the n-type semiconductor layer 35 at a position immediately above the location where the insulating layer 21 is formed. Specifically, after forming an electrode made of Cr having a thickness of 100 nm and Au having a thickness of 3 ⁇ m, sintering is performed at 250 ° C. for 1 minute in a nitrogen atmosphere.
  • the elements are separated from each other by, for example, a laser dicing apparatus, the back surface of the support substrate 11 is joined to the package by, for example, Ag paste, and wire bonding is performed on the n-side electrode 43 as a power supply terminal.
  • wire bonding is performed by connecting a wire 45 made of Au to a bonding region of ⁇ 100 ⁇ m with a load of 50 g. Thereby, the nitride semiconductor light emitting device 1 shown in FIG. 1A is formed.
  • unevenness may be formed on the surface of the n-type semiconductor layer 35 by immersing an alkaline solution such as KOH between Step S8 and Step S9.
  • an insulating layer may be formed so as to cover the side surface of the semiconductor layer 30.
  • FIG. 3 is a cross-sectional view schematically showing the configuration of the semiconductor light emitting device of the second embodiment.
  • the semiconductor light emitting device 1a further includes an insulating layer 22 (corresponding to “second insulating layer”) as compared with the semiconductor light emitting device 1 of the first embodiment.
  • the insulating layer 22 is composed of SiO 2, SiN, Zr 2 O 3 , AlN, Al 2 O 3, etc., like the insulating layer 21.
  • the insulating layer 22 is formed at a position between the reflective electrode 19 and the p-type semiconductor layer 32 at a position immediately below the formation position of the n-side electrode (42, 43). Further, the insulating layer 22 preferably has a narrower width in the direction parallel to the substrate surface of the support substrate 11 than the n-side electrodes (42, 43).
  • each reflective electrode 19 is in contact with the p-type semiconductor layer 32.
  • a part of the upper surface of the reflective electrode 19 is in contact with the insulating layer 22 and the other part is in contact with the p-type semiconductor layer 32.
  • this insulating layer 22 is formed in the position just under the formation location of the n side electrode (42, 43).
  • the insulating layer 22 is formed in a part of the upper surface of the reflective electrode 19, a part of the light emitted downward from the light emitting layer 33 passes through the insulating layer 22.
  • the light passes through and reaches the reflective electrode 19, is further reflected by the reflective electrode 19, passes through the insulating layer 22, and is guided to the n-type semiconductor layer 35 side.
  • the light extraction efficiency is slightly lowered as compared with the semiconductor light emitting device 1 described in the first embodiment.
  • the effect of spreading the current flowing in the light emitting layer 33 in the horizontal direction by the insulating layer 21 formed on the bottom surface of the reflective electrode 19 can be realized.
  • variety of the insulating layer 22 formed in the upper surface of the reflective electrode 19 is realizable narrower than a conventional structure. Therefore, although the semiconductor light emitting device 1a of the present embodiment has the insulating layer 22 on the upper surface of the reflective electrode 19, the light emitted downward from the light emitting layer 33 and reflected by the reflective electrode 19 is within the insulating layer 22 The light passing through can be significantly limited as compared with the prior art. Therefore, the light extraction efficiency can be improved as compared with the conventional configuration.
  • Steps S1 and S2 are executed by the same method as in the first embodiment.
  • Step S3A Next, as illustrated in FIG. 4A, the insulating layer 22 is formed at a predetermined position on the upper layer of the p-type semiconductor layer 32.
  • the insulating layer 22 is formed by making the width in the horizontal direction smaller than that of the n-side electrode (42, 43) at a position located below a region where the n-side electrode (42, 43) is formed in a later step. .
  • Step S3B Next, as illustrated in FIG. 4B, the reflective electrode 19 is formed at a predetermined position on the upper surface of the p-type semiconductor layer 32. At this time, the reflective electrode 19 is formed so as to cover the upper layer of the insulating layer 22.
  • Example 1 The semiconductor light emitting device 1 of the first embodiment manufactured by the method described above is taken as Example 1, the semiconductor light emitting device 1a of the second embodiment is taken as Example 2, and the semiconductor light emitting device 50 shown in FIG. The voltage characteristics and the light emission characteristics were compared.
  • FIG. 5 is a cross-sectional view schematically showing the structure of a semiconductor light emitting device formed as a comparative example.
  • an insulating layer 23 provided on the top surface of the reflective electrode 19 is provided instead of the insulating layer 21 formed on the bottom surface of the reflective electrode 19.
  • the insulating layer 23 is formed for the purpose of spreading the current flowing through the light emitting layer 33 in the horizontal direction by being formed at a position immediately below the n-side electrodes (42, 43).
  • the materials and dimensions constituting the other layers are the same.
  • FIG. 6 is a graph showing the relationship between the flowing current value and the voltage value (IV characteristics) when a voltage is applied to each element of Example 1, Example 2, and Comparative Example. According to FIG. 6, when each element of Example 1 and Example 2 is compared with the comparative example, the voltage values required to flow the same current value are substantially equal, and the low voltage equivalent to the configuration of the comparative example. It can be seen that driving can be realized.
  • FIG. 7 is a graph showing the relationship between the light emission output and the current value obtained when current is supplied to each element of Example 1, Example 2, and Comparative Example. According to FIG. 7, it can be seen that the light emission output is improved in both the elements of Example 1 and Example 2 as compared with the element of the comparative example. It can also be seen that the light emission output of the element of Example 1 is further improved than that of Example 2.
  • the horizontal width of the insulating layer 23 cannot be made narrower than the n-side electrodes (42, 43). If the horizontal width of the insulating layer 23 is narrower than that of the n-side electrodes (42, 43), the reflective electrode 19 is located directly under the n-side electrode 42, and the conductive protective layer 19 and solder are directly underneath. Since the layers (13, 15) are formed, a current path extends in the vertical direction between the n-side electrodes (42, 43) and the reflective electrode 19 located immediately below in the region where the insulating layer 23 is not formed. Will be formed. As a result, a large amount of current flows through the light emitting layer 33 in the region, and the effect of causing the light emitting layer 33 to shine in the entire horizontal direction cannot be obtained, resulting in a reduction in light emission efficiency.
  • the light emitting element made of a nitride semiconductor has been described as the semiconductor light emitting element (1, 1a).
  • the structure of the present invention can also be applied to light emitting elements made of other semiconductors.
  • FIG. 8 is a cross-sectional view schematically showing an example of the configuration of another embodiment of the semiconductor light emitting device.
  • the light emitting layer 33 is formed of a semiconductor layer having a multiple quantum well structure in which an InGaP well layer and an AlGaInP barrier layer are repeated.
  • the semiconductor light emitting device 1b shown in FIG. 8 a p-type semiconductor layer 31, a light emitting layer 33, and an n-side semiconductor layer 35 are stacked in this order on the support substrate 11 in the same manner as the configuration of the first embodiment described above. Is formed.
  • the semiconductor light emitting device 1b includes an n-side electrode (42, 43) formed with the bottom surface in contact with the top surface of the n-type semiconductor layer 35, and the top surface in contact with the bottom surface of the p-type semiconductor layer 31.
  • the reflective electrode 19 formed in a region including the position immediately below the formation position of (42, 43) and the upper surface in contact with the bottom surface of the reflective electrode 19 at a position immediately below the formation position of the n-side electrode (42, 43).
  • the insulating layer 21 is formed.
  • a conductive layer 20 including a bonding layer 14 made of Ni / Au, a protective layer 17 made of TaN / TiW / TaN, and a reflective electrode 19 made of AuSn is formed on the support substrate 11. It is formed.
  • the p-type semiconductor layer 31 has a lower p-type impurity concentration than the diffusion layer 61 and the diffusion layer 62 made of GaP having a high p-type impurity concentration (eg, about 3 ⁇ 10 18 / cm 3 ).
  • the intermediate layer 62 made of AlGaInP made of AlGaInP of about 1 ⁇ 10 18 / cm 3 , and made of AlGaInP having a p-type impurity concentration lower than the intermediate layer 62 (for example, about 3 ⁇ 10 17 / cm 3 ).
  • a p-cladding layer 63 is provided.
  • the n-type semiconductor layer 35 includes a relaxation layer 64 having a multilayer structure in which n-type InGaP and n-type AlInP are repeatedly stacked, and an n-cladding layer 65 made of AlGaInP.
  • the insulating layer 21 is formed at a position immediately below the n-side electrodes (42, 43) for the purpose of extending in a direction parallel to the substrate surface (horizontal direction).
  • the insulating layer 21 is formed not between the reflective electrode 19 and the p-type semiconductor layer 31 but between the reflective electrode 19 and the protective layer 17, that is, so that the top surface is in contact with the bottom surface of the reflective electrode 19.
  • the light traveling toward the support substrate 11 out of the light emitted from the light emitting layer 33 is reflected by the reflective electrode 19 and then travels in the traveling direction. Changes upward (on the n-type semiconductor layer 35 side) and is taken out to the outside. At this time, the light does not pass through the insulating layer 21 until it reaches the reflective electrode 19 and after it reaches the reflective electrode 19 until it is reflected and extracted outside. Therefore, similarly to the elements of the first embodiment and the second embodiment described above, light is not absorbed by the insulating layer 21, and an effect of improving the light extraction efficiency as compared with the related art can be obtained.
  • an n-side electrode (between the reflective electrode 19 and the p-type semiconductor layer 31 is provided immediately below the location where the n-side electrode (42, 43) is formed.
  • the second insulating layer formed with a width thinner than the width of 42, 43) may be formed. In this case, although the light extraction efficiency is lower than that of the element 1b in FIG. 8, the extraction efficiency can be improved as compared with the conventional element.

Abstract

Provided is a semiconductor light emitting element wherein light extraction efficiency is further improved, while ensuring spreading of a current flowing in a light emitting layer, said spreading being in the horizontal direction. This semiconductor light emitting element is configured such that the semiconductor light emitting element has, on a supporting substrate, an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer that is formed between the n-type semiconductor layer and the p-type semiconductor layer. The semiconductor light emitting element is provided with: an n-side electrode that is formed by having the bottom surface thereof in contact with the upper surface of the n-type semiconductor layer; a reflection electrode, which has the upper surface thereof in contact with the bottom surface of the p-type semiconductor layer, and which is formed in a region including a position just below the area where the n-side electrode is formed; and a first insulating layer, which is formed by having the upper surface thereof in contact with the bottom surface of the reflection electrode, said first insulating layer being formed at a position just below the area where the n-side electrode is formed.

Description

半導体発光素子Semiconductor light emitting device
　本発明は、支持基板上に、ｎ型半導体層、ｐ型半導体層、及びこれらの間に形成された発光層を有する半導体発光素子に関する。 The present invention relates to a semiconductor light emitting device having an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer formed therebetween on a support substrate.
　従来、窒化物半導体を用いた発光素子においては、主としてＧａＮが利用されている。この場合、格子整合の観点からサファイア基板上にエピタキシャル成長させて欠陥の少ないＧａＮ膜を形成することで、窒化物半導体からなる発光素子を形成していた。ここで、サファイア基板は絶縁材であることから、ＧａＮ系の発光素子への給電には、ｐ型半導体層の一部を削ってｎ型半導体層を露出させ、ｐ型半導体層及びｎ型半導体層の各半導体層に給電用の電極を形成していた。このように、給電用の電極が同じ向きに配置されている構造の発光素子を「横型構造」と呼び、例えば下記特許文献１にこのような技術が開示されている。 Conventionally, GaN is mainly used in light emitting devices using nitride semiconductors. In this case, from the viewpoint of lattice matching, a GaN film having few defects is formed by epitaxial growth on a sapphire substrate to form a light emitting element made of a nitride semiconductor. Here, since the sapphire substrate is an insulating material, for feeding power to the GaN-based light-emitting element, a part of the p-type semiconductor layer is removed to expose the n-type semiconductor layer, and the p-type semiconductor layer and the n-type semiconductor are exposed. A power feeding electrode is formed on each semiconductor layer. Thus, a light emitting element having a structure in which power feeding electrodes are arranged in the same direction is referred to as a “lateral structure”. For example, Patent Document 1 below discloses such a technique.
　一方で、発光素子の発光効率の改善や光取り出し効率の向上を目的として、ｐ型半導体層とｎ型半導体層を表裏面に配置し給電する、いわゆる「縦型構造」の発光素子の開発が進められている。この縦型構造の発光素子を製造する際には、サファイア基板上に下から順にｎ型半導体層、発光層（「活性層」とも呼ばれる。）、ｐ型半導体層を配置し、当該ｐ型半導体層側にＳｉやＣｕＷからなる支持基板を接合した後、サファイア基板が除去される。この場合、素子表面はｎ型半導体層となり、このｎ型半導体側に電極（ｎ側電極）を設け、このｎ側電極に給電線であるワイヤを繋ぐことで電圧供給を行っている。 On the other hand, for the purpose of improving the light emission efficiency and light extraction efficiency of light-emitting elements, development of a so-called “vertical structure” light-emitting element in which a p-type semiconductor layer and an n-type semiconductor layer are arranged on the front and back surfaces to supply power It is being advanced. When manufacturing a light-emitting element having this vertical structure, an n-type semiconductor layer, a light-emitting layer (also referred to as an “active layer”), and a p-type semiconductor layer are arranged on a sapphire substrate from the bottom, and the p-type semiconductor is arranged. After a support substrate made of Si or CuW is bonded to the layer side, the sapphire substrate is removed. In this case, the element surface is an n-type semiconductor layer, and an electrode (n-side electrode) is provided on the n-type semiconductor side, and a voltage as a power supply line is connected to the n-side electrode.
　縦型の構造においては、ｐ型半導体層側の電極（以下、「ｐ側電極」と呼ぶ。）とｎ側電極の間に電圧が印加されると、ｐ側電極から発光層を介してｎ側電極に電流が流れる。発光層内を電流が流れることで、発光層が発光する。 In the vertical structure, when a voltage is applied between an electrode on the p-type semiconductor layer side (hereinafter referred to as a “p-side electrode”) and the n-side electrode, the n-side electrode is connected to the n-side electrode via the light-emitting layer. Current flows through the side electrode. When a current flows in the light emitting layer, the light emitting layer emits light.
　ｐ側電極とｎ側電極は鉛直方向に対向する位置関係に配置される。このため、両電極間に電圧が印加された場合、ｐ側電極からｎ側電極に向かってほぼ最短距離で向かう鉛直方向の電流経路が形成される。このとき、ｎ側電極の直下に位置する発光層内を大部分の電流が流れ、他の発光層内にはあまり電流が流れず、発光領域が限定的となり発光効率が低くなるという問題がある。 The p-side electrode and the n-side electrode are arranged in a positional relationship facing each other in the vertical direction. For this reason, when a voltage is applied between both electrodes, a current path in the vertical direction is formed that travels from the p-side electrode to the n-side electrode at a substantially shortest distance. At this time, most of the current flows in the light emitting layer located directly under the n-side electrode, and the current does not flow much in the other light emitting layers, so that there is a problem that the light emitting region is limited and the light emitting efficiency is lowered. .
　上記の課題を受け、下記特許文献２には、電流を支持基板の基板面に対して平行な方向に拡げることを目的としてｎ側電極の直下の位置に絶縁層を設ける構成が開示されている。 In response to the above problems, Patent Document 2 below discloses a configuration in which an insulating layer is provided immediately below the n-side electrode for the purpose of spreading the current in a direction parallel to the substrate surface of the support substrate. .
特許第２９７６９５１号明細書Japanese Patent No. 2976951 特許第４２０７７８１号明細書Japanese Patent No. 4207781
　図９は、特許文献２に開示された半導体発光素子の断面図を模式的に示したものである。従来の半導体発光素子９０は、支持基板９１上に導電層９２、反射膜９３、絶縁層９４、反射電極９５、半導体層９９、及びｎ側電極１００を備えて構成される。半導体層９９は、ｐ型半導体層９６、発光層９７、及びｎ型半導体層９８が下からこの順に積層されて構成される。反射電極９５は前述の「ｐ側電極」に対応する電極である。 FIG. 9 schematically shows a cross-sectional view of the semiconductor light-emitting element disclosed in Patent Document 2. The conventional semiconductor light emitting device 90 includes a conductive layer 92, a reflective film 93, an insulating layer 94, a reflective electrode 95, a semiconductor layer 99, and an n-side electrode 100 on a support substrate 91. The semiconductor layer 99 is formed by stacking a p-type semiconductor layer 96, a light emitting layer 97, and an n-type semiconductor layer 98 in this order from the bottom. The reflective electrode 95 is an electrode corresponding to the aforementioned “p-side electrode”.
　絶縁層９４は、ｎ側電極１００が形成されている位置の直下の位置を含む領域に形成される。絶縁層９４の下層には金属材料からなる反射膜９３が形成されているが、この反射膜９３はオーミック性を有さず電極としての機能を奏さない。一方、反射電極９５は金属材料からなり、ｐ型半導体層９６の間でオーミック接触が実現されることで電極（ｐ側電極）として機能している。 The insulating layer 94 is formed in a region including a position immediately below the position where the n-side electrode 100 is formed. A reflective film 93 made of a metal material is formed below the insulating layer 94. However, the reflective film 93 does not have ohmic properties and does not function as an electrode. On the other hand, the reflective electrode 95 is made of a metal material and functions as an electrode (p-side electrode) by realizing ohmic contact between the p-type semiconductor layers 96.
　支持基板９１とｎ側電極１００の間に電圧が印加されると、ｎ側電極１００の直下の位置には絶縁層９４が設けられているため、ｎ側電極１００の直下の位置において発光層９７内を鉛直方向に大部分の電流が流れることが防止される。すなわち、電流は反射電極９５を通過した後、支持基板９１の基板面に対して平行な方向（水平方向）に拡がりながらｎ側電極１００に向かって流れる。これにより、発光層９７内を流れる電流を水平方向に拡げる効果が得られ、発光層９７内の発光領域が水平方向に拡げられる。 When a voltage is applied between the support substrate 91 and the n-side electrode 100, since the insulating layer 94 is provided at a position immediately below the n-side electrode 100, the light emitting layer 97 is provided at a position immediately below the n-side electrode 100. Most of the current is prevented from flowing in the vertical direction. That is, after passing through the reflective electrode 95, the current flows toward the n-side electrode 100 while spreading in a direction parallel to the substrate surface of the support substrate 91 (horizontal direction). Thereby, the effect of expanding the current flowing in the light emitting layer 97 in the horizontal direction is obtained, and the light emitting region in the light emitting layer 97 is expanded in the horizontal direction.
　反射電極９５は、発光層９７で発光した光のうち、支持基板９１に向かう方向（図面下向き）に放射された光を反射させてｎ側半導体層９８側（図面上向き）に取り出すことで、光の取り出し効率を高める目的を兼ねている。反射膜９３も同様の目的で形成されており、反射電極９５が形成されていない箇所を通過して下向きに進行した光を反射させてｎ側半導体層９８側に進行方向を変えることで、光の取り出し効率が高められる。 The reflective electrode 95 reflects the light emitted in the direction toward the support substrate 91 (downward in the drawing) out of the light emitted from the light emitting layer 97 and extracts the light toward the n-side semiconductor layer 98 (upward in the drawing). It also serves the purpose of increasing the take-out efficiency. The reflective film 93 is also formed for the same purpose, and reflects light that travels downward through a portion where the reflective electrode 95 is not formed, and changes the traveling direction to the n-side semiconductor layer 98 side. The take-out efficiency is increased.
　しかし、発光層９７から下向きに放射された光が反射膜９３によって反射されて上向きに取り出されるに際し、この光は、反射膜９３で反射される前と反射した後の２回にわたって、絶縁膜９４内を通過することになる。特許文献２には、絶縁膜９４の材料として、ＳｉＯ２、Ａｌ２Ｏ３、ＺｒＯ２、ＴｉＯ２などの材料が挙げられている。これらの材料によって絶縁膜９４を形成した場合、絶縁膜９４は透明膜として構成されるものの、この絶縁膜９４内を光が通過する際に数％の光が絶縁膜９４によって吸収されてしまう。より詳細には、発光層９７から絶縁膜９４を通過して反射膜９３に達するまでに３－４％程度の光が吸収され、更に反射膜９３で反射された光が絶縁膜９４を通過してｎ型半導体層９８側の外部に取り出されるまでに更に３－４％の光が吸収される。 However, when the light emitted downward from the light emitting layer 97 is reflected by the reflective film 93 and extracted upward, this light is reflected twice before the reflection by the reflective film 93 and after the reflection. Will pass through. Patent Document 2 lists materials such as SiO 2 , Al 2 O 3 , ZrO 2 , and TiO 2 as materials for the insulating film 94. When the insulating film 94 is formed of these materials, although the insulating film 94 is configured as a transparent film, several percent of light is absorbed by the insulating film 94 when light passes through the insulating film 94. More specifically, about 3-4% of light is absorbed from the light emitting layer 97 through the insulating film 94 to reach the reflecting film 93, and the light reflected by the reflecting film 93 passes through the insulating film 94. Thus, 3-4% of light is further absorbed before being extracted to the outside on the n-type semiconductor layer 98 side.
　つまり、従来の構成では、発光層９７から放射された光のうち、下向きに放射された光を反射させて取り出し効率を高めてはいるものの、一部の光が絶縁膜９４内に吸収されてしまっているため、取り出し効率を十分に高められているとはいえない。 That is, in the conventional configuration, although the light emitted from the light emitting layer 97 is reflected downward to improve the extraction efficiency, a part of the light is absorbed in the insulating film 94. Therefore, it cannot be said that the extraction efficiency is sufficiently increased.
　本発明は、上記の課題に鑑み、発光層を流れる電流の水平方向への拡がりを確保しながら、光の取り出し効率を更に向上させた半導体発光素子を提供することを目的とする。 In view of the above-described problems, an object of the present invention is to provide a semiconductor light-emitting device that further improves the light extraction efficiency while ensuring the horizontal spread of the current flowing through the light-emitting layer.
　本発明は、支持基板上に、ｎ型半導体層と、ｐ型半導体層と、前記ｎ型半導体層及び前記ｐ型半導体層の間に形成された発光層とを有する半導体発光素子であって、
　底面を前記ｎ型半導体層の上面に接触して形成されたｎ側電極と、
　上面を前記ｐ型半導体層の底面に接触し、前記ｎ側電極の形成箇所の直下の位置を含む領域に形成された反射電極と、
　前記ｎ側電極の形成箇所の直下の位置において、上面を前記反射電極の底面に接触して形成された第１絶縁層を備えたことを特徴とする。 The present invention is a semiconductor light emitting device having an n-type semiconductor layer, a p-type semiconductor layer, and a light-emitting layer formed between the n-type semiconductor layer and the p-type semiconductor layer on a support substrate,
An n-side electrode formed by contacting the bottom surface with the top surface of the n-type semiconductor layer;
A reflective electrode formed in a region that includes a position directly below the formation position of the n-side electrode, the upper surface being in contact with the bottom surface of the p-type semiconductor layer;
A first insulating layer formed by contacting an upper surface with a bottom surface of the reflective electrode at a position immediately below the formation position of the n-side electrode is provided.
　この構成によれば、反射電極はｎ側電極の直下の位置にまで形成されているものの、その箇所においては底面に第１絶縁層が形成されているため、ｎ側電極の直下の位置において反射電極の底面より下方に電流が流れることがない。電流経路は第１絶縁層が形成されていない領域に形成されることから、上記構成によれば、反射電極とｎ側電極が鉛直方向に対向する位置関係であっても、反射電極とｎ側電極に挟まれた領域における発光層内にのみ大部分の電流が流れるということはない。つまり、上記構成においても、発光層内を流れる電流を支持基板の基板面に平行な方向（水平方向）に拡げる効果が得られる。 According to this configuration, although the reflective electrode is formed up to a position immediately below the n-side electrode, the first insulating layer is formed on the bottom surface at that location, so that the reflective electrode is reflected at a position directly below the n-side electrode. No current flows below the bottom surface of the electrode. Since the current path is formed in a region where the first insulating layer is not formed, according to the above configuration, even if the reflective electrode and the n-side electrode face each other in the vertical direction, the reflective electrode and the n-side Most of the current does not flow only in the light emitting layer in the region sandwiched between the electrodes. That is, also in the above configuration, an effect of spreading the current flowing in the light emitting layer in a direction (horizontal direction) parallel to the substrate surface of the support substrate can be obtained.
　図９を参照して説明した従来の構成であれば、反射膜９３の上層に形成されていた絶縁層９４によって、発光層９７内を流れる電流を水平方向に拡げる効果を実現していた。そして、この反射膜９３の上層に絶縁層９４が設けられていることで、発光層９７から放射された光が反射膜９３で反射されて取り出されるまでの間に、絶縁層９４内を２回通過することを余儀なくされ、この絶縁層９４内で数％の光が吸収されてしまっていた。 In the conventional configuration described with reference to FIG. 9, the effect of spreading the current flowing in the light emitting layer 97 in the horizontal direction is realized by the insulating layer 94 formed in the upper layer of the reflective film 93. Since the insulating layer 94 is provided above the reflective film 93, the light emitted from the light emitting layer 97 is reflected twice by the reflective film 93 and extracted twice in the insulating layer 94. The light was forced to pass through, and several percent of light was absorbed in the insulating layer 94.
　これに対し、上記の構成であれば、反射電極の下層に設けられた第１絶縁層によって発光層内を流れる電流を水平方向に拡げる効果が実現される。このため、反射電極の上層には必ずしも絶縁層を設ける必要がない。この結果、発光層から支持基板側に放射された光が反射電極で反射されてｎ型半導体層側の外部に取り出されるまでに、絶縁層によって吸収されることがなく、従来よりも取り出し効率が高められる。 On the other hand, with the above configuration, the effect of spreading the current flowing in the light emitting layer in the horizontal direction by the first insulating layer provided below the reflective electrode is realized. For this reason, it is not always necessary to provide an insulating layer above the reflective electrode. As a result, the light radiated from the light emitting layer to the support substrate side is not absorbed by the insulating layer until it is reflected by the reflective electrode and taken out to the outside of the n-type semiconductor layer side. Enhanced.
　なお、図９に示す従来の半導体発光素子９０においても、絶縁層９４は反射電極９５の底面の一部に接触するように形成されており、反射電極９５の上面にはｐ型窒化物層９６が形成されている。このため、発光層９７から下向き（支持基板９１側）に放射された光のうち、反射電極９５で反射される光については、絶縁層９４で吸収されるということはない。しかし、図９の構成では、ｎ側電極１００の直下の位置には反射電極９５が形成されておらず、絶縁層９４が形成されている。このため、発光層９７から放射された光のうち、ｎ側電極１００の直下に位置する領域内を下向きに通過する光については、反射電極９５によって反射させることができないため、絶縁層９４の底面に反射膜９３を設ける構成としている。ただし、この反射膜９３で反射された光が外部に取り出されるまでに絶縁層９４において一部が吸収されてしまう点は上述した通りである。 Also in the conventional semiconductor light emitting device 90 shown in FIG. 9, the insulating layer 94 is formed so as to be in contact with a part of the bottom surface of the reflective electrode 95, and the p-type nitride layer 96 is formed on the top surface of the reflective electrode 95. Is formed. For this reason, of the light emitted downward (from the support substrate 91 side) from the light emitting layer 97, the light reflected by the reflective electrode 95 is not absorbed by the insulating layer 94. However, in the configuration of FIG. 9, the reflective electrode 95 is not formed at a position immediately below the n-side electrode 100, and the insulating layer 94 is formed. For this reason, among the light radiated from the light emitting layer 97, the light passing downward in the region located immediately below the n-side electrode 100 cannot be reflected by the reflective electrode 95, and therefore the bottom surface of the insulating layer 94. The reflective film 93 is provided on the surface. However, as described above, a portion of the light reflected by the reflective film 93 is absorbed by the insulating layer 94 before being extracted to the outside.
　図９に示す半導体発光素子９０において、ｎ側電極１００の直下の位置に反射電極９５を形成しない構成としているのは、ｎ側電極１００と反射電極９５を鉛直方向に対向させると、この間に位置する発光層９７の領域にのみ重点的に電流が流れてしまい、発光層９７内の発光領域が限定的になることを想定したものであると考えられる。しかし、「発明を説明するための形態」の項で後述されるように、本発明者の鋭意研究によって、ｎ側電極の直下の位置に反射電極を形成しても、ｎ側電極の直下の位置において反射電極の底面に絶縁層（第１絶縁層）を形成しておくことで、発光層に流れる電流を水平方向に拡げる効果が実現できることを見出した。本発明は、この事実に基づいてなされたものである。 In the semiconductor light emitting device 90 shown in FIG. 9, the configuration in which the reflective electrode 95 is not formed immediately below the n-side electrode 100 is that when the n-side electrode 100 and the reflective electrode 95 are opposed to each other in the vertical direction, It is assumed that the current flows mainly only in the region of the light emitting layer 97 to be limited, and that the light emitting region in the light emitting layer 97 is limited. However, as will be described later in the section “Description of the Invention”, even if a reflective electrode is formed at a position immediately below the n-side electrode, the inventors have intensively studied. It was found that the effect of spreading the current flowing in the light emitting layer in the horizontal direction can be realized by forming an insulating layer (first insulating layer) on the bottom surface of the reflective electrode at the position. The present invention has been made based on this fact.
　特に、上記の構成において、前記反射電極は、上面の全てが前記ｐ型半導体層の底面と接触する構成とすることができる。 In particular, in the above-described configuration, the reflective electrode may be configured such that the entire top surface is in contact with the bottom surface of the p-type semiconductor layer.
　このような構成とすることで、発光層から下向きに放射された光が反射電極によって反射されてｎ型半導体層の上方へ取り出されるまでに、絶縁層によって吸収されることがなくなる。よって、従来構成と比べて光取り出し効率を大きく向上させることができる。 With such a configuration, the light emitted downward from the light emitting layer is not absorbed by the insulating layer until it is reflected by the reflective electrode and taken out above the n-type semiconductor layer. Therefore, the light extraction efficiency can be greatly improved as compared with the conventional configuration.
　また、別の構成として、
　前記ｎ側電極の形成箇所の直下の位置において、前記反射電極と前記ｐ型半導体層に挟まれる位置に形成された第２絶縁層を備え、
　前記第２絶縁層が、当該第２絶縁層の直上に位置する前記ｎ側電極よりも前記支持基板の基板面に平行な方向の幅が狭い構成とすることができる。 As another configuration,
A second insulating layer formed at a position sandwiched between the reflective electrode and the p-type semiconductor layer at a position immediately below the formation position of the n-side electrode;
The second insulating layer may have a narrower width in a direction parallel to the substrate surface of the support substrate than the n-side electrode located immediately above the second insulating layer.
　上記構成の場合、反射電極の上面に第２絶縁層が形成されるため、第２絶縁層内を通過した光については、当該第２絶縁層にて一部の光が吸収されてしまう。しかし、上述したように、本発明の構成では、反射電極の底面に形成された第１絶縁層によって発光層内を流れる電流を水平方向に拡げる効果が実現できている。このため、反射電極の上面に絶縁層（第２絶縁層）を形成する場合には、この第２絶縁層の幅を細くすることが可能である。つまり、第２絶縁層の幅をｎ側電極よりも細くしても、発光層内を流れる電流は第１絶縁層によって水平方向に拡げられる。そして、このように第２絶縁層の幅が細くできるため、反射電極の上面にこの第２絶縁層を形成したとしても、発光層から下向きに放射されて反射電極によって反射される光のうち、当該第２絶縁層内を通過する光を限定的にすることができる。従って、この構成においても、従来よりも光の取り出し効率を向上させることができる。 In the case of the above configuration, since the second insulating layer is formed on the upper surface of the reflective electrode, part of the light that has passed through the second insulating layer is absorbed by the second insulating layer. However, as described above, in the configuration of the present invention, the effect of spreading the current flowing in the light emitting layer in the horizontal direction can be realized by the first insulating layer formed on the bottom surface of the reflective electrode. For this reason, when an insulating layer (second insulating layer) is formed on the upper surface of the reflective electrode, the width of the second insulating layer can be reduced. That is, even if the width of the second insulating layer is narrower than that of the n-side electrode, the current flowing in the light emitting layer is expanded in the horizontal direction by the first insulating layer. And since the width | variety of a 2nd insulating layer can be made thin in this way, even if this 2nd insulating layer is formed in the upper surface of a reflective electrode, among the lights radiated | emitted downward from a light emitting layer and reflected by a reflective electrode, The light passing through the second insulating layer can be limited. Therefore, also in this configuration, the light extraction efficiency can be improved as compared with the conventional case.
　また、上記構成において、
　前記反射電極は、上面に前記第２絶縁層が形成されている領域を除いて、上面の全てが前記ｐ型半導体層の底面と接触している構成とすることができる。 In the above configuration,
The reflective electrode may be configured such that the entire top surface is in contact with the bottom surface of the p-type semiconductor layer except for the region where the second insulating layer is formed on the top surface.
　また、本発明の半導体発光素子は、前記ｎ型半導体層、前記ｐ型半導体層、及び前記発光層の全てを窒化物半導体層で形成した、窒化物半導体発光素子として実現することができる。 In addition, the semiconductor light emitting device of the present invention can be realized as a nitride semiconductor light emitting device in which all of the n-type semiconductor layer, the p-type semiconductor layer, and the light emitting layer are formed of a nitride semiconductor layer.
　本発明の半導体発光素子によれば、発光層を流れる電流の水平方向への拡がりを確保しながら、従来構成よりも光の取り出し効率を更に向上させることができる。 According to the semiconductor light emitting device of the present invention, it is possible to further improve the light extraction efficiency as compared with the conventional configuration while ensuring the horizontal spread of the current flowing through the light emitting layer.
半導体発光素子の第１実施形態の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of 1st Embodiment of a semiconductor light-emitting device. 半導体発光素子の第１実施形態の構成を模式的に示す平面図である。It is a top view which shows typically the structure of 1st Embodiment of a semiconductor light-emitting device. 半導体発光素子の第１実施形態の工程断面図の一部である。It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. 半導体発光素子の第１実施形態の工程断面図の一部である。It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. 半導体発光素子の第１実施形態の工程断面図の一部である。It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. 半導体発光素子の第１実施形態の工程断面図の一部である。It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. 半導体発光素子の第１実施形態の工程断面図の一部である。It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. 半導体発光素子の第１実施形態の工程断面図の一部である。It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. 半導体発光素子の第１実施形態の工程断面図の一部である。It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. 半導体発光素子の第１実施形態の工程断面図の一部である。It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. 半導体発光素子の第１実施形態の工程断面図の一部である。It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. 半導体発光素子の第１実施形態の工程断面図の一部である。It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. 半導体発光素子の第２実施形態の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of 2nd Embodiment of a semiconductor light-emitting device. 半導体発光素子の第２実施形態の工程断面図の一部である。It is a part of process sectional drawing of 2nd Embodiment of a semiconductor light-emitting device. 半導体発光素子の第２実施形態の工程断面図の一部である。It is a part of process sectional drawing of 2nd Embodiment of a semiconductor light-emitting device. 比較例として形成した半導体発光素子の構造を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the semiconductor light-emitting device formed as a comparative example. 実施例１、実施例２、及び比較例の各素子に対して電圧を印加したときの、流れる電流値と電圧値の関係（Ｉ－Ｖ特性）を示すグラフである。It is a graph which shows the relationship (IV characteristic) of the electric current value which flows when a voltage is applied with respect to each element of Example 1, Example 2, and a comparative example. 実施例１、実施例２、及び比較例の各素子に対して電流を供給したときに得られる発光出力と電流値の関係を示すグラフである。It is a graph which shows the relationship between the light emission output obtained when supplying an electric current with respect to each element of Example 1, Example 2, and a comparative example, and an electric current value. 半導体発光素子の別実施形態の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of another embodiment of a semiconductor light-emitting device. 従来の半導体発光素子の構成を模式的に示す断面図である。It is sectional drawing which shows the structure of the conventional semiconductor light-emitting device typically.
　本発明の半導体発光素子につき、図面を参照して説明する。なお、各図において図面の寸法比と実際の寸法比は必ずしも一致しない。また、本明細書において、「第１の層が第２の層の直下に位置する」とは、支持基板の基板面に垂直な方向に関して、第１の層の下方に第２の層が位置することを意味する。 The semiconductor light emitting device of the present invention will be described with reference to the drawings. In each figure, the dimensional ratio in the drawing does not necessarily match the actual dimensional ratio. Further, in this specification, “the first layer is located immediately below the second layer” means that the second layer is located below the first layer in the direction perpendicular to the substrate surface of the support substrate. It means to do.
　［第１実施形態］
　本発明の半導体発光素子の第１実施形態の構成について説明する。 [First Embodiment]
The configuration of the first embodiment of the semiconductor light emitting device of the present invention will be described.
　〈構造〉
　図１Ａは、第１実施形態の半導体発光素子の構成を模式的に示す断面図である。半導体発光素子１は、支持基板１１、導電層２０、絶縁層２１、半導体層３０及びｎ側電極（４２，４３）を含んで構成される。半導体層３０は、ｐ型半導体層（３２，３１）、発光層３３、及びｎ型半導体層３５が下からこの順に積層されて形成されている。なお、図１Ｂは、半導体発光素子１を上面から見たときの模式的な平面図であり、図１Ａは、図１ＢにおけるＡ－Ａ線断面図に対応している。 <Construction>
FIG. 1A is a cross-sectional view schematically showing the configuration of the semiconductor light emitting device of the first embodiment. The semiconductor light emitting device 1 includes a support substrate 11, a conductive layer 20, an insulating layer 21, a semiconductor layer 30, and n-side electrodes (42, 43). The semiconductor layer 30 is formed by stacking a p-type semiconductor layer (32, 31), a light emitting layer 33, and an n-type semiconductor layer 35 in this order from the bottom. 1B is a schematic plan view of the semiconductor light emitting element 1 as viewed from above, and FIG. 1A corresponds to a cross-sectional view taken along line AA in FIG. 1B.
　　（支持基板１１）
　支持基板１１は、例えばＣｕＷ、Ｗ、Ｍｏなどの導電性基板、又はＳｉなどの半導体基板で構成される。 (Support substrate 11)
The support substrate 11 is composed of a conductive substrate such as CuW, W, or Mo, or a semiconductor substrate such as Si.
　　（導電層２０）
　支持基板１１の上層には、多層構造からなる導電層２０が形成されている。この導電層２０は、本実施形態では、ハンダ層１３、ハンダ層１５、保護層１７及び反射電極１９を含む。 (Conductive layer 20)
A conductive layer 20 having a multilayer structure is formed on the support substrate 11. In this embodiment, the conductive layer 20 includes a solder layer 13, a solder layer 15, a protective layer 17, and a reflective electrode 19.
　ハンダ層１３及びハンダ層１５は、例えばＡｕ－Ｓｎ、Ａｕ－Ｉｎ、Ａｕ－Ｃｕ－Ｓｎ、Ｃｕ－Ｓｎ、Ｐｄ－Ｓｎ、Ｓｎなどで構成される。後述するように、これらのハンダ層１３とハンダ層１５は、支持基板１１上に形成されたハンダ層１３と、別の基板（後述するサファイア基板６１）上に形成されたハンダ層１５を対向させた後に、両者を貼り合わせることで形成されたものである。 The solder layer 13 and the solder layer 15 are made of, for example, Au—Sn, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like. As will be described later, the solder layer 13 and the solder layer 15 make the solder layer 13 formed on the support substrate 11 and the solder layer 15 formed on another substrate (a sapphire substrate 61 described later) face each other. Then, the two are bonded together.
　保護層１７は、例えばＰｔ系の金属（ＴｉとＰｔの合金）、Ｗ、Ｍｏ、Ｎｉなどで構成される。後述するように、ハンダ層を介した貼り合わせの際、ハンダを構成する材料が後述する反射電極１９側に拡散し、反射率が落ちることによる発光効率の低下を防止する機能を果たしている。 The protective layer 17 is made of, for example, a Pt-based metal (an alloy of Ti and Pt), W, Mo, Ni, or the like. As will be described later, when bonding is performed via the solder layer, the material constituting the solder is diffused to the reflective electrode 19 side described later, and the function of preventing a decrease in luminous efficiency due to a drop in reflectance is achieved.
　反射電極１９は、例えばＡｇ系の金属（ＮｉとＡｇの合金）、Ａｌ、Ｒｈなどで構成される。半導体発光素子１は、発光層３３から放射された光を、図１Ａの上方向（ｎ型半導体層３５側）に取り出すことを想定しており、反射電極１９は、発光層３３から下向きに放射された光を上向きに反射させることで発光効率を高める機能を果たしている。なお、図１Ａ内における上向きの矢印は、光の取り出し方向を表している。 The reflective electrode 19 is made of, for example, an Ag-based metal (an alloy of Ni and Ag), Al, Rh, or the like. It is assumed that the semiconductor light emitting element 1 takes out the light emitted from the light emitting layer 33 upward (on the n-type semiconductor layer 35 side) in FIG. 1A, and the reflective electrode 19 emits downward from the light emitting layer 33. The function of improving the luminous efficiency is achieved by reflecting the emitted light upward. In addition, the upward arrow in FIG. 1A represents the light extraction direction.
　反射電極１９は、ｎ側電極（４２，４３）の直下の位置を含むｐ型半導体層（３１，３２）の下層に形成されている。特に、図１Ａに示すように、本実施形態では反射電極１９の上面は全てｐ型半導体層３２と接触するように形成されている。そして、支持基板１１とｎ側電極（４２，４３）の間に電圧が印加されると、支持基板１１、ハンダ層（１３，１５）、保護層１７、反射電極１９、半導体層３０を介してｎ側電極（４２，４３）へと流れる電流経路が形成される。 The reflective electrode 19 is formed in the lower layer of the p-type semiconductor layer (31, 32) including the position immediately below the n-side electrode (42, 43). In particular, as shown in FIG. 1A, in this embodiment, the upper surface of the reflective electrode 19 is formed so as to be in contact with the p-type semiconductor layer 32. When a voltage is applied between the support substrate 11 and the n-side electrodes (42, 43), the support substrate 11, the solder layers (13, 15), the protective layer 17, the reflective electrode 19, and the semiconductor layer 30 are interposed. A current path that flows to the n-side electrode (42, 43) is formed.
　　（絶縁層２１）
　絶縁層２１は、例えばＳｉＯ２、ＳｉＮ、Ｚｒ２Ｏ３、ＡｌＮ、Ａｌ２Ｏ３などで構成される。この絶縁層２１は、「第１絶縁層」に対応する。 (Insulating layer 21)
Insulating layer 21 is composed for example SiO 2, SiN, Zr 2 O 3, AlN, etc. Al 2 O 3. The insulating layer 21 corresponds to a “first insulating layer”.
　絶縁層２１は、ｎ側電極（４２，４３）の直下の位置に形成されており、絶縁層２１の上面は反射電極１９の底面に接触している。この絶縁層２１は、発光層３３を流れる電流を支持基板１１の基板面に平行な方向（水平方向）に拡げる役割を果たしている。更に、絶縁層２１は半導体層３０の外側の位置にも形成されており、プロセスの項で後述するように、素子分離時におけるエッチングストッパー層としても機能する。 The insulating layer 21 is formed immediately below the n-side electrodes (42, 43), and the upper surface of the insulating layer 21 is in contact with the bottom surface of the reflective electrode 19. The insulating layer 21 serves to expand the current flowing through the light emitting layer 33 in a direction (horizontal direction) parallel to the substrate surface of the support substrate 11. Furthermore, the insulating layer 21 is also formed at a position outside the semiconductor layer 30 and functions as an etching stopper layer at the time of element isolation, as will be described later in the section of the process.
　　（半導体層３０）
　上述したように、半導体層３０は、ｐ型半導体層３２、ｐ型半導体層３１、発光層３３、及びｎ型半導体層３５が下からこの順に積層されて形成される。 (Semiconductor layer 30)
As described above, the semiconductor layer 30 is formed by stacking the p-type semiconductor layer 32, the p-type semiconductor layer 31, the light emitting layer 33, and the n-type semiconductor layer 35 in this order from the bottom.
　ｐ型半導体層３２は、例えばＧａＮで構成される。また、ｐ型半導体層３１は、例えばＡｌｍＧａ１－ｍＮ（０≦ｍ＜１）で構成される。いずれの層も、Ｍｇ、Ｂｅ、Ｚｎ、又はＣなどのｐ型不純物がドープされている。なお、ｐ型半導体層３２は、ｐ型半導体層３１よりも不純物濃度が高濃度であり、コンタクト層を形成している。 The p-type semiconductor layer 32 is made of, for example, GaN. The p-type semiconductor layer 31 is made of, for example, Al m Ga 1-m N (0 ≦ m <1). All layers are doped with p-type impurities such as Mg, Be, Zn, or C. Note that the p-type semiconductor layer 32 has a higher impurity concentration than the p-type semiconductor layer 31 and forms a contact layer.
　発光層３３は、例えばＩｎＧａＮからなる井戸層とＡｌＧａＮからなる障壁層が繰り返されてなる多重量子井戸構造を有する半導体層で形成される。これらの層はアンドープでもｐ型又はｎ型にドープされていても構わない。 The light emitting layer 33 is formed of a semiconductor layer having a multiple quantum well structure in which, for example, a well layer made of InGaN and a barrier layer made of AlGaN are repeated. These layers may be undoped or p-type or n-type doped.
　ｎ型半導体層３５は、例えばＡｌｎＧａ１－ｎＮ（０≦ｎ＜１）で構成される層（電子供給層）とＧａＮで構成される層（保護層）を含む多層構造で構成される。少なくとも保護層には、Ｓｉ、Ｇｅ、Ｓ、Ｓｅ、Ｓｎ、又はＴｅなどのｎ型不純物がドープされている。 The n-type semiconductor layer 35 has a multilayer structure including, for example, a layer (electron supply layer) made of Al n Ga 1-n N (0 ≦ n <1) and a layer (protective layer) made of GaN. The At least the protective layer is doped with an n-type impurity such as Si, Ge, S, Se, Sn, or Te.
　　（ｎ側電極４２，ｎ側電極４３）
　ｎ側電極（４２，４３）はｎ型半導体層３５の上層であって、図１Ａに示す断面図においてｎ型半導体層３５の端部近傍領域と中央近傍領域に形成され、例えばＣｒ－Ａｕで構成される。端部近傍領域に形成されたものがｎ側電極４３、中央近傍領域に形成されたものがｎ側電極４２に対応する。また、ｎ側電極４３には、例えば領域４３ａ及び４３ｂにおいて、Ａｕ、Ｃｕなどで構成されるワイヤ４５が連絡されており、このワイヤ４５の他方は、半導体発光素子１が配置されている基板（支持基板１１）の給電パターンなどに接続される（不図示）。つまり、ｎ側電極４３は、半導体発光素子１の給電端子として機能している。なお、図１Ａ及び図１Ｂでは、ｎ側電極４２が中央近傍の１箇所に形成される構成としているが、このｎ側電極４２を複数形成することで、格子状に配置するものとしても構わない。更に、ｎ側電極４２同士を交差させて網目状に配置しても構わない。 (N-side electrode 42, n-side electrode 43)
The n-side electrodes (42, 43) are the upper layers of the n-type semiconductor layer 35, and are formed in the region near the end and the region near the center of the n-type semiconductor layer 35 in the cross-sectional view shown in FIG. Composed. What is formed in the region near the end corresponds to the n-side electrode 43, and what is formed in the region near the center corresponds to the n-side electrode 42. Further, a wire 45 made of Au, Cu or the like is connected to the n-side electrode 43, for example, in the regions 43a and 43b, and the other of the wires 45 is a substrate on which the semiconductor light emitting element 1 is disposed ( It is connected to a power supply pattern of the support substrate 11) (not shown). That is, the n-side electrode 43 functions as a power supply terminal of the semiconductor light emitting element 1. 1A and 1B, the n-side electrode 42 is formed at one location near the center. However, a plurality of n-side electrodes 42 may be formed and arranged in a lattice pattern. . Furthermore, the n-side electrodes 42 may be crossed and arranged in a mesh shape.
　また、図１Ｂにも示すように、ｎ側電極４２とｎ側電極４３は半導体層３０の上面において連結されており、半導体層３０の平面上に電流経路を拡げる役目を果たしている。つまり、ｎ型半導体層３５の上面のうち、給電端子を構成するｎ側電極４３とは異なる箇所においてｎ型半導体層３５の上面と接触することで、通電時において水平方向に関してｎ型半導体層３５の広い範囲に電流を流し、これによって発光層３３内の広い範囲に電流を流すことを目的として形成されている。 Further, as shown in FIG. 1B, the n-side electrode 42 and the n-side electrode 43 are connected on the upper surface of the semiconductor layer 30 and serve to expand the current path on the plane of the semiconductor layer 30. That is, by contacting the upper surface of the n-type semiconductor layer 35 at a location different from the n-side electrode 43 constituting the power supply terminal in the upper surface of the n-type semiconductor layer 35, the n-type semiconductor layer 35 in the horizontal direction when energized. It is formed for the purpose of flowing a current over a wide range of the light-emitting layer 33, thereby causing a current to flow over a wide range of the light emitting layer 33.
　なお、図示していないが、半導体層３０の側面に保護膜としての絶縁層を形成しても構わない。なお、この保護膜としての絶縁層は、透光性を有する材料（例えばＳｉＯ２など）で構成するのが好ましい。また、上述の実施形態では、ｐ型半導体層３１を構成する一材料をＡｌｍＧａ１－ｍＮ（０≦ｍ＜１）と記載し、ｎ型半導体層３５を構成する一材料をＡｌｎＧａ１－ｎＮ（０≦ｎ＜１）と記載したが、これらは同一の材料であっても構わない。 Although not shown, an insulating layer as a protective film may be formed on the side surface of the semiconductor layer 30. Note that the insulating layer as the protective film is preferably made of a light-transmitting material (eg, SiO 2 ). In the above-described embodiment, one material constituting the p-type semiconductor layer 31 is described as Al m Ga 1-m N (0 ≦ m <1), and one material constituting the n-type semiconductor layer 35 is Al n n. Although described as Ga 1-n N (0 ≦ n <1), these may be the same material.
　また、光取り出し効率を更に高める目的で、ｎ型半導体層３５の上面に微小の凹凸（メサ構造）を形成しても構わない。 Further, for the purpose of further increasing the light extraction efficiency, minute irregularities (mesa structure) may be formed on the upper surface of the n-type semiconductor layer 35.
　図１Ａに示す構成によれば、反射電極１９はｎ側電極（４２，４３）の直下の位置を含む領域に形成されているものの、ｎ側電極（４２，４３）の直下の位置においては反射電極１９の底面に絶縁層２１が形成されているため、ｎ側電極（４２，４３）の直下の位置において反射電極１９の底面より下方に電流が流れることがない。電流経路は絶縁層２１が形成されていない領域に形成されることから、上記構成によれば、反射電極１９とｎ側電極（４２，４３）が鉛直方向に対向する位置関係であっても、反射電極１９とｎ側電極（４２，４３）に挟まれた領域における発光層３３内にのみ大部分の電流が流れるということはない。つまり、図１Ａに示す半導体発光素子１によれば、反射電極１９の上層に絶縁層を設けなくても、発光層３３内を流れる電流を支持基板１１の基板面に平行な方向（水平方向）に拡げる効果が得られる。 According to the configuration shown in FIG. 1A, the reflective electrode 19 is formed in a region including a position directly below the n-side electrode (42, 43), but is reflected at a position immediately below the n-side electrode (42, 43). Since the insulating layer 21 is formed on the bottom surface of the electrode 19, no current flows below the bottom surface of the reflective electrode 19 at a position immediately below the n-side electrodes (42, 43). Since the current path is formed in a region where the insulating layer 21 is not formed, according to the above configuration, even if the reflective electrode 19 and the n-side electrode (42, 43) are in a positional relationship facing each other in the vertical direction, Most of the current does not flow only in the light emitting layer 33 in the region sandwiched between the reflective electrode 19 and the n-side electrode (42, 43). That is, according to the semiconductor light emitting device 1 shown in FIG. 1A, the current flowing in the light emitting layer 33 is parallel to the substrate surface of the support substrate 11 (horizontal direction) without providing an insulating layer on the reflective electrode 19. The effect can be obtained.
　この結果、発光層３３から支持基板１１側に放射された光が反射電極１９で反射されてｎ型半導体層３５側に取り出されるまでに、絶縁層によって吸収されることがなく、従来よりも取り出し効率が高められる。 As a result, the light radiated from the light emitting layer 33 to the support substrate 11 side is not absorbed by the insulating layer until it is reflected by the reflective electrode 19 and taken out to the n-type semiconductor layer 35 side. Efficiency is increased.
　本実施形態の半導体発光素子１によれば、従来構成と同等の低電圧駆動を実現しながら、従来構成よりも光の取り出し効率が高められていることに関しては、第２実施形態の構成を説明した後、実施例及び比較例の素子による結果を参照して示される。 According to the semiconductor light emitting device 1 of the present embodiment, the configuration of the second embodiment will be described with respect to the fact that the light extraction efficiency is higher than the conventional configuration while realizing the low voltage driving equivalent to the conventional configuration. After that, it will be shown with reference to the results of the elements of the examples and comparative examples.
　〈製造方法〉
　次に、半導体発光素子１の製造方法の一例につき、図２Ａ～図２Ｊに示す工程断面図を参照して説明する。なお、以下で説明する製造条件や膜厚などの寸法は、あくまで一例であって、これらの数値に限定されるものではない。 <Production method>
Next, an example of a method for manufacturing the semiconductor light emitting device 1 will be described with reference to process cross-sectional views shown in FIGS. 2A to 2J. The dimensions such as manufacturing conditions and film thickness described below are merely examples, and are not limited to these numerical values.
　　（ステップＳ１）
　図２Ａに示すように、サファイア基板６１上にエピ層４０を形成する。このステップＳ１は例えば以下の手順により行われる。 (Step S1)
As shown in FIG. 2A, the epi layer 40 is formed on the sapphire substrate 61. This step S1 is performed by the following procedure, for example.
　　　（サファイア基板６１の準備）
　まず、ｃ面サファイア基板６１のクリーニングを行う。このクリーニングは、より具体的には、例えばＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition：有機金属化学気相蒸着）装置の処理炉内にｃ面サファイア基板６１を配置し、処理炉内に流量が１０ｓｌｍの水素ガスを流しながら、炉内温度を例えば１１５０℃に昇温することにより行われる。 (Preparation of sapphire substrate 61)
First, the c-plane sapphire substrate 61 is cleaned. More specifically, for this cleaning, for example, a c-plane sapphire substrate 61 is placed in a processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and hydrogen having a flow rate of 10 slm is placed in the processing furnace. While flowing the gas, the temperature in the furnace is raised to, for example, 1150 ° C.
　　　（アンドープ層３６の形成）
　次に、ｃ面サファイア基板６１の表面に、ＧａＮよりなる低温バッファ層を形成し、更にその上層にＧａＮよりなる下地層を形成する。これらの低温バッファ層及び下地層がアンドープ層３６に対応する。 (Formation of undoped layer 36)
Next, a low-temperature buffer layer made of GaN is formed on the surface of the c-plane sapphire substrate 61, and a base layer made of GaN is further formed thereon. These low-temperature buffer layer and underlayer correspond to the undoped layer 36.
　アンドープ層３６のより具体的な形成方法は例えば以下の通りである。まず、МОＣＶＤ装置の炉内圧力を１００ｋＰａ、炉内温度を４８０℃とする。そして、処理炉内にキャリアガスとして流量がそれぞれ５ｓｌｍの窒素ガス及び水素ガスを流しながら、原料ガスとして、流量が５０μｍｏｌ／ｍｉｎのトリメチルガリウム（ＴＭＧ）及び流量が２５００００μｍｏｌ／ｍｉｎのアンモニアを処理炉内に６８秒間供給する。これにより、ｃ面サファイア基板６１の表面に、厚みが２０ｎｍのＧａＮよりなる低温バッファ層を形成する。 For example, a more specific method for forming the undoped layer 36 is as follows. First, the furnace pressure of the МОCVD apparatus is 100 kPa, and the furnace temperature is 480 ° C. Then, while flowing nitrogen gas and hydrogen gas with a flow rate of 5 slm respectively as carrier gas into the processing furnace, trimethylgallium (TMG) with a flow rate of 50 μmol / min and ammonia with a flow rate of 250,000 μmol / min are used as the raw material gas in the processing furnace. For 68 seconds. As a result, a low-temperature buffer layer made of GaN having a thickness of 20 nm is formed on the surface of the c-plane sapphire substrate 61.
　次に、ＭＯＣＶＤ装置の炉内温度を１１５０℃に昇温する。そして、処理炉内にキャリアガスとして流量が２０ｓｌｍの窒素ガス及び流量が１５ｓｌｍの水素ガスを流しながら、原料ガスとして、流量が１００μｍｏｌ／ｍｉｎのＴＭＧ及び流量が２５００００μｍｏｌ／ｍｉｎのアンモニアを処理炉内に３０分間供給する。これにより、低温バッファ層の表面に、厚みが１．７μｍのＧａＮよりなる下地層を形成する。 Next, the furnace temperature of the MOCVD apparatus is raised to 1150 ° C. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas in the processing furnace, TMG having a flow rate of 100 μmol / min and ammonia having a flow rate of 250,000 μmol / min are introduced into the processing furnace as source gases. Feed for 30 minutes. As a result, a base layer made of GaN having a thickness of 1.7 μm is formed on the surface of the low-temperature buffer layer.
　　〈ｎ型半導体層３５の形成〉
　次に、アンドープ層３６の上層にＡｌｎＧａ１－ｎＮ（０≦ｎ≦１）の組成からなるｎ型半導体層３５を形成する。 <Formation of n-type semiconductor layer 35>
Next, an n-type semiconductor layer 35 having a composition of Al n Ga 1-n N (0 ≦ n ≦ 1) is formed on the undoped layer 36.
　ｎ型半導体層３５のより具体的な形成方法は、例えば以下の通りである。まず、引き続き炉内温度を１１５０℃とした状態で、ＭＯＣＶＤ装置の炉内圧力を３０ｋＰａとする。そして、処理炉内にキャリアガスとして流量が２０ｓｌｍの窒素ガス及び流量が１５ｓｌｍの水素ガスを流しながら、原料ガスとして、流量が９４μｍｏｌ／ｍｉｎのＴＭＧ、流量が６μｍｏｌ／ｍｉｎのトリメチルアルミニウム（ＴＭＡ）、流量が２５００００μｍｏｌ／ｍｉｎのアンモニア及び流量が０．０２５μｍｏｌ／ｍｉｎのテトラエチルシランを処理炉内に６０分間供給する。これにより、例えばＡｌ０．０６Ｇａ０．９４Ｎの組成を有し、Ｓｉ濃度が３×１０１９／ｃｍ３で、厚みが２μｍのｎ型半導体層３５がアンドープ層３６の上層に形成される。 A more specific method for forming the n-type semiconductor layer 35 is, for example, as follows. First, with the furnace temperature kept at 1150 ° C., the furnace pressure of the MOCVD apparatus is set to 30 kPa. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas into the processing furnace, TMG having a flow rate of 94 μmol / min, trimethylaluminum (TMA) having a flow rate of 6 μmol / min, Ammonia with a flow rate of 250,000 μmol / min and tetraethylsilane with a flow rate of 0.025 μmol / min are supplied into the treatment furnace for 60 minutes. Thereby, for example, an n-type semiconductor layer 35 having a composition of Al 0.06 Ga 0.94 N, a Si concentration of 3 × 10 19 / cm 3 , and a thickness of 2 μm is formed in the upper layer of the undoped layer 36. .
　なお、この後、ＴＭＡの供給を停止すると共に、それ以外の原料ガスを６秒間供給することにより、ｎ－ＡｌＧａＮ層の上層に厚みが５ｎｍのｎ型ＧａＮよりなる保護層を有するｎ型半導体層３５を実現してもよい。 After that, the supply of TMA is stopped, and other source gases are supplied for 6 seconds, whereby an n-type semiconductor layer having a protective layer made of n-type GaN having a thickness of 5 nm on the n-AlGaN layer. 35 may be realized.
　上記の説明では、ｎ型半導体層３５に含まれるｎ型不純物をＳｉとする場合について説明したが、ｎ型不純物としては、Ｓｉ以外にＧｅ、Ｓ、Ｓｅ、Ｓｎ又はＴｅ等を用いることができる。 In the above description, the case where Si is used as the n-type impurity contained in the n-type semiconductor layer 35 has been described. However, Ge, S, Se, Sn, Te, or the like can be used as the n-type impurity in addition to Si. .
　　〈発光層３３の形成〉
　次に、ｎ型半導体層３５の上層にＩｎＧａＮで構成される井戸層及びｎ型ＡｌＧａＮで構成される障壁層が周期的に繰り返される多重量子井戸構造を有する発光層３３を形成する。 <Formation of the light emitting layer 33>
Next, a light emitting layer 33 having a multiple quantum well structure in which a well layer made of InGaN and a barrier layer made of n-type AlGaN are periodically repeated is formed on the n-type semiconductor layer 35.
　具体的には、まずＭＯＣＶＤ装置の炉内圧力を１００ｋＰａ、炉内温度を８３０℃とする。そして、処理炉内にキャリアガスとして流量が１５ｓｌｍの窒素ガス及び流量が１ｓｌｍの水素ガスを流しながら、原料ガスとして、流量が１０μｍｏｌ／ｍｉｎのＴＭＧ、流量が１２μｍｏｌ／ｍｉｎのトリメチルインジウム（ＴＭＩ）及び流量が３０００００μｍｏｌ／ｍｉｎのアンモニアを処理炉内に４８秒間供給するステップを行う。その後、流量が１０μｍｏｌ／ｍｉｎのＴＭＧ、流量が１．６μｍｏｌ／ｍｉｎのＴＭＡ、０．００２μｍｏｌ／ｍｉｎのテトラエチルシラン及び流量が３０００００μｍｏｌ／ｍｉｎのアンモニアを処理炉内に１２０秒間供給するステップを行う。以下、これらの２つのステップを繰り返すことにより、厚みが２ｎｍのＩｎＧａＮよりなる井戸層及び厚みが７ｎｍのｎ型ＡｌＧａＮよりなる障壁層による１５周期の多重量子井戸構造を有する発光層３３が、ｎ型半導体層３５の上層に形成される。 Specifically, first, the furnace pressure of the MOCVD apparatus is set to 100 kPa, and the furnace temperature is set to 830 ° C. Then, while flowing nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 1 slm as a carrier gas in the processing furnace, TMG having a flow rate of 10 μmol / min, trimethylindium (TMI) having a flow rate of 12 μmol / min, and A step of supplying ammonia at a flow rate of 300,000 μmol / min into the processing furnace for 48 seconds is performed. Thereafter, TMG having a flow rate of 10 μmol / min, TMA having a flow rate of 1.6 μmol / min, tetraethylsilane having a flow rate of 0.002 μmol / min, and ammonia having a flow rate of 300,000 μmol / min are supplied into the processing furnace for 120 seconds. Hereinafter, by repeating these two steps, the light-emitting layer 33 having a multi-quantum well structure of 15 periods with a well layer made of InGaN having a thickness of 2 nm and a barrier layer made of n-type AlGaN having a thickness of 7 nm is formed into an n-type. It is formed in the upper layer of the semiconductor layer 35.
　　〈ｐ型半導体層３１の形成〉
　次に、発光層３３の上層に、ＡｌｍＧａ１－ｍＮ（０≦ｍ≦１）で構成されるｐ型半導体層３１を形成する。 <Formation of p-type semiconductor layer 31>
Next, a p-type semiconductor layer 31 composed of Al m Ga 1-m N (0 ≦ m ≦ 1) is formed on the light emitting layer 33.
　具体的には、ＭＯＣＶＤ装置の炉内圧力を１００ｋＰａに維持し、処理炉内にキャリアガスとして流量が１５ｓｌｍの窒素ガス及び流量が２５ｓｌｍの水素ガスを流しながら、炉内温度を１０２５℃に昇温する。その後、原料ガスとして、流量が３５μｍｏｌ／ｍｉｎのＴＭＧ、流量が２０μｍｏｌ／ｍｉｎのＴＭＡ、流量が２５００００μｍｏｌ／ｍｉｎのアンモニア及びｐ型不純物をドープするための流量が０．１μｍｏｌ／ｍｉｎのビスシクロペンタジエニルマグネシウム（ＣＰ２Ｍｇ）を処理炉内に６０秒間供給する。これにより、発光層３３の表面に、厚みが２０ｎｍのＡｌ０．３Ｇａ０．７Ｎの組成を有する正孔供給層を形成する。その後、ＴＭＡの流量を４μｍｏｌ／ｍｉｎに変更して原料ガスを３６０秒間供給することにより、厚みが１２０ｎｍのＡｌ０．１３Ｇａ０．８７Ｎの組成を有する正孔供給層を形成する。これらの正孔供給層によりｐ型半導体層３１が形成される。このｐ型半導体層３１のｐ型不純物濃度は、例えば３×１０１９／ｃｍ３程度である。 Specifically, the furnace pressure of the MOCVD apparatus is maintained at 100 kPa, and the furnace temperature is raised to 1025 ° C. while nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 25 slm are supplied as carrier gases in the processing furnace. To do. Thereafter, as source gases, TMG with a flow rate of 35 μmol / min, TMA with a flow rate of 20 μmol / min, ammonia with a flow rate of 250,000 μmol / min, and biscyclopentadiene with a flow rate of 0.1 μmol / min for doping p-type impurities. Enilmagnesium (CP 2 Mg) is fed into the processing furnace for 60 seconds. Thereby, a hole supply layer having a composition of Al 0.3 Ga 0.7 N having a thickness of 20 nm is formed on the surface of the light emitting layer 33. Thereafter, by changing the flow rate of TMA to 4 μmol / min and supplying the source gas for 360 seconds, a hole supply layer having a composition of Al 0.13 Ga 0.87 N having a thickness of 120 nm is formed. A p-type semiconductor layer 31 is formed by these hole supply layers. The p-type impurity concentration of the p-type semiconductor layer 31 is, for example, about 3 × 10 19 / cm 3 .
　　〈ｐ型半導体層３２の形成〉
　更にその後、ＴＭＡの供給を停止すると共に、ＣＰ２Ｍｇの流量を０．２μｍｏｌ／ｍｉｎに変更して原料ガスを２０秒間供給することにより、厚みが５ｎｍ程度で、ｐ型不純物濃度が１×１０２０／ｃｍ３程度のｐ＋ＧａＮよりなるｐ型半導体層３２を形成する。 <Formation of p-type semiconductor layer 32>
Thereafter, the supply of TMA is stopped, the flow rate of CP 2 Mg is changed to 0.2 μmol / min, and the raw material gas is supplied for 20 seconds, whereby the thickness is about 5 nm and the p-type impurity concentration is 1 × 10. A p-type semiconductor layer 32 made of p + GaN of about 20 / cm 3 is formed.
　このようにしてサファイア基板６１上に、アンドープ層３６、ｎ型半導体層３５、発光層３３、ｐ型半導体層３１、及びｐ型半導体層３２からなるエピ層４０が形成される。 In this way, the epi layer 40 including the undoped layer 36, the n-type semiconductor layer 35, the light emitting layer 33, the p-type semiconductor layer 31, and the p-type semiconductor layer 32 is formed on the sapphire substrate 61.
　　（ステップＳ２）
　次に、ステップＳ１で得られたウェハに対して活性化処理を行う。より具体的には、ＲＴＡ（Rapid Thermal Anneal：急速加熱）装置を用いて、窒素雰囲気下中６５０℃で１５分間の活性化処理を行う。 (Step S2)
Next, an activation process is performed on the wafer obtained in step S1. More specifically, activation is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal) device.
　　（ステップＳ３）
　次に、図２Ｂに示すように、ｐ型半導体層３２の上面の所定箇所に反射電極１９を形成する。ここでは、ｐ型半導体層３２の形成領域よりも内側において、ｐ型半導体層３２のほぼ全域に反射電極１９を形成する場合を示している。より具体的には、後の工程で給電端子としてのｎ側電極４２を形成する領域の直下に位置する箇所を含むように反射電極１９を形成する。 (Step S3)
Next, as shown in FIG. 2B, the reflective electrode 19 is formed at a predetermined location on the upper surface of the p-type semiconductor layer 32. Here, a case is shown in which the reflective electrode 19 is formed in almost the entire region of the p-type semiconductor layer 32 inside the region where the p-type semiconductor layer 32 is formed. More specifically, the reflective electrode 19 is formed so as to include a portion located immediately below a region where the n-side electrode 42 as a power supply terminal is formed in a later step.
　反射電極１９は、一例として、スパッタ装置にてｐ型半導体層３２の上面に膜厚０．７ｎｍのＮｉ及び膜厚１５０ｎｍのＡｇを成膜した後、ＲＴＡ装置を用いてドライエア雰囲気中で４００℃、２分間のコンタクトアニールを行うことで形成される。なお、ここでは、反射電極１９の材料としてＮｉとＡｇの合金を採用しているが、ＡｌやＲｈによって反射電極１９を形成することもできる。 For example, the reflective electrode 19 is formed by depositing 0.7 nm-thickness Ni and 150 nm-thick Ag on the upper surface of the p-type semiconductor layer 32 by a sputtering apparatus, and then using an RTA apparatus in a dry air atmosphere at 400 ° C. It is formed by performing contact annealing for 2 minutes. Here, although the alloy of Ni and Ag is adopted as the material of the reflective electrode 19, the reflective electrode 19 can also be formed of Al or Rh.
　　（ステップＳ４）
　次に、図２Ｃに示すように、反射電極１９の上層の所定箇所に絶縁層２１を形成する。特に、後の工程でｎ側電極（４２，４３）を形成する領域の下方に位置する箇所に絶縁層２１を形成する。このとき、図２Ｃに示すように、絶縁層２１の一部が反射電極１９の側面を覆うように形成することができる。 (Step S4)
Next, as shown in FIG. 2C, an insulating layer 21 is formed at a predetermined position on the upper layer of the reflective electrode 19. In particular, the insulating layer 21 is formed at a location located below a region where the n-side electrode (42, 43) is formed in a later step. At this time, as shown in FIG. 2C, a part of the insulating layer 21 can be formed so as to cover the side surface of the reflective electrode 19.
　より具体的には、絶縁層２１の非形成領域に係る反射電極１９の上層をマスクしておき、例えばＳｉＯ２をスパッタリング法によって膜厚２００ｎｍ程度成膜する。なお成膜する材料は絶縁性材料であればよく、例えばＳｉＮ、Ａｌ２Ｏ３でも良い。 More specifically, the upper layer of the reflective electrode 19 in the region where the insulating layer 21 is not formed is masked, and, for example, SiO 2 is formed to a thickness of about 200 nm by sputtering. Note that the material for forming the film may be an insulating material, such as SiN or Al 2 O 3 .
　　（ステップＳ５）
　図２Ｄに示すように、金属電極１９及び絶縁層２１の上面を覆うように保護層１７及びハンダ層１５を形成する。 (Step S5)
As shown in FIG. 2D, the protective layer 17 and the solder layer 15 are formed so as to cover the upper surfaces of the metal electrode 19 and the insulating layer 21.
　より詳細には、電子線蒸着装置（ＥＢ装置）にて金属電極１９及び絶縁層２１の上面を覆うように、膜厚１００ｎｍのＴｉと膜厚２００ｎｍのＰｔを３周期成膜することで、保護層１７を形成する。更にその後、保護層１７の上面（Ｐｔ表面）に、膜厚１０ｎｍのＴｉを蒸着させた後、Ａｕ８０％Ｓｎ２０％で構成されるＡｕ－Ｓｎハンダを膜厚３μｍ蒸着させることで、ハンダ層１５を形成する。 More specifically, the protective film is formed by depositing 100-nm-thick Ti and 200-nm-thick Pt for three periods so as to cover the upper surfaces of the metal electrode 19 and the insulating layer 21 with an electron beam evaporation apparatus (EB apparatus). Layer 17 is formed. Further, after depositing Ti with a thickness of 10 nm on the upper surface (Pt surface) of the protective layer 17, Au—Sn solder composed of Au 80% Sn 20% is deposited with a thickness of 3 μm. Form.
　なお、このハンダ層１５の形成ステップにおいて、サファイア基板６１とは別に準備された支持基板１１の上面にもハンダ層１３を形成するものとして構わない（図２Ｅ参照）。このハンダ層１３は、ハンダ層１５と同一の材料で構成されるものとしてよく、次のステップにおいてハンダ層１３と接合されることで、サファイア基板６１と支持基板１１が貼り合わせられる。この支持基板１１としては、構造の項で前述したように、例えばＣｕＷが用いられる。 In the step of forming the solder layer 15, the solder layer 13 may be formed on the upper surface of the support substrate 11 prepared separately from the sapphire substrate 61 (see FIG. 2E). The solder layer 13 may be made of the same material as the solder layer 15, and is bonded to the solder layer 13 in the next step, whereby the sapphire substrate 61 and the support substrate 11 are bonded together. For example, CuW is used as the support substrate 11 as described above in the section of the structure.
　更に、この図２Ｅにおいて、支持基板１１上にハンダ層１３の材料の拡散を防止するための保護層を保護層１７と同様の材料で形成し、この保護層の上層にハンダ層１３を形成するものとしても構わない。 Further, in FIG. 2E, a protective layer for preventing diffusion of the material of the solder layer 13 is formed on the support substrate 11 with the same material as the protective layer 17, and the solder layer 13 is formed on the protective layer. It does n’t matter.
　　（ステップＳ６）
　次に、図２Ｆに示すように、サファイア基板６１と支持基板１１とを貼り合わせる。より具体的には、２８０℃の温度、０．２ＭＰａの圧力下で、ハンダ層１５と支持基板１１の上層に形成されたハンダ層１３とを貼り合わせる。 (Step S6)
Next, as shown in FIG. 2F, the sapphire substrate 61 and the support substrate 11 are bonded together. More specifically, the solder layer 15 and the solder layer 13 formed on the support substrate 11 are bonded together at a temperature of 280 ° C. and a pressure of 0.2 MPa.
　　（ステップＳ７）
　次に、図２Ｇに示すように、サファイア基板６１を剥離する。より具体的には、サファイア基板６１を上に、支持基板１１を下に向けた状態で、サファイア基板６１側からＫｒＦエキシマレーザを照射して、サファイア基板６１とエピ層４０の界面を分解させることでサファイア基板６１の剥離を行う。サファイア６１はレーザが通過する一方、その下層のＧａＮ（アンドープ層３６）はレーザを吸収するため、この界面が高温化してＧａＮが分解される。これによってサファイア基板６１が剥離される。 (Step S7)
Next, as shown in FIG. 2G, the sapphire substrate 61 is peeled off. More specifically, the interface between the sapphire substrate 61 and the epi layer 40 is decomposed by irradiating a KrF excimer laser from the sapphire substrate 61 side with the sapphire substrate 61 facing upward and the support substrate 11 facing downward. Then, the sapphire substrate 61 is peeled off. While the laser passes through the sapphire 61, the underlying GaN (undoped layer 36) absorbs the laser, so that this interface is heated to decompose GaN. As a result, the sapphire substrate 61 is peeled off.
　その後、図２Ｈに示すように、ウェハ上に残存しているＧａＮ（アンドープ層３６）を、塩酸等を用いたウェットエッチング、又はＩＣＰ装置を用いたドライエッチングによって除去し、ｎ型半導体層３５を露出させる。なお、本ステップＳ７においてアンドープ層３６が除去されて、ｐ型半導体層３２、ｐ型半導体層３１、発光層３３、及びｎ型半導体層３５が下からこの順に積層されてなる半導体層３０が残存する。 Thereafter, as shown in FIG. 2H, GaN (undoped layer 36) remaining on the wafer is removed by wet etching using hydrochloric acid or the like, or dry etching using an ICP apparatus, and the n-type semiconductor layer 35 is removed. Expose. In step S7, the undoped layer 36 is removed, and the semiconductor layer 30 in which the p-type semiconductor layer 32, the p-type semiconductor layer 31, the light emitting layer 33, and the n-type semiconductor layer 35 are stacked in this order from the bottom remains. To do.
　　（ステップＳ８）
　次に、図２Ｉに示すように、隣接する素子同士を分離する。具体的には、隣接素子との境界領域に対し、ＩＣＰ装置を用いて絶縁層２１の上面が露出するまで半導体層３０をエッチングする。上述したように、このとき絶縁層２１はエッチング時のストッパーとしても機能する。 (Step S8)
Next, as shown in FIG. 2I, adjacent elements are separated from each other. Specifically, the semiconductor layer 30 is etched using an ICP device until the upper surface of the insulating layer 21 is exposed in a boundary region with an adjacent element. As described above, at this time, the insulating layer 21 also functions as a stopper during etching.
　　（ステップＳ９）
　次に、図２Ｊに示すように、ｎ型半導体層３５の上面のうち、絶縁層２１が形成されている箇所の直上の位置にｎ側電極（４２，４３）を形成する。具体的には、膜厚１００ｎｍのＣｒと膜厚３μｍのＡｕからなる電極を形成した後、窒素雰囲気中で２５０℃、１分間のシンタリングを行う。 (Step S9)
Next, as shown in FIG. 2J, n-side electrodes (42, 43) are formed on the upper surface of the n-type semiconductor layer 35 at a position immediately above the location where the insulating layer 21 is formed. Specifically, after forming an electrode made of Cr having a thickness of 100 nm and Au having a thickness of 3 μm, sintering is performed at 250 ° C. for 1 minute in a nitrogen atmosphere.
　そして、各素子同士を例えばレーザダイシング装置によって分離し、支持基板１１の裏面を例えばＡｇペーストにてパッケージと接合し、給電端子としてのｎ側電極４３に対してワイヤボンディングを行う。例えば、５０ｇの荷重でΦ１００μｍのボンディング領域にＡｕからなるワイヤ４５を連結させることで、ワイヤボンディングを行う。これにより、図１Ａに示す窒化物半導体発光素子１が形成される。 Then, the elements are separated from each other by, for example, a laser dicing apparatus, the back surface of the support substrate 11 is joined to the package by, for example, Ag paste, and wire bonding is performed on the n-side electrode 43 as a power supply terminal. For example, wire bonding is performed by connecting a wire 45 made of Au to a bonding region of Φ100 μm with a load of 50 g. Thereby, the nitride semiconductor light emitting device 1 shown in FIG. 1A is formed.
　なお、ステップＳ８とステップＳ９の間に、ＫＯＨ等のアルカリ溶液を浸すことでｎ型半導体層３５の表面に凹凸（メサ構造）を形成しても構わない。また、ｎ型半導体層３５の上面にｎ側電極（４２，４３）を形成した後、半導体層３０の側面を覆うように絶縁層を形成しても構わない。 Note that unevenness (mesa structure) may be formed on the surface of the n-type semiconductor layer 35 by immersing an alkaline solution such as KOH between Step S8 and Step S9. In addition, after the n-side electrode (42, 43) is formed on the upper surface of the n-type semiconductor layer 35, an insulating layer may be formed so as to cover the side surface of the semiconductor layer 30.
　［第２実施形態］
　本発明の半導体発光素子の第２実施形態の構成について説明する。なお、第１実施形態と同一の構成については同一の符号を付してその説明を省略する。 [Second Embodiment]
The configuration of the second embodiment of the semiconductor light emitting device of the present invention will be described. In addition, about the structure same as 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.
　〈構造〉
　図３は、第２実施形態の半導体発光素子の構成を模式的に示す断面図である。半導体発光素子１ａは、第１実施形態の半導体発光素子１と比較して、絶縁層２２（「第２絶縁層」に対応）を更に備えている。この絶縁層２２は、絶縁層２１と同様にＳｉＯ２、ＳｉＮ、Ｚｒ２Ｏ３、ＡｌＮ、Ａｌ２Ｏ３などで構成される。 <Construction>
FIG. 3 is a cross-sectional view schematically showing the configuration of the semiconductor light emitting device of the second embodiment. The semiconductor light emitting device 1a further includes an insulating layer 22 (corresponding to “second insulating layer”) as compared with the semiconductor light emitting device 1 of the first embodiment. The insulating layer 22 is composed of SiO 2, SiN, Zr 2 O 3 , AlN, Al 2 O 3, etc., like the insulating layer 21.
　より詳細には、この絶縁層２２は、ｎ側電極（４２，４３）の形成箇所の直下の位置において、反射電極１９とｐ型半導体層３２に挟まれる位置に形成されている。更に、この絶縁層２２は、ｎ側電極（４２，４３）よりも支持基板１１の基板面に平行な方向の幅が狭いことが好ましい。 More specifically, the insulating layer 22 is formed at a position between the reflective electrode 19 and the p-type semiconductor layer 32 at a position immediately below the formation position of the n-side electrode (42, 43). Further, the insulating layer 22 preferably has a narrower width in the direction parallel to the substrate surface of the support substrate 11 than the n-side electrodes (42, 43).
　第１実施形態では、反射電極１９の上面は全てｐ型半導体層３２に接触していた。これに対し、第２実施形態では、反射電極１９の上面のうち、一部が絶縁層２２と接触し、それ以外の箇所はｐ型半導体層３２に接触する構成である。そして、この絶縁層２２は、ｎ側電極（４２，４３）の形成箇所の直下の位置に形成されている。 In the first embodiment, the upper surface of each reflective electrode 19 is in contact with the p-type semiconductor layer 32. On the other hand, in the second embodiment, a part of the upper surface of the reflective electrode 19 is in contact with the insulating layer 22 and the other part is in contact with the p-type semiconductor layer 32. And this insulating layer 22 is formed in the position just under the formation location of the n side electrode (42, 43).
　この構成によれば、反射電極１９の上面の一部の箇所に絶縁層２２が形成されるため、発光層３３から下向きに放射された光のうち、一部の光はこの絶縁層２２内を通過して反射電極１９に達し、更に反射電極１９によって反射された後に絶縁層２２内を通過してｎ型半導体層３５側に導かれることになる。このとき、絶縁層２２にて光の一部が吸収されてしまうため、確かに第１実施形態で説明した半導体発光素子１と比べると、光の取り出し効率が少し低下する。 According to this configuration, since the insulating layer 22 is formed in a part of the upper surface of the reflective electrode 19, a part of the light emitted downward from the light emitting layer 33 passes through the insulating layer 22. The light passes through and reaches the reflective electrode 19, is further reflected by the reflective electrode 19, passes through the insulating layer 22, and is guided to the n-type semiconductor layer 35 side. At this time, since a part of light is absorbed by the insulating layer 22, the light extraction efficiency is slightly lowered as compared with the semiconductor light emitting device 1 described in the first embodiment.
　しかし、第１実施形態において上述したように、本実施形態においても反射電極１９の底面に形成された絶縁層２１によって発光層３３内を流れる電流を水平方向に拡げる効果が実現できている。このため、反射電極１９の上面に形成される絶縁層２２の幅を従来構成よりも細く実現できる。よって、本実施形態の半導体発光素子１ａは、反射電極１９の上面に絶縁層２２を有するものの、発光層３３から下向きに放射されて反射電極１９によって反射される光のうち、当該絶縁層２２内を通過する光を従来よりも著しく限定的にすることができる。従って、従来構成と比べると光の取り出し効率を向上させることができる。 However, as described above in the first embodiment, also in this embodiment, the effect of spreading the current flowing in the light emitting layer 33 in the horizontal direction by the insulating layer 21 formed on the bottom surface of the reflective electrode 19 can be realized. For this reason, the width | variety of the insulating layer 22 formed in the upper surface of the reflective electrode 19 is realizable narrower than a conventional structure. Therefore, although the semiconductor light emitting device 1a of the present embodiment has the insulating layer 22 on the upper surface of the reflective electrode 19, the light emitted downward from the light emitting layer 33 and reflected by the reflective electrode 19 is within the insulating layer 22 The light passing through can be significantly limited as compared with the prior art. Therefore, the light extraction efficiency can be improved as compared with the conventional configuration.
　〈製造方法〉
　以下、本実施形態の半導体発光素子１ａの製造方法につき、第１実施形態と異なる箇所のみを説明する。 <Production method>
Hereinafter, only the part different from the first embodiment will be described for the method for manufacturing the semiconductor light emitting device 1a of the present embodiment.
　第１実施形態と同様の方法によってステップＳ１及びＳ２を実行する。 Steps S1 and S2 are executed by the same method as in the first embodiment.
　　（ステップＳ３Ａ）
　次に、図４Ａに示すように、ｐ型半導体層３２の上層の所定箇所に絶縁層２２を形成する。特に、後の工程でｎ側電極（４２，４３）を形成する領域の下方に位置する箇所において、ｎ側電極（４２，４３）よりも水平方向の幅を薄くして絶縁層２２を形成する。 (Step S3A)
Next, as illustrated in FIG. 4A, the insulating layer 22 is formed at a predetermined position on the upper layer of the p-type semiconductor layer 32. In particular, the insulating layer 22 is formed by making the width in the horizontal direction smaller than that of the n-side electrode (42, 43) at a position located below a region where the n-side electrode (42, 43) is formed in a later step. .
　　（ステップＳ３Ｂ）
　次に、図４Ｂに示すように、ｐ型半導体層３２の上面の所定箇所に反射電極１９を形成する。このとき、絶縁層２２の上層を覆うように反射電極１９を形成する。 (Step S3B)
Next, as illustrated in FIG. 4B, the reflective electrode 19 is formed at a predetermined position on the upper surface of the p-type semiconductor layer 32. At this time, the reflective electrode 19 is formed so as to cover the upper layer of the insulating layer 22.
　以後は、第１実施形態と同様に、ステップＳ４～Ｓ９を実行することで、図３に示す半導体発光素子１ａが形成される。 Thereafter, similarly to the first embodiment, by performing steps S4 to S9, the semiconductor light emitting element 1a shown in FIG. 3 is formed.
　［実施例］
　上述した方法によって製造された第１実施形態の半導体発光素子１を実施例１、第２実施形態の半導体発光素子１ａを実施例２とし、図５に示す半導体発光素子５０を比較例として、電流電圧特性と発光特性を対比した。 [Example]
The semiconductor light emitting device 1 of the first embodiment manufactured by the method described above is taken as Example 1, the semiconductor light emitting device 1a of the second embodiment is taken as Example 2, and the semiconductor light emitting device 50 shown in FIG. The voltage characteristics and the light emission characteristics were compared.
　図５は、比較例として形成した半導体発光素子の構造を模式的に示す断面図である。半導体発光素子１と比較して、反射電極１９の底面に形成された絶縁層２１に代えて、反射電極１９の上面に設けられた絶縁層２３を有している。この絶縁層２３は、ｎ側電極（４２，４３）の直下の位置に形成されることで、発光層３３を流れる電流を水平方向に拡げる目的で形成されている。なお、その他の層を構成する材料や寸法は共通としている。 FIG. 5 is a cross-sectional view schematically showing the structure of a semiconductor light emitting device formed as a comparative example. Compared to the semiconductor light emitting element 1, an insulating layer 23 provided on the top surface of the reflective electrode 19 is provided instead of the insulating layer 21 formed on the bottom surface of the reflective electrode 19. The insulating layer 23 is formed for the purpose of spreading the current flowing through the light emitting layer 33 in the horizontal direction by being formed at a position immediately below the n-side electrodes (42, 43). The materials and dimensions constituting the other layers are the same.
　図６は、実施例１、実施例２、及び比較例の各素子に対して電圧を印加したときの、流れる電流値と電圧値の関係（Ｉ－Ｖ特性）を示すグラフである。図６によれば、実施例１、実施例２の各素子と比較例を対比すると、同一の電流値を流すのに必要な電圧値はほぼ同等であり、比較例の構成と同等の低電圧駆動が実現できていることが分かる。 FIG. 6 is a graph showing the relationship between the flowing current value and the voltage value (IV characteristics) when a voltage is applied to each element of Example 1, Example 2, and Comparative Example. According to FIG. 6, when each element of Example 1 and Example 2 is compared with the comparative example, the voltage values required to flow the same current value are substantially equal, and the low voltage equivalent to the configuration of the comparative example. It can be seen that driving can be realized.
　図７は、実施例１、実施例２、及び比較例の各素子に対して電流を供給したときに得られる発光出力と電流値の関係を示すグラフである。図７によれば、比較例の素子と比べて実施例１及び実施例２の両素子ともに発光出力が向上していることが分かる。また、実施例２よりも実施例１の素子の方が、更に発光出力が向上していることが分かる。 FIG. 7 is a graph showing the relationship between the light emission output and the current value obtained when current is supplied to each element of Example 1, Example 2, and Comparative Example. According to FIG. 7, it can be seen that the light emission output is improved in both the elements of Example 1 and Example 2 as compared with the element of the comparative example. It can also be seen that the light emission output of the element of Example 1 is further improved than that of Example 2.
　この結果より、比較例の構成では、反射電極１９の上層に形成された絶縁層２３によって一部の光が吸収されていたが、実施例１の素子では、反射電極１９の上層に絶縁層を設けない構成としたことで、この光の吸収がなくなったことで光の取り出し効率が向上していることが分かる。また、実施例２の素子では、反射電極１９の上層に絶縁層２２を設けているため、実施例１と比べると光の取り出し効率が低下しているものの、絶縁層２２をｎ側電極（４２，４３）の幅より薄く形成できるため、比較例よりは光の取り出し効率が向上していることが分かる。 From this result, in the configuration of the comparative example, a part of light was absorbed by the insulating layer 23 formed on the upper layer of the reflective electrode 19, but in the element of Example 1, the insulating layer was formed on the upper layer of the reflective electrode 19. It can be seen that the light extraction efficiency is improved by eliminating the light absorption by adopting the configuration in which the light is not provided. Further, in the element of Example 2, since the insulating layer 22 is provided on the reflective electrode 19, the light extraction efficiency is lower than that of Example 1, but the insulating layer 22 is formed on the n-side electrode (42). 43), the light extraction efficiency is improved as compared with the comparative example.
　なお、比較例の構成では絶縁層２３によって水平方向に電流を拡げる効果を実現しているため、絶縁層２３をｎ側電極（４２，４３）よりも水平方向の幅を狭くすることはできない。仮に絶縁層２３をｎ側電極（４２，４３）よりも水平方向の幅を狭くした場合、ｎ側電極４２の直下に反射電極１９が位置し、その直下には導電性の保護層１９、ハンダ層（１３，１５）が形成されているため、絶縁層２３が形成されていない領域において、ｎ側電極（４２，４３）とその直下に位置する反射電極１９の間に、鉛直方向に電流経路が形成されてしまう。この結果、当該領域の発光層３３に多くの電流が流れることになり、発光層３３を水平方向全体に光らせる効果が得られず、発光効率が低下してしまう。 In the configuration of the comparative example, since the effect of spreading the current in the horizontal direction is realized by the insulating layer 23, the horizontal width of the insulating layer 23 cannot be made narrower than the n-side electrodes (42, 43). If the horizontal width of the insulating layer 23 is narrower than that of the n-side electrodes (42, 43), the reflective electrode 19 is located directly under the n-side electrode 42, and the conductive protective layer 19 and solder are directly underneath. Since the layers (13, 15) are formed, a current path extends in the vertical direction between the n-side electrodes (42, 43) and the reflective electrode 19 located immediately below in the region where the insulating layer 23 is not formed. Will be formed. As a result, a large amount of current flows through the light emitting layer 33 in the region, and the effect of causing the light emitting layer 33 to shine in the entire horizontal direction cannot be obtained, resulting in a reduction in light emission efficiency.
　［別実施形態］
　上述の実施形態では、半導体発光素子（１，１ａ）として、窒化物半導体からなる発光素子を採り上げて説明した。しかし、本発明の構成は、他の半導体からなる発光素子にも適用が可能である。 [Another embodiment]
In the above-described embodiment, the light emitting element made of a nitride semiconductor has been described as the semiconductor light emitting element (1, 1a). However, the structure of the present invention can also be applied to light emitting elements made of other semiconductors.
　図８は、半導体発光素子の別実施形態の構成の一例を模式的に示す断面図である。この図８に示す半導体発光素子１ｂでは、発光層３３がＩｎＧａＰの井戸層とＡｌＧａＩｎＰの障壁層とが繰り返されてなる多重量子井戸構造を有する半導体層で形成される。 FIG. 8 is a cross-sectional view schematically showing an example of the configuration of another embodiment of the semiconductor light emitting device. In the semiconductor light emitting device 1b shown in FIG. 8, the light emitting layer 33 is formed of a semiconductor layer having a multiple quantum well structure in which an InGaP well layer and an AlGaInP barrier layer are repeated.
　図８に示す半導体発光素子１ｂは、上述した第１実施形態の構成と同様に、支持基板１１上に、ｐ型半導体層３１、発光層３３及びｎ側半導体層３５がこの順に下から積層されて形成されている。そして、半導体発光素子１ｂは、底面をｎ型半導体層３５の上面に接触して形成されたｎ側電極（４２，４３）と、上面をｐ型半導体層３１の底面に接触し、ｎ側電極（４２，４３）の形成箇所の直下の位置を含む領域に形成された反射電極１９と、ｎ側電極（４２，４３）の形成箇所の直下の位置において、上面を反射電極１９の底面に接触して形成された絶縁層２１を備えている。 In the semiconductor light emitting device 1b shown in FIG. 8, a p-type semiconductor layer 31, a light emitting layer 33, and an n-side semiconductor layer 35 are stacked in this order on the support substrate 11 in the same manner as the configuration of the first embodiment described above. Is formed. The semiconductor light emitting device 1b includes an n-side electrode (42, 43) formed with the bottom surface in contact with the top surface of the n-type semiconductor layer 35, and the top surface in contact with the bottom surface of the p-type semiconductor layer 31. The reflective electrode 19 formed in a region including the position immediately below the formation position of (42, 43) and the upper surface in contact with the bottom surface of the reflective electrode 19 at a position immediately below the formation position of the n-side electrode (42, 43). The insulating layer 21 is formed.
　より詳細には、支持基板１１上に、Ｎｉ／Ａｕで構成された接合層１４、ＴａＮ／ＴｉＷ／ＴａＮで構成された保護層１７、及びＡｕＳｎで構成された反射電極１９を含む導電層２０が形成される。また、ｐ型半導体層３１は、ｐ型不純物濃度が高濃度（例えば３×１０１８／ｃｍ３程度）のＧａＰで構成された拡散層６１、拡散層６２よりもｐ型不純物濃度が低濃度（例えば１×１０１８／ｃｍ３程度）のＡｌＧａＩｎＰで構成された中間層６２、及び中間層６２よりもｐ型不純物濃度が低濃度（例えば３×１０１７／ｃｍ３程度）のＡｌＧａＩｎＰで構成されたｐ－クラッド層６３を備える。 More specifically, a conductive layer 20 including a bonding layer 14 made of Ni / Au, a protective layer 17 made of TaN / TiW / TaN, and a reflective electrode 19 made of AuSn is formed on the support substrate 11. It is formed. The p-type semiconductor layer 31 has a lower p-type impurity concentration than the diffusion layer 61 and the diffusion layer 62 made of GaP having a high p-type impurity concentration (eg, about 3 × 10 18 / cm 3 ). For example, the intermediate layer 62 made of AlGaInP made of AlGaInP of about 1 × 10 18 / cm 3 , and made of AlGaInP having a p-type impurity concentration lower than the intermediate layer 62 (for example, about 3 × 10 17 / cm 3 ). A p-cladding layer 63 is provided.
　そして、ｎ型半導体層３５は、ｎ型ＩｎＧａＰとｎ型ＡｌＩｎＰが繰り返し積層されてなる多層構造で構成された緩和層６４と、ＡｌＧａＩｎＰで構成されたｎ－クラッド層６５を備える。 The n-type semiconductor layer 35 includes a relaxation layer 64 having a multilayer structure in which n-type InGaP and n-type AlInP are repeatedly stacked, and an n-cladding layer 65 made of AlGaInP.
　図８に示す半導体発光素子１ｂにおいても、ｎ側電極（４２，４３）の直下の位置において、発光層３３内を延長方向に大部分の電流が流れることのないよう、すなわち、電流を支持基板１１の基板面に平行な方向（水平方向）に拡げる目的で、ｎ側電極（４２，４３）の直下の位置に絶縁層２１が形成されている。そして、この絶縁層２１は、反射電極１９とｐ型半導体層３１の間ではなく、反射電極１９と保護層１７の間、すなわち上面が反射電極１９の底面に接触するように形成されている。 Also in the semiconductor light emitting element 1b shown in FIG. 8, at the position immediately below the n-side electrodes (42, 43), most of the current does not flow in the extending direction in the light emitting layer 33, that is, the current is supplied to the support substrate. The insulating layer 21 is formed at a position immediately below the n-side electrodes (42, 43) for the purpose of extending in a direction parallel to the substrate surface (horizontal direction). The insulating layer 21 is formed not between the reflective electrode 19 and the p-type semiconductor layer 31 but between the reflective electrode 19 and the protective layer 17, that is, so that the top surface is in contact with the bottom surface of the reflective electrode 19.
　このような構成において、上述した第１実施形態の構成と同様、発光層３３から放射された光のうち、支持基板１１に向かって進行する光は、反射電極１９によって反射された後、進行方向を上向き（ｎ型半導体層３５側）へと変化して、外部に取り出される。このとき、前記の光は、反射電極１９に到達するまで、及び到達後反射されて外部に取り出されるまでの間に、絶縁層２１内を通過することがない。従って、上述した第１実施形態及び第２実施形態の素子と同様に、絶縁層２１によって光が吸収されずに、従来よりも光取り出し効率が向上する効果が得られる。 In such a configuration, as in the configuration of the first embodiment described above, the light traveling toward the support substrate 11 out of the light emitted from the light emitting layer 33 is reflected by the reflective electrode 19 and then travels in the traveling direction. Changes upward (on the n-type semiconductor layer 35 side) and is taken out to the outside. At this time, the light does not pass through the insulating layer 21 until it reaches the reflective electrode 19 and after it reaches the reflective electrode 19 until it is reflected and extracted outside. Therefore, similarly to the elements of the first embodiment and the second embodiment described above, light is not absorbed by the insulating layer 21, and an effect of improving the light extraction efficiency as compared with the related art can be obtained.
　なお、図８において、第２実施形態の構成と同様に、ｎ側電極（４２，４３）の形成箇所の直下の位置において、反射電極１９とｐ型半導体層３１の間に、ｎ側電極（４２，４３）の幅よりも薄い幅で形成された第２絶縁層を形成しても構わない。この場合、図８の素子１ｂよりは光取り出し効率が低下するものの、従来の素子よりは取り出し効率を向上させることができる。 In FIG. 8, similarly to the configuration of the second embodiment, an n-side electrode (between the reflective electrode 19 and the p-type semiconductor layer 31 is provided immediately below the location where the n-side electrode (42, 43) is formed. The second insulating layer formed with a width thinner than the width of 42, 43) may be formed. In this case, although the light extraction efficiency is lower than that of the element 1b in FIG. 8, the extraction efficiency can be improved as compared with the conventional element.
　　　　１　　　：　　第１実施形態の半導体発光素子
　　　　１ａ　　：　　第２実施形態の半導体発光素子
　　　　１ｂ　　：　　別実施形態の半導体発光素子
　　　１１　　　：　　支持基板
　　　１３　　　：　　ハンダ層
　　　１４　　　：　　接合層
　　　１５　　　：　　ハンダ層
　　　１７　　　：　　保護層
　　　１９　　　：　　反射電極
　　　２０　　　：　　導電層
　　　２１　　　：　　絶縁層（第１絶縁層）
　　　２２　　　：　　絶縁層（第２絶縁層）
　　　２３　　　：　　絶縁層
　　　３０　　　：　　半導体層
　　　３１　　　：　　ｐ型半導体層
　　　３２　　　：　　ｐ型半導体層
　　　３３　　　：　　発光層
　　　３５　　　：　　ｎ型半導体層
　　　３６　　　：　　アンドープ層
　　　４０　　　：　　エピ層
　　　４２　　　：　　ｎ側電極
　　　４３　　　：　　ｎ側電極（給電端子）
　　　４３ａ，４３ｂ　　　：　　ｎ側電極上のワイヤ連絡領域
　　　４５　　　：　　ワイヤ
　　　６１　　　：　　拡散層
　　　６２　　　：　　中間層
　　　６３　　　：　　ｐ－クラッド層
　　　６４　　　：　　緩和層
　　　６５　　　：　　ｎ－クラッド層
　　　９０　　　：　　従来の半導体発光素子
　　　９１　　　：　　支持基板
　　　９２　　　：　　導電層
　　　９３　　　：　　反射膜
　　　９４　　　：　　絶縁層
　　　９５　　　：　　反射電極
　　　９６　　　：　　ｐ型半導体層
　　　９７　　　：　　発光層
　　　９８　　　：　　ｎ型半導体層
　　　９９　　　：　　半導体層
　　１００　　　：　　ｎ側電極
  DESCRIPTION OF SYMBOLS 1: Semiconductor light emitting element of 1st Embodiment 1a: Semiconductor light emitting element of 2nd Embodiment 1b: Semiconductor light emitting element of another embodiment 11: Support substrate 13: Solder layer 14: Bonding layer 15: Solder layer 17: Protective layer 19 : Reflective electrode 20: Conductive layer 21: Insulating layer (first insulating layer)
22: Insulating layer (second insulating layer)
23: Insulating layer 30: Semiconductor layer 31: p-type semiconductor layer 32: p-type semiconductor layer 33: light emitting layer 35: n-type semiconductor layer 36: undoped layer 40: epi layer 42: n-side electrode 43: n-side electrode (power feeding Terminal)
43a, 43b: Wire connection region on n-side electrode 45: Wire 61: Diffusion layer 62: Intermediate layer 63: p-clad layer 64: Relaxation layer 65: n-clad layer 90: Conventional semiconductor light emitting device 91: Support substrate 92: conductive layer 93: reflective film 94: insulating layer 95: reflective electrode 96: p-type semiconductor layer 97: light-emitting layer 98: n-type semiconductor layer 99: semiconductor layer 100: n-side electrode

Claims (5)

  1. 　支持基板上に、ｎ型半導体層と、ｐ型半導体層と、前記ｎ型半導体層及び前記ｐ型半導体層の間に形成された発光層とを有する半導体発光素子であって、
    　底面を前記ｎ型半導体層の上面に接触して形成されたｎ側電極と、
    　上面を前記ｐ型半導体層の底面に接触し、前記ｎ側電極の形成箇所の直下の位置を含む領域に形成された反射電極と、
    　前記ｎ側電極の形成箇所の直下の位置において、上面を前記反射電極の底面に接触して形成された第１絶縁層を備えたことを特徴とする半導体発光素子。     A semiconductor light emitting device comprising an n-type semiconductor layer, a p-type semiconductor layer, and a light-emitting layer formed between the n-type semiconductor layer and the p-type semiconductor layer on a support substrate,
    An n-side electrode formed by contacting the bottom surface with the top surface of the n-type semiconductor layer;
    A reflective electrode formed in a region that includes a position directly below the formation position of the n-side electrode, the upper surface being in contact with the bottom surface of the p-type semiconductor layer;
    A semiconductor light emitting device comprising: a first insulating layer formed at a position immediately below the formation position of the n-side electrode so that the upper surface is in contact with the bottom surface of the reflective electrode.
  2. 　前記反射電極は、上面の全てが前記ｐ型半導体層の底面と接触していることを特徴とする請求項１に記載の半導体発光素子。 2. The semiconductor light emitting element according to claim 1, wherein the reflective electrode has the entire upper surface in contact with the bottom surface of the p-type semiconductor layer.
  3. 　前記ｎ側電極の形成箇所の直下の位置において、前記反射電極と前記ｐ型半導体層に挟まれる位置に形成された第２絶縁層を備え、
    　前記第２絶縁層が、当該第２絶縁層の直上に位置する前記ｎ側電極よりも前記支持基板の基板面に平行な方向の幅が狭いことを特徴とする請求項１に記載の半導体発光素子。     A second insulating layer formed at a position sandwiched between the reflective electrode and the p-type semiconductor layer at a position immediately below the formation position of the n-side electrode;
    2. The semiconductor light emitting device according to claim 1, wherein the second insulating layer has a narrower width in a direction parallel to the substrate surface of the support substrate than the n-side electrode located immediately above the second insulating layer. element.
  4. 　前記反射電極は、上面に前記第２絶縁層が形成されている領域を除いて、上面の全てが前記ｐ型半導体層の底面と接触していることを特徴とする請求項３に記載の半導体発光素子。 4. The semiconductor according to claim 3, wherein all of the upper surface of the reflective electrode is in contact with the bottom surface of the p-type semiconductor layer except for a region where the second insulating layer is formed on the upper surface. Light emitting element.
  5. 　前記ｎ型半導体層、前記ｐ型半導体層、及び前記発光層の全てが窒化物半導体層で形成されていることを特徴とする請求項１～４のいずれか１項に記載の半導体発光素子。
          The semiconductor light-emitting device according to claim 1, wherein all of the n-type semiconductor layer, the p-type semiconductor layer, and the light-emitting layer are formed of a nitride semiconductor layer.
PCT/JP2014/070711 2013-08-30 2014-08-06 Semiconductor light emitting element WO2015029727A1 (en)

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