JP2015050381A - Semiconductor light-emitting element, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element capable of further improving the light extraction efficiency by suppressing generation of voids on a reflection electrode surface, and to provide a method of manufacturing the same.SOLUTION: There is provided a method of manufacturing a semiconductor light-emitting element comprising: an n-type or p-type first semiconductor layer 35; a second semiconductor layer 31 of a conductivity type different from that of the first semiconductor layer; and a light-emitting layer 33 formed between the first semiconductor layer and the second semiconductor layer. The method includes the step of: (a) preparing a substrate; (b) forming on the substrate the first semiconductor layer, the light-emitting layer, and the second semiconductor layer sequentially from a lower part; (c) evaporating a first conductive layer configuring a reflection electrode 19 on an upper layer of the second semiconductor layer; (d) evaporating a second conductive layer configuring a protection layer 18 on the whole of an upper surface of the first conductive layer without performing an annealing step, after the step (c); and (e) performing annealing at such a temperature that an ohmic contact is formed between the first conductive layer and the second semiconductor layer, after the step (d).

Description

  The present invention relates to a semiconductor light emitting device having an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer formed therebetween on a support substrate. The present invention also relates to a method for manufacturing such a semiconductor light emitting device.

  As a conventional semiconductor light emitting device, for example, a structure described in Patent Document 1 is disclosed.

  FIG. 12 schematically shows a cross-sectional view of the semiconductor light emitting device disclosed in Patent Document 1. As shown in FIG. The conventional semiconductor light emitting device 90 includes a conductive layer 92, a reflective film 93, an insulating layer 94, a reflective electrode 95, a semiconductor layer 99, and an n-side electrode 100 on a support substrate 91. The semiconductor layer 99 is formed by stacking a p-type semiconductor layer 96, a light emitting layer 97, and an n-type semiconductor layer 98 in this order from the bottom.

  The insulating layer 94 is formed in a region including a position immediately below the position where the n-side electrode 100 is formed. A reflective film 93 made of a metal material is formed below the insulating layer 94. However, the reflective film 93 does not have ohmic properties and does not function as an electrode. On the other hand, the reflective electrode 95 is made of a metal material and functions as an electrode (p-side electrode) by realizing ohmic contact between the p-type semiconductor layers 96.

  The reflective electrode 95 reflects the light emitted in the direction toward the support substrate 91 (downward in the drawing) out of the light emitted from the light emitting layer 97 and extracts the light toward the n-side semiconductor layer 98 (upward in the drawing). It also serves the purpose of increasing the take-out efficiency. The reflective film 93 is also formed for the same purpose, and reflects light that travels downward through a portion where the reflective electrode 95 is not formed, and changes the traveling direction to the n-side semiconductor layer 98 side. The take-out efficiency is increased.

Japanese Patent No. 4207781

  The semiconductor light emitting device 90 shown in FIG. 12 is manufactured as follows. First, the semiconductor layer 99 is grown on a predetermined substrate. Next, after depositing an electrode material constituting the reflective electrode 95 so that the bottom surface is in contact with the upper surface of the semiconductor layer 99, an ohmic contact between the electrode material and the semiconductor layer 99 (more specifically, the p-type semiconductor layer 96). In order to obtain the contact, for example, annealing is performed at a high temperature of about 400 ° C. to 600 ° C. After that, after the insulating layer 94, the reflective film 93, and the conductive layer 92 are sequentially stacked, the support substrate 91 is bonded from the conductive layer 92 side, and the substrate on which the semiconductor layer 99 is grown is peeled off.

  A metal material is used as the material constituting the reflective electrode 95. The work functions of metal and semiconductor are different, and a difference occurs in the energy level at the contact interface, resulting in a barrier. If there is a barrier, current does not easily flow and the operating voltage increases. Therefore, in an element in which a work function such as metal and semiconductor contacts to form an interface, the barrier between the energy levels of both is reduced, and the contact resistance between the reflective electrode 95 and the semiconductor layer 99 is reduced. The above-described high temperature annealing treatment is required.

  As described above, the reflective electrode 95 increases the light extraction efficiency by reflecting the light emitted in the direction toward the support substrate 91 out of the light emitted from the light emitting layer 97 to the n-side semiconductor layer 98 side. It is formed with the intention. For this reason, the constituent material of the reflective electrode 95 is preferably a material having a high light reflectance, and examples of such a material include Ag and Al. However, it has been found that when the semiconductor light emitting device 90 is manufactured by the above method, many voids are generated on the surface of the reflective electrode 95.

  FIG. 13 shows a case where the semiconductor layer 99 is manufactured from the light extraction side (above the n-type semiconductor layer 98 in FIG. 12) when the reflective electrode 95 is annealed when the semiconductor light emitting device 90 is manufactured by the above method. It is a photograph taken through a substrate to be grown. In the photograph of FIG. 13, many black spots derived from the void 101 appear on the surface of the reflective electrode 95. When a large number of such voids 101 are generated on the surface of the reflective electrode 95, the light reflectivity on the surface of the reflective electrode 95 is lowered, so that the light extraction efficiency is lowered.

  An object of the present invention is to realize a semiconductor light emitting device and a method for manufacturing the same, in which light extraction efficiency is further improved by suppressing generation of voids on the surface of a reflective electrode.

The present invention provides an n-type or p-type first semiconductor layer, a second semiconductor layer having a conductivity type different from that of the first semiconductor layer, and light emission formed between the first semiconductor layer and the second semiconductor layer. A method of manufacturing a semiconductor light emitting device having a layer,
Preparing a substrate (a),
Forming the first semiconductor layer, the light emitting layer, and the second semiconductor layer on the substrate in order from the bottom (b);
Depositing a first conductive layer constituting a reflective electrode on the second semiconductor layer (c);
A step (d) of depositing a second conductive layer constituting a protective layer on the entire upper surface of the first conductive layer without performing an annealing step after the step (c);
And after the step (d), the method includes a step (e) of annealing at a temperature at which an ohmic contact is formed between the first conductive layer and the second semiconductor layer.

  The present inventor has intensively studied that a large number of voids appearing on the surface of the reflective electrode by the conventional manufacturing method are deposited in the process of annealing at a high temperature after the electrode material constituting the reflective electrode is deposited. It was inferred that it was caused by agglomeration. Therefore, in the method of the present invention, after the first conductive layer constituting the reflective electrode is deposited, the second conductive layer constituting the protective layer is deposited on the entire upper surface of the first conductive layer without annealing, and then the first conductive layer is formed. Annealing is performed to realize ohmic contact between the conductive layer and the second semiconductor layer.

  According to this method, since the upper surface of the first conductive layer is covered with the second conductive layer and is not exposed during annealing, the material constituting the first conductive layer does not aggregate during annealing. As a result, as will be described later in the section “DETAILED DESCRIPTION OF THE INVENTION”, the formation of voids on the reflective electrode surface of the semiconductor light emitting device manufactured by the method is greatly suppressed, and the light extraction efficiency is improved. .

  By setting the annealing temperature in the step (e) to 450 ° C. or more and 550 ° C. or less, generation of voids is suppressed to the maximum while realizing ohmic contact between the first conductive layer and the second semiconductor layer. be able to.

  The first conductive layer is preferably made of a material having a high light reflectance, and for example, a material containing at least one of Ag or Al can be used. When the reflective electrode is composed of these materials, a high reflectance can be realized, but if the void is generated on the surface of the reflective electrode, the light extraction efficiency is greatly reduced. According to the above method, even if the reflective electrode is formed of a material that can ensure such a high reflectivity, generation of voids on the surface of the reflective electrode is suppressed, so that high light extraction efficiency can be realized.

  The film thickness of the first conductive layer can be set to 150 nm or less, for example. From the viewpoint of preventing the formation of voids on the surface of the reflective electrode, a method of forming a thick film on the order of μm is also conceivable. However, when the reflective electrode is formed with a thick film in this way, the vapor deposition process takes an extremely long time, which not only hinders other processes, but also has a difference in height from the surrounding portions, which makes it difficult to ensure flatness. According to the above method, even when the reflective electrode is formed with a thin film thickness of 150 nm or less, generation of voids on the surface is suppressed.

The semiconductor light emitting device of the present invention is
Light emission formed on a substrate between an n-type or p-type first semiconductor layer, a second semiconductor layer having a conductivity type different from that of the first semiconductor layer, and the first semiconductor layer and the second semiconductor layer. A semiconductor light emitting device having a layer,
A reflective electrode formed in contact with at least one of the first semiconductor layer and the second semiconductor layer;
And a protective layer made of a conductive material different from the reflective electrode, the entire surface being in contact with the reflective electrode.

  Here, as a semiconductor light emitting device of the present invention, an n-side electrode and a p-side electrode are formed vertically so as to sandwich a stacked body including the first semiconductor layer, the second semiconductor layer, and the light emitting layer. In the case of adopting a mold structure, the substrate may be a support substrate. In this case, the reflective electrode is formed in contact with the bottom surface of the second semiconductor layer formed at a position closer to the substrate than the first semiconductor layer, and the protective layer is formed on the entire top surface. Can be formed in contact with the bottom surface of the reflective electrode.

  In the case of adopting a so-called lateral structure in which the n-side electrode and the p-side electrode are formed apart from each other in the direction parallel to the substrate surface, the substrate can be a sapphire substrate, for example. In this case, it may be configured to include a reflective electrode formed in contact with one of the first semiconductor layer or the second semiconductor layer, and the reflective electrode formed in contact with the first semiconductor layer and the second semiconductor layer may be provided. It may be configured to include both of the reflective electrodes formed in contact with each other.

In the case where the semiconductor light emitting device has the vertical structure, a first electrode formed by contacting an upper surface with a bottom surface of the first semiconductor layer;
An insulating layer formed by contacting the upper surface with the bottom surface of the protective layer may be further provided at a position immediately below the formation position of the first electrode.

  According to this configuration, the insulating layer is formed on the bottom surface of the protective layer formed in contact with the bottom surface of the reflective electrode at a position immediately below the location where the first electrode is formed. For this reason, even if the reflective electrode is formed at a position immediately below the location where the first electrode is formed, no current flows below the reflective electrode at this location. Since the current path is formed in a region where the insulating layer is not formed, according to the above configuration, even if the reflective electrode and the first electrode face each other in the vertical direction, the reflective electrode and the first electrode are connected to each other. Most current does not flow only in the light emitting layer in the sandwiched region. Thereby, the effect of spreading the current flowing in the light emitting layer in the direction parallel to the substrate surface of the support substrate (horizontal direction) is obtained, and the light extraction efficiency is further improved.

  The reflective electrode can be made of a material containing at least one of Ag and Al. Since these materials have high reflectivity, the effect of further improving the light extraction efficiency can be obtained by not forming voids on the surface.

  The reflective electrode can be formed with a film thickness of 150 nm or less, for example. As a result, a reflective electrode having a high reflectivity is formed without forming voids on the surface while being formed with a thin film thickness, so that a light-emitting element having a high light extraction efficiency can be realized.

  The semiconductor light emitting device of the present invention can be realized as a nitride semiconductor light emitting device in which all of the first semiconductor layer, the second semiconductor layer, and the light emitting layer are formed of a nitride semiconductor layer.

  According to the present invention, it is possible to realize a semiconductor light emitting device that suppresses generation of voids on the surface of the reflective electrode, exhibits high reflectance, and has high light extraction efficiency.

It is sectional drawing which shows typically the structure of 1st Embodiment of a semiconductor light-emitting device. It is the photograph which image | photographed the semiconductor light-emitting device of 1st Embodiment from the light extraction side. It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 1st Embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically the structure of 2nd Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 2nd Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 2nd Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of 2nd Embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically the structure of another embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically the structure of another embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of another embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of another embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing of another embodiment of a semiconductor light-emitting device. 6 is a cross-sectional view schematically showing the structure of a semiconductor light emitting device formed as Comparative Example 1. FIG. 10 is a cross-sectional view schematically showing the structure of a semiconductor light emitting device formed as Comparative Example 2. FIG. 10 is a cross-sectional view schematically showing the structure of a semiconductor light emitting device formed as Comparative Example 3. FIG. It is a graph which shows the relationship (IV characteristic) of the electric current value which flows when a voltage is applied with respect to each element of an Example and a comparative example, and a voltage value. It is a graph which shows the relationship between the light emission output obtained when an electric current is supplied with respect to each element of an Example and a comparative example, and an electric current value. It is sectional drawing which shows the structure of the conventional semiconductor light-emitting device typically. It is the photograph which image | photographed the semiconductor light-emitting device manufactured with the conventional manufacturing method from the light extraction side.

  The semiconductor light emitting device of the present invention will be described with reference to the drawings. In each figure, the dimensional ratio in the drawing does not necessarily match the actual dimensional ratio. Further, in this specification, “the first layer is located immediately below the second layer” means that the second layer is located below the first layer in the direction perpendicular to the substrate surface of the support substrate. It means to do.

[First Embodiment]
The configuration of the first embodiment of the semiconductor light emitting device of the present invention will be described.

<Construction>
FIG. 1 is a cross-sectional view schematically showing the configuration of the semiconductor light emitting device of the first embodiment. The semiconductor light emitting device 1 includes a support substrate 11, a conductive layer 20, an insulating layer 21, a semiconductor layer 30, and n-side electrodes (42, 43). The semiconductor layer 30 is formed by stacking a p-type semiconductor layer (32, 31), a light emitting layer 33, and an n-type semiconductor layer 35 in this order from the bottom.

(Support substrate 11)
The support substrate 11 is composed of a conductive substrate such as CuW, W, or Mo, or a semiconductor substrate such as Si.

(Conductive layer 20)
A conductive layer 20 having a multilayer structure is formed on the support substrate 11. In this embodiment, the conductive layer 20 includes a solder layer 13, a solder layer 15, a solder diffusion prevention layer 17, a protective layer 18, and a reflective electrode 19.

  The solder layer 13 and the solder layer 15 are made of, for example, Au—Sn, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like. As will be described later, the solder layer 13 and the solder layer 15 make the solder layer 13 formed on the support substrate 11 and the solder layer 15 formed on another substrate (a sapphire substrate 61 described later) face each other. Then, the two are bonded together.

  The solder diffusion preventing layer 17 is made of, for example, a Pt-based metal (an alloy of Ti and Pt), W, Mo, Ni, or the like. As will be described later, when bonding is performed via the solder layer, the material constituting the solder is diffused to the reflective electrode 19 side described later, and the function of preventing a decrease in luminous efficiency due to a drop in reflectance is achieved.

  The reflective electrode 19 is made of a material containing at least one of Ag or Al. These are all materials showing high reflectance. The semiconductor light emitting element 1 assumes that light emitted from the light emitting layer 33 is extracted upward (on the n-type semiconductor layer 35 side) in FIG. 1, and the reflective electrode 19 radiates downward from the light emitting layer 33. The function of improving the luminous efficiency is achieved by reflecting the emitted light upward. In addition, the upward arrow in FIG. 1 represents the light extraction direction.

  In the configuration of this embodiment, the reflective electrode 19 is formed in the lower layer of the p-type semiconductor layer (31, 32) including the position immediately below the n-side electrode (42, 43). In particular, as shown in FIG. 1, in the present embodiment, the upper surface of the reflective electrode 19 is formed so as to be in contact with the p-type semiconductor layer 32. When a voltage is applied between the support substrate 11 and the n-side electrodes (42, 43), the support substrate 11, the solder layers (13, 15), the solder diffusion prevention layer 17, the protective layer 18, the reflective electrode 19, A current path that flows to the n-side electrode (42, 43) through the semiconductor layer 30 is formed.

  In this embodiment, the protective layer 18 is formed in a multilayer structure of Ni / Ti / Pt in order from the side closer to the reflective electrode 19. The protective layer 18 is formed such that the entire upper surface is in contact with the bottom surface of the reflective electrode 19. As the protective layer 18, Cu, Au, Mg, Ni, or the like can be used at a location (uppermost surface) in contact with the reflective electrode 19, and Mo, W, or the like can be used at the opposite location (lowermost surface). Rh, Pt, etc. can be used. If the protective layer 18 has sufficient adhesion to the reflective electrode 19, the Ti layer may not be formed.

  As will be described later, the protective layer 18 has a function of preventing voids from being formed on the surface of the reflective electrode 19.

(Insulating layer 21)
Insulating layer 21 is composed for example _{SiO 2, SiN, Zr 2 O} 3, AlN, etc. _Al 2 _{O 3.} The insulating layer 21 is formed at a position immediately below the n-side electrodes (42, 43), and the upper surface of the insulating layer 21 is in contact with the bottom surface of the protective layer 18. The insulating layer 21 serves to expand the current flowing through the light emitting layer 33 in a direction (horizontal direction) parallel to the substrate surface of the support substrate 11. Furthermore, the insulating layer 21 is also formed at a position outside the semiconductor layer 30 and functions as an etching stopper layer at the time of element isolation, as will be described later in the section of the process. In the semiconductor light emitting device 1 shown in FIG. 1, the insulating layer 21 at the outer peripheral position is formed so as to be in contact with the side surfaces of the protective layer 18 and the reflective electrode 19.

(Semiconductor layer 30)
As described above, the semiconductor layer 30 is formed by stacking the p-type semiconductor layer 32, the p-type semiconductor layer 31, the light emitting layer 33, and the n-type semiconductor layer 35 in this order from the bottom.

The p-type semiconductor layer 32 is made of, for example, GaN. The p-type semiconductor layer 31 is made of, for example, Al _m Ga _1-m N (0 ≦ m <1). All layers are doped with p-type impurities such as Mg, Be, Zn, or C. Note that the p-type semiconductor layer 32 has a higher impurity concentration than the p-type semiconductor layer 31 and forms a contact layer. In the present embodiment, these p-type semiconductor layers (31, 32) correspond to “second semiconductor layers”.

  The light emitting layer 33 is formed of a semiconductor layer having a multiple quantum well structure in which, for example, a well layer made of InGaN and a barrier layer made of AlGaN are repeated. These layers may be undoped or p-type or n-type doped.

The n-type semiconductor layer 35 has a multilayer structure including, for example, a layer composed of Al _n Ga _1-n N (0 ≦ n <1) and a layer composed of GaN. At least a layer composed of GaN is doped with an n-type impurity such as Si, Ge, S, Se, Sn, or Te. In the present embodiment, the n-type semiconductor layer 35 corresponds to a “first semiconductor layer”.

(N-side electrode 42, n-side electrode 43)
The n-side electrodes (42, 43) are formed in the upper layer of the n-type semiconductor layer 35 and are made of, for example, Cr—Au. Among these, a wire 45 made of, for example, Au or Cu is connected to the n-side electrode 43, and the other of the wire 45 is a substrate (support substrate 11) on which the semiconductor light emitting element 1 is disposed. It is connected to a power supply pattern (not shown). That is, the n-side electrode 43 functions as a power supply terminal of the semiconductor light emitting element 1.

  On the other hand, the n-side electrode 42 is electrically connected to the n-side electrode 43 and formed, for example, in a mesh shape over a wide range of the upper surface of the n-type semiconductor layer 35. That is, by contacting the upper surface of the n-type semiconductor layer 35 at a location different from the n-side electrode 43 constituting the power supply terminal in the upper surface of the n-type semiconductor layer 35, the n-type semiconductor layer 35 in the horizontal direction when energized. It is formed for the purpose of flowing a current over a wide range of the light-emitting layer 33, thereby flowing a current over a wide range of the light emitting layer 33. In the present embodiment, these n-side electrodes (42, 43) correspond to “first electrodes”.

Although not shown, an insulating layer as a protective film may be formed on the side surface of the semiconductor layer 30. Note that the insulating layer as the protective film is preferably made of a light-transmitting material (eg, SiO ₂ ). In the above-described embodiment, one material constituting the p-type semiconductor layer 31 is described as Al _m Ga _1-m N (0 ≦ m <1), and one material constituting the n-type semiconductor layer 35 is Al _n. Although described as Ga _1-n N (0 ≦ n <1), these may be the same material.

  Further, for the purpose of further increasing the light extraction efficiency, minute irregularities (mesa structure) may be formed on the upper surface of the n-type semiconductor layer 35.

  2 shows the semiconductor layer 30 from the light extraction side at the stage of annealing the reflective electrode 19 and the protective layer 18 of the semiconductor light emitting device 1 shown in FIG. It is the photograph taken through the substrate which grows. Compared with the photograph of FIG. 13, no black spots appear on the surface of the reflective electrode 19, and it can be confirmed that no void is formed. As a result, the light extraction efficiency is improved as compared with the conventional semiconductor light emitting device 90, as shown in the examples described later.

  Further, according to the configuration shown in FIG. 1, the reflective electrode 19 is formed in a region including a position immediately below the n-side electrode (42, 43), but at a position immediately below the n-side electrode (42, 43). Since the insulating layer 21 is formed on the bottom surface of the reflective electrode 19, no current flows below the bottom surface of the reflective electrode 19 at a position immediately below the n-side electrodes (42, 43). Since the current path is formed in a region where the insulating layer 21 is not formed, according to the above configuration, even if the reflective electrode 19 and the n-side electrode (42, 43) are in a positional relationship facing each other in the vertical direction, Most of the current does not flow only in the light emitting layer 33 in the region sandwiched between the reflective electrode 19 and the n-side electrode (42, 43). That is, according to the semiconductor light emitting device 1 shown in FIG. 1, the current flowing in the light emitting layer 33 is parallel to the substrate surface of the support substrate 11 (horizontal direction) without providing an insulating layer on the reflective electrode 19. The effect can be obtained.

Also in the semiconductor light emitting device 90 shown in FIG. 12, an insulating layer 94 is provided for the purpose of spreading the current in the horizontal direction. However, when the light emitted downward from the light emitting layer 97 is reflected by the reflective film 93 and extracted upward, this light is reflected twice before the reflection by the reflective film 93 and after the reflection. Will pass through. In Patent Document 1, materials such as SiO ₂ , Al ₂ O ₃ , ZrO ₂ , and TiO ₂ are listed as materials for the insulating film 94. When the insulating film 94 is formed of these materials, the insulating film 94 is used. Although 94 is configured as a transparent film, several% of light is absorbed by the insulating film 94 when light passes through the insulating film 94. More specifically, about 3-4% of light is absorbed from the light emitting layer 97 through the insulating film 94 to reach the reflecting film 93, and the light reflected by the reflecting film 93 passes through the insulating film 94. Thus, 3-4% of light is further absorbed before being extracted to the outside on the n-type semiconductor layer 98 side.

  On the other hand, according to the configuration shown in FIG. 1, the light emitted from the light emitting layer 33 to the support substrate 11 side is absorbed by the insulating layer before being reflected by the reflective electrode 19 and taken out to the n-type semiconductor layer 35 side. Therefore, the light extraction efficiency is further improved as compared with the prior art.

<Production method>
Next, an example of a method for manufacturing the semiconductor light emitting device 1 will be described with reference to process cross-sectional views shown in FIGS. 3A to 3K. The dimensions such as manufacturing conditions and film thickness described below are merely examples, and are not limited to these numerical values.

(Step S1)
As shown in FIG. 3A, the epi layer 40 is formed on the sapphire substrate 61. This step S1 is performed by the following procedure, for example.

(Preparation of sapphire substrate 61)
First, the c-plane sapphire substrate 61 is cleaned. More specifically, for this cleaning, for example, a c-plane sapphire substrate 61 is placed in a processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and hydrogen having a flow rate of 10 slm is placed in the processing furnace. While flowing the gas, the temperature in the furnace is raised to, for example, 1150 ° C.

(Formation of undoped layer 36)
Next, a low-temperature buffer layer made of GaN is formed on the surface of the c-plane sapphire substrate 61, and a base layer made of GaN is further formed thereon. These low-temperature buffer layer and underlayer correspond to the undoped layer 36.

  A more specific method for forming the undoped layer 36 is, for example, as follows. First, the furnace pressure of the МОCVD apparatus is 100 kPa, and the furnace temperature is 480 ° C. Then, while flowing nitrogen gas and hydrogen gas with a flow rate of 5 slm respectively as carrier gas into the processing furnace, trimethylgallium (TMG) with a flow rate of 50 μmol / min and ammonia with a flow rate of 250,000 μmol / min are used as the raw material gas in the processing furnace. For 68 seconds. As a result, a low-temperature buffer layer made of GaN having a thickness of 20 nm is formed on the surface of the c-plane sapphire substrate 61.

  Next, the furnace temperature of the MOCVD apparatus is raised to 1150 ° C. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas in the processing furnace, TMG having a flow rate of 100 μmol / min and ammonia having a flow rate of 250,000 μmol / min are introduced into the processing furnace as source gases. Feed for 30 minutes. As a result, a base layer made of GaN having a thickness of 1.7 μm is formed on the surface of the low-temperature buffer layer.

<Formation of n-type semiconductor layer 35>
Next, an n-type semiconductor layer 35 having a composition of Al _n Ga _1-n N (0 ≦ n ≦ 1) is formed on the undoped layer 36.

A more specific method for forming the n-type semiconductor layer 35 is, for example, as follows. First, with the furnace temperature kept at 1150 ° C., the furnace pressure of the MOCVD apparatus is set to 30 kPa. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas into the processing furnace, TMG having a flow rate of 94 μmol / min, trimethylaluminum (TMA) having a flow rate of 6 μmol / min, Ammonia with a flow rate of 250,000 μmol / min and tetraethylsilane with a flow rate of 0.025 μmol / min are supplied into the treatment furnace for 60 minutes. Thereby, for example, an n-type semiconductor layer 35 having a composition of Al _0.06 Ga _0.94 N, a Si concentration of 3 × 10 ¹⁹ / cm ³ , and a thickness of 2 μm is formed in the upper layer of the undoped layer 36. .

  After that, the supply of TMA is stopped, and other source gases are supplied for 6 seconds, thereby realizing an n-type semiconductor layer 35 having n-type GaN with a thickness of 5 nm on the n-AlGaN layer. May be.

  In the above description, the case where Si is used as the n-type impurity contained in the n-type semiconductor layer 35 has been described. However, Ge, S, Se, Sn, Te, or the like can be used as the n-type impurity in addition to Si. .

<Formation of the light emitting layer 33>
Next, a light emitting layer 33 having a multiple quantum well structure in which a well layer made of InGaN and a barrier layer made of n-type AlGaN are periodically repeated is formed on the n-type semiconductor layer 35.

  Specifically, first, the furnace pressure of the MOCVD apparatus is set to 100 kPa, and the furnace temperature is set to 830 ° C. Then, while flowing nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 1 slm as a carrier gas in the processing furnace, TMG having a flow rate of 10 μmol / min, trimethylindium (TMI) having a flow rate of 12 μmol / min, and A step of supplying ammonia at a flow rate of 300,000 μmol / min into the processing furnace for 48 seconds is performed. Thereafter, TMG having a flow rate of 10 μmol / min, TMA having a flow rate of 1.6 μmol / min, tetraethylsilane having a flow rate of 0.002 μmol / min, and ammonia having a flow rate of 300,000 μmol / min are supplied into the processing furnace for 120 seconds. Hereinafter, by repeating these two steps, the light-emitting layer 33 having a multi-quantum well structure of 15 periods with a well layer made of InGaN having a thickness of 2 nm and a barrier layer made of n-type AlGaN having a thickness of 7 nm is formed into an n-type. It is formed in the upper layer of the semiconductor layer 35.

<Formation of p-type semiconductor layer 31>
Next, a p-type semiconductor layer 31 composed of Al _m Ga _1-m N (0 ≦ m ≦ 1) is formed on the light emitting layer 33.

Specifically, the furnace pressure of the MOCVD apparatus is maintained at 100 kPa, and the furnace temperature is raised to 1025 ° C. while nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 25 slm are supplied as carrier gases in the processing furnace. To do. Thereafter, as source gases, TMG with a flow rate of 35 μmol / min, TMA with a flow rate of 20 μmol / min, ammonia with a flow rate of 250,000 μmol / min, and biscyclopentadiene with a flow rate of 0.1 μmol / min for doping p-type impurities. Enilmagnesium (CP ₂ Mg) is fed into the processing furnace for 60 seconds. Thereby, a hole supply layer having a composition of Al _0.3 Ga _0.7 N having a thickness of 20 nm is formed on the surface of the light emitting layer 33. Thereafter, by changing the flow rate of TMA to 4 μmol / min and supplying the source gas for 360 seconds, a hole supply layer having a composition of Al _0.13 Ga _0.87 N having a thickness of 120 nm is formed. A p-type semiconductor layer 31 is formed by these hole supply layers. The p-type impurity concentration of the p-type semiconductor layer 31 is, for example, about 3 × 10 ¹⁹ / cm ³ .

<Formation of p-type semiconductor layer 32>
Thereafter, the supply of TMA is stopped, the flow rate of CP ₂ Mg is changed to 0.2 μmol / min, and the raw material gas is supplied for 20 seconds, whereby the thickness is about 5 nm and the p-type impurity concentration is 1 × 10. ^A p-type semiconductor layer 32 made of p ⁺ GaN of about ²⁰ / cm ³ is formed.

  In this manner, the epi layer 40 including the undoped layer 36, the n-type semiconductor layer 35, the light emitting layer 33, the p-type semiconductor layer 31, and the p-type semiconductor layer 32 is formed on the sapphire substrate 61.

(Step S2)
Next, an activation process is performed on the wafer obtained in step S1. More specifically, activation is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal) device.

(Step S3)
Next, as shown in FIG. 3B, an electrode material (first conductive layer 19 a) that constitutes the reflective electrode 19 is deposited on a predetermined portion of the upper surface of the p-type semiconductor layer 32. Here, a case is shown in which the reflective electrode 19 is formed in almost the entire region of the p-type semiconductor layer 32 inside the region where the p-type semiconductor layer 32 is formed. More specifically, the p-type semiconductor layer is formed by, for example, a sputtering apparatus so that the reflective electrode 19 is formed so as to include a portion located immediately below a region where the n-side electrode 42 as a power supply terminal is formed in a later step. A first conductive layer 19a is deposited by depositing 0.7 nm thick Ni and 130 nm thick Ag on the upper surface of 32. The thickness of the first conductive layer 19a is preferably 50 nm or more and 150 nm or less.

  In addition, although the alloy of Ni and Ag is employ | adopted as the material of the 1st conductive layer 19a here, the material containing Al can also be used.

(Step S4)
After depositing the first conductive layer 19a in step S3, without conducting an annealing process, as shown in FIG. 3C, the conductive material (second layer) that forms the protective layer 18 over the entire upper surface of the first conductive layer 19a. A conductive layer is deposited. As an example, the protective layer 18 is formed by depositing Ni with a thickness of 20 nm, Ti with a thickness of 20 nm, and Pt with a thickness of 30 nm. The thickness of the protective layer 18 is preferably 20 nm or more and 100 nm or less.

  In addition, as a material of the second conductive layer forming the protective layer 18, Cu, Au, Mg or the like can be used in addition to Ni at a portion in contact with the first conductive layer 19a. In addition to Pt, Mo, W, Rh, or the like can be used. In addition, when the protective layer 18 can ensure sufficient adhesion to the first conductive layer 19a, Ti as an intermediate layer may not be formed.

(Step S5)
An annealing process is performed at 450 ° C. to 550 ° C. for 60 seconds to 300 seconds in a dry air atmosphere using an RTA apparatus or the like to form ohmic contact between the first conductive layer 19a and the p-type semiconductor layers (31, 32). Through this step, the first conductive layer 19 a functions as the reflective electrode 19.

  In Step S4, by performing the annealing process according to Step S5 with the protective layer 18 formed on the entire upper surface of the first conductive layer 19a, the protective layer 18 functions as a barrier layer, and voids on the upper surface of the reflective electrode 19 are formed. The effect of preventing the formation of is obtained.

(Step S6)
Next, as shown in FIG. 3D, an insulating layer 21 is formed at a predetermined position on the upper layer of the protective layer 18. In particular, the insulating layer 21 is formed at a location located below a region where the n-side electrode (42, 43) is formed in a later step. At this time, as shown in FIG. 3D, a part of the insulating layer 21 can be formed so as to cover the side surfaces of the protective layer 18 and the reflective electrode 19.

More specifically, the upper layer of the protective layer 18 in the region where the insulating layer 21 is not formed is masked, and, for example, SiO _{2 is formed} to a thickness of about 200 nm by sputtering. Note that the material for forming the film may be an insulating material, such as SiN or Al ₂ O ₃ .

(Step S7)
As shown in FIG. 3E, the solder diffusion preventing layer 17 and the solder layer 15 are formed so as to cover the upper surfaces of the protective layer 18 and the insulating layer 21.

  More specifically, solder is formed by depositing three periods of 100 nm thick Ti and 200 nm thick Pt so as to cover the upper surfaces of the protective layer 18 and the insulating layer 21 with an electron beam evaporation apparatus (EB apparatus). A diffusion prevention layer 17 is formed. Further, after depositing 10 nm thick Ti on the upper surface (Pt surface) of the solder diffusion preventing layer 17, Au-Sn solder composed of 80% Sn 20% Au is deposited to a thickness of 3 μm. 15 is formed.

  In the step of forming the solder layer 15, the solder layer 13 may be formed on the upper surface of the support substrate 11 prepared separately from the sapphire substrate 61 (see FIG. 3F). The solder layer 13 may be made of the same material as the solder layer 15, and is bonded to the solder layer 13 in the next step, whereby the sapphire substrate 61 and the support substrate 11 are bonded together. For example, CuW is used as the support substrate 11 as described above in the section of the structure.

  Further, in FIG. 3F, a protective layer for preventing the material of the solder layer 13 from diffusing is formed on the support substrate 11 with the same material as the solder diffusion preventing layer 17, and the solder layer 13 is formed on the protective layer. It may be formed.

(Step S8)
Next, as shown in FIG. 3G, the sapphire substrate 61 and the support substrate 11 are bonded together. As an example, the solder layer 15 and the solder layer 13 formed on the upper layer of the support substrate 11 are bonded together at a temperature of 280 ° C. and a pressure of 0.2 MPa.

(Step S9)
Next, as shown in FIG. 3H, the sapphire substrate 61 is peeled off. More specifically, the interface between the sapphire substrate 61 and the epi layer 40 is decomposed by irradiating a KrF excimer laser from the sapphire substrate 61 side with the sapphire substrate 61 facing upward and the support substrate 11 facing downward. Then, the sapphire substrate 61 is peeled off. While the laser passes through the sapphire 61, the underlying GaN (undoped layer 36) absorbs the laser, so that this interface is heated to decompose GaN. As a result, the sapphire substrate 61 is peeled off.

  Thereafter, as shown in FIG. 3I, GaN (undoped layer 36) remaining on the wafer is removed by wet etching using hydrochloric acid or the like, or dry etching using an ICP apparatus, and the n-type semiconductor layer 35 is removed. Expose. In this step S9, the undoped layer 36 is removed, and the semiconductor layer 30 in which the p-type semiconductor layer 32, the p-type semiconductor layer 31, the light emitting layer 33, and the n-type semiconductor layer 35 are stacked in this order from the bottom remains. To do.

(Step S10)
Next, as shown in FIG. 3J, adjacent elements are separated from each other. Specifically, the semiconductor layer 30 is etched using an ICP device until the upper surface of the insulating layer 21 is exposed in a boundary region with an adjacent element. As described above, at this time, the insulating layer 21 also functions as a stopper during etching.

(Step S11)
Next, as shown in FIG. 3K, n-side electrodes (42, 43) are formed on the upper surface of the n-type semiconductor layer 35 at a position immediately above the location where the insulating layer 21 is formed. Specifically, after forming an electrode made of Cr having a thickness of 100 nm and Au having a thickness of 3 μm, sintering is performed at 250 ° C. for 1 minute in a nitrogen atmosphere.

  Then, the elements are separated from each other by, for example, a laser dicing apparatus, the back surface of the support substrate 11 is joined to the package by, for example, Ag paste, and wire bonding is performed on the n-side electrode 43 as a power supply terminal. For example, wire bonding is performed by connecting a wire 45 made of Au to a bonding region of Φ100 μm with a load of 50 g. Thereby, the nitride semiconductor light emitting device 1 shown in FIG. 1 is formed.

  In addition, an unevenness (mesa structure) may be formed on the surface of the n-type semiconductor layer 35 by immersing an alkaline solution such as KOH between Step S10 and Step S11. In addition, after the n-side electrode (42, 43) is formed on the upper surface of the n-type semiconductor layer 35, an insulating layer may be formed so as to cover the side surface of the semiconductor layer 30.

[Second Embodiment]
The configuration of the second embodiment of the semiconductor light emitting device of the present invention will be described. In addition, about the structure same as 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  FIG. 4 is a cross-sectional view schematically showing the configuration of the semiconductor light emitting device of the second embodiment. The semiconductor light emitting device 1a is different from the semiconductor light emitting device 1 of the first embodiment in that the insulating layer 21 is formed in contact with the p-type semiconductor layer 32. More specifically, the difference is that the insulating layer 21 is formed prior to the reflective electrode 19 and the protective layer 18 during the process.

  Hereinafter, only the differences from the first embodiment will be described with respect to the method for manufacturing the semiconductor light emitting device 1a shown in FIG.

  First, as in the first embodiment, steps S1 and S2 are executed to form the epi layer 40 on the upper layer of the sapphire substrate 61.

(Step S2A)
Next, as shown in FIG. 5A, the insulating layer 21 is formed at a position located below a region where the n-side electrode (42, 43) is formed in a later step by the same method as Step S 6 of the first embodiment. Form.

(Step S2B)
Next, as shown in FIG. 5B, an electrode material (first conductive layer 19a) constituting the reflective electrode 19 is deposited by the same method as in step S3. In the present embodiment, the first conductive layer 19 a is deposited on the entire surface so as to cover the upper surfaces of the insulating layer 21 and the p-type semiconductor layer 32.

(Step S2C)
Next, as shown in FIG. 5C, a conductive material (second conductive layer) constituting the protective layer 18 is deposited on the entire upper surface of the first conductive layer 19a by the same method as in step S4. At this time, as in the first embodiment, this step is executed without performing the annealing step after step S2B.

  Thereafter, an annealing process is performed in the same manner as in step S5 to form ohmic contact between the first conductive layer 19a and the p-type semiconductor layers (31, 32). Through this step, the first conductive layer 19 a functions as the reflective electrode 19. In the following, the semiconductor light emitting element 1a shown in FIG. 4 is formed by executing Steps S7 to S11 as in the first embodiment.

  Also in the configuration of the present embodiment, as in the first embodiment, the annealing process is not performed after the deposition of the first conductive layer 19a constituting the reflective electrode 19, and the entire upper surface of the first conductive layer 19a is covered with the protective layer 18. Since the annealing process is performed in a broken state, formation of voids on the upper surface of the reflective electrode 19 is prevented, and high reflectance is ensured.

  According to the semiconductor light emitting device 1a shown in FIG. 4, when light emitted downward from the light emitting layer 33 is reflected by the reflective electrode 19 and extracted upward, this light is reflected before being reflected by the reflective electrode 19. The light passes through the insulating film 21 twice after being reflected. For this reason, the light extraction efficiency is somewhat lower than the configuration of the first embodiment in that a part of this light is absorbed in the insulating layer 21. However, the formation of voids on the upper surface of the reflective electrode 19 is prevented and a high reflectance is realized, so that the light extraction efficiency is improved as compared with the conventional case.

[Another embodiment]
Hereinafter, another embodiment will be described.

  <1> The present invention is not limited to the structure shown in FIG. 1 and FIG. 4 described above, and after depositing the conductive material (first conductive layer 19a) constituting the reflective electrode 19, the first treatment is performed without performing annealing. Semiconductor light emission realized by covering the upper surface of the conductive layer 19a with the protective layer 18 and then performing an annealing process for realizing ohmic contact between the reflective electrode 19 and the semiconductor layer 30 (more specifically, the p-type semiconductor layer 32). Target the device.

  FIG. 6 is a cross-sectional view schematically showing an example of the configuration of the semiconductor light emitting element 1b according to another embodiment. In this configuration, the reflective electrode 19 is not formed immediately below the n-side electrode (42, 43), and the insulating layer 21 is formed immediately below the n-side electrode (42, 43). . A reflective film 18 is formed on the bottom surface of the insulating layer 21.

  The semiconductor light emitting device 1b is formed by performing an annealing process after depositing this electrode material when forming the reflective electrode 95 (corresponding to the reflective electrode 19 in FIG. 6) in the conventional semiconductor light emitting device 90 shown in FIG. The protective layer 18 is formed without performing the annealing process.

  Also in the semiconductor light emitting device 1b shown in FIG. 6, since the formation of voids on the upper surface of the reflective electrode 19 can be prevented, the reflectance at the reflective electrode 19 is improved compared to the conventional semiconductor light emitting device 90, and high light Extraction efficiency is realized.

  <2> The semiconductor light emitting devices (1, 1a, 1b) according to the respective embodiments described above are assumed to be realized with the light extraction surface as the n side and the opposite side as the p side. However, the present invention may be realized as a configuration in which the n side and the p side are completely inverted.

  <3> In the above-described embodiment, the light-emitting element made of a nitride semiconductor has been described as the semiconductor light-emitting element (1, 1a, 1b). However, the structure of the present invention can also be applied to light emitting elements made of other semiconductors.

  <4> In the semiconductor light emitting device (1, 1a, 1b) according to each of the above-described embodiments, the current flowing in the light emitting layer 33 is positioned directly below the n-side electrode (42, 43) for the purpose of spreading the current in the horizontal direction. The insulating layer 21 is provided. However, in the present invention, the insulating layer 21 is not necessarily provided. However, it is preferable to provide the insulating layer 21 from the viewpoint of improving the light extraction efficiency with the same amount of current.

  <5> In each of the above-described embodiments, the n-side electrodes (42, 43) included in the semiconductor light-emitting element and the reflective electrode 19 constituting the p-side electrode are arranged apart from each other in the vertical direction so as to sandwich the semiconductor layer 30. The case where the so-called “vertical structure” is shown has been described. However, the present invention can also be applied to a case where a so-called “lateral structure” in which the n-side electrode and the p-side electrode are arranged in the same direction with respect to the semiconductor layer 30 is shown. In this case, the semiconductor light emitting element is formed on the sapphire substrate 61 without the step of lifting off the sapphire substrate 61 (step S9).

  FIG. 7 is a schematic cross-sectional view of a nitride semiconductor light emitting device 1c according to another embodiment. In addition, about the same material as 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted. Moreover, the arrow in FIG. 7 has shown the extraction direction of light, and the light extraction direction is opposite to the nitride semiconductor light-emitting device 1 shown in FIG.

  The nitride semiconductor light emitting device 1c includes a sapphire substrate 61, a semiconductor layer 30a, reflection electrodes 19 and 19b, a protective layer 18, a power supply terminal 51, and a power supply terminal 52. The semiconductor layer 30 a includes a p-type semiconductor layer 31, a p-type semiconductor layer 32, a light emitting layer 33, an n-type semiconductor layer 35, and an undoped layer 36. In this embodiment, in order to distinguish from the reflective electrode 19 formed on the upper surface of the p-type semiconductor layer 32, the reflective electrode formed on the upper surface of the n-type semiconductor layer 35 is referred to as a “reflective electrode 19b”. However, both may be made of the same material.

  Also in this configuration, as in the above-described embodiments, after depositing the metal material (first conductive layer) that constitutes the reflective electrodes 19 and 19b, the protective layer 18 is formed without performing an annealing process, and thereafter By performing the annealing treatment, formation of voids on the surfaces of the reflective electrodes 19 and 19b is prevented.

  Hereinafter, only the points different from the first embodiment will be described for the method of manufacturing the nitride semiconductor light emitting device 1c shown in FIG.

  First, similarly to the first embodiment, step S1 and step S2 are executed.

(Step S12)
After step S2 (see FIG. 3A), as shown in FIG. 8A, the p-type semiconductor layer 32, the p-type semiconductor layer 31, and the light-emitting layer 33 are placed on the ICP until a partial upper surface of the n-type semiconductor layer 35 is exposed. It is removed by dry etching using an apparatus. In this step, the n-type semiconductor layer 35 may also be partially removed by etching.

(Step S13)
As shown in FIG. 8B, the same electrode material (first conductive layer 19a) as that in the first embodiment is deposited on the upper surface of the p-type semiconductor layer 32 and the exposed upper surface of the n-type semiconductor layer 35.

(Step S14)
Next, after depositing the first conductive layer 19a in step S13, the conductive material (second conductive layer) constituting the protective layer 18 is continuously deposited without performing an annealing process. The material of the protective layer 18 can be the same material as in the first embodiment.

(Step S15)
Similarly to step S5 of the first embodiment, annealing is performed at 450 ° C. to 550 ° C. for 60 seconds to 300 seconds in a dry air atmosphere using an RTA apparatus or the like, and the first conductive layer 19a and the p-type semiconductor layer (31 , 32), and ohmic contact between the first conductive layer 19a and the n-type semiconductor layer 35 is formed. Through this step, the first conductive layer 19a functions as the reflective electrode 19 and the reflective electrode 19b (see FIG. 8C). Also in this embodiment, since the annealing process according to step S15 is performed in a state where the protective layer 18 is formed on the entire upper surface of the first conductive layer 19a in step S14, the protective layer 18 functions as a barrier layer, and the reflective electrode 19, the effect of preventing the formation of voids on the upper surface of the reflective electrode 19b can be obtained.

(Step S16)
Thereafter, the power supply terminal 51 is formed on the upper surface of the protective layer 18 on the reflective electrode 19b side, and the power supply terminal 52 is formed on the upper surface of the protective layer 18 on the reflective electrode 19 side. More specifically, after forming a conductive material film (for example, a material film made of Cr with a thickness of 100 nm and Au with a thickness of 3 μm) to form the power supply terminals 51 and 52, the power supply terminals 51 and 52 are formed by lift-off. To do. Thereafter, sintering is performed at 250 ° C. for 1 minute in a nitrogen atmosphere.

  Then, the substrate 55 and the power supply terminal 51 are connected via the bonding electrode 53, and the substrate 55 and the power supply terminal 52 are connected via the bonding electrode 54, thereby forming the nitride semiconductor light emitting element 1c shown in FIG. The

[Example]
The current-voltage characteristics and the light emission characteristics were compared for each element of the example and the comparative example.

(Example 1)
The semiconductor light emitting device 1 (FIG. 1) of the first embodiment manufactured by the method described above was taken as Example 1. The reflective electrode 19 was formed with Ni having a thickness of 1 nm and Ag having a thickness of 130 nm, and the protective layer 18 was formed with Ni having a thickness of 20 nm, Ti having a thickness of 20 nm, and Pt having a thickness of 30 nm.

(Example 2)
The semiconductor light emitting device 1a (FIG. 4) according to the second embodiment manufactured by the above-described method was taken as Example 2. The configurations of the reflective electrode 19 and the protective layer 18 were the same as those in Example 1.

Example 3
A semiconductor light emitting device 1b (FIG. 6) according to another embodiment manufactured by the above-described method was taken as Example 3. The configurations of the reflective electrode 19 and the protective layer 18 were the same as those in Example 1.

(Comparative Example 1)
The device 1 of Example 1 was configured such that the protective layer 18 was not provided (see FIG. 9A). That is, in the element 2 of Comparative Example 1, after the conductive material constituting the reflective electrode 19 was deposited, the reflective electrode 19 was formed by performing an annealing process without forming the protective layer 18. The conductive layer 20 a included in the element 2 of Comparative Example 1 includes a solder layer (13, 15), a solder diffusion prevention layer 17, and a reflective electrode 19.

(Comparative Example 2)
A configuration in which the protective layer 18 is not provided for the element 1a of Example 2 was used (see FIG. 9B). That is, in the element 2a of Comparative Example 2, after the conductive material constituting the reflective electrode 19 was deposited, the reflective electrode 19 was formed by annealing without forming the protective layer 18. The conductive layer 20 a included in the element 2 a of Comparative Example 2 includes a solder layer (13, 15), a solder diffusion prevention layer 17, and a reflective electrode 19.

(Comparative Example 3)
A configuration in which the protective layer 18 is not provided for the element 1b of Example 3 was used (see FIG. 9C). That is, in the element 2b of Comparative Example 3, after the conductive material constituting the reflective electrode 19 was deposited, the reflective electrode 19 was formed by performing an annealing process without forming the protective layer 18. The conductive layer 20 a included in the element 2 b of Comparative Example 3 includes a solder layer (13, 15), a solder diffusion prevention layer 17, and a reflective electrode 19. The reflective film 93 is also composed of a conductive layer.

  FIG. 10 shows the relationship between the flowing current value and the voltage value when voltage is applied to each element (1, 1a, 1b) of the example and each element (2, 2a, 2b) of the comparative example (I− It is a graph which shows a V characteristic. When comparing each element of the example and each element of the comparative example, the voltage values required to flow the same current value are almost the same, and the low voltage driving equivalent to the configuration of the comparative example can be realized. I understand.

  FIG. 11 is a graph showing the relationship between the light emission output and the current value obtained when current is supplied to each element (1, 1a, 1b) of the example and each element (2, 2a, 2b) of the comparative example. It is. Comparing Comparative Example 1 and Example 1, Comparative Example 2 and Example 2, and Comparative Example 3 and Example 3, respectively, according to FIG. It can be seen that the light emission output is improved from the corresponding comparative example.

  From this result, the formation of voids on the upper surface of the reflective electrode 19 is prevented in the embodiment in which the electrode layer constituting the reflective electrode 19 is deposited and then the protective layer 18 is formed and then annealed. It can be seen that the light extraction efficiency is improved as the rate is improved.

  Further, comparing Example 2 and Example 1, Example 1 has higher light extraction efficiency. Thus, it can be seen that the configuration in which the insulating layer is not provided on the reflective electrode 19 eliminates the absorption of a part of the light in the insulating layer and further improves the light extraction efficiency.

DESCRIPTION OF SYMBOLS 1: Semiconductor light emitting element of 1st Embodiment 1a: Semiconductor light emitting element of 2nd Embodiment 1b: Semiconductor light emitting element of another embodiment 1c: Semiconductor light emitting element of another embodiment 2: Semiconductor light emitting element 2a of Comparative Example 1: Comparison Semiconductor light emitting device 2b of Example 2: Semiconductor light emitting device of Comparative Example 11: Support substrate 13: Solder layer 15: Solder layer 17: Solder diffusion prevention layer 18: Protective layer 19: Reflective electrode 19a: First conductive layer 19b: Reflective Electrode 20: Conductive layer 21: Insulating layer 30, 30a: Semiconductor layer 31: p-type semiconductor layer 32: p-type semiconductor layer 33: light-emitting layer 35: n-type semiconductor layer 36: undoped layer 40: epi layer 42: n-side electrode 43: n-side electrode (feeding terminal)
45: Wire 51: Power supply terminal 52: Power supply terminal 53: Bonding electrode 55: Substrate 90: Conventional semiconductor light emitting device 91: Support substrate 92: Conductive layer 93: Reflective film 94: Insulating layer 95: Reflective electrode 96: P-type semiconductor Layer 97: Light emitting layer 98: N-type semiconductor layer 99: Semiconductor layer 100: N-side electrode 101: Void

Claims (11)

an n-type or p-type first semiconductor layer; a second semiconductor layer having a conductivity type different from that of the first semiconductor layer; and a light emitting layer formed between the first semiconductor layer and the second semiconductor layer. A method for manufacturing a semiconductor light emitting device, comprising:
Preparing a substrate (a),
Forming the first semiconductor layer, the light emitting layer, and the second semiconductor layer on the substrate in order from the bottom (b);
Depositing a first conductive layer constituting a reflective electrode on the second semiconductor layer (c);
A step (d) of depositing a second conductive layer constituting a protective layer on the entire upper surface of the first conductive layer without performing an annealing step after the step (c);
And a step (e) of annealing at a temperature at which an ohmic contact is formed between the first conductive layer and the second semiconductor layer after the step (d). .   The method of manufacturing a semiconductor light emitting element according to claim 1, wherein the step (e) is a step of annealing at a temperature of 450 ° C or higher and 550 ° C or lower.   3. The method for manufacturing a semiconductor light emitting element according to claim 1, wherein the first conductive layer is made of a material containing at least one of Ag and Al. 4.   The method for manufacturing a semiconductor light-emitting element according to claim 1, wherein the first conductive layer is formed with a thickness of 150 nm or less.   5. The semiconductor light-emitting element according to claim 1, wherein all of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer are formed of a nitride semiconductor layer. 6. Production method. Light emission formed on a substrate between an n-type or p-type first semiconductor layer, a second semiconductor layer having a conductivity type different from that of the first semiconductor layer, and the first semiconductor layer and the second semiconductor layer. A semiconductor light emitting device having a layer,
A reflective electrode formed in contact with at least one of the first semiconductor layer and the second semiconductor layer;
A semiconductor light emitting element comprising: a protective layer made of a conductive material different from the reflective electrode, the entire surface being in contact with the reflective electrode. The reflective electrode is formed in contact with the bottom surface of the second semiconductor layer formed at a position closer to the substrate than the first semiconductor layer,
The semiconductor light emitting device according to claim 6, wherein the protective layer is formed so that the entire upper surface is in contact with the bottom surface of the reflective electrode. A first electrode formed by contacting an upper surface with a bottom surface of the first semiconductor layer;
8. The semiconductor light emitting element according to claim 7, further comprising: an insulating layer formed so that an upper surface thereof is in contact with a bottom surface of the protective layer at a position immediately below a position where the first electrode is formed.   The semiconductor light emitting element according to claim 6, wherein the reflective electrode is made of a material containing at least one of Ag and Al.   The semiconductor light-emitting element according to claim 6, wherein the reflective electrode has a thickness of 150 nm or less.   11. The semiconductor light emitting element according to claim 6, wherein all of the first semiconductor layer, the second semiconductor layer, and the light emitting layer are formed of a nitride semiconductor layer.