WO2016158093A1

WO2016158093A1 - Nitride semiconductor light-emitting element

Info

Publication number: WO2016158093A1
Application number: PCT/JP2016/055177
Authority: WO
Inventors: 晃平三好
Original assignee: ウシオ電機株式会社
Priority date: 2015-03-31
Filing date: 2016-02-23
Publication date: 2016-10-06
Also published as: TW201705534A; JP2016195176A

Abstract

Provided is a nitride semiconductor light-emitting element capable of emitting light at a low operation voltage while minimizing any decrease in light extraction efficiency. A semiconductor light-emitting element has a support substrate; a semiconductor layer; a first electrode formed on the surface that, among the surfaces of the semiconductor layer, is on the side closer to the support substrate; a second electrode formed on the surface that, among the surfaces of the semiconductor layer, is on the side opposite to the side where the first electrode is formed; and an electroconductive protective layer formed on the surface that, among the surfaces of the first electrode, is on the side opposite to the side where the semiconductor layer is formed. The semiconductor layer comprises a nitride semiconductor, the protective layer includes a metal material having a higher melting point than that of Ag, and the first electrode comprises an Ag alloy containing Ge and Cu.

Description

Nitride semiconductor light emitting device

The present invention relates to a nitride semiconductor light emitting device.

In recent years, light-emitting elements using nitride semiconductors have been developed. This light-emitting element includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer formed so as to be sandwiched between the n-type semiconductor layer and the p-type semiconductor layer. By providing a potential difference between the n-type semiconductor layer and the p-type semiconductor layer, a current flows between them, and electrons and holes are recombined in the active layer to emit light. Various researches and developments are in progress to effectively use the light generated in the active layer.

For example, the following Patent Document 1 discloses a light-emitting element having a so-called “vertical structure”. An element having a vertical structure refers to an element in which the active layer emits light when a voltage is applied to the active layer in a direction perpendicular to the substrate.

Especially in the case of an element having a vertical structure, a reflective material is often provided in order to increase the light extraction efficiency. Patent Document 1 also describes that a highly reflective material is provided on the electrode, and there is a description that Ag is particularly preferable.

FIG. 12 schematically shows a cross-sectional view of the light-emitting element disclosed in Patent Document 1. A conventional light emitting device 90 includes a conductive layer 92, a reflective film 93, an insulating layer 94, a reflective electrode 95, a semiconductor layer 99, and an n-side electrode 100 on a support substrate 91. The semiconductor layer 99 is configured by sequentially stacking a p-type semiconductor layer 96, an active layer 97, and an n-type semiconductor layer 98 from the support substrate 91 side.

A reflective film 93 made of a metal material is formed under the insulating layer 94, but the reflective film 93 does not have ohmic properties and does not function as an electrode. On the other hand, the reflective electrode 95 is made of a metal material and functions as an electrode (p-side electrode) by realizing ohmic contact between the p-type semiconductor layers 96.

The reflective electrode 95 reflects the light emitted in the direction toward the support substrate 91 (downward in the drawing) out of the light generated in the active layer 97, and extracts it to the n-type semiconductor layer 98 side (upward in the drawing). It also serves to increase the light extraction efficiency. In Patent Document 1, Ag is preferable as the reflective electrode 95 as described above.

Japanese Patent No. 4207781

In recent years, there has been a demand for a light-emitting element that achieves high luminance at a lower operating voltage. As a result of diligent research by the present inventor, it has been found that when the reflective electrode 95 is made of Ag in FIG. 12, it is difficult to emit light at a low operating voltage.

In view of the above problems, an object of the present invention is to realize a nitride semiconductor light emitting device capable of emitting light at a low operating voltage while suppressing a decrease in light extraction efficiency.

The nitride semiconductor light emitting device according to the present invention is
A support substrate;
An n-type semiconductor layer, a p-type semiconductor layer, and an active layer sandwiched between the n-type semiconductor layer and the p-type semiconductor layer in a direction perpendicular to the surface of the support substrate; Including a semiconductor layer;
Of the surface of the semiconductor layer, a first electrode formed on the surface near the support substrate;
A second electrode formed on the surface of the semiconductor layer opposite to the side on which the first electrode is formed;
A conductive protective layer formed on the surface of the first electrode opposite to the surface on which the semiconductor layer is formed;
The semiconductor layer is made of a nitride semiconductor,
The protective layer includes a metal material having a melting point higher than Ag,
The first electrode is made of an Ag alloy containing Ge and Cu.

The work function of Ag is 4.3 eV, the work function of Ge is 5.1 eV, and the work function of Cu is 4.6 eV. According to said structure, in addition to Ag as a constituent material of a 1st electrode, Ge and Cu which are materials with a large work function are contained, An ohmic contact between semiconductor layers can be formed easily. . Moreover, heat resistance improves because Cu is contained in the constituent material of the first electrode. As a result, Ag ball-up is suppressed, and the adhesion between the semiconductor layer and the first electrode is improved. As a result, the contact resistance between the semiconductor layer and the first electrode is lowered, so that the operating voltage can be reduced as compared with the conventional case. “Ag ball-up” refers to a phenomenon of partial condensation due to Ag migration.

Furthermore, oxidation resistance improves more than pure Ag because Cu is contained in the first electrode. Further, since Ge is contained in the first electrode, the sulfidation resistance is improved as compared with pure Ag. As a result, it is possible to suppress the reflectance from decreasing due to oxidation or sulfuration of Ag contained in the first electrode.

That is, according to the first electrode, it is possible to reduce the contact resistance with the semiconductor layer while suppressing a decrease in reflectance. Therefore, according to the nitride semiconductor light emitting device including such a first electrode, both high light extraction efficiency and low operating voltage can be achieved.

The nitride semiconductor light emitting device may have a bonding layer formed on the surface of the protective layer opposite to the surface on which the first electrode is formed. At this time, the protective layer may include at least one of Pt and Ti.

This bonding layer is provided for bonding the growth substrate and the support substrate after growing the semiconductor layer on a substrate (growth substrate) different from the support substrate when manufacturing the nitride semiconductor light emitting device. . The material constituting the bonding layer (for example, Au—Sn) has a significantly lower reflectance than Ag. For this reason, if the material which comprises a joining layer will diffuse to the 1st electrode side, the reflectance of the light in a 1st electrode will fall, and the fall of light extraction efficiency will be caused. As described above, by providing the protective layer including at least one of Pt or Ti between the bonding layer and the first electrode, the material forming the bonding layer may diffuse to the first electrode side. Since it is suppressed, it is suppressed that a reflectance falls.

The p-type semiconductor layer may be in contact with the first electrode.

At this time, both the n-type semiconductor layer and the p-type semiconductor layer may be made of a nitride semiconductor containing Al and Ga. The active layer may be formed of a nitride semiconductor capable of generating light having a wavelength of 365 nm to 405 nm.

Near-ultraviolet light having a wavelength of 365 nm or more and 405 nm or less is absorbed by GaN by about 5% or more and 90% or less. Therefore, a nitride light-emitting device that emits light in the near-ultraviolet region is composed of a nitride semiconductor (for example, AlGaN or AlInGaN) containing AlN having a higher band gap energy than GaN from the viewpoint of improving light extraction efficiency. It is preferable to do this.

However, since the mixed crystal material of AlN and GaN (herein referred to as AlGaN) has a higher band gap energy than GaN, the acceptor level becomes deep when p-type. That is, even if a p-type dopant is introduced at the same impurity concentration with respect to GaN and AlGaN, for example, when AlGaN is configured with an Al composition of about 20%, the hole concentration is about one order of magnitude lower in AlGaN than in GaN. Resulting in. For this reason, when the p-type semiconductor layer is made of AlGaN, the operating voltage tends to be higher than when it is made of GaN.

However, according to the above configuration, since the first electrode formed in contact with the p-type semiconductor layer is composed of an Ag alloy containing Ge and Cu, the adhesiveness with the p-type semiconductor layer is high. . Therefore, even when the p-type semiconductor layer is composed of a nitride semiconductor containing Al and Ga, a low contact resistance between the first electrode and the p-type semiconductor layer can be realized. As a result, a near-ultraviolet semiconductor light emitting device with a low operating voltage can be realized. In addition, since the p-type semiconductor layer formed in the region in contact with the first electrode, that is, the p-type contact layer, can be composed of a nitride semiconductor containing Al and Ga, which has a lower absorption rate than GaN, high light Extraction efficiency is realized.

The Ag alloy constituting the first electrode may contain Al.

When the first electrode contains Al, Ag migration is suppressed and Ag aggregation is suppressed. As a result, since the ball up of Ag is suppressed, the adhesion between the semiconductor layer and the first electrode can be further improved, and the operating voltage can be lowered.

Moreover, when the light generated in the active layer is in the near-ultraviolet wavelength band, the reflectance can be improved by including Al in the first electrode.

The Ag alloy constituting the first electrode may contain Pd.

* The work function of Pd is 5.1 eV. According to said structure, ohmic contact between a semiconductor layer can be easily formed because Pd which is a material with a large work function is contained in a 1st electrode.

The Ag alloy constituting the first electrode may have a Ge mass% concentration of 0.1 wt% or less and a Cu mass% concentration of 0.5 wt% or less.

According to the above configuration, a nitride semiconductor light emitting device with a low operating voltage can be realized while suppressing a decrease in reflectance to the maximum.

According to the nitride semiconductor light emitting device of the present invention, the operating voltage can be lowered while suppressing the light extraction efficiency from being lowered.

It is sectional drawing which shows typically the structure of one Embodiment of the nitride semiconductor light-emitting device. FIG. 3 is a part of a process cross-sectional view schematically showing a method for manufacturing a nitride semiconductor light emitting device. FIG. 3 is a part of a process cross-sectional view schematically showing a method for manufacturing a nitride semiconductor light emitting device. FIG. 3 is a part of a process cross-sectional view schematically showing a method for manufacturing a nitride semiconductor light emitting device. FIG. 3 is a part of a process cross-sectional view schematically showing a method for manufacturing a nitride semiconductor light emitting device. FIG. 3 is a part of a process cross-sectional view schematically showing a method for manufacturing a nitride semiconductor light emitting device. FIG. 3 is a part of a process cross-sectional view schematically showing a method for manufacturing a nitride semiconductor light emitting device. FIG. 3 is a part of a process cross-sectional view schematically showing a method for manufacturing a nitride semiconductor light emitting device. FIG. 3 is a part of a process cross-sectional view schematically showing a method for manufacturing a nitride semiconductor light emitting device. FIG. 3 is a part of a process cross-sectional view schematically showing a method for manufacturing a nitride semiconductor light emitting device. FIG. 3 is a part of a process cross-sectional view schematically showing a method for manufacturing a nitride semiconductor light emitting device. It is sectional drawing which shows typically the structure of the nitride semiconductor light-emitting device for verification. It is sectional drawing which shows typically the structure of the nitride semiconductor light-emitting device for verification. It is a graph which shows the current-voltage characteristic of the light emitting element shown to FIG. 3A. It is a graph which shows the current-voltage characteristic of the light emitting element shown to FIG. 3B. It is sectional drawing which shows typically the structure of the nitride semiconductor light-emitting device for verification. 6 is a graph comparing the current-voltage characteristics of the light emitting device shown in FIG. 1 and the light emitting device shown in FIG. 5. 6 is a photograph in the middle of manufacturing the light emitting device shown in FIG. 2 is a photograph in the middle of manufacturing the light emitting device shown in FIG. It is a table | surface which shows the relationship between the density | concentration of Cu mixed in a 1st electrode, the reflective characteristic of a 1st electrode, and the surface state of the 1st electrode after annealing. It is a table | surface which shows the density | concentration of Ge mixed with a 1st electrode, the operating voltage of a light emitting element, and the relationship of an optical output. 6 is a table comparing operating voltages in the case where the p-type contact layer is formed of GaN and the case of formation of AlGaN in both the light-emitting element shown in FIG. 1 and the light-emitting element shown in FIG. It is sectional drawing which shows typically the structure of another embodiment of the nitride semiconductor light-emitting device. 1 is a diagram schematically illustrating a configuration of a conventional light emitting device.

The nitride semiconductor light emitting device of the present invention will be described with reference to the drawings. In each figure, the dimensional ratio in the drawing does not necessarily match the actual dimensional ratio. In the following, the description “AlGaN” is synonymous with the description Al _m Ga _1-m N (0 <m <1), and the description of the composition ratio of Al and Ga is simply omitted. And it is not the meaning limited to the case where the composition ratio of Al and Ga is 1: 1. The same applies to the description “InGaN”.

[Constitution]
FIG. 1 is a cross-sectional view schematically showing a configuration of an embodiment of a nitride semiconductor light emitting device of the present invention. The nitride semiconductor light emitting device 1 shown in FIG. 1 includes a support substrate 3, a semiconductor layer 5, a first electrode 13, a second electrode 15, and a protective layer 17. Hereinafter, the nitride semiconductor light emitting device 1 is simply abbreviated as “light emitting device 1” as appropriate.

(Support substrate 3)
The support substrate 3 is composed of a conductive substrate such as CuW, W, or Mo, or a semiconductor substrate such as Si.

(Semiconductor layer 5)
In this embodiment, the semiconductor layer 5 is formed by sequentially stacking a p-type semiconductor layer 11, an active layer 9, and an n-type semiconductor layer 7 from the side close to the support substrate 3.

In this embodiment, the p-type semiconductor layer 11 is made of AlGaN doped with a p-type impurity such as Mg, Be, Zn, or C, for example.

The active layer 9 is formed of a semiconductor layer in which, for example, a light emitting layer made of InGaN and a barrier layer made of n-type AlGaN are periodically repeated. These layers may be undoped or p-type or n-type doped. The active layer 9 only needs to be configured by laminating layers made of at least two kinds of materials having different energy band gaps. The constituent material of the active layer 9 is appropriately selected according to the wavelength of light to be generated. In the present embodiment, it is assumed that the active layer 9 is made of a nitride semiconductor capable of generating light having a wavelength of 365 nm or more and 405 nm or less.

In the present embodiment, the n-type semiconductor layer 7 is made of AlGaN doped with an n-type impurity such as Si, Ge, S, Se, Sn, or Te. The n-type semiconductor layer 7 may be made of a material having a composition different from that of the p-type semiconductor layer 11.

(First electrode 13, second electrode 15)
The first electrode 13 is made of a conductive material exhibiting a high reflectance (for example, 75% or more, more preferably 90% or more) with respect to light emitted from the active layer 9. More specifically, it is made of an Ag alloy containing Ge and Cu. In the present embodiment, the first electrode 13 constitutes a p-side electrode.

The second electrode 15 is formed on the upper surface of the n-type semiconductor layer 7 and is made of, for example, Cr—Au. The second electrode 15 may be connected to a wire (not shown) made of, for example, Au or Cu. At this time, the second electrode 15 functions as a power supply terminal of the light emitting element 1 by connecting the other end of the wire to the power supply pattern of the package substrate. In the present embodiment, the second electrode 15 constitutes an n-side electrode.

When a voltage is applied between the first electrode 13 and the second electrode 15, a current flows in the active layer 9, and the active layer 9 emits light.

As described above, the first electrode 13 is made of a material that exhibits a high reflectance with respect to the light generated in the active layer 9. The light-emitting element 1 is assumed to extract light emitted from the active layer 9 upward (on the n-type semiconductor layer 7 side) in FIG. The first electrode 13 functions to increase light extraction efficiency by reflecting light emitted from the active layer 9 toward the support substrate 3 toward the n-type semiconductor layer 7.

(Conductive layer 20)
The conductive layer 20 is formed in the upper layer of the support substrate 3. In the present embodiment, the conductive layer 20 has a multilayer structure of a protective layer 23, a bonding layer 21, a bonding layer 19, and a protective layer 17.

The bonding layer 19 and the bonding layer 21 are made of, for example, Au—Sn, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like. As will be described later, the bonding layer 19 and the bonding layer 21 make the bonding layer 21 formed on the support substrate 3 and the bonding layer 19 formed on another substrate (a growth substrate 25 described later) face each other. Then, the two are bonded together. The bonding layer 19 and the bonding layer 21 may be integrated as a single layer.

In this embodiment, the protective layer 17 has a multilayer structure of Ni / Ti / Pt. Among these, the Ti / Pt layer is provided for the purpose of suppressing the material constituting the bonding layer (19, 21) from diffusing to the first electrode 13 side and reducing the reflectance of the first electrode 13. Yes. The Ni layer is provided for the purpose of suppressing the material contained in the Ti / Pt layer, particularly Ti, from diffusing to the first electrode 13 side and the reflectance of the first electrode 13 from decreasing. However, the protective layer 17 should just be comprised with the material which has a function which suppresses that the material which comprises a joining layer (19,21) diffuses at least, and should just contain at least one of Pt and Ti. .

The protective layer 23 is made of, for example, the same material as that of the protective layer 17, and is provided for the purpose of suppressing the material constituting the bonding layers (19, 21) from diffusing to the support substrate 3 side. However, the protective layer 23 may not necessarily be provided.

(Current blocking layer 14)
The light emitting element 1 includes a current blocking layer 14 on a partial upper surface of the conductive layer 20. In the present embodiment, the current blocking layer 14 is made of the same material as the first electrode 13, that is, an Ag alloy.

As shown in FIG. 1, the first electrode 13 and the current blocking layer 14 are both formed in contact with the p-type semiconductor layer 11. The first electrode 13 is in ohmic contact with the p-type semiconductor layer 11. On the other hand, the current blocking layer 14 is in Schottky contact with the p-type semiconductor layer 11, and the contact resistance with the p-type semiconductor layer 11 is higher than that of the first electrode 13.

The current blocking layer 14 is formed at a position facing the second electrode 15 in a direction orthogonal to the surface of the support substrate 3 (hereinafter referred to as “vertical direction” as an example). If a layer having a low contact resistance with the p-type semiconductor layer 11 is formed at a position facing the second electrode 15 in the vertical direction, when a voltage is applied to the light emitting element 1, the second in the vertical direction. Most of the current flows in a region facing the electrode 15. As a result, only a specific region of the active layer 9 emits light, and the light emission efficiency decreases. The current blocking layer 14 has a function of increasing the luminous efficiency of the active layer 9 by spreading the current flowing through the active layer 9 in a direction parallel to the surface of the support substrate 3 (hereinafter referred to as “horizontal direction” as an example). have.

Further, as in the present embodiment, the current blocking layer 14 is formed of a material having a high reflectance with respect to the light generated in the active layer 9, so that the light blocking layer 14 can be used for the same reason as the first electrode 13. The extraction efficiency can be improved.

(Insulating layer 24)
In the present embodiment, the light emitting element 1 includes an insulating layer 24 formed on a part of the upper surface of the current blocking layer 14. Insulating layer 24 is composed for example _{_{SiO 2, SiN, Zr 2 O}} 3, AlN, etc. Al ₂ O _3. The insulating layer 24 is provided for the purpose of functioning as an etching stopper during element isolation, as will be described later in the section of the manufacturing method.

Although not shown in FIG. 1, an insulating layer as a protective film may be formed on the side surface of the semiconductor layer 5. Note that the insulating layer as the protective film is preferably made of a light-transmitting material (for example, SiO ₂ ). Further, for the purpose of further increasing the light extraction efficiency, minute irregularities (mesa structure) may be formed on the upper surface of the n-type semiconductor layer 7.

According to the light-emitting element 1 shown in FIG. 1, the fact that light can be emitted at a lower operating voltage than conventional elements while suppressing the light extraction efficiency from being lowered is described after the description of the manufacturing method. It will be described later with reference to an example.

[Production method]
Next, an example of a method for manufacturing the light-emitting element 1 will be described with reference to process cross-sectional views schematically shown in FIGS. 2A to 2J. In addition, dimensions such as manufacturing conditions and film thickness described below are merely examples.

(Step S1)
As shown in FIG. 2A, a growth substrate 25 is prepared. As an example of the growth substrate 25, a sapphire substrate having a C-plane can be used.

As a preparation step, the growth substrate 25 is cleaned. As a more specific example of this cleaning, a growth substrate 25 is arranged in a processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and hydrogen having a flow rate of, for example, 10 slm is placed in the processing furnace. While flowing the gas, the temperature in the furnace is raised to, for example, 1150 ° C.

(Step S2)
As shown in FIG. 2B, an undoped layer 27, an n-type semiconductor layer 7, an active layer 9, and a p-type semiconductor layer 11 are sequentially formed on the growth substrate 25. This step S2 is performed by the following procedure, for example.

First, a low-temperature buffer layer made of GaN is formed on the upper surface of the growth substrate 25, and a base layer made of GaN is formed thereon. These low-temperature buffer layer and underlayer correspond to the undoped layer 27. A specific method for forming the undoped layer 27 is, for example, as follows.

First, the furnace pressure of the МОCVD apparatus is set to 100 kPa, and the furnace temperature is set to 480 ° C. Then, while flowing nitrogen gas and hydrogen gas with a flow rate of 5 slm respectively as carrier gas into the processing furnace, trimethylgallium (TMG) with a flow rate of 50 μmol / min and ammonia with a flow rate of 250,000 μmol / min are used as the raw material gas in the processing furnace. For 68 seconds. Thereby, a low-temperature buffer layer made of GaN having a thickness of 20 nm is formed on the surface of the growth substrate 25.

Next, the furnace temperature of the MOCVD apparatus is raised to 1150 ° C. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas in the processing furnace, TMG having a flow rate of 100 μmol / min and ammonia having a flow rate of 250,000 μmol / min are introduced into the processing furnace as source gases. Feed for 30 minutes. As a result, a base layer made of GaN having a thickness of 1.7 μm is formed on the surface of the low-temperature buffer layer.

Next, the n-type semiconductor layer 7 is formed on the undoped layer 27. A specific method for forming the n-type semiconductor layer 7 is, for example, as follows.

First, with the furnace temperature kept at 1150 ° C., the furnace pressure of the MOCVD apparatus is set to 30 kPa. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas into the processing furnace, TMG having a flow rate of 94 μmol / min, trimethylaluminum (TMA) having a flow rate of 6 μmol / min, Ammonia with a flow rate of 250,000 μmol / min and tetraethylsilane with a flow rate of 0.013 μmol / min are supplied into the treatment furnace for 60 minutes. Thereby, for example, an n-type semiconductor layer 7 having a composition of Al _0.06 Ga _0.94 N and a thickness of 2 μm is formed on the undoped layer 27.

After this, the supply of TMA is stopped, and other source gases are supplied for 6 seconds, thereby having a protective layer made of n-type GaN having a thickness of about 5 nm on the n-type AlGaN layer. An n-type semiconductor layer 7 may be realized.

In the above description, the case where Si is used as the n-type impurity contained in the n-type semiconductor layer 7 has been described. However, as the n-type impurity, Ge, S, Se, Sn, Te, or the like can be used in addition to Si. .

Next, an active layer 9 is formed on the n-type semiconductor layer 7. A specific method for forming the active layer 9 is, for example, as follows.

First, the furnace pressure of the MOCVD apparatus is set to 100 kPa, and the furnace temperature is set to 830 ° C. Then, while flowing nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 1 slm as a carrier gas in the processing furnace, TMG having a flow rate of 10 μmol / min, trimethylindium (TMI) having a flow rate of 12 μmol / min, and A step of supplying ammonia at a flow rate of 300,000 μmol / min into the processing furnace for 48 seconds is performed. Thereafter, TMG having a flow rate of 10 μmol / min, TMA having a flow rate of 1.6 μmol / min, tetraethylsilane having a flow rate of 0.002 μmol / min, and ammonia having a flow rate of 300,000 μmol / min are supplied into the processing furnace for 120 seconds. Hereinafter, by repeating these two steps, an active layer 9 in which a light-emitting layer made of InGaN having a thickness of 2 nm and a barrier layer made of n-type AlGaN having a thickness of 7 nm are stacked for 15 periods is formed into an n-type semiconductor layer. 7 is formed on the upper layer.

Next, the p-type semiconductor layer 11 is formed on the active layer 9. A specific method for forming the p-type semiconductor layer 11 is, for example, as follows.

Specifically, the furnace pressure of the MOCVD apparatus is maintained at 100 kPa, and the furnace temperature is raised to 1025 ° C. while nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 25 slm are supplied as carrier gases in the processing furnace. To do. Thereafter, as source gases, TMG with a flow rate of 35 μmol / min, TMA with a flow rate of 20 μmol / min, ammonia with a flow rate of 250,000 μmol / min, and biscyclopentadiene with a flow rate of 0.1 μmol / min for doping p-type impurities. Enilmagnesium (Cp ₂ Mg) is fed into the processing furnace for 60 seconds. Thus, a hole supply layer having a composition of Al _0.3 Ga _0.7 N having a thickness of 20 nm is formed on the surface of the active layer 9. Thereafter, by changing the flow rate of TMA to 4 μmol / min and supplying the source gas for 360 seconds, a hole supply layer having a composition of Al _0.13 Ga _0.87 N having a thickness of 120 nm is formed. A p-type semiconductor layer 11 is formed by these hole supply layers.

Note that a contact layer having a high p-type impurity concentration may be formed on the hole supply layer described above. In this case, specifically, the source gas is TMG having a flow rate of 17 μmol / min, TMA having a flow rate of 2 μmol / min, ammonia having a flow rate of 250,000 μmol / min, and a flow rate for doping p-type impurities of 0.2 μmol / min. Min biscyclopentadienyl magnesium (Cp ₂ Mg) is supplied into the processing furnace for 180 seconds. As a result, a p-AlGaN contact layer having a composition of Al _0.1 Ga _0.9 N having a thickness of 20 nm is formed on the surface of the active layer 9.

(Step S3)
An activation process is performed on the wafer obtained in step S2. As a specific example, an activation process is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal) apparatus.

(Step S4)
An insulating layer 24 is formed at a predetermined location on the upper surface of the p-type semiconductor layer 11 (see FIG. 2C).

More specifically, the insulating layer 24 is formed by depositing, for example, Al ₂ O ₃ with a thickness of about 100 nm on the upper surface of the p-type semiconductor layer 11 in a region serving as a boundary between adjacent elements by a sputtering method. . It should be noted that the material to be deposited may be an insulating material, and may be SiN or SiO _{2 in} addition to Al ₂ O ₃ . The film thickness of the insulating layer 24 may be set as appropriate.

(Step S5)
The first electrode 13 is formed in a predetermined region on the upper surface of the p-type semiconductor layer 11 (see FIG. 2C). A specific method for forming the first electrode 13 is, for example, as follows.

A material film made of an Ag alloy containing Ge and Cu is formed in a predetermined region on the upper surface of the p-type semiconductor layer 11. As an example, an Ag alloy having a thickness of about 200 nm is formed in a predetermined region on the upper surface of the p-type semiconductor layer 11 by a sputtering apparatus. In this embodiment, as an example, an Ag alloy containing 0.05% wt Ge and 0.3% wt Cu is formed as a film.

Thereafter, contact annealing is performed under a predetermined temperature condition in dry air or an inert gas atmosphere using an RTA apparatus or the like to form an ohmic contact between the Ag alloy and the p-type semiconductor layer 11. Thereby, the 1st electrode 13 comprised with Ag alloy is formed.

In addition, you may perform this step S5 before step S4.

(Step S6)
The current blocking layer 14 is formed on the region where the p-type semiconductor layer 11 is exposed and on the upper surface of the insulating layer 24 (see FIG. 2D).

As a more specific example, an Ag alloy film having a thickness of 200 nm is formed by a sputtering apparatus as in step S5. In this embodiment, the case where the same material film as that in step S5 is formed will be described, but the film forming material may be different.

And, annealing is performed at a lower temperature than step S5, or annealing is not performed. Thereby, Schottky contact is formed between the Ag alloy and the p-type semiconductor layer 11 formed in this step. Thereby, the current interruption layer 14 is formed.

(Step S7)
A protective layer 17 is formed on the entire surface so as to cover the upper surfaces of the first electrode 13 and the current blocking layer 14. Thereafter, the bonding layer 19 is formed on the upper surface of the protective layer 17 (see FIG. 2E). An example of a specific method is as follows.

First, the protective layer 17 is formed by depositing 100 nm of Ti and 200 nm of Pt for three periods using an electron beam evaporation apparatus (EB apparatus). After that, Ti having a thickness of 10 nm is deposited on the upper surface (Pt surface) of the protective layer 17, and then a bonding layer 19 is formed by depositing Au—Sn solder composed of Au 80% Sn20% to a thickness of 3 μm. To do.

(Step S8)
A protective layer 23 and a bonding layer 21 are formed on the upper surface of the support substrate 3 prepared separately from the growth substrate 25 by the same method as in step S7 (see FIG. 2F). As the support substrate 3, as described above, a conductive substrate such as CuW, W, and Mo, or a semiconductor substrate such as Si can be used. The protective layer 23 may not be formed.

(Step S9)
As shown in FIG. 2G, the bonding layer 19 formed on the upper layer of the growth substrate 25 and the bonding layer 21 formed on the upper layer of the support substrate 3 are bonded to bond the growth substrate 25 and the support substrate 3 together. Do. As a specific example, the bonding process is performed at a temperature of 280 ° C. and a pressure of 0.2 MPa.

In this step, the bonding layer 19 and the bonding layer 21 are melted and bonded to form a structure in which the support substrate 3 and the growth substrate 25 are bonded to the front and back surfaces. That is, the bonding layer 19 and the bonding layer 21 may be integrated after this step. And since the protective layer 23 and the protective layer 17 are formed in the stage before execution of this step S9, the spreading | diffusion of the structural material of a joining layer (19, 21) is suppressed.

(Step S10)
Next, the growth substrate 25 is peeled off (see FIG. 2H). More specifically, the laser is irradiated from the growth substrate 25 side with the growth substrate 25 facing upward and the support substrate 3 facing downward. Here, the laser to be irradiated is light having a wavelength that transmits the constituent material of the growth substrate 25 (sapphire in this embodiment) and is absorbed by the constituent material of the undoped layer 27 (GaN in this embodiment). As a result, the laser light is absorbed by the undoped layer 27, so that the interface between the growth substrate 25 and the undoped layer 27 is heated to decompose GaN, and the growth substrate 25 is peeled off.

Thereafter, GaN (undoped layer 27) remaining on the wafer is removed by wet etching using hydrochloric acid or the like, or dry etching using an ICP apparatus, and the n-type semiconductor layer 7 is exposed. In this step S10, the undoped layer 27 is removed, and the semiconductor layer 5 in which the p-type semiconductor layer 11, the active layer 9, and the n-type semiconductor layer 7 are stacked in this order from the support substrate 3 side remains ( (See FIG. 2I).

(Step S11)
Next, as shown in FIG. 2J, adjacent elements are separated from each other. Specifically, the semiconductor layer 5 is etched using the ICP apparatus until the upper surface of the insulating layer 24 is exposed in the boundary region with the adjacent element. At this time, as described above, the insulating layer 24 functions as an etching stopper.

In FIG. 2J, the side surface of the semiconductor layer 5 is illustrated so as to be inclined with respect to the vertical direction, but this is an example and is not intended to be limited to such a shape.

(Step S12)
Next, a predetermined region on the upper surface of the n-type semiconductor layer 7, more specifically, a part of the upper surface of the n-type semiconductor layer 7 that does not face the first electrode 13 in the vertical direction, that is, current blocking. The second electrode 15 is formed in a part of the region facing the layer 14 in the vertical direction. As an example of a specific method for forming the second electrode 15, after depositing Cr having a thickness of 100 nm and Au having a thickness of 3 μm, annealing is performed at 250 ° C. for about 1 minute in a nitrogen atmosphere.

(Step S13)
Next, the elements are separated from each other by, for example, a laser dicing apparatus, and the back surface of the support substrate 3 is joined to the package by, for example, Ag paste. Thereafter, wire bonding is performed on a partial region of the second electrode 15. The light emitting element 1 shown in FIG. 1 is manufactured through the above steps.

[Verification]
Hereinafter, according to the light emitting device 1 of the present embodiment, the point that the operating voltage can be lowered as compared with the conventional device will be described.

3A and 3B are cross-sectional views schematically showing a configuration of a light-emitting element created for verification, and each element has a so-called flip-chip structure. Note that in FIGS. 3A and 3B, the same reference numerals are given to components made of the same material as the light-emitting element 1 shown in FIG. 1.

The light-emitting element 40a for verification shown in FIG. 3A is an element manufactured by the following procedure.

First, the same steps as steps S1 to S3 described above are performed. Thereafter, the p-type semiconductor layer 11 and the active layer 9 in a partial region are etched to expose the n-type semiconductor layer 7. Thereafter, the first electrode 13 made of an Ag alloy containing Ge and Cu is formed on the upper surface of the p-type semiconductor layer 11 as in Step S5, and the second electrode is formed on the upper surface of the n-type semiconductor layer 7 as in Step S12. 15 is formed. And after forming the pad electrode 43 used as a current supply part with respect to each of the 1st electrode 13 and the 2nd electrode 15, the element substrate 41 in which the wiring pattern was formed, and the pad electrode 43 are connected by the bonding electrode 45 To do. Thereby, the light emitting element 40a shown in FIG. 3A is formed.

The verification light-emitting element 40b shown in FIG. 3B has the same configuration as the light-emitting element 40a except that a first electrode 50 made of pure Ag is formed instead of the first electrode 13 made of Ag alloy. is there.

FIG. 4A is a graph showing current-voltage characteristics of the light emitting element 40a shown in FIG. 3A. 4B is a graph showing current-voltage characteristics of the light emitting element 40b shown in FIG. 3B. According to FIGS. 4A and 4B, the flip chip type light emitting device includes a case where the first electrode 13 made of an Ag alloy containing Ge and Cu is provided, and a case where the first electrode 50 made of pure Ag is provided. It is confirmed that there is almost no difference in operating voltage.

FIG. 5 is a cross-sectional view schematically showing a configuration of a light-emitting element manufactured for verification. The light emitting element 40c shown in FIG. 5 is different from the light emitting element 1 of FIG. 1 in that both the first electrode 50 and the current blocking layer 51 are made of pure Ag.

FIG. 6 is a graph comparing the current-voltage characteristics of the light emitting element 40c of FIG. 5 and the light emitting element 1 of FIG. Unlike the results shown in FIGS. 4A and 4B, according to FIG. 6, the light-emitting element 1 in which the first electrode 13 is formed of an Ag alloy is lighter than the light-emitting element 40c in which the first electrode 50 is formed of pure Ag. It can be seen that the operating voltage is reduced as compared with FIG.

From the above results, comparing the case where the electrode for supplying current to the p-type semiconductor layer 11 is made of Ag alloy and the case where it is made of pure Ag, there is no difference in operating voltage in the flip chip type device. On the other hand, it can be seen that an effect of lowering the operating voltage can be obtained by forming the vertical element with an Ag alloy in the vertical type element. The reason for this is not clear at the present time, but the present inventor speculates as follows.

Ag constituting the first electrode 50 of the light emitting element 40c has a property of being easily aggregated by heating. Therefore, the first electrode 50 is heated by the annealing step (step S5) for securing ohmic contact with the p-type semiconductor layer 11, and Ag constituting the first electrode 50 is aggregated. Ball up phenomenon occurs in some areas. On the other hand, when the 1st electrode 13 is comprised with Ag alloy like the light emitting element 1, expression of this ball-up phenomenon is suppressed.

7A and 7B are photographs showing the surface state after heating with the first electrode (13, 50) formed. 7A corresponds to a photograph of the light emitting element 40c, and FIG. 7B corresponds to a photograph of the light emitting element 1. In the photograph of FIG. 7A, many black spots 60 appear on the surface, suggesting that the ball-up phenomenon of Ag has occurred. On the other hand, the spot of FIG. 7A hardly appears in the photograph of FIG. 7B.

By the way, sapphire used as the growth substrate 25 and each semiconductor layer (27, 7, 9, 11) have different lattice constants. Therefore, when the epitaxial growth process of each semiconductor layer is completed (see FIG. 2B), each semiconductor layer (27, 7, 9, 11) is actually grown in a state of being distorted with respect to the growth substrate 25. is doing. That is, the p-type semiconductor layer 11 positioned at the upper layer at this time is actually formed with the upper surface curved.

In the case of forming the light emitting element 1 and the light emitting element 40c, the first electrode (13, 50) and the protective layer 17 are formed on the upper surface of the p-type semiconductor layer 11 having the curved upper surface in this way, and then the bonding step ( Step S9) is performed. For this reason, in the bonding step, it is necessary to apply a predetermined pressure under a temperature condition in which the bonding layers (19, 21) can be melted. In particular, the first electrode (13, 50) is placed in a heating / pressurizing environment in a state of being sandwiched between the protective layer 17 made of a refractory metal and the p-type semiconductor layer 11.

By being placed in such an environment, in the light emitting element 40c, the adhesion between the first electrode 50 and the p-type semiconductor layer 11 where the ball-up phenomenon has occurred in some places is reduced, and the contact resistance is reduced. It is thought that it decreased. On the other hand, in the case of the light emitting element 1, since the first electrode 13 is made of an Ag alloy and the occurrence of the ball-up phenomenon is suppressed, the light emitting element 40c is still placed even in the above environment. It is considered that the adhesiveness with the p-type semiconductor layer 11 is higher than that of FIG. This consideration shows that there is no difference in operating voltage in a flip chip type structure that does not require a bonding process (FIGS. 4A and 4B), while a vertical structure includes a first electrode 13 made of an Ag alloy. In the light emitting device 1, the result that the operating voltage is lower than that of the light emitting device 40c including the first electrode 50 made of Ag (FIG. 6) is met.

As one of the reasons that the adhesion with the p-type semiconductor layer 11 is increased by providing the first electrode 13 made of an Ag alloy like the light emitting element 1, the present inventor has made Cu into the first electrode 13. I guess that it was mixed. As a result of improving the heat resistance by including Cu in Ag, it is considered that the phenomenon of Ag aggregation during heating is suppressed.

Incidentally, Cu has a lower reflectance with respect to light emitted from the active layer 9 than Ag. For this reason, when Cu is mixed excessively, there is a possibility that the light extraction efficiency is lowered. FIG. 8 is a table showing the relationship between the Cu concentration D1 mixed in the first electrode 13, the reflection characteristics of the first electrode 13, and the surface state of the first electrode 13 after annealing.

Specifically, the reflection characteristics are those in which an alloy of Ag and Cu is irradiated with light having a wavelength of 365 nm and the amount of light received as reflected light is 80% or more with respect to incident light. The evaluation was “B”. Also, regarding the surface condition, a photograph of the annealed Ag—Cu alloy was taken with a photograph, and the “B” evaluation was made with a high percentage of ball-up occurring, and it was confirmed that almost no ball-up was confirmed. The thing with the low ratio was made into "A" evaluation. Here, the ratio of the area occupied by the ball-up state area is 10% or more with respect to the area of the photographed Ag—Cu alloy, and it is determined that the ratio of the developed ball-up is high. did.

Compared with the case where Cu is not mixed at all in Ag, it is considered that the addition of even a small amount of Cu increases the heat resistance and suppresses the occurrence of the ball-up phenomenon, thereby contributing to a decrease in contact resistance. However, when the ratio of Cu contained in the Ag alloy is less than 0.1 wt% in weight%, it cannot be said that the occurrence of the ball-up phenomenon can be largely suppressed, and the effect of lowering the operating voltage of the light emitting element. Is not considered very large. Therefore, in order to significantly reduce the operating voltage of the light emitting element, it is preferable that the ratio of Cu contained in the Ag alloy constituting the first electrode 13 is 0.1 wt% or more by weight%.

On the other hand, if the ratio of Cu contained in the Ag alloy is mixed more than 0.5 wt% by weight%, the reflectance with respect to the light generated in the active layer 9 is lowered, so that the light extraction efficiency is lowered. I will let you. Therefore, from the viewpoint of suppressing a decrease in light extraction efficiency, the ratio of Cu contained in the Ag alloy constituting the first electrode 13 is preferably 0.5 wt% or less by weight%.

Cu is a material with a large work function compared to Ag. For this reason, it is considered that mixing Cu with Ag makes it easy to ensure good contact with the p-type semiconductor layer 11. That is, by mixing Cu with Ag, not only the heat resistance of Ag is improved, but also the work function of the first electrode 13 itself is increased, thereby contributing to the reduction of the contact resistance with the p-type semiconductor layer 11. It is thought that there is. Furthermore, by mixing Cu with Ag, the oxidation resistance is enhanced and the Ag is suppressed from being oxidized, so that it is considered that there is also an effect of suppressing a decrease in reflectance.

Incidentally, Ag is known not only to oxidize but also to easily sulfidize. Then, when oxidation or sulfidation occurs, Ag changes to another substance and the reflectance decreases. Therefore, the first electrode 13 provided in the light emitting element 1 is mixed with Ge in Ag for the purpose of improving the sulfidation resistance. Since this Ge is a substance having a work function larger than that of Ag, similarly to Cu, by mixing Ge, the contact resistance with the p-type semiconductor layer 11 can be reduced while suppressing a decrease in reflectance. It is presumed that

FIG. 9 is a table showing the relationship between the Ge concentration D2 mixed in the first electrode 13, the operating voltage of the light-emitting element 1, and the light output. “Voltage” in FIG. 9 represents an operating voltage required to flow a current of 1 A to the light emitting element 1. Further, “output” in FIG. 9 refers to the light output taken out when 1 A is supplied to the light emitting element 1 and taken out when 1 A is supplied to the light emitting element 40 c having the first electrode 50 made of pure Ag. This is expressed as a relative value when the output light output is 1.

FIG. 9 shows that the operating voltage can be reduced as the concentration of Ge mixed in the first electrode 13 is increased within the range where the weight% concentration of Ge is 0.1% wt or less. This suggests that since Ge is a material having a large work function, the first electrode 13 can easily secure a good contact with the p-type semiconductor layer 11 by mixing Ge. is there. That is, from the viewpoint of improving contactability, it can be said that it is preferable to mix Ge in the first electrode 13 even in a small amount.

On the other hand, according to FIG. 9, when Ge at a concentration by weight exceeds 0.1% wt or less, the operating voltage of the light-emitting element 1 increases as compared with the case of 0.01% wt to 0.1% wt. is doing. This is presumably due to the fact that the specific resistance of the first electrode 13 itself has increased because Ge is a material having a large specific resistance.

Also, when the weight percentage of Ge exceeds 0.1% wt or less, the light output also decreases. This is considered to be caused by the fact that the reflectivity was lowered due to the large amount of Ge contained in the first electrode 13.

Based on the above, from the viewpoint of reducing the operating voltage while suppressing a decrease in light extraction efficiency of the light-emitting element 1, the concentration of Ge mixed in the first electrode 13 is 0.1 wt% or less by weight%. It can be said that it is preferable.

When the concentration of Ge mixed in the first electrode 13 is 0.1 wt% or less by weight%, the same result as FIG. 8 is obtained when the concentration of Cu mixed in the first electrode 13 is changed. Was confirmed. Further, when the concentration of Cu mixed in the first electrode 13 is 0.5 wt% or less by weight%, the same result as FIG. 9 is obtained when the concentration of Ge mixed in the first electrode 13 is changed. Was confirmed. Therefore, the light-emitting element 1 is configured to include the first electrode 13 made of an Ag alloy containing Cu and Ge, the Cu concentration contained in the Ag alloy is 0.5 wt% or less by weight, and the Ge concentration is weight. By setting the percentage to 0.1 wt% or less, the operating voltage can be lowered while maintaining high light extraction efficiency. Furthermore, the light extraction efficiency is improved by setting the Cu concentration contained in the Ag alloy to 0.1 wt% or more and 0.5 wt% or less in terms of wt% and the Ge concentration being 0.01 wt% or more and 0.1 wt% or less in terms of wt%. The effect of improving and the effect of reducing the operating voltage can be enhanced.

FIG. 10 shows a case where a region in contact with the first electrode (13, 50), that is, a p-type contact layer is formed of GaN as the p-type semiconductor layer 11 in both the light-emitting element 1 and the light-emitting element 40c. AlGaN (where the Al _0.1 Ga _0.9 N) and a case formed by a table comparing the operating voltage. FIG. 10 shows an operating voltage necessary for supplying a current of 1 A to the light emitting element (1, 40c).

The light-emitting element 1 used for this verification was an element manufactured through steps S1 to S13 described above. In addition, as for the light emitting element 40c, an element produced by the same procedure as that of the light emitting element 1 was adopted except that pure Ag was formed in place of the Ag alloy in Steps S5 and S6.

Since AlGaN has a higher band gap energy than GaN, it is expected that the hole concentration will be lower and the operating voltage will be higher. For this reason, in the case of manufacturing a light emitting element having a wavelength band of 365 nm or more and 405 nm or less (for example, near-ultraviolet light), GaN is conventionally used as the p-type contact layer.

However, according to FIG. 10, according to the light emitting device 1 including the first electrode 13 made of an Ag alloy, the p-type contact layer is made of AlGaN, but the operating voltage is almost the same as that of the case of being made of GaN. Is confirmed to be realized. On the other hand, in the case of the light emitting element 40c including the first electrode 50 made of pure Ag, the operating voltage is higher when the p-type contact layer is made of AlGaN than when it is made of GaN. . As described above, since it is difficult to achieve a high hole concentration with AlGaN, it is considered that the contact resistance is higher than that with GaN.

As a result of the above verification, according to the light-emitting element 1 in which the first electrode 13 is made of an Ag alloy containing Cu and Ge, compared to the light-emitting element 40 c in which the first electrode 50 is made of pure Ag, a p-type semiconductor. It can be seen that the contact resistance with the layer 11 can be reduced and a low operating voltage can be realized. In addition, by setting the mixed Cu and Ge to a concentration within a predetermined range, the first electrode 13 made of an Ag alloy can also achieve a reflectance equivalent to or higher than that of the Ag electrode.

In addition, Ge has a property which has a sulfidation resistance. For this reason, by mixing Ge in the 1st electrode 13, the effect which suppresses that a reflectance falls by Ag sulfidation with use is also acquired. According to FIG. 9, the light emitting element 1 including the first electrode 13 having a Ge concentration of 0.1 wt% or less has the same light output as the light emitting element 40 c including the first electrode 50 made of pure Ag. As shown, this is due to the supply of 1A in a short time. That is, when light is emitted continuously, the reflectance of the first electrode 50 decreases in the light emitting element 40c due to the sulfurization of Ag over time, while the first electrode 13 included in the light emitting element 1 Since the sulfidity is enhanced, the rate of decrease in reflectance is slower than that of the light emitting element 40c. As a result, it is assumed that the light output of the light emitting element 40c is lower than the light output of the light emitting element 1 with the passage of time.

[Another embodiment]
Hereinafter, another embodiment will be described.

<1> As in the light emitting element 1a shown in FIG. 11, a configuration in which the insulating layer 24 is provided in the place without including the current blocking layer 14 may be adopted. However, the light-emitting element 1 including the current blocking layer 14 made of a highly reflective material can further increase the light extraction efficiency than the light-emitting element 1a.

In the light emitting device 1 shown in FIG. 1, the current blocking layer 14 may be made of pure Ag. Since this region does not have a problem of contact with the p-type semiconductor layer 11, the operating voltage can be lowered similarly to the light-emitting element 1 even if it is composed of pure Ag. However, in the case of pure Ag, oxidation or sulfidation is likely to occur, and this may reduce the reflectance. Therefore, the current blocking layer 14 is also made of an Ag alloy, so that higher light extraction efficiency is realized. The

<2> As shown in FIG. 10, even when the p-type contact layer is made of GaN, the light-emitting element 1 can achieve an operating voltage lower than that of the light-emitting element 40c. For this reason, the p-type contact layer of the p-type semiconductor layer 11 can achieve a lower operating voltage than the conventional one even in the light-emitting element 1 made of GaN.

<3> In the embodiment described above, the first electrode 13 is made of an alloy in which Ge and Cu are mixed in Ag. In addition to this, as a constituent material of the first electrode 13, a small amount of Pd, which is a material having a large work function, may be mixed in order to further reduce the operating voltage. In addition, as a constituent material of the first electrode 13, a small amount of Al which is a material exhibiting a high reflectance with respect to light in the near ultraviolet region may be mixed in order to improve the reflectance. In addition, since the effect which suppresses the ball up of Ag is also expressed by mixing Al with the 1st electrode 13, the effect which further reduces operating voltage is acquired.

In the step of forming the first electrode 13 (step S5), a Ni thin film having a thickness of about several nm may be formed on the upper surface of the Ag alloy. By setting it as such a structure, the effect which suppresses the ball up of Ag can further be heightened.

<4> In the embodiment described above, the n-type semiconductor layer 7 has been described as being composed of AlGaN. However, the present invention is not limited to AlGaN, and is composed of a nitride semiconductor containing Al and Ga, such as AlInGaN. It does not matter. The same applies to the p-type semiconductor layer 11.

In the present invention, when the wavelength of light emitted from the active layer 9 is 365 nm or more and 405 nm or less, the n-type semiconductor layer 7 or the p-type semiconductor layer 11 includes a thin GaN layer. It is not intended to be excluded from the scope of rights.

<5> In the above-described embodiment, the case where the active layer 9 is formed of a nitride semiconductor capable of generating light having a wavelength of 365 nm to 405 nm is described. However, the active layer 9 is formed of a material capable of generating light of other wavelengths. It does not matter if it is

DESCRIPTION OF

SYMBOLS

1,1a: Nitride semiconductor light-emitting device 3: Support substrate 5: Semiconductor layer 7: N-type semiconductor layer 9: Active layer 11: P-type semiconductor layer 13: First electrode 14: Current blocking layer 15: Second electrode 17: Protective layer 19: bonding layer 21: bonding layer 23: protective layer 24: insulating layer 25: growth substrate 27:

undoped layer

40a, 40b, 40c: semiconductor light emitting device for verification 41: device substrate 43: pad electrode 45: bonding electrode 50: First electrode made of Ag 60: Spot (ball up)
90: Conventional light emitting device 91: Support substrate 92: Conductive layer 93: Reflective film 94: Insulating layer 95: Reflective electrode 96: P-type semiconductor layer 97: Active layer 98: N-type semiconductor layer 99: Semiconductor layer 100: N side electrode

Claims

A support substrate;
An n-type semiconductor layer, a p-type semiconductor layer, and an active layer sandwiched between the n-type semiconductor layer and the p-type semiconductor layer in a direction perpendicular to the surface of the support substrate; Including a semiconductor layer;
Of the surface of the semiconductor layer, a first electrode formed on the surface near the support substrate;
A second electrode formed on the surface of the semiconductor layer opposite to the side on which the first electrode is formed;
A conductive protective layer formed on the surface of the first electrode opposite to the surface on which the semiconductor layer is formed;
The semiconductor layer is made of a nitride semiconductor,
The protective layer includes a metal material having a melting point higher than Ag,
The first electrode is composed of an Ag alloy containing Ge and Cu.
Of the surface of the protective layer, having a bonding layer formed on the surface opposite to the side on which the first electrode is formed,
The nitride semiconductor light emitting element according to claim 1, wherein the protective layer includes at least one of Pt and Ti.
The nitride semiconductor light emitting element according to claim 1 or 2, wherein the p-type semiconductor layer is in contact with the first electrode.
The n-type semiconductor layer and the p-type semiconductor layer are both composed of a nitride semiconductor containing Al and Ga.
4. The nitride semiconductor light emitting device according to claim 3, wherein the active layer is made of a nitride semiconductor capable of generating light having a wavelength of 365 nm or more and 405 nm or less.
The nitride semiconductor light emitting element according to any one of claims 1 to 4, wherein the Ag alloy constituting the first electrode contains Al.
6. The nitride semiconductor light emitting device according to claim 1, wherein the Ag alloy constituting the first electrode contains Pd.
7. The Ag alloy constituting the first electrode has a Ge mass% concentration of 0.1 wt% or less and a Cu mass% concentration of 0.5 wt% or less. 2. The nitride semiconductor light emitting device according to claim 1.