TWI700389B - 針對側壁孔隙密封及通孔清潔度的互聯整合 - Google Patents

針對側壁孔隙密封及通孔清潔度的互聯整合 Download PDF

Info

Publication number
TWI700389B
TWI700389B TW105119681A TW105119681A TWI700389B TW I700389 B TWI700389 B TW I700389B TW 105119681 A TW105119681 A TW 105119681A TW 105119681 A TW105119681 A TW 105119681A TW I700389 B TWI700389 B TW I700389B
Authority
TW
Taiwan
Prior art keywords
substrate
pore sealing
layer
exposing
porous low
Prior art date
Application number
TW105119681A
Other languages
English (en)
Other versions
TW201706448A (zh
Inventor
任河
美荷Ｂ 那克
迪尼斯 帕奇
普力楊卡 達許
巴斯卡 古莫
亞歷山卓Ｔ 狄摩斯
Original Assignee
美商應用材料股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商應用材料股份有限公司 filed Critical 美商應用材料股份有限公司
Publication of TW201706448A publication Critical patent/TW201706448A/zh
Application granted granted Critical
Publication of TWI700389B publication Critical patent/TWI700389B/zh

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/36—Carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/48—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
    • C23C16/482—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation using incoherent light, UV to IR, e.g. lamps
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02359—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the surface groups of the insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

提供了一種用於密封多孔低k介電膜的方法。該方法包含以下步驟：將基板曝露於UV輻射和第一反應氣體，其中基板具有限定在基板中的開口特徵，開口特徵係由多孔低k介電層和導電材料所界定，其中多孔低k介電層是含矽和碳材料且使用UV輔助光化學氣相沉積而在多孔低k介電層的曝露表面上選擇性地形成孔隙密封層在開口特徵中。

Description

針對側壁孔隙密封及通孔清潔度的互聯整合
於此所述的實施例大體涉及低k介電膜的處理。更具體地，於此所述的實施例關於用於密封多孔低k介電膜的製程。
隨著裝置規模持續，在半導體製造中之介電膜的介電常數（k）不斷地下降。最大限度地減少對低介電常數（低k）膜的整合損害是使特徵尺寸持續降低的一個因素。然而，由於特徵尺寸縮小，介電膜的電阻電容和可靠性之改良成為重要的挑戰。
包括(例如)摻碳的氧化物（CDO）之多孔低k介電膜在通過管線的後端（BEOL）的集成之後會由於在曝露孔隙中的污染(這導致較大的電阻-電容（RC）延遲)而遭受顯著的損害。例如，金屬和金屬前驅物傾向擴散到多孔低k介電膜的孔隙中。為維持多孔低k介電膜的完整性，並盡量減少多孔低k介電膜的介電常數的可靠性劣化，多孔低k介電膜通常在隨後的金屬化製成之前被密封。然而，目前的密封製程通常會導致增加的接觸電阻。
因此，存在有減輕對多孔低k介電膜的損壞，同時也降低接觸電阻之方法的需求。
於此所述的實施例大體關於低k介電膜的處理。更具體地，於此所述的實施例關於用於密封多孔低k介電膜的製程。在一個實施例中，提供了一種用於密封多孔低k介電膜的方法。該方法包含以下步驟：將基板曝露於UV輻射和第一反應氣體，其中基板具有限定在基板中的開口特徵，開口特徵係由多孔低k介電層和導電材料所界定，其中多孔低k介電層是含矽和碳材料；及使用UV輔助光化學氣相沉積而選擇性在多孔低k介電層的曝露表面上形成孔隙密封層在開口特徵中。
在另一個實施例中，提供了一種用於密封多孔低k介電膜的方法。該方法包含以下步驟：將基板曝露於UV輻射和含氮前驅物，其中基板具有限定在基板中的溝槽和通孔，溝槽和通孔係由多孔低k介電層和導電材料所界定，其中多孔低k介電層是含矽和碳材料；使用UV輔助光化學氣相沉積而選擇性地在通孔中之多孔低k介電層的曝露表面上形成孔隙密封層，並在通孔中之曝露的導電材料上形成孔隙密封殘餘物；及將基板曝露於後沉積處理製程，以從通孔的導電材料移除孔隙密封殘餘物。
在又一個實施例中，提供了一種用於密封多孔低k介電膜的方法。該方法包含以下步驟：將基板曝露於UV輻射和含氮前驅物，其中基板具有限定在基板中的溝槽和通孔，溝槽和通孔係由多孔低k介電層和導電材料所界定，其中多孔低k介電層是含矽和碳材料；使用UV輔助光化學氣相沉積而選擇性地在通孔中之多孔低k介電層的曝露表面上形成孔隙密封層，並在通孔中之曝露的導電材料上形成孔隙密封殘餘物；及將基板曝露於後沉積處理製程，以從通孔的導電材料移除孔隙密封殘餘物，其中孔隙密封層的沉積率係大於孔隙密封殘餘物的沉積率。
以下的說明書描述了用於密封多孔低k介電膜的製程。某些細節係在以下的實施方式中和在第1-3圖中提出，以提供對本說明書的各種實施例的通盤了解。描述通常與低k介電膜的處理相關聯的已知結構和系統之其他細節係未在以下的說明書中提出，以避免不必要地混淆各種實施例的說明。
在圖式中所示的許多細節、尺寸、角度和其它特徵係僅用於說明特定的實施例。因此，其他的實施例可具有其它的細節、部件、尺寸、角度和特徵，而不背離本說明書的精神或範圍。此外，本說明書之進一步的實施例可被實施而無需以下所述的一些細節。
因為特徵尺寸的減小，電容規模變得更具挑戰性。低介電常數膜(如，低於2.4的k值)正被考慮，以滿足減少的特徵尺寸之需求。這些低k材料通常具有高孔隙率，高孔隙率在金屬化之前需要密封，以防止金屬擴散並進入多孔低k材料中，並導致可靠性的劣化。合適的孔隙密封製程通常包括側壁鈍化以及清潔通孔的底部接觸。傳統的物理密封方式包括共形介電層的沉積。然而，儘管共形介電層有助於以物理膜而鈍化側壁，在通孔之底部處的物理膜的沉積增加了確保通孔接觸的難度。
其它的傳統方式包括基於熱/電漿處理多孔低k側壁。這些基於熱/電漿的處理緻密了多孔低k側壁，或以分子(孔隙填充)填充側壁的孔隙。然而，這些基於熱/電漿的處理通常損壞了多孔低k材料，導致多孔低k材料之介電常數的增加，這違背了使用低k膜的目的。於此所述的實施例引進了用以確保側壁孔隙的密封及通孔清潔度兩者達到對先進的多孔低k膜之孔隙密封之整合需求的方法。
於此所述的實施例引進了整合選項，使孔隙密封具有最小的通孔阻抗(通孔接觸)損失。該方式包括達成上述目標的多個製程。首先，實施基於紫外線(UV)的密封製程。在寬頻UV能量的存在中使用矽-碳-氮基的前驅物。由於多孔低k膜和導電材料的不同表面活化能量，孔隙密封膜的沉積速率在在多孔低k膜的表面處較高，且在通孔之底部處的導電材料的表面處較低。通常的操作狀態包括200-3000瓦的UV光功率、具有100mTorr至10Torr的範圍內的腔室壓力的100-2000sccm之前驅物流動。不受理論限制，但應認為UV光優先地破壞配位鍵結，並將矽-碳-氮基的膜附著在多孔低k表面上，並最小化在導電材料上之孔隙密封材料的沉積。
在孔隙密封材料的沉積之後，基於UV或熱的處理可在用於進一步沉積之製備中被用以改善表面鍵結。例如，基於NH3的UV處理可以具有200-1,000瓦UV光功率和50-800 sccm的NH3 流率之操作狀態而被用以製備具有-NH繫鏈鍵結的孔隙密封層之表面。前驅物浸泡和處理可為循環的用於孔隙密封層的持續生成。因此，含矽-碳-氮層被沉積在多孔低k表面上，密封多孔低k表面的奈米孔隙，同時在通孔之底部上之矽-碳-氮基的殘餘物比沉積在側壁上之矽-碳-氮基的層薄。
其次，可實施後密封層沉積殘餘物移除製程。為確保通孔歐姆接觸(ohmic contact)，可實施第二製程以移除在通孔之底部處的殘餘物。作為一個例子，輕度濕式清潔製程可被用以移除在通孔之底部上沉積的含矽-碳-氮基的殘餘物層而不減少在通孔之側壁上沉積的孔隙密封層。濕式清潔化學作用可含有氧化劑(諸如過氧化物)和經調節的pH值，用於改善溶解。作為另一個例子，可使用剝離方法以清潔通孔底部，以移除氧化物殘餘物。該製程可為基於乙酸清潔的氧化還原反應。作為又一個例子，基於偏壓的處理製程可被加入，以蝕刻/濺射通孔底部殘餘物。偏壓功率可以低（20-300瓦）範圍而施加，以避免在通孔的底部處的低k損壞。
第1圖是描繪形成根據於此所述之一些實施例的互連結構之方法100的流程圖。方法100在製造製程期間被實施於工件上。方法100可被用以形成在第2A-2E圖(第2A-2E圖係討論於下)中所描繪的製造階段順序中所描繪之雙鑲嵌結構。第2A-2E圖描繪在基板210上形成的雙鑲嵌結構之製造製程的剖面概要圖。 雖然第1圖係參照雙鑲嵌製程而說明，應理解參照雙鑲嵌製程是僅說明性的，且在第1圖中所述的製程適用於欲用以在多孔低k膜之上形成孔隙密封層的任何製程。
在方塊110處，提供具有在多孔低K介電層中形成之開口特徵的基板。開口特徵具有曝露的多孔低k表面和曝露的導電表面。開口特徵可包括溝槽、通孔、孔、開口、線等以及它們的組合。多孔低k介電層可為具有低於約3之k值的任何傳統的多孔、低k、矽基介電層。在一個實施例中，多孔低k介電層是有機矽酸鹽玻璃（OSG，如SiCOH），有機矽酸鹽玻璃是包含碳原子和氫原子之氧化矽。多孔低k層可具有直徑在約0.5奈米至約20奈米範圍中的微孔隙。曝露的導電表面可以是任何的金屬材料。在一個實施例中，金屬材料可以選自以下金屬所組成的群組：銅（Cu）、鈷（Co）、鎢（W）、鎳（Ni）、金（Au）、鋁（Al）和它們的組合。
具有開口特徵的基板可類似於在第2A-2E圖中所描繪的基板210。基板210具有經圖案化的膜堆疊250形成於基板210上。基板210可包括半導體基板，且可包括形成在基板210中或基板210上之完全或部分形成的層及/或裝置。例如，在一些實施例中，且如第2A圖中描繪，基板可具有設置在金屬互連結構214A、214B（統稱214）的頂部上之低k介電阻障層212，金屬互連結構214A、214B（統稱214）形成在低k介電層216中。低k介電阻障層212可包含任何合適的材料層，諸如氮化矽（SiN）、碳化矽（SiC）、氮摻雜碳化矽（SiNC）、碳氮化矽（SiCN）、矽碳氧化物（SiCO）、氧和氮摻雜碳化矽（SiONC）或類似物。此碳化矽基材料的一個例子是BLOKTM（阻障低k）膜，可由加州聖克拉拉市的應用材料公司所取得。金屬互連結構214可包含導電材料，諸如金屬，例如銅（Cu）、鈷（Co）、鎢（W）、鎳（Ni）、金（Au）、鋁（Al）或類似物。金屬互連結構214可具有上表面208A、208B（統稱208），上表面208A、208B（統稱208）係與低k介電層216的上表面實質地共面或齊平。低k介電層216可為具有介電常數低於二氧化矽（SiCO2 ）的介電常數(為約3.9)之任何有機的、低ķ介電材料。用於低k介電層216的合適材料包括摻雜碳的氧化物（CDO）、有機矽酸鹽玻璃（OSG）、未摻雜的矽玻璃（USG），諸如氧化矽或TEOS、硼-矽酸鹽玻璃（BSG）、磷矽酸鹽玻璃（PSG）、硼-磷矽酸鹽玻璃（BPSG）和它們的組合。
在一個實施例中，經圖案化的膜堆疊250包含低k介電層218和一或多個頂層或遮罩層232、234設置在經圖案化的膜堆疊250上。低k介電層218可被沉積在基板210的頂部上（如，當低k介電阻障層212存在時，在低k介電阻障層212的頂部上，或可能存在於基板210上的任何其它層的頂部上）。低k介電層218可被設置在低k介電阻障層212上。低k介電層218可選自與低k介電層216相同的材料。低k介電層216、218可如於此所述是多孔的。一或多個遮罩層232和234可各自單獨地為選自由以下所組成的群組之介電層：氧化物層、氮化物層、金屬層、耐熱金屬氮化物層、氧化物和氮化物的複合層、夾著氮化物層之至少兩個或更多個氧化物層，以及它們的組合等等。示例性的耐火金屬氮化物層是選自由以下所組成的群組：氮化鈦、氮化鉭及氮化鎢。示例性的金屬層包括鈦和鎢。
低k介電層218可為具有介電常數少於二氧化矽(SiO2)的介電常數(為約3.9)之任何有機的、低ķ介電材料。例如，有機材料可為摻雜碳的氧化物(CDO)(諸如Black Diamond或Black Diamond II，可由應用材料公司取得)、有機矽酸鹽玻璃(OSG)材料、基於聚合物的低k介電材料(諸如SiLK®、可由Dow Chemical Company取得)、有機聚合物(諸如FLARETM，橋接聚亞芳基醚可由Honeywell Advanced Microelectronic Materials取得)，或類似物。在於此所描繪的示例性實施例中，低k介電層218為有機矽酸鹽玻璃(OSG)層。在於此所描繪的另一個示例性實施例中，低k介電層218是摻雜碳的氧化物。在一個實施例中，低k介電層218具有在約300埃至約1500埃之間，諸如約400埃到約1200埃之間，例如約1000埃的厚度。在一個實施例中，遮罩層232是富矽氧化物層或SiON層，且遮罩層234是含鈦層（如，氮化鈦層或鈦層）。
在第2A圖中所描繪的實施例中，工件200已預先經過幾個製程，包括沉積、蝕刻和圖案化製程，其中為簡便起見，刪除這些製程的描述。膜堆疊被圖案化，以形成如第2A圖中所示之經圖案化的膜堆疊250。 經圖案化的膜堆疊250可利用對本領域中具有通常知識者已知的一系列製程而被圖案化，以形成開口特徵260在經圖案化的膜堆疊250中。開口特徵260通常形成側壁220和互連結構214之上表面208的曝露部分。於此所述的開口特徵260可包括溝槽、通孔、開口、孔、線等等以及它們的組合。開口特徵260可使用包括製程氣體或製程氣體混合物的電漿蝕刻製程而形成，製程氣體或製程氣體混合物包含碳氟化合物氣體、含氮氣體和惰性氣體。當於此使用時，片語“製程氣體”和“製程氣體混合物”是可互換的，且可包含一或多種氣體。任選地，還可提供氫氟碳化物氣體。在形成開口特徵260的期間，經圖案化的膜堆疊250之曝露表面可能被損壞。可實施各種修復製程以修復對經圖案化膜堆疊250的曝露表面的損害。
在方塊120處，開口特徵之曝露的介電和導電表面係曝露於預沉積UV處理製程。開口特徵可為開口特徵260。曝露表面可包括側壁220和曝露的導電表面上，例如，在開口特徵的底部處之互連結構214的上表面208。UV處理製程可在密封層被沉積的腔室中，或在不同的腔室中實施。在一個實施例中，UV處理製程是在負載鎖定腔室中實施，負載鎖定腔室是在與在方塊130處，密封層被沉積的處理腔室之相同的主要框架中。
UV輔助處理製程可包括將反應氣體流入具有曝露的介電和導電表面之基板被設置在其中的腔室中。 UV能量藉由接通一或多個UV燈而被引導到曝露的介電和導電表面。腔室壓力的範圍可從約6 Torr至約200 Torr（如，從約10 Torr至約50 Torr；從約20 Torr至約30 Torr）。UV功率的範圍可從約40％至約100％（如，從約50％至約100％；從約60％至約90％；從約70％至約80％）。反應氣體可具有流率的範圍為從約20 sccm到約2000 sccm（如，從約50 sccm至約800 sccm；從約100 sccm至約500 sccm）。反應氣體的例子包括NH3 、H2 、O2 、N2 O、CO2 或它們的組合。在一個實施例中，反應氣體是NH3 。諸如Ar或He之惰性氣體也可以範圍為從約20 sccm到約2000 sccm（如，從約50 sccm至約800 sccm；從約100 sccm至約500 sccm）的流率被引入到腔室中。處理時間的範圍可為從約10秒至約600秒（如，從約60秒至約300秒；從約120秒至約200秒）。
在負載鎖定腔室中之方塊120的UV輔助處理製程可包括將反應氣體流入負載鎖定腔室中，具有多孔低k介電膜設置在其上的基板係設置在該負載鎖定腔室中。UV能量藉由接通一或多個UV燈而被引導到密封層。負載鎖定腔室之壓力的範圍可從約0.07 Torr至約20 Torr（如，從約1 Torr至約10 Torr）。UV功率的範圍可從約40％至約100％（如，50％到100％；60％到90％；70％至80％）。反應氣體可具有的流率範圍為從約20 sccm到約2000 sccm（如，約50 sccm至約800 sccm）。基板溫度可為在攝氏200度和攝氏400度之間。反應氣體的例子包括NH3 、H2 、O2 、N2 O、CO2 或它們的組合。在一個實施例中，反應氣體是NH3 。諸如Ar或He之惰性氣體也可以範圍為從約20 sccm到約2000 sccm（如，從約50 sccm至約800 sccm；從約100 sccm至約500 sccm）的流率被引入到腔室中。處理時間的範圍可為從約10秒至約600秒（如，從約60秒至約300秒；從約120秒至約200秒）。
在一些實施例中，方塊120的UV輔助處理製程可以電漿處理取代。電漿處理可在負載鎖定腔室中實施。電漿處理可為遠端電漿處理。電漿通常由合適的處理氣體所產生，例如氨、氫或它們的組合。電漿處理可包括將電漿和載氣流入負載鎖定腔室中，具有多孔低k介電膜設置在其上的基板係設置於該負載鎖定腔室中。諸如氨、氫、氮、氬、氦或其組合的載氣可被引入到具有電漿的負載鎖定腔室中。負載鎖定腔室的壓力的範圍可從約500 mTorr至約20 Torr（如，從約1 Torr至約10 Torr）。遠端電漿功率的範圍可從約200瓦至約5000瓦（如，從約500瓦至約1000瓦）。載氣可具有流率的範圍從約20 sccm到約2000 sccm（如，約50 sccm至約800 sccm）。處理時間的範圍可從約5秒至約120秒。
方塊120的處理製程可在與方塊130的UV輔助沉積製程相同的腔室中實施。不受理論的限制，但應理解曝露的介電和導電表面之UV輔助處理製程相對於曝露的介電表面，增加了曝露的導電表面之疏水性。此增加的導電表面之疏水性導致了在方塊130處之隨後沉積的孔隙密封層在曝露的導電表面上之減少的沉積。
在方塊130處，孔隙密封層係形成在開口特徵的曝露的多孔低k介電層的表面上。孔隙密封層係相對於開口特徵之曝露的導電表面而選擇性地形成在曝露的多孔低k介電表面上。在方塊130的製程中之沉積孔隙密封層期間，孔隙密封殘餘物可形成在開口特徵之曝露的導電表面上。孔隙密封殘餘物可為非共形的孔隙密封層。孔隙密封層係以相較於在導電表面上所形成的孔隙密封殘餘物之沉積速率更大的沉積速率而在多孔低k介電層之上方形成。孔隙密封層比孔隙密封殘餘物更厚。孔隙密封層可使用紫外線（UV）輔助光化學氣相沉積而沉積於多孔低k介電層上。UV輔助光化學氣相沉積可在多孔低k介電膜被沉積在其中的腔室中，或在不同的腔室中實施。在一個實施例中，UV輔助光化學氣相沉積是在UV處理腔室中實施。具有曝露的多孔低k介電膜和曝露的導電表面之基板被放置在處理腔室中。
UV輔助光化學氣相沉積製程包括將前驅物化合物和載氣引入處理腔室中並通過打開一或多個UV燈而將UV能量傳送到設置在基板上的多孔低k介電膜。在一個實施例中，前驅物化合物是包含矽、碳和氮的前驅物化合物。前驅物化合物可為含氮的甲矽烷基化劑(nitrogen containing silylation agent)，諸如三(二甲基氨基)甲基矽烷(tris(dimethylamino)methylsilane)、四(二甲基氨基)矽烷(tetrakis(dimethylamino)silane)、三(二甲氨基)矽烷(tris(dimethylamino)silane)、雙(二甲氨基)二甲基矽烷(bis(dimethylamino)dimethylsilane)、雙(二甲基氨基)甲基乙烯基矽烷(bis(dimethylamino)methylvinylsilane)、三甲矽烷基氨(trisilylamine)、二甲氨基三甲基矽烷(dimethylaminotrimethylsilane)、環三矽氮烷(cyclotrisilazane)、三甲基三乙烯基環三矽氮烷(trimethyltrivinylcyclotrisilazane)、六甲基環三矽氮烷(hexamethylcyclotrisilazane)、九甲基環三矽氮烷(nonamethycyclotrisilazane)或含有矽、氫、氮及碳的其他化合物。載氣可被用以協助將前驅物化合物流至處理腔室中。載氣可為惰性氣體，諸如He、Ar、N2 及它們的組合。在一個實施例中，基板是300 mm的基板，而前驅物化合物之流率的範圍可從約每分鐘100毫克（mgm）到約2,000 mgm且載氣之流率的範圍可從約500每分鐘標準立方釐米(sccm)到約5000 sccm。
UV輔助光化學氣相沉積製程可以約50 mTorr和500 Torr（如，從約100 mTorr至約10 Torr；從約1 Torr至約5 Torr）之間的處理室壓力而進行。基板溫度可為約攝氏100度至約攝氏400度之間。處理時間可為約15秒至約900秒之間。UV功率可為約20％至約100％（如，從約20％至約80％；從約30％至約50％）之間。UV功率可為約200瓦和約3000瓦之間（如，約1100瓦和約2500瓦之間；約1500瓦和約2000瓦之間）。孔隙密封層的厚度的範圍對每個沉積循環而言可為從約1埃至約5埃。在重複沉積循環之後，孔隙密封層可具有5至50埃的總厚度。
在方塊130處所形成的孔隙密封層可為如在第2B圖中所示的孔隙密封層240。在方塊130處形成在導電表面上的孔隙密封殘餘物可為孔隙密封殘餘物242A、242B（統稱為242）。相對於在導電表面(例如，互連結構214A、214B的上表面208A、208B)上所形成的孔隙密封殘餘物242的沉積速率，孔隙密封層240以較高的沉積速率而形成在多孔低k絕緣層(例如，側壁220)之上。因此，在多孔低k絕緣層之上的所形成的孔隙密封層240的部分比在導電表面之上所形成的孔隙密封殘餘物242的部分厚。
在方塊140處，所沉積的孔隙密封層可被曝露於後沉積處理製程。處理製程可為UV輔助處理製程。處理製程可在孔隙密封層被沉積的腔室中，或在不同的腔室中實施。在一個實施例中，處理製程是在負載鎖定腔室中實施，負載鎖定腔室是在密封層被沉積的處理腔室之相同的主要框架中。UV輔助處理製程可包括將反應氣體流入腔室中，具有多孔低k介電膜和設置在多孔低k介電膜上的孔隙密封層之基板係設置在該腔室中。UV能量通過接通一或多個UV燈而被引導到密封層。腔室壓力的範圍可從約6Torr至約200Torr(如，從約10Torr至約50Torr；從約20Torr至約30Torr)。UV功率可在約20%至約100%(如，從約20%至約80%；從約30%至約50%)。UV功率可為約200瓦和約1000瓦之間(如，在約200瓦至約500瓦之間；在約250瓦和約350瓦之間)。反應氣體可具有範圍為從約20sccm到約2000sccm(如，約50sccm至約800sccm)的流率。反應氣體的例子包括NH3、H2、O2、N2O、CO2或它們的組合。諸如Ar或He的惰性氣體也可以範圍從約20sccm到約2000sccm(如，約50sccm至約800sccm)的流率而被引入到腔室中。基板溫度可為在攝氏200度和攝氏400度之間。處理時間的範圍可 從約10秒至約600秒(如，從約60秒至約300秒；從約120秒至約200秒)。
在負載鎖定腔室中的UV輔助處理製程可包括將反應氣體流入負載鎖定腔室中，具有多孔低k介電膜和設置在多孔低k介電膜上的孔隙密封層之基板係設置在該負載鎖定腔室中。UV能量通過接通一或多個UV燈而被引導到密封層。負載鎖定腔室之壓力的範圍可從約0.07Torr至約20Torr。UV功率可以是在約20%至約100%(如，從約20%至約80%；從約30%至約50%)。UV功率可為約200瓦和約1000瓦之間(例如，在約200瓦至約500瓦之間；在約250瓦至約350瓦之間)。反應氣體可以具範圍從約20sccm到約2000sccm(如，約50sccm至約800sccm)的流率。反應氣體的例子包括NH3、H2、O2、N2O、CO2或它們的組合。諸如Ar或He的惰性氣體也可以範圍從約20sccm到約2000sccm(如，約50sccm至約800sccm)的流率而被引入到腔室中。基板溫度可為在攝氏200度和攝氏400度之間。處理時間的範圍可從約10秒至約600秒(如，從約60秒至約300秒；從約120秒至約200秒)。
在一些實施例中，方塊140的UV輔助處理製程以電漿處理所取代。電漿處理可在負載鎖定室中實施。電漿處理可為遠端電漿處理。電漿通常由合適的處理氣體所產生，例如氨、氫或它們的組合。電漿處理可 包括將電漿和載氣流入負載鎖定腔室中，具有多孔低k介電膜設置在其上的基板係設置於該負載鎖定腔室中。諸如氨、氫、氮、氬、氦或其組合的載氣可被引入到具有電漿的負載鎖定腔室中。負載鎖定腔室的壓力的範圍可從約500mTorr至約20Torr。遠端電漿功率的範圍可從約200瓦至約5000瓦。載氣可具有範圍從約20sccm到約2000sccm(如，約50sccm至約800sccm)的流率。處理時間的範圍可從約5秒至約120秒。
處理製程可在與UV輔助沉積製程相同的腔室中實施。在一個實施例中，處理室能夠執行UV輔助沉積製程和UV處理製程兩者。密封層的處理製程在密封層的表面上產生更多的反應位點，導致當後續的密封層被沉積在經處理的密封層上時之改善的膜品質。密封層的沉積和密封層的處理可被重複，直到所得到的密封層達到預定的厚度。孔隙密封層每個沉積循環可具有範圍從約1埃至約5埃的厚度。在一個實施例中，在重複沉積循環之後，預定厚度的範圍從約5埃至約200埃(如，約5埃至約50埃)。所得到的密封層的厚度可取決於應用。若一個沉積製程和一個處理製程被視為一循環，循環的數目的範圍可從約2至100。
在一個實施例中，方塊130的UV輔助光化學氣相沉積製程和方塊140的UV處理可為連續的UV處理，其中方塊130的製程氣體被停止，以執行方塊140的UV處理。
如第1圖中所示，在方塊150處，若孔隙密封層還沒有達到預定的厚度，方塊130和140中的至少一者被重複。每次中間孔隙密封層被沉積在先前沉積和處理的孔隙密封層上時，中間孔隙密封層的表面被處理，以用於待沉積於其上之下個孔隙密封層。若所得到的孔隙密封層已達到預定的厚度，可不實施後續的處理製程。循環的數目可取決於所得到的孔隙密封層之所欲厚度。通過使用循環製程，孔隙密封層被共形地沉積在多孔低k介電層上，且可有效地減少在多孔低k介電層的表面處之多孔低k介電層的孔隙率。
在方塊160處，可實施可選的後沉積處理製程，以從曝露的導電表面移除孔隙密封殘餘物。經移除的孔隙密封殘餘物可為孔隙密封殘餘物242。可選的後處理製程也可移除已形成在導電表面上的任何氧化物污染物。可使用足以從導電表面移除孔隙密封殘餘物、移除氧化污染物或兩者之任何可選的後處理製程。後處理製程可為乾式蝕刻製程、濕式蝕刻製程或兩者。
在一個實施例中，後處理製程是遠端電漿輔助乾式蝕刻類型的製程，包括將基板同時地曝露至NF3 和NH3 之電漿副產物。在一個例子中，電漿蝕刻製程可類似於或者可包括可從美國加州聖克拉拉市應用材料公司所取得的SiCoNi®蝕刻製程。在一些實施例中，後處理製程包括使用提供能量給製程氣體的遠端電漿激發源，使得經激發的氣體物種在處理期間不損壞基板。遠端電漿蝕刻可對於在導電表面上的孔隙密封殘餘物具有較大地選擇性的。
在另一個實施例中，後處理製程是濕式蝕刻類型的製程，可包括將工件曝露於稀釋的氫氟酸(“HF”)溶液(如，約6：1至約1100：1比例的H2O：HF；約800：1至約1000：1的比例的H2O：HF)。濕式蝕刻類型的製程可含有氧化劑(諸如過氧化物)和經調節的pH值，用於改善溶解。作為另一個例子，可使用剝離方法以清潔通孔底部，以移除氧化物殘餘物。該製程可為基於乙酸清潔的氧化還原反應。
在另一個實施例中，後處理製程是濕式蝕刻類型的製程，可包括將工件曝露於基於乙酸的溶液。在一個實施例中，基於乙酸的溶液可含有重量百分比低於約20%的水(如，重量百分比約1%和20%之間的水)，且在一個特定實施例中，用以清潔具有銅金屬化之基板的基於乙酸的溶液可具有重量百分比約1%和10%之間的水(如，重量百分比約1%和5%之間的水)。基於乙酸的清潔溶液還可以包括表面活性劑。表面活性劑可為聚氧乙烯醚表面活性劑和乙氧基化醇表面活性劑的混合物。
在又另一實施例中，後處理製程是濺射清潔製程。濺射清潔製程可為氬濺射清潔製程。在一個實施例中，濺射清潔製程是以約10瓦和約1000瓦之間(約10瓦至約400瓦之間；約20瓦和300瓦之間；約50瓦和 100瓦之間)的RF偏壓功率而實施。濺射清潔製程可以在225W和300W之間的電漿功率而實施。氣流可為約3sccm和100sccm之間。濺射清潔製程的持續時間可為約5秒和35秒之間。濺射製程可在經配置以實施電漿蝕刻製程的製程腔室中實施，例如，具有氬氣濺射能力的預清潔腔室。合適的電漿蝕刻製程腔室的例子包括可購自加州聖克拉拉市的應用材料公司之處理腔室的PC-XT®線，或預清潔腔室的Preclean II線之任一者。
在方塊160的製程之後可實施工件200之額外處理。例如，如第2圖中所示，雙鑲嵌結構可被填充有導電材料270。導電材料270可包含任何合適的材料，例如金屬，諸如銅、鋁、它們的合金或類似物。導電材料270可通過任何合適的製程(諸如電鍍、化學或物理沉積，或類似者)而沉積。工件200可被曝露於拋光製程(如，化學機械拋光)，以移除導電材料270、遮罩層232和遮罩層234的一部分，以曝露低k介電層218的頂部272，隨後沉積阻障層274，如第2E圖中所示。在阻障層274的沉積之後，製程結束，且基板可繼續進行進一步的處理，(例如)以完成被形成在基板上的裝置的形成，或所欲的其它者。
第3圖顯示雙容積處理系統300的剖視圖。處理系統300顯示可購自加州聖克拉拉市的應用材料公司之300mm，或450mm的PRODUCER®處理系統的示例性實施例。於此所述的實施例還可有利地採用 PRODUCER®NANOCURETM和PRODUCER®ONYXTM系統，兩者皆可由加州聖克拉拉市的應用材料公司取得，或其他合適地適用的處理系統，包括那些來自其它製造商者。
處理系統300提供兩個分開和相鄰的處理區域在腔室本體中，用於處理該基板。處理系統300具有蓋302、外殼304和功率源306。外殼304之每一者覆蓋分別設置在由本體362所界定的兩個處理區域360之上的兩個UV燈322之各一者。處理區域360之每一者包括加熱基板支撐件，諸如基板支撐件324，用於支撐在處理區域360內的工件200。UV燈322發射被導引通過視窗308和噴淋頭310至位於每一處理區域內之每一基板上的UV光。基板支撐件324可由陶瓷或諸如鋁的金屬所製成。基板支撐件324可耦接到延伸通過本體362的底部且被驅動系統330所操作的桿328，以在處理區域360中移動基板支撐件324朝向和遠離UV燈322。驅動系統330可以在固化期間也旋轉及/或平移基板支撐件324，以進一步強化基板照明的均勻性。示例性的串聯處理系統300可被併入可購自加州聖克拉拉市的應用材料公司之處理系統(諸如ProducerTM處理系統)中。
UV燈322可為利用包括(但不限於)微波弧、射頻燈絲(電容耦合電漿)和電感耦合電漿(ICP)燈的任何合適的UV照射源之發光二極管或燈泡的陣列。UV光可在固化製程期間被脈衝化。用於強化基板照明的均勻性的各種概念包括使用也可被用於改變入射光的波長分布、基板和燈頭的相對運動(包括旋轉和週期性平移（掃略）)和燈反射器的形狀及/或位置之即時改變的燈陣列。UV燈322是紫外線輻射的來源，且可發送寬光譜範圍之UV和紅外線（IR）輻射的波長。
UV燈322可發射遍及170 nm至400 nm之寬頻的波長。選擇用於在UV燈322內使用的氣體可決定所發射的波長。從UV燈322所發射的UV光藉由通過設置在蓋302中之孔中的視窗308和氣體分配噴淋頭310而進入處理區域360。視窗308可由無OH的合成石英玻璃所製成，且具有足夠的厚度，以維持真空而不裂開。視窗308可為經熔融的二氧化矽，傳送低於約150 nm的UV光。噴淋頭310可由透明的材料(諸如石英或藍寶石)所製成，且位於視窗308和基板支撐件324之間。由於蓋302密封至本體362，且視窗308被密封至蓋302，處理區域360提供足以維持從約1 Torr至約650 Torr的壓力之容積。處理或清潔氣體可經由兩個入口通道332的各一者進入處理區域360。處理或清潔氣體接著經由共用出口埠334離開處理區域360。
外殼304之每一者包括鄰近於功率源306的孔315。外殼304可包括由塗覆有二向色膜的鑄造石英襯裡336所界定的內側拋物表面。二向色膜通常構成週期性多層膜，週期性多層膜由具有交替的高和低折射率之不同的介電材料所構成。因此，石英襯裡336可傳送紅外光並反射從UV燈322所發射的UV光。石英襯裡336可藉由移動和改變內側拋物線表面的形狀而被調整，以更適合每一製程或任務。
於此所揭露的實施例致使在互聯整合流程內孔隙密封多孔低k膜。實施例提供由使用多孔低k膜的電容優點、藉由孔隙密封之良好的可靠性和藉由殘餘物移除的良好的通孔接觸。
雖然前面部分是關於本說明書的實施例，本說明書的其他和進一步的實施例可經設計而不背離本說明書的基本範圍，且本說明書的範圍是藉由以下的申請專利範圍而決定。
100:方法
110:方塊
120:方塊
130:方塊
140:方塊
150:方塊
160:方塊
200:工件
208:上表面
208A:上表面
208B:上表面
210‧‧‧基板212‧‧‧低K介電阻障層214‧‧‧互連結構214A‧‧‧金屬互連結構214B‧‧‧金屬互連結構216‧‧‧低K介電層218‧‧‧低K介電層220‧‧‧側壁232‧‧‧遮罩層234‧‧‧遮罩層240‧‧‧孔隙密封層242‧‧‧孔隙密封殘餘物242A‧‧‧孔隙密封殘餘物242B‧‧‧孔隙密封殘餘物250‧‧‧經圖案化的膜堆疊260‧‧‧開口特徵270‧‧‧導電材料272‧‧‧頂部274‧‧‧阻障層300‧‧‧處理系統302‧‧‧蓋304‧‧‧外殼306‧‧‧功率源308‧‧‧視窗310‧‧‧噴淋頭315‧‧‧孔322‧‧‧uv燈324‧‧‧基板支撐件328‧‧‧桿330‧‧‧驅動系統332‧‧‧入口通道334‧‧‧共用出口埠336‧‧‧石英襯裡360‧‧‧處理區362‧‧‧本體
因此，本說明書之以上所載的特徵可被詳細理解之方式，可藉由參照實施例(一些實施例係顯示於附隨的圖式中)而獲得前面所簡單地摘要之實施例之較特定的說明。然而，應理解附隨的圖示僅描繪此說明書的通常實施例，且不因此被視為限制本說明書之範圍，因為本說明書可允許其他等效的實施例。
第1圖是顯示一種形成根據於此所述之實施例的密封層之方法的製程流程圖；第2A-2E圖描繪根據於此所述的實施例而處理之工件的剖視概要圖；及第3圖是本說明書的實施例可被實施於中之UV熱處理腔室的一剖視圖。
為幫助理解，儘可能地使用相同的元件符號以指定共用於圖式中的相同元件。應理解一個實施例的元件和特徵可被有利地併入其他實施例中而無需進一步詳述。然而，應注意附隨的圖式僅顯示此說明書的示例 性實施例，且不因此被視為限制本說明書之範圍，因為本說明書可允許其他等效的實施例。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
(請換頁單獨記載) 無
200‧‧‧工件
208A‧‧‧上表面
208B‧‧‧上表面
210‧‧‧基板
212‧‧‧低K介電阻障層
214A‧‧‧金屬互連結構
214B‧‧‧金屬互連結構
216‧‧‧低K介電層
218‧‧‧低K介電層
272‧‧‧頂部
274‧‧‧阻障層

Claims (20)

  1. 一種處理一低k介電膜的方法，包含以下步驟：將一基板曝露於UV輻射和第一反應氣體，其中該基板具有限定在該基板中的一開口特徵，該開口特徵係由一多孔低k介電層和一導電材料所界定，其中該多孔低k介電層是一含矽和碳材料；及使用UV輔助光化學氣相沉積而選擇性在該多孔低k介電層的多個曝露表面上形成一孔隙密封層在該開口特徵中。
  2. 如請求項1所述之方法，其中該UV輔助光化學氣相沉積包含：將該基板曝露至一載氣和包含矽、碳和氮之一前驅物化合物，同時傳送UV輻射至該多孔低k介電層。
  3. 如請求項2所述之方法，進一步包含以下步驟：在將該基板曝露至包含矽、碳和氮之該前驅物化合物之後，曝露所沉積的該孔隙密封層至UV輻射。
  4. 如請求項3所述之方法，進一步包含以下步驟：重複該UV輔助光化學氣相沉積之步驟和在將該基板曝露至包含矽、碳和氮之該前驅物化合物之後，曝 露所沉積的該孔隙密封層至UV輻射之步驟，直到該孔隙密封層達成一預定的厚度。
  5. 如請求項4所述之方法，進一步包含以下步驟：將該基板曝露至一後沉積處理製程，以從該開口特徵之該導電材料移除一孔隙密封殘餘物。
  6. 如請求項4所述之方法，進一步包含以下步驟：以一第二導電材料充填該開口特徵。
  7. 如請求項1所述之方法，其中在該開口特徵之該多孔低k介電層上的該孔隙密封層的一沉積速率係大於在該開口特徵之該導電材料上之一孔隙密封殘餘物之一沉積速率。
  8. 如請求項2所述之方法，其中該前驅物化合物係選自三(二甲基氨基)甲基矽烷(tris(dimethylamino)methylsilane)、四(二甲基氨基)矽烷(tetrakis(dimethylamino)silane)、三(二甲氨基)矽烷(tris(dimethylamino)silane)、雙(二甲氨基)二甲基矽烷(bis(dimethylamino)dimethylsilane)、雙(二甲基氨基)甲基乙烯基矽烷 (bis(dimethylamino)methylvinylsilane)、三甲矽烷基氨(trisilylamine)、二甲氨基三甲基矽烷(dimethylaminotrimethylsilane)、環三矽氮烷(cyclotrisilazane)、三甲基三乙烯基環三矽氮烷(trimethyltrivinylcyclotrisilazane)、六甲基環三矽氮烷(hexamethylcyclotrisilazane)、九甲基環三矽氮烷(nonamethycyclotrisilazane)或它們的組合。
  9. 如請求項2所述之方法，其中該載氣係選自氦氣、氬氣、氮氣或它們的組合。
  10. 如請求項1所述之方法，其中該孔隙密封層對每一沉積循環具有範圍從約1埃至約5埃的一厚度。
  11. 如請求項3所述之方法，其中曝露所沉積的該孔隙密封層至UV輻射之步驟包含以下步驟：將一第二反應氣體流入一腔室中，該基板被設置在該腔室中。
  12. 如請求項11所述之方法，其中該第二反應氣體係選自NH3、H2、O2、N2O、CO2或它們的組合。
  13. 如請求項12所述之方法，其中曝露所沉積的該孔隙密封層至UV輻射之步驟係以在約6Torr 和200Torr之間的一腔室壓力所實施。
  14. 如請求項4所述之方法，其中該預定的厚度之範圍從約5埃至約200埃。
  15. 如請求項1所述之方法，其中該開口特徵係選自多個溝槽、多個通孔、多個孔、多個開口、多個線，以及它們的組合。
  16. 一種處理一低k介電膜的方法，包含以下步驟：將一基板曝露於UV輻射和一含氮前驅物，其中該基板具有限定在該基板中的一溝槽和通孔，該溝槽和通孔係由一多孔低k介電層和一導電材料所界定，其中該多孔低k介電層是一含矽和碳材料；使用UV輔助光化學氣相沉積而選擇性地在該通孔中之該多孔低k介電層的多個曝露表面上形成一孔隙密封層，並在該通孔中之曝露的該導電材料上形成一孔隙密封殘餘物；及將該基板曝露於一後沉積處理製程，以從該通孔的該導電材料移除該孔隙密封殘餘物。
  17. 如請求項16所述之方法，其中該後沉積處理製程係選自一乾式蝕刻製程、一濕式蝕刻製程或他們的組合。
  18. 如請求項16所述之方法，其中該UV輔 助光化學氣相沉積包含：將該基板曝露至一載氣和包含矽、碳和氮之一前驅物化合物，同時傳送UV輻射至該基板。
  19. 如請求項18所述之方法，進一步包含以下步驟：在將該基板曝露至包含矽、碳和氮之該前驅物化合物之後，將所沉積的該孔隙密封層曝露至UV輻射。
  20. 一種處理一低k介電膜的方法，包含以下步驟：將一基板曝露於UV輻射和一含氮前驅物，其中該基板具有限定在該基板中的一溝槽和通孔，該溝槽和通孔係由一多孔低k介電層和一導電材料所界定，其中該多孔低k介電層是一含矽和碳材料；使用UV輔助光化學氣相沉積而選擇性地在該通孔中之該多孔低k介電層的多個曝露表面上形成一孔隙密封層，並在該通孔中之曝露的該導電材料上形成一孔隙密封殘餘物；及將該基板曝露於一後沉積處理製程，以從該通孔的該導電材料移除該孔隙密封殘餘物，其中該孔隙密封層的一沉積速率係大於該孔隙密封殘餘物的一沉積速率。
TW105119681A 2015-06-25 2016-06-23 針對側壁孔隙密封及通孔清潔度的互聯整合 TWI700389B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/750,778 2015-06-25
US14/750,778 US9793108B2 (en) 2015-06-25 2015-06-25 Interconnect integration for sidewall pore seal and via cleanliness

Publications (2)

Publication Number Publication Date
TW201706448A TW201706448A (zh) 2017-02-16
TWI700389B true TWI700389B (zh) 2020-08-01

Family

ID=57585549

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105119681A TWI700389B (zh) 2015-06-25 2016-06-23 針對側壁孔隙密封及通孔清潔度的互聯整合

Country Status (6)

Country Link
US (1) US9793108B2 (zh)
JP (1) JP6821607B2 (zh)
KR (1) KR102565172B1 (zh)
CN (1) CN107743651B (zh)
TW (1) TWI700389B (zh)
WO (1) WO2016209539A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3000602B1 (fr) * 2012-12-28 2016-06-24 Commissariat A L Energie Atomique Et Aux Energies Alternatives Procede de gravure d'un materiau dielectrique poreux
US11177127B2 (en) 2017-05-24 2021-11-16 Versum Materials Us, Llc Functionalized cyclosilazanes as precursors for high growth rate silicon-containing films
US12057310B2 (en) 2018-05-22 2024-08-06 Versum Materials Us, Llc Functionalized cyclosilazanes as precursors for high growth rate silicon-containing films
US11837618B1 (en) 2020-08-21 2023-12-05 Samsung Electronics Co., Ltd. Image sensor including a protective layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4581249A (en) * 1984-03-30 1986-04-08 Canon Kabushiki Kaisha Photochemical vapor deposition method
US20090286394A1 (en) * 2006-05-31 2009-11-19 Chung-Chi Ko Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections
TW201243948A (en) * 2011-04-25 2012-11-01 Applied Materials Inc UV assisted silylation for recovery and pore sealing of damaged low k films

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6440289B1 (en) * 1999-04-02 2002-08-27 Advanced Micro Devices, Inc. Method for improving seed layer electroplating for semiconductor
US6759325B2 (en) 2000-05-15 2004-07-06 Asm Microchemistry Oy Sealing porous structures
US6482733B2 (en) 2000-05-15 2002-11-19 Asm Microchemistry Oy Protective layers prior to alternating layer deposition
US7276441B1 (en) 2003-04-15 2007-10-02 Lsi Logic Corporation Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures
JP2005167081A (ja) * 2003-12-04 2005-06-23 Renesas Technology Corp 半導体装置およびその製造方法
WO2006058034A2 (en) 2004-11-22 2006-06-01 Intermolecular, Inc. Molecular self-assembly in substrate processing
US7648927B2 (en) 2005-06-21 2010-01-19 Applied Materials, Inc. Method for forming silicon-containing materials during a photoexcitation deposition process
US20080032064A1 (en) * 2006-07-10 2008-02-07 President And Fellows Of Harvard College Selective sealing of porous dielectric materials
JP5548332B2 (ja) * 2006-08-24 2014-07-16 富士通セミコンダクター株式会社 半導体デバイスの製造方法
US10037905B2 (en) * 2009-11-12 2018-07-31 Novellus Systems, Inc. UV and reducing treatment for K recovery and surface clean in semiconductor processing
JP2008263097A (ja) * 2007-04-13 2008-10-30 Toshiba Corp 半導体装置及び半導体装置の製造方法
US7781332B2 (en) * 2007-09-19 2010-08-24 International Business Machines Corporation Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer
US8105465B2 (en) * 2008-10-14 2012-01-31 Applied Materials, Inc. Method for depositing conformal amorphous carbon film by plasma-enhanced chemical vapor deposition (PECVD)
US8216861B1 (en) * 2011-06-28 2012-07-10 Applied Materials, Inc. Dielectric recovery of plasma damaged low-k films by UV-assisted photochemical deposition
KR20150010720A (ko) * 2012-04-25 2015-01-28 어플라이드 머티어리얼스, 인코포레이티드 Ｕｖ 기반 실릴화 챔버 세정을 위한 방법
US20140162194A1 (en) * 2012-05-25 2014-06-12 Applied Materials, Inc. Conformal sacrificial film by low temperature chemical vapor deposition technique
US9058980B1 (en) * 2013-12-05 2015-06-16 Applied Materials, Inc. UV-assisted photochemical vapor deposition for damaged low K films pore sealing
US10049921B2 (en) * 2014-08-20 2018-08-14 Lam Research Corporation Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4581249A (en) * 1984-03-30 1986-04-08 Canon Kabushiki Kaisha Photochemical vapor deposition method
US20090286394A1 (en) * 2006-05-31 2009-11-19 Chung-Chi Ko Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections
TW201243948A (en) * 2011-04-25 2012-11-01 Applied Materials Inc UV assisted silylation for recovery and pore sealing of damaged low k films

Also Published As

Publication number Publication date
WO2016209539A1 (en) 2016-12-29
TW201706448A (zh) 2017-02-16
JP6821607B2 (ja) 2021-01-27
KR20180012878A (ko) 2018-02-06
US9793108B2 (en) 2017-10-17
KR102565172B1 (ko) 2023-08-10
CN107743651A (zh) 2018-02-27
CN107743651B (zh) 2022-02-01
US20160379819A1 (en) 2016-12-29
JP2018520518A (ja) 2018-07-26

Similar Documents

Publication Publication Date Title
JP6422536B2 (ja) 気相化学曝露による低誘電率誘電体の損傷修復
US7851232B2 (en) UV treatment for carbon-containing low-k dielectric repair in semiconductor processing
TWI464805B (zh) 低介電常數介電質之整合方法
TWI700389B (zh) 針對側壁孔隙密封及通孔清潔度的互聯整合
KR101425332B1 (ko) Uv 처리를 사용하는 탄소 함유 로우-k 유전율 복구
TWI402887B (zh) 用以整合具有改良可靠度之超低ｋ介電質之結構與方法
US8455849B2 (en) Method and apparatus for modulating wafer treatment profile in UV chamber
US8753449B2 (en) Enhancement in UV curing efficiency using oxygen-doped purge for ultra low-K dielectric film
TWI392024B (zh) 將溼蝕刻之底切最小化以及提供超低介電常數（ｋ＜２.５）之介電質封孔之方法
KR102305536B1 (ko) 배선 구조를 위한 패시베이션 보호물을 형성하기 위한 방법들
TWI581331B (zh) 降低多孔低ｋ膜的介電常數之方法
US9269563B2 (en) Methods for forming interconnect structure utilizing selective protection process for hardmask removal process
US9004914B2 (en) Method of and apparatus for active energy assist baking
KR20160093689A (ko) 손상된 저 ｋ 필름들의 기공 밀봉을 위한 uv-보조된 광화학 증기 증착법
KR20070071025A (ko) 씨모스이미지센서의 금속배선 제조 방법