JP6821607B2 - 側壁ポアの封止とビアの清浄性のための配線集積化 - Google Patents
側壁ポアの封止とビアの清浄性のための配線集積化 Download PDFInfo
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- JP6821607B2 JP6821607B2 JP2017567077A JP2017567077A JP6821607B2 JP 6821607 B2 JP6821607 B2 JP 6821607B2 JP 2017567077 A JP2017567077 A JP 2017567077A JP 2017567077 A JP2017567077 A JP 2017567077A JP 6821607 B2 JP6821607 B2 JP 6821607B2
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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Description
デバイスの相次ぐスケーリングによって、半導体製造における誘電膜の誘電率(k)は低下し続けている。低誘電率(low−k)膜への集積化損傷を最小限に抑えることは、特徴(feature)サイズの継続的な低下を可能にする因子の1つである。しかしながら、特徴サイズが縮小するにつれ、誘電膜の抵抗容量及び信頼性向上が深刻な課題となる。
Claims (15)
- 基板をUV放射及び第1の反応性ガスに晒すことであって、前記基板には開口特徴部が画定されており、前記開口特徴部が多孔性低誘電率誘電体層及び導電性材料によって画定されており、前記多孔性低誘電率誘電体層がケイ素及び炭素含有材料であること、並びに
UVアシスト光化学蒸着を用いて、前記開口特徴部において前記多孔性低誘電率誘電体層の露出した表面にポア封止層を選択的に形成すること
を含む方法であって、
前記UVアシスト光化学蒸着が、前記多孔性低誘電率誘電体層にUV放射を送達しながら、前記基板を、キャリアガス、並びにケイ素、炭素、及び窒素を含む前駆体化合物に晒すこと
を含む、方法。 - 前記基板をケイ素、炭素、及び窒素を含む前記前駆体化合物に晒した後、堆積した前記ポア封止層をUV放射に晒すこと
を更に含む、請求項1に記載の方法。 - 前記UVアシスト光化学蒸着、並びに、前記基板をケイ素、炭素、及び窒素を含む前記前駆体化合物に晒した後に堆積した前記ポア封止層をUV放射に晒すことを含む、堆積サイクルを、前記ポア封止層が所定の厚さに到達するまで繰り返すこと
を更に含む、請求項2に記載の方法。 - 前記開口特徴部の前記導電性材料からポア封止残留物を除去するために、前記基板を堆積後の処置プロセスに晒すこと
を更に含む、請求項1から3のいずれか一項に記載の方法。 - 前記開口特徴部を第2の導電性材料で充填すること
を更に含む、請求項1から4のいずれか一項に記載の方法。 - 前記開口特徴部の前記多孔性低誘電率誘電体層への前記ポア封止層の堆積レートが、前記開口特徴部の前記導電性材料へのポア封止残留物の堆積レートよりも大きい、請求項1から5のいずれか一項に記載の方法。
- 前記前駆体化合物が、トリス(ジメチルアミノ)メチルシラン、テトラキス(ジメチルアミノ)シラン、トリス(ジメチルアミノ)シラン、ビス(ジメチルアミノ)ジメチルシラン、ビス(ジメチルアミノ)メチルビニルシラン、トリシリルアミン、ジメチルアミノトリメチルシラン、シクロトリシラザン、トリメチルトリビニルシクロトリシラザン、ヘキサメチルシクロトリシラザン、ノナメチシクロトリシラザン、又はそれらの組み合わせから選択される、請求項1から6のいずれか一項に記載の方法。
- 前記キャリアガスが、ヘリウム、アルゴン、窒素、又はそれらの組み合わせから選択される、請求項1から7のいずれか一項に記載の方法。
- 前記ポア封止層が、前記堆積サイクルの各々において、約1オングストロームから約5オングストロームの範囲の厚さを有する、請求項3に記載の方法。
- 堆積した前記ポア封止層をUV放射に晒すことが、前記基板が配置されているチャンバに第2の反応性ガスを流入させることを含む、請求項2または3に記載の方法。
- 前記第2の反応性ガスが、NH3、H2、O2、N2O、CO2、又はそれらの組み合わせから選択される、請求項10に記載の方法。
- 堆積した前記ポア封止層をUV放射に晒すことが、約6Torrから約200Torrの間のチャンバ圧力で行われる、請求項10または11に記載の方法。
- 前記所定の厚さが約5オングストロームから約200オングストロームの範囲である、請求項3に記載の方法。
- 前記開口特徴部が、トレンチ、ビア、孔、開口、ライン、及びそれらの組み合わせから選択される、請求項1から13のいずれか一項に記載の方法。
- 前記第1の反応性ガスがNH 3 を含む、請求項6に記載の方法。
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US14/750,778 | 2015-06-25 | ||
US14/750,778 US9793108B2 (en) | 2015-06-25 | 2015-06-25 | Interconnect integration for sidewall pore seal and via cleanliness |
PCT/US2016/034434 WO2016209539A1 (en) | 2015-06-25 | 2016-05-26 | Interconnect integration for sidewall pore seal and via cleanliness |
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US11177127B2 (en) | 2017-05-24 | 2021-11-16 | Versum Materials Us, Llc | Functionalized cyclosilazanes as precursors for high growth rate silicon-containing films |
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US6440289B1 (en) * | 1999-04-02 | 2002-08-27 | Advanced Micro Devices, Inc. | Method for improving seed layer electroplating for semiconductor |
US6482733B2 (en) | 2000-05-15 | 2002-11-19 | Asm Microchemistry Oy | Protective layers prior to alternating layer deposition |
US6759325B2 (en) | 2000-05-15 | 2004-07-06 | Asm Microchemistry Oy | Sealing porous structures |
US7276441B1 (en) | 2003-04-15 | 2007-10-02 | Lsi Logic Corporation | Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures |
JP2005167081A (ja) * | 2003-12-04 | 2005-06-23 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US7309658B2 (en) | 2004-11-22 | 2007-12-18 | Intermolecular, Inc. | Molecular self-assembly in substrate processing |
US7648927B2 (en) | 2005-06-21 | 2010-01-19 | Applied Materials, Inc. | Method for forming silicon-containing materials during a photoexcitation deposition process |
US20070278682A1 (en) | 2006-05-31 | 2007-12-06 | Chung-Chi Ko | Self-assembled mono-layer liner for cu/porous low-k interconnections |
US20080032064A1 (en) * | 2006-07-10 | 2008-02-07 | President And Fellows Of Harvard College | Selective sealing of porous dielectric materials |
JP5548332B2 (ja) | 2006-08-24 | 2014-07-16 | 富士通セミコンダクター株式会社 | 半導体デバイスの製造方法 |
US10037905B2 (en) * | 2009-11-12 | 2018-07-31 | Novellus Systems, Inc. | UV and reducing treatment for K recovery and surface clean in semiconductor processing |
JP2008263097A (ja) * | 2007-04-13 | 2008-10-30 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
US7781332B2 (en) * | 2007-09-19 | 2010-08-24 | International Business Machines Corporation | Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer |
US8105465B2 (en) * | 2008-10-14 | 2012-01-31 | Applied Materials, Inc. | Method for depositing conformal amorphous carbon film by plasma-enhanced chemical vapor deposition (PECVD) |
US8492170B2 (en) * | 2011-04-25 | 2013-07-23 | Applied Materials, Inc. | UV assisted silylation for recovery and pore sealing of damaged low K films |
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KR20150010720A (ko) * | 2012-04-25 | 2015-01-28 | 어플라이드 머티어리얼스, 인코포레이티드 | Uv 기반 실릴화 챔버 세정을 위한 방법 |
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US9058980B1 (en) * | 2013-12-05 | 2015-06-16 | Applied Materials, Inc. | UV-assisted photochemical vapor deposition for damaged low K films pore sealing |
US10049921B2 (en) * | 2014-08-20 | 2018-08-14 | Lam Research Corporation | Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor |
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