TWI699458B - Lead frame material and manufacturing method thereof - Google Patents

Lead frame material and manufacturing method thereof Download PDF

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TWI699458B
TWI699458B TW105134728A TW105134728A TWI699458B TW I699458 B TWI699458 B TW I699458B TW 105134728 A TW105134728 A TW 105134728A TW 105134728 A TW105134728 A TW 105134728A TW I699458 B TWI699458 B TW I699458B
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layer
vertical
roughened
alloy
lead frame
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TW105134728A
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TW201726983A (en
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小林良聡
橋本真
柴田邦夫
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日商古河電氣工業股份有限公司
日商古河精密金屬工業股份有限公司
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60Electroplating characterised by the structure or texture of the layers
    • C25D5/615Microstructure of the layers, e.g. mixed structure
    • C25D5/617Crystalline layers
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10Electroplating with more than one layer of the same or of different metals
    • C25D5/12Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60Electroplating characterised by the structure or texture of the layers
    • C25D5/605Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads

Abstract

提供一種適宜製作近年來謀求之可改善高溫、高濕環境中之樹脂密接性之引線框架的引線框架材及其製造方法。 Provided is a lead frame material suitable for manufacturing a lead frame capable of improving resin adhesion in a high temperature and high humidity environment that has been sought in recent years, and a manufacturing method thereof.

一種引線框架材及其製造方法,該引線框架材於導電性基體(1)上具有粗化層,該粗化層由複數層粗化層構成,上述粗化層於導電性基體之垂直方向具有由至少1層構成之垂直粗化層(2),並且進一步於該垂直粗化層之上層具有至少1層以上之附加粗化層(3),於上述垂直粗化層及附加粗化層各自所具有之凹凸之中,上述垂直粗化層之相鄰凸部之頂點的間隔與上述附加粗化層之相鄰凸部之頂點的間隔不同。 A lead frame material and a manufacturing method thereof. The lead frame material has a roughened layer on a conductive substrate (1), the roughened layer is composed of a plurality of roughened layers, and the roughened layer has a vertical direction of the conductive substrate A vertical roughening layer (2) composed of at least one layer, and further having at least one additional roughening layer (3) above the vertical roughening layer, and each of the vertical roughening layer and the additional roughening layer Among the unevennesses, the interval between the vertices of the adjacent convex portions of the vertical roughening layer is different from the interval between the vertices of the adjacent convex portions of the additional roughening layer.

Description

引線框架材及其製造方法 Lead frame material and manufacturing method thereof

本發明係關於一種用於將半導體元件與實施過鍍覆處理之引線框架相互電連接並利用塑模(mold)樹脂密封該等而成之樹脂密封型半導體裝置的引線框架材及其製造方法。 The present invention relates to a lead frame material for electrically connecting a semiconductor element and a lead frame subjected to a plating process to each other and sealing the resin-sealed semiconductor device with a mold resin, and a manufacturing method thereof.

該種樹脂密封型半導體裝置係利用塑模樹脂密封藉由金屬線等而相互電連接之半導體元件與引線框架而成者。於此種樹脂密封型半導體裝置中,主流為引線框架被實施Sn-Pb、Sn-Bi等外裝鍍覆。 This type of resin-sealed semiconductor device is formed by sealing a semiconductor element and a lead frame electrically connected to each other by a metal wire or the like with a mold resin. In this type of resin-sealed semiconductor device, the mainstream is that the lead frame is subjected to exterior plating such as Sn-Pb, Sn-Bi.

其中,近年來為了組裝步驟之簡化及降低成本,開始採用預先於引線框架表面實施鍍覆(例如Ni/Pd/Au)之引線框架(Pre Plated Frame,以下簡稱為PPF),該鍍覆係如於利用焊料等安裝於印刷基板時,提高與焊料之潤濕性之規格的鍍覆(例如,參照專利文獻1)。 Among them, in recent years, in order to simplify the assembly steps and reduce costs, lead frames (Pre Plated Frame, hereinafter referred to as PPF) that have been plated (such as Ni/Pd/Au) on the surface of the lead frame in advance have begun to be used. When mounting on a printed circuit board with solder or the like, plating is a specification that improves the wettability with solder (for example, refer to Patent Document 1).

又,另一方面,提出有如下技術,即,為了提高樹脂密封型半導體裝置中之引線框架與塑模樹脂之密接性,將引線框架之鍍覆表面粗化(例如,參照專利文獻2、專利文獻3)。 On the other hand, a technique has been proposed to roughen the plating surface of the lead frame in order to improve the adhesion between the lead frame and the mold resin in the resin-sealed semiconductor device (for example, refer to Patent Document 2, Patent Literature 3).

該等將鍍覆表面粗化之技術係藉由將引線框架之鍍覆表面粗化,而期望(1)引線框架之與塑模樹脂之接著面積變大之效果、(2)塑模樹脂易於進入經粗化之鍍膜之凹凸之效果(即定錨(anchor)效果)等。 These techniques for roughening the plating surface are by roughening the plating surface of the lead frame, and it is expected that (1) the bonding area between the lead frame and the mold resin becomes larger, and (2) the mold resin is easy to Enter the roughening effect of the coating (anchor effect), etc.

根據以上所述,引線框架對塑模樹脂之密接性提高,能夠防 止引線框架與塑模樹脂之間之剝離,樹脂密封型半導體裝置之可靠性提高。 According to the above, the adhesion of the lead frame to the mold resin is improved, which can prevent The peeling between the lead frame and the mold resin is prevented, and the reliability of the resin-sealed semiconductor device is improved.

[專利文獻1]日本特開平4-115558號 [Patent Document 1] Japanese Patent Application Publication No. 4-115558

[專利文獻2]日本特開平6-29439號 [Patent Document 2] Japanese Patent Application Laid-Open No. 6-29439

[專利文獻3]日本特開平10-27873號 [Patent Document 3] Japanese Patent Application Laid-Open No. 10-27873

基於該等形狀之粗化鍍覆確實較先前更能提高樹脂密接性。然而,可知於近年來所要求之高可靠性之水準,例如溫度85℃、濕度85%之環境下經過168小時後,樹脂與引線框架之間產生間隙之情形隨處可見。認為其原因在於:習知以來不常用之QFN(Quad Flat Non-Leaded Package)型或SOP(Small Outline Package)型等封裝變得被大量使用,對於密接性之要求程度更高。如此,可知尚有改善之餘地。 Rough plating based on these shapes can indeed improve resin adhesion better than before. However, it can be known that under the high reliability level required in recent years, for example, after 168 hours in an environment with a temperature of 85°C and a humidity of 85%, gaps between the resin and the lead frame can be seen everywhere. It is believed that the reason is: QFN (Quad Flat Non-Leaded Package) type or SOP (Small Outline Package) type packages, which are not commonly used since the past, have become widely used, and the requirements for adhesion are higher. In this way, it can be seen that there is still room for improvement.

本發明之課題在於提供一種適宜製作近年來謀求之可改善高溫、高濕環境中之樹脂密接性之引線框架的引線框架材及其製造方法。 The subject of the present invention is to provide a lead frame material suitable for manufacturing a lead frame capable of improving resin adhesion in a high temperature and high humidity environment that has been sought in recent years, and a manufacturing method thereof.

本發明人等對上述先前之問題進行努力研究開發,結果著眼於形成於導電性基體上之粗化層之形狀,對可最大限度發揮引線框架材與樹脂之定錨效果之形狀進行努力研究。結果發現,不僅具有垂直粗化層(於基體之垂直方向形成至少1層以上之粗化層),進一步於其上層亦具有至少1層以上附加粗化層(粗化後之形狀),於上述垂直粗化層及附加粗化層各自所具有之凹凸中,上述垂直粗化層之相鄰凸部(凹凸之峰)之頂點的間 隔與上述附加粗化層之相鄰凸部(凹凸之峰)之頂點的間隔不同,藉此而使樹脂密接性較先前明顯提高,可確保高溫高濕試驗中之樹脂密接性。本發明係基於該知識見解而完成者。 The inventors of the present invention made efforts to research and develop the aforementioned problems. As a result, they focused on the shape of the roughened layer formed on the conductive substrate, and studied the shape that can maximize the anchoring effect of the lead frame material and the resin. As a result, it was found that not only a vertical roughening layer (at least one roughening layer is formed in the vertical direction of the substrate), but also at least one additional roughening layer (shape after roughening) on the upper layer. Among the concavities and convexities of the vertical roughening layer and the additional roughening layer, the space between the apexes of the adjacent convex portions (concave and convex peaks) of the vertical roughening layer The gap is different from the apex of the adjacent convex portion (concave-convex peak) of the additional roughening layer, thereby significantly improving the resin adhesion compared with the previous one, and can ensure the resin adhesion in the high temperature and high humidity test. The present invention was completed based on this knowledge.

即,本發明提供以下之手段: That is, the present invention provides the following means:

(1)一種引線框架材,於導電性基體上具有粗化層,其特徵在於:該粗化層由複數層粗化層構成,上述粗化層於導電性基體之垂直方向具有由至少1層構成之垂直粗化層,並且進一步於該垂直粗化層之上層具有至少1層以上之附加粗化層,於上述垂直粗化層及附加粗化層各自所具有之凹凸中,上述垂直粗化層之相鄰凸部之頂點的間隔與上述附加粗化層之相鄰凸部之頂點的間隔不同。 (1) A lead frame material having a roughened layer on a conductive substrate, wherein the roughened layer is composed of a plurality of roughened layers, and the roughened layer has at least one layer in the vertical direction of the conductive substrate. Constitute a vertical roughened layer, and further have at least one or more additional roughened layers on the upper layer of the vertical roughened layer, and in the concavities and convexities of the vertical roughened layer and the additional roughened layer, the vertical roughened The interval between the apexes of adjacent convex portions of the layer is different from the interval between the apexes of adjacent convex portions of the additional roughening layer.

(2)如(1)之引線框架材,其中,最表層剖面之線段長度(最表層剖面線段長度,包含附加粗化層在內之引線框架材之最表層之剖面之線段長度)(A)與導電性基體剖面之線段長度(導電性基體剖面線段長度)(B)之比(A/B)的值為1.2以上且4以下。 (2) The lead frame material as in (1), wherein the line segment length of the outermost layer section (the line segment length of the outermost layer section, the line segment length of the outermost layer section of the lead frame material including the additional roughening layer) (A) The value of the ratio (A/B) to the line segment length of the conductive substrate cross section (the conductive substrate cross section line segment length) (B) is 1.2 or more and 4 or less.

(3)如(1)或(2)之引線框架材,其特徵在於:上述導電性基體為銅或銅合金、鐵或鐵合金、鋁或鋁合金。 (3) The lead frame material according to (1) or (2), characterized in that: the conductive substrate is copper or copper alloy, iron or iron alloy, aluminum or aluminum alloy.

(4)如(1)至(3)中任一項之引線框架材,其特徵在於:上述複數層粗化層由2層構成,具有於導電性基體之垂直方向被粗化之第一垂直粗化層與該垂直粗化層之上層之第二附加粗化層,並且該垂直粗化層與附加粗化層各自之成分不同。 (4) The lead frame material according to any one of (1) to (3), characterized in that the plurality of roughened layers are composed of two layers, and have a first vertical roughened in the vertical direction of the conductive substrate. The roughened layer and the second additional roughened layer above the vertical roughened layer, and the vertical roughened layer and the additional roughened layer have different compositions.

(5)如(4)之引線框架材,其特徵在於:上述附加粗化層之凸部之頂點的間隔較第一垂直粗化層之凸部之頂點的間隔窄。 (5) The lead frame material according to (4), wherein the interval between the apexes of the convex portions of the additional roughening layer is narrower than the interval between the apexes of the convex portions of the first vertical roughening layer.

(6)如(1)至(5)中任一項之引線框架材,其特徵在於:上述垂直粗化層之成分由銅或銅合金構成。 (6) The lead frame material according to any one of (1) to (5), characterized in that the composition of the vertical roughening layer is made of copper or copper alloy.

(7)如(1)至(6)中任一項之引線框架材,其特徵在於:上述附加粗化層之成分由鎳、鎳合金、鈷、鈷合金中之任一者構成。 (7) The lead frame material according to any one of (1) to (6), wherein the composition of the additional roughening layer is composed of any one of nickel, nickel alloy, cobalt, and cobalt alloy.

(8)如(1)至(7)中任一項之引線框架材,其特徵在於:上述導電性基體具有於垂直方向被粗化之垂直粗化層,並且具有附加粗化層作為該垂直粗化層之上層,進一步於附加粗化層之上層,在引線框架材之整面或局部地具有單層或複數層由鈀、鈀合金、銠、銠合金、釕、釕合金、鉑、鉑合金、銥、銥合金、金、金合金、銀、銀合金中之任一者構成的表層。 (8) The lead frame material according to any one of (1) to (7), wherein the conductive substrate has a vertical roughening layer that is roughened in a vertical direction, and has an additional roughening layer as the vertical The upper layer of the roughened layer, and the layer above the additional roughened layer, has a single layer or multiple layers on the entire surface or part of the lead frame material made of palladium, palladium alloy, rhodium, rhodium alloy, ruthenium, ruthenium alloy, platinum, platinum A surface layer composed of any one of alloy, iridium, iridium alloy, gold, gold alloy, silver, and silver alloy.

(9)一種引線框架材之製造方法,其係(1)至(8)中任一項之引線框架材之製造方法,其特徵在於:上述垂直粗化層及附加粗化層中之任一者或兩者藉由電鍍而形成。 (9) A method of manufacturing a lead frame material, which is the method of manufacturing a lead frame material according to any one of (1) to (8), characterized in that: any one of the above-mentioned vertical roughening layer and additional roughening layer Either or both are formed by electroplating.

(10)一種半導體封裝,其使用有上述(1)至(8)中任一項之引線框架材。 (10) A semiconductor package using the lead frame material of any one of (1) to (8) above.

本發明人等發現,於具有形成於導電性基體上之粗化層之引線框架材中,該所形成之粗化層由複數層粗化層構成,上述粗化層具有形成於導電性基體之垂直方向之由至少1層以上構成之垂直粗化層,並且進一步該垂直粗化層之上層亦具有至少1層以上之被粗化之附加粗化層,於上述垂直粗化層及附加粗化層各自所具有之凹凸中,上述垂直粗化層之相鄰凸部之頂點的間隔與上述附加粗化層之相鄰凸部之頂點的間隔不同,藉此樹脂不僅滲入基體之垂直方向,亦滲入水平方向,不僅藉由如先前之粗 化處理使表面積增大,而且藉由基於附加粗化層之楔入作用,與樹脂之機械性接合強度顯著增大。結果獲得先前以來無法耐受之樹脂之高溫高濕密接性,例如即便於85℃、85%之環境下經過168小時之高溫高濕環境下,亦可大幅度抑制引線框架材與樹脂之間之間隙之產生,獲得優異之樹脂密接性。 The inventors of the present invention have found that in a lead frame material having a roughened layer formed on a conductive substrate, the formed roughened layer is composed of a plurality of roughened layers, and the roughened layer has a surface formed on the conductive substrate. A vertical roughening layer composed of at least one or more layers in the vertical direction, and further the upper layer of the vertical roughening layer also has at least one or more additional roughening layers that are roughened, in the vertical roughening layer and the additional roughening In the unevenness of each layer, the interval between the apexes of the adjacent protrusions of the vertical roughening layer is different from the interval between the apexes of the adjacent protrusions of the additional roughening layer, whereby the resin not only penetrates into the vertical direction of the substrate, but also Penetrate into the horizontal direction, not only by being as thick as before The chemical treatment increases the surface area, and through the wedging effect based on the additional roughening layer, the mechanical bonding strength with the resin is significantly increased. As a result, the high-temperature and high-humidity adhesion of the resin that could not be tolerated before is obtained. For example, even in a high-temperature and high-humidity environment of 168 hours at 85°C and 85%, the lead frame material and the resin can be greatly suppressed The generation of gaps provides excellent resin adhesion.

1‧‧‧導電性基體 1‧‧‧Conductive substrate

2‧‧‧垂直粗化層 2‧‧‧Vertical roughening layer

3‧‧‧附加粗化層 3‧‧‧Additional roughening layer

4‧‧‧表層 4‧‧‧Surface

4'‧‧‧第一表層 4'‧‧‧First surface

5‧‧‧第二表層 5‧‧‧Second surface

6‧‧‧垂直粗化層之間隔 6‧‧‧Interval between vertical roughening layers

7‧‧‧附加粗化層之間隔 7‧‧‧Additional roughening layer interval

8‧‧‧基體剖面長度 8‧‧‧Substrate section length

9‧‧‧最表層剖面長度 9‧‧‧Extreme surface section length

9a‧‧‧最表層剖面長度之總長 9a‧‧‧Total length of the section length of the outermost layer

11‧‧‧導電性基體(銅、銅合金、鐵、鐵合金等) 11‧‧‧Conductive substrate (copper, copper alloy, iron, iron alloy, etc.)

12‧‧‧銅基底鍍覆層 12‧‧‧Copper base plating layer

13‧‧‧鎳粗化鍍覆層 13‧‧‧Nickel roughening coating

14‧‧‧表層(沿鎳粗化鍍覆層生長) 14‧‧‧Surface layer (grows along the nickel roughening coating)

圖1係本發明之一形態之概略剖面示意圖。 Figure 1 is a schematic cross-sectional view of one aspect of the present invention.

圖2係本發明之另一形態之概略剖面示意圖。 Figure 2 is a schematic cross-sectional view of another aspect of the present invention.

圖3係本發明之進一步另一形態之概略剖面示意圖。 Fig. 3 is a schematic cross-sectional view of another aspect of the present invention.

圖4係本發明之一形態之概略剖面示意圖之放大圖。 Fig. 4 is an enlarged view of a schematic cross-sectional view of an aspect of the present invention.

圖5係本發明之圖4所示之上述一形態之概略剖面示意圖之放大圖。 Fig. 5 is an enlarged view of a schematic cross-sectional view of the above-mentioned form shown in Fig. 4 of the present invention.

圖6係先前之一形態之概略剖面示意圖。圖6中,11表示導電性基體,12表示銅基底鍍覆層,13表示鎳粗化鍍覆層,14表示表層。 Figure 6 is a schematic cross-sectional view of the previous form. In FIG. 6, 11 represents a conductive substrate, 12 represents a copper base plating layer, 13 represents a nickel roughened plating layer, and 14 represents a surface layer.

(垂直粗化層) (Vertical roughening layer)

根據本發明,首先具有相對於導電性基體(以下簡稱為基體)垂直之方向之粗化層、即垂直粗化層。該引線框架材所具有之粗化層由複數層垂直粗化層構成,較佳為具有一層垂直粗化層。該垂直粗化層表示形成於相對於基體之主表面垂直之方向之粗化層,意指大致形成於基體之主表面垂線方向者。較佳為自相對於基體為縱向之垂直剖面觀察時,該粗化層凸部之(峰之頂點之)生長方向形成於自基體主表面之垂線起20°以內。該垂直 粗化層為成為用於賦予樹脂密接性之基礎之粗化層,例如較佳為由銅、銅合金、鎳、鎳合金、鈷、鈷合金等構成。尤其就提高對於基體與上層之皮膜(下述之附加粗化層等)之密接性之觀點而言,更佳為由銅或銅合金構成之垂直粗化層。作為銅合金、鎳合金、鈷合金,可列舉銅-錫合金作為銅合金,鎳-鋅合金作為鎳合金,鈷-錫合金作為鈷合金等。 According to the present invention, first, there is a roughened layer in a direction perpendicular to the conductive substrate (hereinafter referred to as the substrate), that is, a vertical roughened layer. The roughened layer of the lead frame material is composed of a plurality of vertical roughened layers, and preferably has one vertical roughened layer. The vertical roughened layer refers to a roughened layer formed in a direction perpendicular to the main surface of the substrate, and means that is formed approximately in the direction perpendicular to the main surface of the substrate. Preferably, when viewed from a vertical cross section with respect to the longitudinal direction of the substrate, the growth direction of the convex portion of the roughened layer (the apex of the peak) is formed within 20° from the perpendicular to the main surface of the substrate. The vertical The roughened layer is a roughened layer that serves as a basis for imparting adhesiveness to the resin, and is preferably composed of copper, copper alloy, nickel, nickel alloy, cobalt, cobalt alloy, or the like, for example. In particular, from the viewpoint of improving the adhesion between the substrate and the upper film (additional roughening layer etc. below), the vertical roughening layer made of copper or copper alloy is more preferable. Examples of copper alloys, nickel alloys, and cobalt alloys include copper-tin alloys as copper alloys, nickel-zinc alloys as nickel alloys, and cobalt-tin alloys as cobalt alloys.

(垂直粗化層之膜厚) (The thickness of the vertical roughening layer)

再者,垂直粗化層之厚度並無特別限制,但存在膜厚越大基於粗化之凹凸越大之傾向。因此,為了增大粗化形狀,垂直粗化層之被覆厚度較佳為0.2μm以上,更佳為0.5μm以上,再更佳為0.8μm以上。另一方面,若被覆厚度超過3μm,則有搬送時之粗化層之脫落、所謂「落粉」變多之擔憂。因此,垂直粗化層之被覆厚度較佳為3μm以下,更佳為2μm以下,再更佳為1.5μm以下。又,若考慮製造步驟之繁雜性等,則垂直粗化層之層數較佳為2層以內。再者,該等被覆厚度表示非局部判斷而至少藉由螢光X射線法(例如SII公司製造SFT9400(商品名)等膜厚測定裝置)以準直器徑0.2mm以上測定任意3點而得之平均膜厚。 Furthermore, the thickness of the vertical roughening layer is not particularly limited, but there is a tendency that the larger the film thickness, the larger the unevenness due to roughening. Therefore, in order to increase the roughened shape, the coating thickness of the vertical roughened layer is preferably 0.2 μm or more, more preferably 0.5 μm or more, and still more preferably 0.8 μm or more. On the other hand, if the thickness of the coating exceeds 3 μm, there is a concern that the roughened layer may fall off during transportation, and the so-called "dust falling" may increase. Therefore, the coating thickness of the vertical roughening layer is preferably 3 μm or less, more preferably 2 μm or less, and still more preferably 1.5 μm or less. In addition, considering the complexity of the manufacturing steps, etc., the number of vertical roughening layers is preferably within 2 layers. In addition, these coating thicknesses represent non-local judgments and can be obtained by measuring at least three arbitrary points with a collimator diameter of 0.2 mm or more by the fluorescent X-ray method (for example, a film thickness measuring device such as SFT9400 (trade name) manufactured by SII) The average film thickness.

(附加粗化層) (Additional roughening layer)

又,根據本發明,於垂直粗化層之上層具有由一層以上構成之附加粗化層,較佳為具有一層附加粗化層。藉由該附加粗化層之存在,可賦予僅利用先前之凹凸粗化(例如,參照圖6)則無法達成之水準之樹脂密接性。該附加粗化層係於垂直粗化層之上層,較佳為以峰與峰之間隔較垂直粗化層變窄(變小)之方式粗化而成之部分。附加粗化層係為了對於樹脂賦予楔入作用而形成。附加粗化層較佳為儘可能形成以偏離基體之90°垂線±20° 以上之角度所形成之部分。即,較佳為附加粗化層相對於基體之90°垂線更大程度地傾斜。藉此,不僅一層之定錨效果增大,對於因高溫環境下或高濕環境所致之樹脂之膨脹收縮亦不僅可二維追隨,亦可三維追隨,故而樹脂密接性較以往得以改善。附加粗化層較佳為由與垂直粗化層之密接性良好之材料構成,例如可列舉銅、銅合金、鎳、鎳合金、鈷、鈷合金、銀、銀合金等。其中,就亦可賦予作為防止基體成分之擴散之障壁層之功能之方面而言,較佳為鎳、鎳合金、鈷、鈷合金中之任一者。再者,附加粗化層較佳為由與垂直粗化層不同之成分構成。作為銅合金、鎳合金、鈷合金、銀合金,可列舉銅-錫合金作為銅合金,鎳-鋅合金作為鎳合金,鈷-錫合金作為鈷合金,銀-錫合金作為銀合金等。 Furthermore, according to the present invention, the layer above the vertical roughening layer has an additional roughening layer composed of one or more layers, preferably one additional roughening layer. With the presence of the additional roughening layer, it is possible to impart resin adhesion to a level that cannot be achieved only by the previous roughening of the unevenness (for example, refer to FIG. 6). The additional roughening layer is a layer above the vertical roughening layer, and is preferably a part that is roughened in such a way that the peak-to-peak interval is narrower (smaller) than the vertical roughening layer. The additional roughening layer is formed to impart a wedging effect to the resin. The additional roughening layer is preferably formed as much as possible to deviate from the 90° perpendicular to the substrate ±20° The part formed by the above angle. That is, it is preferable that the additional roughening layer is more inclined with respect to the 90° perpendicular to the base. As a result, not only the anchoring effect of the first layer is increased, but the expansion and contraction of the resin caused by the high temperature environment or high humidity environment can also be followed not only in two dimensions but also in three dimensions. Therefore, the resin adhesion is improved compared with the past. The additional roughening layer is preferably made of a material with good adhesion to the vertical roughening layer, and examples thereof include copper, copper alloy, nickel, nickel alloy, cobalt, cobalt alloy, silver, and silver alloy. Among them, it is preferably any one of nickel, nickel alloy, cobalt, and cobalt alloy in terms of imparting a function as a barrier layer to prevent diffusion of the matrix component. Furthermore, the additional roughening layer is preferably composed of a different composition from the vertical roughening layer. Examples of copper alloys, nickel alloys, cobalt alloys, and silver alloys include copper-tin alloys as copper alloys, nickel-zinc alloys as nickel alloys, cobalt-tin alloys as cobalt alloys, and silver-tin alloys as silver alloys.

(附加粗化層之膜厚) (Film thickness of additional roughening layer)

附加粗化層之厚度並無特別限制,但存在膜厚越大基於粗化之凹凸越大之傾向。另一方面,若過厚,則有填埋垂直粗化層之凹凸之擔憂。因此,為垂直粗化層被覆厚度之1/10以上,較佳為1/5以上較佳。另一方面,作為附加粗化層之上限被覆厚度,較佳為最大為與垂直粗化層之被覆厚度同等厚度以下,進一步更佳為垂直粗化層厚之2/3以下。 The thickness of the additional roughening layer is not particularly limited, but there is a tendency that the larger the film thickness, the larger the unevenness due to roughening. On the other hand, if it is too thick, the irregularities of the vertical roughened layer may be buried. Therefore, it is 1/10 or more of the coating thickness of the vertical roughening layer, preferably 1/5 or more. On the other hand, the upper limit of the coating thickness of the additional roughening layer is preferably at most the same thickness as the coating thickness of the vertical roughening layer, and more preferably 2/3 or less of the vertical roughening layer thickness.

(垂直粗化層與附加粗化層之形狀(厚度)) (Shape (thickness) of the vertical roughening layer and the additional roughening layer)

又,因本發明中所獲得之粗化層之形狀利用了基於附加粗化層之楔入作用,故而利用根據表面之粗度測定則無法表現其程度。因此,可測定自剖面觀察時之所有皮膜層(上述之各粗化層)形成後之最表層之剖面的線段長度(最表層之剖面之線段長度之總長),將其相對於導電性基體剖面之線段長度之比率的值用作長度指標。於將導電性基體剖面之線段長度(B) 設為1時,最表層剖面之線段長度(最表層剖面線段長度)(A)之比率(A/B)之值較佳為1.2倍以上,更佳為2倍以上。藉此,比表面積增大,而與樹脂之密接性增大。另一方面,於將導電性基體剖面之線段長度(B)設為1時,若最表層剖面之線段長度(A)之比(A/B)之值超過4倍左右,則有易於落粉之擔憂,因此較佳為4倍以下,更佳為3.5倍以下。 In addition, since the shape of the roughened layer obtained in the present invention utilizes the wedging effect based on the additional roughened layer, its degree cannot be expressed by measurement of the roughness of the surface. Therefore, it is possible to measure the line segment length (total length of the line segment length of the cross section of the outermost layer) of the cross section of the outermost layer after all the film layers (the above-mentioned roughened layers) are formed during the cross-sectional observation, and compare it to the cross-section of the conductive substrate The value of the ratio of the length of the line segment is used as a length indicator. The length of the line section of the conductive substrate (B) When set to 1, the value of the ratio (A/B) of the line segment length of the outermost surface section (the line segment length of the outermost surface section) (A) is preferably 1.2 times or more, more preferably 2 times or more. As a result, the specific surface area increases, and the adhesion to the resin increases. On the other hand, when the line segment length (B) of the conductive substrate cross-section is set to 1, if the value of the ratio (A/B) of the line segment length (A) of the outermost cross-section exceeds about 4 times, the powder will fall off easily. Therefore, it is preferably 4 times or less, and more preferably 3.5 times or less.

於本發明中,可利用垂直粗化層與附加粗化層改善與密封材之樹脂密接性。 In the present invention, the vertical roughening layer and the additional roughening layer can be used to improve the resin adhesion to the sealing material.

(各粗化層之形狀) (Shape of each roughening layer)

再者,於本發明中因形成垂直粗化層與附加粗化層,故而僅根據最表層之測定則無法掌握各自之凹凸,而藉由自剖面進行觀察,能夠觀察各粗化層之相鄰凸部之頂點間隔(各粗化層之凹凸)。關於此事,例如可藉由Focused Ion Beam:FIB加工任意之粗化層剖面後,藉由Scanning Ion Mycroscope:SIM圖像並根據結晶粒徑之對比度進行確認,各粗化層之相鄰凸部之頂點的間隔可根據標度進行判斷。於各粗化層中,將垂直粗化層及附加粗化層各自相鄰之各凸部之頂點彼此之平均間隔稱為「垂直粗化層之間隔(凸部之間隔)」及「附加粗化層之間隔(凸部之間隔)」時,垂直粗化層之間隔與附加粗化層之間隔不同。較佳為垂直粗化層之間隔大於附加粗化層之間隔。藉此,因樹脂容易進入垂直粗化層之間,故而可進一步提高樹脂密接性。作為該間隔之比率,較佳為附加粗化層之間隔為垂直粗化層之間隔之1/2以下,更佳為1/4以下。另一方面,若超過1/20,則附加粗化層變得過細而密接力持續降低,故而較佳為1/20以上,更佳為1/15以上。再者,於垂直粗化層有複數層時,將成為其最大間隔之垂直粗 化層設為其對象,又,於附加粗化層有複數層時,將形成於其最表面之附加粗化層設為其對象。又,作為該各粗化層之間隔比,係指算出自剖面觀察之任意5處相鄰之凸與凸之間隔之平均值而得者。 Furthermore, in the present invention, the vertical roughened layer and the additional roughened layer are formed, so the respective concavities and convexities cannot be grasped only by the measurement of the outermost layer, but by observing from the cross section, the adjacent roughened layers can be observed The distance between the apexes of the convex part (concave and convex of each roughened layer). Regarding this matter, for example, after processing any roughened layer section by Focused Ion Beam: FIB, it can be confirmed by Scanning Ion Mycroscope: SIM image based on the contrast of the crystal grain size. The adjacent convex portions of each roughened layer The interval of the vertices can be judged according to the scale. In each roughening layer, the average interval between the vertices of the adjacent convex portions of the vertical roughening layer and the additional roughening layer is called "the interval between the vertical roughening layer (the interval between the convex portions)" and the "additional roughening layer". In the case of "interval between the raised layers", the interval between the vertical roughening layer and the interval between the additional roughening layer are different. Preferably, the interval between the vertical roughening layer is larger than the interval between the additional roughening layer. Thereby, since the resin easily enters between the vertical roughened layers, the resin adhesion can be further improved. As the ratio of the interval, the interval of the additional roughening layer is preferably 1/2 or less of the interval of the vertical roughening layer, more preferably 1/4 or less. On the other hand, if it exceeds 1/20, the additional roughening layer becomes too fine and the adhesive force continues to decrease, so it is preferably 1/20 or more, and more preferably 1/15 or more. Furthermore, when there are multiple vertical roughening layers, it will be the vertical roughness of the maximum interval. The roughened layer is the target, and when the additional roughened layer has a plurality of layers, the additional roughened layer formed on the outermost surface is the target. In addition, as the interval ratio of each roughened layer, it is obtained by calculating the average value of the interval between the protrusions and the protrusions at any five adjacent positions in the cross-sectional observation.

於垂直粗化層中,藉由改變電流密度或被覆厚度,可使粗化層之結晶粒徑變化而控制附加粗化層之凸凸間隔。藉由分別對不同成分之粗化層進行粗化鍍覆,可控制凸凸之間隔比之變化。具體而言,各粗化層之厚度與平均間隔可按照如下方式分開設定:電流密度越高間隔越窄,電流密度越低間隔越寬。 In the vertical roughening layer, by changing the current density or the coating thickness, the crystal grain size of the roughening layer can be changed to control the convex-convex spacing of the additional roughening layer. By performing roughening plating on the roughening layers of different compositions, the variation of the interval ratio of the protrusions can be controlled. Specifically, the thickness and average interval of each roughening layer can be set separately as follows: the higher the current density, the narrower the interval, and the lower the current density, the wider the interval.

(導電性基體) (Conductive substrate)

又,作為所使用之金屬基體(導電性基體)成分,較佳為銅或銅合金、鐵或鐵合金、鋁或鋁合金等,其中,較佳為導電率良好之銅或銅合金。 In addition, the metal matrix (conductive matrix) component used is preferably copper or copper alloy, iron or iron alloy, aluminum or aluminum alloy, etc. Among them, copper or copper alloy having good electrical conductivity is preferable.

例如作為銅合金之一例,可使用作為CDA(Copper Development Association)揭示合金之「C14410(Cu-0.15Sn、古河電氣工業(股)製造、商品名:EFTEC(註冊商標)-3)」、「C19400(Cu-Fe系合金材料、Cu-2.3Fe-0.03P-0.15Zn)」、「C18045(Cu-0.3Cr-0.25Sn-0.5Zn、古河電氣工業(股)製造、商品名:EFTEC-64T)」等。再者,各元素前之數字之單位為質量%。因該等銅合金基體之導電率或強度分別不同,故而根據適當要求特性選定並使用,但較佳設為導電率為50%IACS以上之銅合金之條材。 For example, as an example of a copper alloy, "C14410 (Cu-0.15Sn, manufactured by Furukawa Electric Co., Ltd., trade name: EFTEC (registered trademark)-3)", "C19400", which is an alloy disclosed by CDA (Copper Development Association), can be used. (Cu-Fe-based alloy material, Cu-2.3Fe-0.03P-0.15Zn)", "C18045 (Cu-0.3Cr-0.25Sn-0.5Zn, manufactured by Furukawa Electric Co., Ltd., trade name: EFTEC-64T) "Wait. Furthermore, the unit of the number before each element is mass%. Since the electrical conductivity or strength of the copper alloy substrates are different, they are selected and used according to the appropriate required characteristics, but it is preferable to set the copper alloy strips with electrical conductivity above 50% IACS.

又,作為鐵或鐵合金,例如使用42合金(Fe-42mass%Ni)或不鏽鋼等。該等鐵合金基體之導電率並不那麼高,但可應用於對導電率並無那麼高的要求,而以電信號之傳輸為目的之引線框架。 Moreover, as iron or iron alloy, 42 alloy (Fe-42mass%Ni), stainless steel, etc. are used, for example. The conductivity of these ferroalloy substrates is not so high, but it can be applied to lead frames that do not have such high requirements for conductivity and are used for the transmission of electrical signals.

又,作為鋁或鋁合金,例如使用A5052等。 In addition, as aluminum or aluminum alloy, for example, A5052 or the like is used.

基體之厚度並無特別限制,通常為0.05mm~2mm,較佳為0.1mm~1mm。 The thickness of the substrate is not particularly limited, and is usually 0.05 mm to 2 mm, preferably 0.1 mm to 1 mm.

(粗化鍍覆之上層、表層) (Roughened plating upper layer and surface layer)

又,根據本發明,為了對附加粗化層之更上層(表層)賦予引線框架之焊料潤濕性或線結合(wire bonding)性、晶粒結著(die bonding)性等特性,亦可於引線框架材料之整面或局部地形成單層或複數層由鈀、鈀合金、銠、銠合金、釕、釕合金、鉑、鉑合金、銥、銥合金、金、金合金、銀、銀合金中之任一者構成之皮膜。其中,作為具有代表性之層構成,可列舉自粗化層側至表面依序為Pd/Au被覆、Pd/Ag/Au被覆、Pd/Rh/Au被覆、Ru/Pd/Au被覆等。該等被覆之厚度並無特別限制,但若過厚則存在填埋粗化層凹凸而無法發揮功能之可能性,或存在因以貴金屬為主而導致成本增加之可能性。於本文中,「以貴金屬為主」係指於構成成分之中50質量%以上為貴金屬。就該等而言,總被覆厚度較佳為1μm以下。作為鈀合金、銠合金、釕合金、鉑合金、銥合金、金合金、銀合金,可列舉鈀-銀合金作為鈀合金,銠-鈀合金作為銠合金,釕-銥合金作為釕合金,鉑-金合金作為鉑合金,銥-釕合金作為銥合金,金-銀合金作為金合金,銀-錫合金作為銀合金等。 In addition, according to the present invention, in order to impart the solder wettability, wire bonding, die bonding, and other characteristics of the lead frame to the upper layer (surface layer) of the additional roughening layer, The entire surface or part of the lead frame material is formed into a single layer or multiple layers made of palladium, palladium alloy, rhodium, rhodium alloy, ruthenium, ruthenium alloy, platinum, platinum alloy, iridium, iridium alloy, gold, gold alloy, silver, silver alloy A film composed of any one of them. Among them, as a representative layer structure, Pd/Au coating, Pd/Ag/Au coating, Pd/Rh/Au coating, Ru/Pd/Au coating, etc., in order from the roughened layer side to the surface can be cited. The thickness of the coating is not particularly limited, but if it is too thick, there is a possibility that the roughened layer may be buried in unevenness and cannot function, or the cost may increase due to precious metals. In this article, "predominantly precious metals" means that more than 50% by mass of the constituent components are precious metals. In terms of these, the total coating thickness is preferably 1 μm or less. Palladium alloys, rhodium alloys, ruthenium alloys, platinum alloys, iridium alloys, gold alloys, and silver alloys include palladium-silver alloys as palladium alloys, rhodium-palladium alloys as rhodium alloys, ruthenium-iridium alloys as ruthenium alloys, and platinum- Gold alloy is used as platinum alloy, iridium-ruthenium alloy is used as iridium alloy, gold-silver alloy is used as gold alloy, silver-tin alloy is used as silver alloy and so on.

(粗化層之被覆部) (Coated part of roughened layer)

再者,本發明中之粗化層之形成部位只要形成有被樹脂塑模之部分之至少一部分即可。例如較佳為引線框架被樹脂塑模之部分之至少1/5以上,更佳為形成為1/2以上之面積,藉此發揮密接性提高效果。最佳為於被樹脂塑模之整面加以實施。作為該局部設置之粗化層之形狀,能夠採用 條狀、點狀、環狀等各種形態。進一步,於如僅單面進行樹脂塑模之製品中,例如亦能夠僅於單面形成上述粗化層。 In addition, the formation site of the roughened layer in the present invention only needs to be formed with at least a part of the resin molded part. For example, it is preferable to form at least 1/5 or more of the part of the lead frame molded by resin, and it is more preferable to form it to an area of 1/2 or more, thereby exhibiting the effect of improving adhesion. It is best to implement it on the entire surface of the resin mold. As the shape of the partially arranged roughening layer, it is possible to adopt Various forms such as strips, dots, and rings. Furthermore, in a product in which resin molding is performed on only one side, for example, the roughened layer can be formed on only one side.

又,根據本發明,藉由電流密度或攪拌可相對容易地控制粗化鍍覆且簡便,因此於形成垂直粗化層及附加粗化層中之任一者或兩者時,較佳為利用電鍍法形成。進一步,就生產性之觀點而言,更佳為藉由濕式鍍覆形成兩者。 In addition, according to the present invention, the roughening plating can be controlled relatively easily by current density or stirring and is simple. Therefore, when either or both of the vertical roughening layer and the additional roughening layer are formed, it is preferable to use Formed by electroplating. Further, from the viewpoint of productivity, it is more preferable to form both by wet plating.

以下,基於圖式詳細地說明本發明。 Hereinafter, the present invention will be explained in detail based on the drawings.

圖1係本發明之一形態之概略剖面示意圖。於導電性基體1之上層形成有垂直粗化層2,於其更上層形成有附加粗化層3。附加粗化層3之上部利用樹脂塑模覆蓋(未圖示)。如本態樣,於如僅單面進行樹脂塑模之製品(半導體封裝)中,例如亦能夠僅於單面形成上述粗化層,當然亦可於雙面形成。 Figure 1 is a schematic cross-sectional view of one aspect of the present invention. A vertical roughening layer 2 is formed on the upper layer of the conductive substrate 1, and an additional roughening layer 3 is formed on the upper layer. The upper part of the additional roughening layer 3 is covered with a resin mold (not shown). As in this aspect, in a product (semiconductor package) in which resin molding is performed on only one side, for example, the roughened layer can be formed on only one side, and of course it can also be formed on both sides.

圖2係本發明之另一形態之概略剖面示意圖。於導電性基體1之上層形成有垂直粗化層2,於其更上層形成有附加粗化層3,進一步,為了對其表層賦予引線框架之焊料潤濕性或線結合性、晶粒結著性等特性,而於整面以單層之形式形成有由鈀、鈀合金、銠、銠合金、釕、釕合金、鉑、鉑合金、銥、銥合金、金、金合金、銀、銀合金中之任一者構成之皮膜層(表層)4。皮膜層4之上部利用樹脂塑模覆蓋(未圖示)。該皮膜層4係用以賦予引線框架之焊料潤濕性或線結合性、晶粒結著性等特性而形成之層,例如亦可局部地形成於被樹脂塑模之部分。其形狀亦可形成為條狀、點狀、環狀等。 Figure 2 is a schematic cross-sectional view of another aspect of the present invention. A vertical roughening layer 2 is formed on the upper layer of the conductive substrate 1, and an additional roughening layer 3 is formed on the upper layer, and further, in order to impart solder wettability or wire bonding properties of the lead frame to the surface layer, and grain bonding The whole surface is formed in a single layer with palladium, palladium alloy, rhodium, rhodium alloy, ruthenium, ruthenium alloy, platinum, platinum alloy, iridium, iridium alloy, gold, gold alloy, silver, silver alloy Film layer (surface layer) 4 composed of any one of them. The upper part of the film layer 4 is covered with a resin mold (not shown). The coating layer 4 is a layer formed to impart characteristics such as solder wettability, wire bonding, and die bonding properties of the lead frame, and may be partially formed, for example, on a portion molded by resin. The shape can also be formed into strips, dots, rings, etc.

圖3係本發明之進一步另一形態之概略剖面示意圖。於導電 性基體1之上層形成有垂直粗化層2,於其更上層形成有附加粗化層3,進一步,為了對其表層賦予引線框架之焊料潤濕性或線結合性、晶粒結著性等特性,以2層之形式形成有由鈀、鈀合金、銠、銠合金、釕、釕合金、鉑、鉑合金、銥、銥合金、金、金合金、銀、銀合金中之任一者構成之皮膜層4'(第一表層)及皮膜層5(第二表層)。皮膜層5之上部利用樹脂塑模覆蓋(未圖示)。此時,皮膜層4'及5由不同金屬種類形成。例如皮膜層4'較佳為Pd、Rh、Ru、Ir等,皮膜層5較佳為Au、Ag、Pt等。於圖3中,皮膜層4'及5整面地形成,但為了削減貴金屬使用量,皮膜層4'及5亦可僅形成於需要線結合或焊接等作用之部分,由此藉由省貴金屬化而採用對環境友善且低成本之形態。 Fig. 3 is a schematic cross-sectional view of another aspect of the present invention. For conductivity A vertical roughening layer 2 is formed on the upper layer of the flexible substrate 1, and an additional roughening layer 3 is formed on the upper layer, and further, in order to impart solder wettability, wire bonding, and crystal grain adhesion to the surface layer of the lead frame. Features, formed in two layers, made of any one of palladium, palladium alloy, rhodium, rhodium alloy, ruthenium, ruthenium alloy, platinum, platinum alloy, iridium, iridium alloy, gold, gold alloy, silver, and silver alloy The film layer 4'(first surface layer) and the film layer 5 (second surface layer). The upper part of the film layer 5 is covered with a resin mold (not shown). At this time, the coating layers 4'and 5 are formed of different metal types. For example, the coating layer 4'is preferably Pd, Rh, Ru, Ir, etc., and the coating layer 5 is preferably Au, Ag, Pt, etc. In FIG. 3, the coating layers 4'and 5 are formed on the entire surface. However, in order to reduce the amount of precious metals used, the coating layers 4'and 5 can also be formed only on parts that require wire bonding or welding, etc., thereby saving precious metals It adopts an environment-friendly and low-cost form.

圖4係本發明之一形態之概略剖面示意圖之放大圖,於導電性基體1之上層形成有垂直粗化層2,於其更上層形成有附加粗化層3,且該圖4係表示該垂直粗化層之間隔6與附加粗化層之間隔7之示意圖。如此,垂直粗化層2與附加粗化層3之間隔(分別為6及7)不同。又,較佳為附加粗化層之間隔7較垂直粗化層之間隔6小(窄)。其原因在於:被塑模之樹脂進入相對較大之垂直粗化層2之間隙中,藉由本發明而形成之附加粗化層3對該樹脂採取楔入作用,藉此較先前更強力地與樹脂密接,結果,對於高溫高濕等嚴酯之試驗亦可保持樹脂密接性。 Fig. 4 is an enlarged view of a schematic cross-sectional view of one aspect of the present invention. A vertical roughening layer 2 is formed on the conductive substrate 1 and an additional roughening layer 3 is formed on the upper layer, and this Fig. 4 shows the A schematic diagram of the interval 6 between the vertical roughening layer and the interval 7 between the additional roughening layer. In this way, the intervals between the vertical roughening layer 2 and the additional roughening layer 3 (6 and 7 respectively) are different. Furthermore, it is preferable that the interval 7 between the additional roughening layer is smaller (narrow) than the interval 6 between the vertical roughening layer. The reason is that the resin being molded enters the gap of the relatively large vertical roughened layer 2, and the additional roughened layer 3 formed by the present invention takes the wedging effect on the resin, thereby more powerfully and Resin adhesion, as a result, the resin adhesion can be maintained even in tests with severe esters such as high temperature and humidity.

圖5係本發明之圖4所示之上述一形態之概略剖面示意圖之放大圖,於導電性基體1之上層形成有垂直粗化層2,於其更上層形成有附加粗化層3,且該圖5係表示該導電性基體剖面線段長度8(B)與最表層之剖面線段長度9(A)之示意圖。此處,所謂最表層之剖面線段長度9係 指圖示之鋸齒狀之長度之總長(圖5所示之將鋸齒拉伸後之長度9a)。本發明中,於該最表層之剖面線段長度之總長9a(A)除以導電性基體剖面線段長度8(B)所得之值中,其比率(A/B)之值(最表層剖面線段長度之總長9a(A)除以導電性基體剖面長度8(B)所得之比之值)較佳為1.2以上,更佳為2以上,藉此比表面積增大而與樹脂之密接性增大。另一方面,若上述線段長度之比(A/B)之值超過4左右,則有易於落粉之擔憂,因此該線段長度之比(A/B)之值較佳為4以下,更佳為3.5倍以下。 5 is an enlarged view of the schematic cross-sectional view of the above-mentioned form shown in FIG. 4 of the present invention. A vertical roughening layer 2 is formed on the conductive substrate 1 and an additional roughening layer 3 is formed on the upper layer, and FIG. 5 is a schematic diagram showing the cross-sectional line length 8 (B) of the conductive substrate and the cross-sectional line length 9 (A) of the outermost layer. Here, the so-called section line length of the most surface layer is 9 series Refers to the total length of the zigzag as shown in the figure (the length 9a after the zigzag is stretched as shown in Figure 5). In the present invention, in the value obtained by dividing the total length of the section line segment length of the outermost layer 9a(A) by the section length of the conductive substrate 8(B), the value of the ratio (A/B) (length of the section line section of the outermost layer) The ratio of the total length 9a (A) divided by the cross-sectional length of the conductive substrate 8 (B)) is preferably 1.2 or more, more preferably 2 or more, whereby the specific surface area increases and the adhesion to the resin increases. On the other hand, if the value of the ratio of line segment length (A/B) exceeds about 4, it may be easy to fall off. Therefore, the value of the ratio of line segment length (A/B) is preferably 4 or less, more preferably It is 3.5 times or less.

[實施例] [Example]

以下基於實施例進一步詳細地說明本發明,但本發明並不限定於該等。 Hereinafter, the present invention will be described in further detail based on examples, but the present invention is not limited to these.

預先準備切斷為試片尺寸40mm×40mm之板厚0.2mm之表1所示之各種導電性基體,經過下述所示之陰極電解脫脂、酸洗步驟之預處理後,於發明例中形成垂直粗化層及附加粗化層。作為比較例,形成垂直粗化層後,形成普通Ni層作為附加粗化層。進一步,作為先前例,準備僅形成粗化Ni層作為粗化層者。又,作為各試樣之更上層,於附加粗化層之上層形成0.02μm之鍍Pd後,進一步於其上層形成0.01μm之鍍Au作為最表層。發明例1~15係圖3所示之形態。比較例1係於圖6所示之形態中未設置Cu基底鍍覆層12之形態。先前例1係圖6所示之形態。各粗化層之厚度與平均間隔可按照如下方式分開設定:電流密度越高間隔越窄,電流密度越低間隔越寬。 The various conductive substrates shown in Table 1 with a test piece size of 40mm×40mm and a thickness of 0.2mm are prepared in advance. After pretreatment of the cathodic electrolytic degreasing and pickling steps shown below, they are formed in the invention example Vertical roughening layer and additional roughening layer. As a comparative example, after forming the vertical roughened layer, a normal Ni layer was formed as an additional roughened layer. Furthermore, as the previous example, it is prepared to form only a roughened Ni layer as a roughened layer. In addition, as the upper layer of each sample, after forming a 0.02 μm Pd plating on the upper layer of the additional roughening layer, a 0.01 μm Au plating was further formed on the upper layer as the outermost layer. Invention Examples 1 to 15 are the forms shown in FIG. 3. Comparative Example 1 is a form in which the Cu base plating layer 12 is not provided in the form shown in FIG. 6. The previous example 1 is the form shown in FIG. 6. The thickness and average interval of each roughening layer can be set separately as follows: the higher the current density, the narrower the interval, and the lower the current density, the wider the interval.

於垂直粗化層,藉由改變電流密度或被覆厚度,使垂直粗化層之結晶 粒徑變化而控制附加粗化層之凸凸間隔。藉由分別對不同成分之層進行粗化鍍覆,凸凸之間隔發生變化,藉此控制間隔(比率)。可分別為粗化厚度根據處理時間設定,平均間隔根據電流密度設定。又,測定最表層剖面線段長度(最表層剖面線段長度之總長)(A)與導電性基體剖面線段長度(B),求出其比率(最表層剖面線段長度之總長9a(A)除以導電性基體剖面線段長度8(B)所得之值)(A/B)之值。將其於表中示為「表層剖面線段長度比」。 In the vertical roughening layer, the crystallization of the vertical roughening layer is achieved by changing the current density or coating thickness The particle size changes to control the convex-convex spacing of the additional roughened layer. By performing roughening plating on the layers of different compositions, the interval between the protrusions is changed, thereby controlling the interval (ratio). The roughening thickness can be set according to the processing time, and the average interval can be set according to the current density. In addition, measure the length of the outermost section line segment (the total length of the outermost section line segment) (A) and the conductive substrate section line segment length (B), and find the ratio (the total length of the outermost section line section length 9a (A) divided by the conductive The length of the cross section of the sex matrix is 8 (B) value) (A/B) value. Show it in the table as "Surface Section Line Segment Length Ratio".

(預處理條件) (Pretreatment conditions)

[陰極電解脫脂] [Cathode Electrolytic Degreasing]

脫脂液:NaOH 60g/升 Degreasing liquid: NaOH 60g/liter

脫脂條件:2.5A/dm2、溫度60℃、脫脂時間60秒 Degreasing conditions: 2.5A/dm 2 , temperature 60℃, degreasing time 60 seconds

[酸洗] [Pickling]

酸洗液:10%硫酸 Pickling liquid: 10% sulfuric acid

酸洗條件:30秒、浸漬、室溫 Pickling conditions: 30 seconds, immersion, room temperature

(粗化鍍覆條件) (Roughening plating conditions)

[粗化鍍Cu(形成垂直粗化層)] [Roughened Cu plating (forms vertical roughening layer)]

鍍覆液:硫酸銅:銅濃度為5~10g/升、硫酸:30~120g/升、鉬酸銨:Mo金屬為0.1~5.0g/升 Plating solution: copper sulfate: copper concentration is 5~10g/liter, sulfuric acid: 30~120g/liter, ammonium molybdate: Mo metal is 0.1~5.0g/liter

鍍覆條件:浴溫20~60℃、電流密度10~60A/dm2 Plating conditions: bath temperature 20~60℃, current density 10~60A/dm 2

[粗化鍍Ni(形成附加粗化層)] [Roughening Ni plating (form additional roughening layer)]

鍍覆液:世界金屬(World Metal)股份有限公司製造WDB-321(商品名) Plating solution: WDB-321 (trade name) manufactured by World Metal Co., Ltd.

鍍覆條件:電流密度8A/dm2、溫度70℃ Plating conditions: current density 8A/dm 2 , temperature 70℃

(普通中間鍍覆條件) (General intermediate plating conditions)

[鍍Ni](普通鍍Ni) [Ni Plating] (Normal Ni Plating)

鍍覆液:Ni(SO3NH2)2。4H2O 500g/升、NiCl2 30g/升、H3BO3 30g/升 Plating solution: Ni(SO 3 NH 2 ) 2 . 4H 2 O 500g/liter, NiCl 2 30g/liter, H 3 BO 3 30g/liter

鍍覆條件:電流密度10A/dm2、溫度50℃ Plating conditions: current density 10A/dm 2 , temperature 50℃

[鍍Co(形成附加粗化層)] [Co Plating (form additional roughening layer)]

鍍覆液:Co(SO3NH2)2‧4H2O 500g/升、CoCl2 30g/升、H3BO3 30g/升 Plating solution: Co(SO 3 NH 2 ) 2 ‧4H 2 O 500g/liter, CoCl 2 30g/liter, H 3 BO 3 30g/liter

鍍覆條件:電流密度10A/dm2、溫度50℃ Plating conditions: current density 10A/dm 2 , temperature 50℃

(鍍Pd條件) (Pd plating conditions)

[鍍Pd(形成第一表層)] [Pd plating (form the first surface layer)]

鍍覆液:Pd(NH3)2Cl2 45g/升、NH4OH 90毫升/升、(NH4)2SO4 50g Plating solution: Pd(NH 3 ) 2 Cl 2 45g/liter, NH 4 OH 90 ml/liter, (NH 4 ) 2 SO 4 50g

/升、Para Sigma光澤劑(商品名、松田產業股份有限公司製造)10毫升/升 /L, Para Sigma gloss agent (trade name, manufactured by Matsuda Industrial Co., Ltd.) 10ml/L

鍍覆條件:電流密度5A/dm2、溫度60℃ Plating conditions: current density 5A/dm 2 , temperature 60℃

(鍍Au條件) (Au plating conditions)

[鍍Au(形成第二表層)] [Au plating (form second surface layer)]

鍍覆液:KAu(CN)2 14.6g/升、C6H8O7 150g/升、K2C6H4O7 180g/升 Plating solution: KAu(CN) 2 14.6g/liter, C 6 H 8 O 7 150g/liter, K 2 C 6 H 4 O 7 180g/liter

鍍覆條件:溫度40℃ Plating conditions: temperature 40℃

對於分別製作之發明例、比較例、先前例之試片,藉由上瀧 精機公司製造之轉注成形(transfer mold)試驗裝置(製品名:Model FTS)將樹脂塑模形成為接觸面積為4mm2之布丁狀試片。將該試片投入高溫高濕試驗(85℃、85%RH、168小時),對該試片實施樹脂密接性評價等。將結果示於表1。 For the test pieces of the invention example, the comparative example, and the previous example produced separately, the resin mold was formed into a contact area of 4mm 2 by a transfer mold test device (product name: Model FTS) manufactured by Uitaki Seiki Co., Ltd. The pudding-like test piece. This test piece was put into a high temperature and high humidity test (85° C., 85% RH, 168 hours), and the test piece was subjected to resin adhesion evaluation and the like. The results are shown in Table 1.

(樹脂密接性評價) (Evaluation of resin adhesion)

評價樹脂:G630L、住友電木公司製造(商品名) Evaluation resin: G630L, manufactured by Sumitomo Bakelite Co., Ltd. (trade name)

評價條件: Evaluation conditions:

裝置:4000Plus、Nordson‧Advanced‧Technology公司製造(商品名)、 Device: 4000Plus, manufactured by Nordson‧Advanced‧Technology (trade name),

荷重元:50kg Load yuan: 50kg

測定範圍:10kg Measuring range: 10kg

測試速度:100μm/s Testing speed: 100μm/s

測試高度:10μm Test height: 10μm

「A」(優)表示平均為10kgf/mm2以上之情形,「B」(良)表示平均為5kgf/mm2以上且未達10kgf/mm2之情形,「D」(不合格)表示平均為0kgf/mm2以上且未達5kgf/mm2之情形。 "A" (excellent) means an average of 10kgf/mm 2 or more, "B" (good) means an average of 5kgf/mm 2 or more and less than 10kgf/mm 2 , "D" (unqualified) means an average In the case of 0kgf/mm 2 or more and less than 5kgf/mm 2 .

(落粉性評價) (Evaluation of falling powder)

藉由目測進行官能評價。「A」(優)表示未確認到落粉之情形,「B」(良)表示產生較少落粉之情形,「C」(合格)表示產生稍多落粉之情形,「D」(不合格)表示產生非常多落粉之情形。A~C為供實用之等級。 Sensory evaluation was performed by visual inspection. "A" (excellent) means that no powder fall is confirmed, "B" (good) means less powder fall, "C" (pass) indicates a little more powder fall, "D" (unqualified) ) Indicates a situation where a lot of powder falling occurs. A~C are practical grades.

(平均間隔之評價) (Evaluation of average interval)

作為各粗化層之間隔之比,於自垂直剖面利用掃描式電子顯微鏡(SEM)所觀察之圖像中確定任意之各層之凸部,測定自此處向右方向連 續10處之相鄰凸與凸之間隔(頂點間隔),根據其平均值求出比。又,所謂間隔比(附加/垂直)係指算出附加粗化層之間隔相對於垂直粗化層之間隔之比率所得之值。再者,各凸凸間隔之測定如圖4所示,取藉由上述垂直剖面觀察所確認之凸部頂點與相鄰凸部頂點之間隔(垂直粗化層之間隔6、附加粗化層之間隔7)之平均值,將「平均間隔」示於表1。又,於條之TD方向大致10等分之各部位進行SEM觀察,根據所獲得之SEM圖像測定最表層之剖面之線段長度(最表層之剖面之線段長度之總長)(A)與導電性基體剖面之線段長度(B),求出其比率(最表層之剖面之線段長度之總長9a(A)除以導電性基體剖面之線段長度8(B)所得之值)(A/B)之值。將其於表中示為「表層剖面線段長度比」。 As the ratio of the interval between each roughened layer, the convex part of each layer is determined in the image observed by the scanning electron microscope (SEM) from the vertical section, and the measurement is measured from here to the right Continuing 10 adjacent convex and convex intervals (vertex interval), calculate the ratio from the average value. In addition, the so-called spacing ratio (additional/vertical) refers to a value obtained by calculating the ratio of the spacing of the additional roughening layer to the spacing of the vertical roughening layer. Furthermore, the measurement of the interval between each convexity is shown in Figure 4, taking the interval between the apex of the convex part and the apex of the adjacent convex part confirmed by the above-mentioned vertical cross-sectional observation (the interval between the vertical roughening layer 6, the additional roughening layer For the average value of interval 7), the "average interval" is shown in Table 1. In addition, perform SEM observation on approximately 10 equal parts of the strip in the TD direction, and determine the line segment length of the outermost cross section (the total length of the line segment length of the outermost cross section) (A) and conductivity based on the obtained SEM image The line segment length (B) of the cross-section of the substrate, and the ratio (the total length of the line segment length of the outermost cross-section 9a(A) divided by the line segment length 8(B) of the conductive substrate cross-section is the value) (A/B) value. Show it in the table as "Surface Section Line Segment Length Ratio".

Figure 105134728-A0202-12-0018-1
Figure 105134728-A0202-12-0018-1

1‧‧‧導電性基體 1‧‧‧Conductive substrate

2‧‧‧垂直粗化層 2‧‧‧Vertical roughening layer

3‧‧‧附加粗化層 3‧‧‧Additional roughening layer

Claims (9)

一種引線框架材,於導電性基體上具有粗化層,其特徵在於:該粗化層由複數層粗化層構成,該粗化層於導電性基體之垂直方向具有由至少1層構成之垂直粗化層,並且進一步於該垂直粗化層之上層具有至少1層以上之附加粗化層,於該垂直粗化層及附加粗化層各自所具有之凹凸之中,該垂直粗化層之相鄰凸部之頂點的間隔與該附加粗化層之相鄰凸部之頂點的間隔不同;該引線框架材其最表層剖面之線段長度(A)與導電性基體剖面之線段長度(B)之比(A/B)的值為1.2以上且4以下。 A lead frame material having a roughened layer on a conductive substrate, characterized in that the roughened layer is composed of a plurality of roughened layers, and the roughened layer has at least one vertical layer in the vertical direction of the conductive substrate. A roughened layer, and further have at least one additional roughened layer on the upper layer of the vertical roughened layer. Among the concavities and convexities of the vertical roughened layer and the additional roughened layer, the vertical roughened layer The interval between the apexes of the adjacent protrusions is different from the interval between the apexes of the adjacent protrusions of the additional roughening layer; the line segment length (A) of the outermost layer section of the lead frame material and the line segment length (B) of the conductive substrate section The value of the ratio (A/B) is 1.2 or more and 4 or less. 如申請專利範圍第1項之引線框架材,其中,該導電性基體為銅或銅合金、鐵或鐵合金、鋁或鋁合金。 For example, the lead frame material of item 1 in the scope of patent application, wherein the conductive substrate is copper or copper alloy, iron or iron alloy, aluminum or aluminum alloy. 如申請專利範圍第1或2項之引線框架材,其中,該複數層粗化層由2層構成,具有於導電性基體之垂直方向被粗化之第一垂直粗化層與該垂直粗化層之上層之第二附加粗化層,並且該垂直粗化層與附加粗化層各自之成分不同。 For example, the lead frame material of item 1 or 2 of the scope of patent application, wherein the plurality of roughened layers are composed of two layers, and the first vertical roughened layer that is roughened in the vertical direction of the conductive substrate and the vertical roughened The second additional roughening layer above the layer, and the vertical roughening layer and the additional roughening layer have different compositions. 如申請專利範圍第3項之引線框架材,其中,該第二附加粗化層之凸部之頂點的間隔較第一垂直粗化層之凸部之頂點的間隔窄。 Such as the lead frame material of item 3 of the scope of patent application, wherein the interval between the apexes of the convex portions of the second additional roughening layer is narrower than the interval between the apexes of the convex portions of the first vertical roughening layer. 如申請專利範圍第1或2項之引線框架材,其中,該垂直粗化層之成分由銅或銅合金構成。 For example, the lead frame material of item 1 or 2 of the scope of patent application, wherein the composition of the vertical roughening layer is composed of copper or copper alloy. 如申請專利範圍第1或2項之引線框架材,其中,該附加粗化層之成分由鎳、鎳合金、鈷、鈷合金中之任一者構成。 For example, the lead frame material of item 1 or 2 of the scope of patent application, wherein the composition of the additional roughening layer is composed of any one of nickel, nickel alloy, cobalt, and cobalt alloy. 如申請專利範圍第1或2項之引線框架材,其中,該導電性基體具有 於垂直方向被粗化之垂直粗化層,並且具有附加粗化層作為該垂直粗化層之上層,進一步於附加粗化層之上層,在引線框架材之整面或局部地具有單層或複數層由鈀、鈀合金、銠、銠合金、釕、釕合金、鉑、鉑合金、銥、銥合金、金、金合金、銀、銀合金中之任一者構成的表層。 For example, the lead frame material of item 1 or 2 of the scope of patent application, wherein the conductive substrate has The vertical roughening layer that is roughened in the vertical direction, and has an additional roughening layer as the upper layer of the vertical roughening layer, and further the upper layer of the additional roughening layer has a single layer or a single layer on the entire surface or part of the lead frame material The plural layers are a surface layer composed of any one of palladium, palladium alloy, rhodium, rhodium alloy, ruthenium, ruthenium alloy, platinum, platinum alloy, iridium, iridium alloy, gold, gold alloy, silver, and silver alloy. 一種引線框架材之製造方法,其係申請專利範圍第1至7項中任一項之引線框架材之製造方法,其中,該垂直粗化層及附加粗化層中之任一者或兩者藉由電鍍而形成。 A method for manufacturing a lead frame material, which is a method for manufacturing a lead frame material according to any one of items 1 to 7 of the scope of patent application, wherein either or both of the vertical roughening layer and the additional roughening layer It is formed by electroplating. 一種半導體封裝,其使用有申請專利範圍第1至7項中任一項之引線框架材。 A semiconductor package that uses a lead frame material of any one of items 1 to 7 in the scope of patent application.
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