JP6789965B2 - Lead frame material and its manufacturing method - Google Patents

Lead frame material and its manufacturing method Download PDF

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JP6789965B2
JP6789965B2 JP2017548714A JP2017548714A JP6789965B2 JP 6789965 B2 JP6789965 B2 JP 6789965B2 JP 2017548714 A JP2017548714 A JP 2017548714A JP 2017548714 A JP2017548714 A JP 2017548714A JP 6789965 B2 JP6789965 B2 JP 6789965B2
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layer
roughened
vertical
alloy
lead frame
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JPWO2017077903A1 (en
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良聡 小林
良聡 小林
真 橋本
真 橋本
邦夫 柴田
邦夫 柴田
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THE FURUKAW ELECTRIC CO., LTD.
Furukawa Precision Engineering Co Ltd
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60Electroplating characterised by the structure or texture of the layers
    • C25D5/615Microstructure of the layers, e.g. mixed structure
    • C25D5/617Crystalline layers
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10Electroplating with more than one layer of the same or of different metals
    • C25D5/12Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60Electroplating characterised by the structure or texture of the layers
    • C25D5/605Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
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  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)

Description

本発明は、半導体素子とメッキ処理が施されたリードフレームとを互いに電気的に接続し、これらをモールド樹脂で封止してなる樹脂封止型半導体装置に用いられるリードフレーム材およびその製造方法に関する。 The present invention is a lead frame material used in a resin-sealed semiconductor device in which a semiconductor element and a plated lead frame are electrically connected to each other and sealed with a mold resin, and a method for manufacturing the same. Regarding.

この種の樹脂封止型半導体装置は、ワイヤなどによって互いに電気的に接続された半導体素子とリードフレームとがモールド樹脂で封止されてなるものである。このような樹脂封止型半導体装置において、リードフレームは、Sn−Pb、Sn−Biなどの外装メッキが施されているのが主流である。 In this type of resin-sealed semiconductor device, a semiconductor element electrically connected to each other by a wire or the like and a lead frame are sealed with a mold resin. In such a resin-sealed semiconductor device, the lead frame is mainly plated with an exterior such as Sn-Pb or Sn-Bi.

ここで、近年では、組み付け工程の簡略化およびコストダウンのために、あらかじめリードフレーム表面に、プリント基板へのはんだなどによる実装において、はんだとの濡れ性を高めるような仕様のメッキ(たとえばNi/Pd/Au)を施しているリードフレーム(Pre Plated Frame、以下PPFと略記する)が採用され始めている(例えば、特許文献1参照)。 Here, in recent years, in order to simplify the assembly process and reduce costs, plating (for example, Ni /) on the surface of the lead frame in advance with specifications that enhance the wettability with solder when mounting on a printed circuit board by soldering or the like. Lead frames with Pd / Au) (Pre Plated Frame, hereinafter abbreviated as PPF) have begun to be adopted (see, for example, Patent Document 1).

また、一方で、樹脂封止型半導体装置におけるリードフレームとモールド樹脂との密着性を高めるために、リードフレームのメッキ表面を粗化する技術が提案されている(例えば、特許文献2、特許文献3参照)。 On the other hand, in order to improve the adhesion between the lead frame and the mold resin in the resin-sealed semiconductor device, a technique for roughening the plated surface of the lead frame has been proposed (for example, Patent Document 2 and Patent Document). 3).

これらのメッキ表面を粗化する技術は、リードフレームのメッキ表面を粗化することによって、(1)リードフレームにおけるモールド樹脂との接着面積が大きくなる効果、(2)粗化されたメッキ膜の凹凸に、モールド樹脂が食いつきやすくなる効果(つまり、アンカー効果)、などを期待するものである。 These techniques for roughening the plated surface are: (1) the effect of increasing the adhesive area of the lead frame with the mold resin by roughening the plated surface of the lead frame, and (2) the roughened plating film. It is expected that the mold resin will easily bite into the unevenness (that is, the anchor effect).

これらにより、リードフレームのモールド樹脂への密着性が向上し、リードフレームとモールド樹脂との間の剥離を防止することが可能となり、樹脂封止型半導体装置の信頼性が向上している。 As a result, the adhesion of the lead frame to the mold resin is improved, peeling between the lead frame and the mold resin can be prevented, and the reliability of the resin-sealed semiconductor device is improved.

特開平4−115558号Japanese Patent Application Laid-Open No. 4-115558 特開平6−29439号Japanese Patent Application Laid-Open No. 6-29439 特開平10−27873号Japanese Patent Application Laid-Open No. 10-27873

これらの形状による粗化めっきは、確かに従来よりも樹脂密着性は向上することができた。しかしながら、近年要求される高信頼性の水準、例えば温度85℃、湿度85%の環境下で168時間後において、樹脂とリードフレームとの間に隙間が生じてしまうケースが散見されることが分かった。これは、従来にはあまり多用されていなかったQFN(Quad Flat Non−Leaded Package)タイプやSOP(Small Outline Package)タイプ等のパッケージが多く用いられるようになり、より密着性に対する要求レベルが高くなってきたためと考えられる。このように、未だに改善の余地があることが分かった。 The roughened plating with these shapes was able to improve the resin adhesion as compared with the conventional case. However, it has been found that there are some cases where a gap is formed between the resin and the lead frame after 168 hours in an environment of high reliability required in recent years, for example, a temperature of 85 ° C. and a humidity of 85%. It was. As for this, packages such as QFN (Quad Flat Non-Leaded Package) type and SOP (Small Outline Package) type, which have not been widely used in the past, are often used, and the required level for adhesion becomes higher. It is thought that it was because it came. In this way, it turned out that there is still room for improvement.

本発明は、近年求められる高温・高湿環境における樹脂密着性を改善できるリードフレームを作成するのに好適なリードフレーム材およびその製造方法を提供することを課題とする。 An object of the present invention is to provide a lead frame material suitable for producing a lead frame capable of improving resin adhesion in a high temperature and high humidity environment required in recent years, and a method for producing the same.

上記従来の問題点に対して鋭意研究開発を進めた結果、本発明者らは、導電性基体上に形成された粗化層の形状に着目し、リードフレーム材と樹脂とのアンカー効果を最大限出現できる形状について鋭意検討した。その結果、垂直粗化層(基体の垂直方向に少なくとも1層以上形成された粗化層)だけでなく、さらにその上層にも付化粗化層(粗化された形状)を少なくとも1層以上有し、前記垂直粗化層及び付加粗化層がそれぞれ有する凹凸の内、前記垂直粗化層の隣り合う凸部(凹凸の山)の頂点の間隔と前記付加粗化層の隣り合う凸部(凹凸の山)の頂点の間隔とが異なるようにすることで、樹脂密着性が従来よりも格段に向上し、高温高湿試験における樹脂密着性を確保できることを見出した。本発明はこの知見に基づいて完成するに至ったものである。 As a result of diligent research and development on the above-mentioned conventional problems, the present inventors focused on the shape of the roughened layer formed on the conductive substrate, and maximized the anchor effect between the lead frame material and the resin. We diligently examined the shapes that can appear only. As a result, not only the vertical roughened layer (roughened layer formed at least one layer in the vertical direction of the substrate) but also at least one layered roughened layer (roughened shape) on the upper layer thereof. Among the irregularities of the vertical roughening layer and the additional roughening layer, the distance between the vertices of the adjacent convex portions (ridges of the unevenness) of the vertical roughening layer and the adjacent convex portions of the additional roughening layer. It has been found that the resin adhesion can be remarkably improved as compared with the conventional case and the resin adhesion in the high temperature and high humidity test can be ensured by making the distance between the vertices of the (uneven mountain) different. The present invention has been completed based on this finding.

すなわち、本発明は、以下の手段を提供する:
(1)導電性基体上に粗化層を有するリードフレーム材において、その粗化層は、複数層の粗化層からなり、前記粗化層が、導電性基体の垂直方向に少なくとも1層からなる垂直粗化層を有するとともに、さらにその垂直粗化層の上層に付加粗化層を少なくとも1層以上有し、前記垂直粗化層及び付加粗化層がそれぞれ有する凹凸の内、前記付加粗化層の隣り合う凸部の頂点の平均間隔が前記垂直粗化層の隣り合う凸部の頂点の平均間隔の1/20以上3/4以下であることを特徴とするリードフレーム材。
(2)最表層断面の線分長さ(最表層断面線分長さ。付加粗化層を含め、リードフレーム材の最表層の断面の線分長さである。)(A)と導電性基体断面の線分長さ(導電性基体断面線分長さ)(B)の比(A/B)の値が1.2以上4以下である(1)に記載のリードフレーム材。
(3)前記導電性基体は、銅または銅合金、鉄または鉄合金、アルミニウムまたはアルミニウム合金であることを特徴とする、(1)または(2)に記載のリードフレーム材。
(4)前記複数の粗化層は2層からなり、導電性基体の垂直方向に粗化された第一の垂直粗化層と、その垂直粗化層の上層の第二の付加粗化層を有し、さらにその垂直粗化層と付加粗化層それぞれの成分が異なることを特徴とする、(1)から(3)のいずれか1項に記載のリードフレーム材。
)前記垂直粗化層の成分が、銅または銅合金からなることを特徴とする、(1)〜()のいずれか1項に記載のリードフレーム材。
)前記付加粗化層の成分が、ニッケル、ニッケル合金、コバルト、コバルト合金のうちのいずれかからなることを特徴とする、(1)〜()のいずれか1項に記載のリードフレーム材。
)前記導電性基体は、垂直方向に粗化された垂直粗化層を有するとともに、その垂直粗化層の上層として付加粗化層を有し、さらに付加粗化層の上層に、パラジウム、パラジウム合金、ロジウム、ロジウム合金、ルテニウム、ルテニウム合金、白金、白金合金、イリジウム、イリジウム合金、金、金合金、銀、銀合金のうちいずれかからなる表層を、リードフレーム材の全面あるいは部分的に、単層または複数層有することを特徴とする、(1)〜()のいずれか1項に記載のリードフレーム材。
)前記垂直粗化層および付加粗化層のうち、いずれかまたは双方とも電気めっきにより形成されることを特徴とする、(1)〜()のいずれか1項に記載のリードフレーム材の製造方法。
)前記(1)〜()のいずれか1項に記載のリードフレーム材を使用した、半導体パッケージ。
That is, the present invention provides the following means:
(1) In a lead frame material having a roughened layer on a conductive substrate, the roughened layer is composed of a plurality of roughened layers, and the roughened layer is formed from at least one layer in the vertical direction of the conductive substrate. In addition to having a vertical roughening layer, at least one additional roughening layer is provided on the upper layer of the vertical roughening layer, and among the irregularities of the vertical roughening layer and the additional roughening layer, the additional roughening is performed. A lead frame material, characterized in that the average distance between the vertices of adjacent convex portions of the chemical layer is 1/20 or more and 3/4 or less of the average distance between the vertices of adjacent convex portions of the vertical roughening layer .
(2) Line segment length of the outermost layer cross section (line segment length of the outermost layer cross section; the line segment length of the cross section of the outermost layer of the lead frame material including the additional roughening layer) (A) and conductivity. The lead frame material according to (1), wherein the value of the ratio (A / B) of the line segment length of the base cross section (conductive base cross section line segment length) (B) is 1.2 or more and 4 or less.
(3) The lead frame material according to (1) or (2), wherein the conductive substrate is copper or a copper alloy, iron or an iron alloy, aluminum or an aluminum alloy.
(4) The plurality of roughened layers are composed of two layers, a first vertical roughened layer roughly roughened in the vertical direction of the conductive substrate, and a second additional roughened layer above the vertical roughened layer. The lead frame material according to any one of (1) to (3), wherein the components of the vertical roughening layer and the additional roughening layer are different.
( 5 ) The lead frame material according to any one of (1) to ( 4 ), wherein the component of the vertically roughened layer is made of copper or a copper alloy.
( 6 ) The lead according to any one of (1) to ( 5 ), wherein the component of the additional roughened layer is composed of any one of nickel, nickel alloy, cobalt, and cobalt alloy. Frame material.
( 7 ) The conductive substrate has a vertical roughened layer roughened in the vertical direction, has an additional roughened layer as an upper layer of the vertical roughened layer, and has palladium as an upper layer of the additional roughened layer. , Palladium alloy, rhodium, rhodium alloy, ruthenium, ruthenium alloy, platinum, platinum alloy, iridium, iridium alloy, gold, gold alloy, silver, silver alloy, all or part of the surface layer of the lead frame material The lead frame material according to any one of (1) to ( 6 ), which has a single layer or a plurality of layers.
( 8 ) The lead frame according to any one of (1) to ( 7 ), wherein either or both of the vertical roughening layer and the additional roughening layer are formed by electroplating. Material manufacturing method.
( 9 ) A semiconductor package using the lead frame material according to any one of (1) to ( 7 ) above.

本発明者らは、導電性基体上に形成された粗化層を有するリードフレーム材において、その形成された粗化層は、複数層の粗化層からなり、前記粗化層が、導電性基体の垂直方向に形成した少なくとも1層以上からなる垂直粗化層を有するとともに、さらにその垂直粗化層の上層も粗化されている付加粗化層を少なくとも1層以上有し、前記垂直粗化層及び付加粗化層がそれぞれ有する凹凸の内、前記垂直粗化層の隣り合う凸部の頂点の間隔と前記付加粗化層の隣り合う凸部の頂点の間隔とが異なるようにすることで、樹脂が基体の垂直方向だけでなく水平方向にも侵入し、従来のような粗化処理により表面積を増大させるだけでなく、付加粗化層による楔作用により機械的な樹脂との接合強度が著しく増大することを見出した。この結果、従来では耐えられなかった樹脂の高温高湿密着性、例えば85℃、85%の環境において168時間もの高温高湿環境下においても、リードフレーム材と樹脂の間の隙間の発生が大幅に抑制され、優れた樹脂密着性が得られるものである。 In a lead frame material having a roughened layer formed on a conductive substrate, the present inventors have formed the roughened layer composed of a plurality of roughened layers, and the roughened layer is conductive. It has at least one vertical roughening layer formed in the vertical direction of the substrate, and also has at least one additional roughening layer in which the upper layer of the vertical roughening layer is roughened. Among the irregularities of the chemical layer and the additional roughening layer, the distance between the apex of the adjacent convex portion of the vertical roughening layer and the distance between the apex of the adjacent convex portion of the additional roughening layer should be different. Therefore, the resin penetrates not only in the vertical direction but also in the horizontal direction of the substrate, and not only the surface area is increased by the conventional roughening treatment, but also the bonding strength with the mechanical resin is caused by the wedge action of the additional roughening layer. Was found to increase significantly. As a result, the high-temperature and high-humidity adhesion of the resin, which could not be tolerated in the past, for example, even in a high-temperature and high-humidity environment of 168 hours at 85 ° C. and 85%, a large gap is generated between the lead frame material and the resin. It is suppressed to and excellent resin adhesion can be obtained.

図1は、本発明の一形態における概略断面模式図である。FIG. 1 is a schematic cross-sectional schematic diagram according to an embodiment of the present invention. 図2は、本発明の別の形態における概略断面模式図である。FIG. 2 is a schematic cross-sectional schematic view of another embodiment of the present invention. 図3は、本発明のさらに別の形態における概略断面模式図である。FIG. 3 is a schematic cross-sectional schematic view of still another embodiment of the present invention. 図4は、本発明の一形態における概略断面模式図の拡大図である。FIG. 4 is an enlarged view of a schematic cross-sectional view according to an embodiment of the present invention. 図5は、本発明の、図4に示した前記一形態における概略断面模式図の拡大図である。FIG. 5 is an enlarged view of a schematic cross-sectional schematic diagram of the above embodiment shown in FIG. 4 of the present invention. 図6は、従来の一形態における概略断面模式図である。図6中、11は導電性基体、12は銅下地めっき層、13はニッケル粗化めっき層、14は表層を示す。FIG. 6 is a schematic cross-sectional schematic diagram of a conventional form. In FIG. 6, 11 is a conductive substrate, 12 is a copper base plating layer, 13 is a nickel roughened plating layer, and 14 is a surface layer.

(垂直粗化層)
本発明によれば、まず導電性基体(以下、単に基体という。)に対して垂直方向の粗化層、すなわち垂直粗化層を有している。このリードフレーム材が有する粗化層は複数層の垂直粗化層からなり、好ましくは一層の垂直粗化層を有する。この垂直粗化層は、基体の主表面に対して垂直方向に形成した粗化層を示し、概ね基体の主表面垂線方向に形成するものを意味する。基体に対して縦方向の垂直断面から観察したときに、その粗化層凸部の(山の頂点の)成長方向が基体主表面の垂線から20°以内に形成されたものであることが好ましい。この垂直粗化層は、樹脂密着性を付与するための根幹となる粗化層となり、例えば銅、銅合金、ニッケル、ニッケル合金、コバルト、コバルト合金などからなることが好ましい。特に、基体と上層の皮膜(下記の付加粗化層など)に対する密着性を向上させる観点から、銅または銅合金からなる垂直粗化層であることがより好ましい。銅合金、ニッケル合金、コバルト合金としては、銅合金としては銅−錫合金、ニッケル合金としてはニッケル−亜鉛合金、コバルト合金としてはコバルト−錫合金などが挙げられる。
(Vertical roughening layer)
According to the present invention, first, a roughening layer in the direction perpendicular to a conductive substrate (hereinafter, simply referred to as a substrate), that is, a vertical roughening layer is provided. The roughened layer of the lead frame material is composed of a plurality of vertical roughened layers, and preferably has one vertical roughened layer. This vertically roughened layer indicates a roughened layer formed in the direction perpendicular to the main surface of the substrate, and means a layer formed substantially in the direction perpendicular to the main surface of the substrate. When observed from a vertical cross section in the vertical direction with respect to the substrate, it is preferable that the growth direction of the convex portion of the roughened layer (at the apex of the mountain) is formed within 20 ° from the perpendicular line of the main surface of the substrate. .. This vertical roughened layer is a roughened layer that serves as a basis for imparting resin adhesion, and is preferably made of, for example, copper, a copper alloy, nickel, a nickel alloy, cobalt, or a cobalt alloy. In particular, a vertically roughened layer made of copper or a copper alloy is more preferable from the viewpoint of improving the adhesion between the substrate and the upper film (such as the additional roughened layer described below). Examples of copper alloys, nickel alloys, and cobalt alloys include copper-tin alloys as copper alloys, nickel-zinc alloys as nickel alloys, and cobalt-tin alloys as cobalt alloys.

(垂直粗化層の膜厚)
なお、垂直粗化層の厚みについて特に制限はないが、膜厚が大きければ大きいほど粗化による凹凸が大きくなる傾向にある。そのため、粗化形状を大きくするために垂直粗化層の被覆厚は、好ましくは0.2μm以上、より好ましくは0.5μm以上、さらに好ましくは0.8μm以上である。一方、被覆厚が3μmを超えると、搬送時の粗化層の脱落、いわゆる「粉落ち」が多くなる懸念がある。このため、垂直粗化層の被覆厚は、好ましくは3μm以下、より好ましくは2μm以下、さらに好ましくは1.5μm以下である。また、垂直粗化層の層数は2層以内であることが製造工程の煩雑性などを考慮すると好ましい。なお、これらの被覆厚は局所的では判断せず、少なくとも蛍光X線法(例えばSII社製SFT9400(商品名)などの膜厚測定装置)によりコリメータ径0.2mm以上で任意の3点を測定した平均的な膜厚を示すものとする。
(Film thickness of vertical roughened layer)
The thickness of the vertical roughening layer is not particularly limited, but the larger the film thickness, the larger the unevenness due to roughening tends to be. Therefore, the coating thickness of the vertical roughened layer is preferably 0.2 μm or more, more preferably 0.5 μm or more, and further preferably 0.8 μm or more in order to increase the roughened shape. On the other hand, if the coating thickness exceeds 3 μm, there is a concern that the roughened layer may fall off during transportation, so-called “powder drop”. Therefore, the coating thickness of the vertical roughening layer is preferably 3 μm or less, more preferably 2 μm or less, and further preferably 1.5 μm or less. Further, it is preferable that the number of vertical roughened layers is 2 or less in consideration of the complexity of the manufacturing process. These coating thicknesses are not determined locally, and at least any three points are measured with a collimator diameter of 0.2 mm or more by a fluorescent X-ray method (for example, a film thickness measuring device such as SFT9400 (trade name) manufactured by SII). It shall show the average film thickness.

(付加粗化層)
また本発明によれば、垂直粗化層の上層に、一層以上からなる付加粗化層を有してなり、好ましくは一層の付加粗化層を有する。この付加粗化層の存在により、従来の凹凸粗化のみ(例えば、図6参照)では達成しえなかった水準での樹脂密着性を付与することができる。この付加粗化層は、垂直粗化層の上層に、好ましくは垂直粗化層よりも山と山の間隔が狭く(小さく)なるように粗化された部分である。付加粗化層は、樹脂に対して楔作用を持たせるために形成される。付加粗化層は、基体の90°垂線よりも±20°以上の角度で形成されている部分を少しでも形成することが好ましい。つまり、基体の90°垂線に対して、付加粗化層はより大きく傾いていることが好ましい。これによって、一層のアンカー効果が増大するだけでなく、高温環境下や高湿環境による樹脂の膨張収縮に対しても2次元のみならず3次元的に追従することができるため、従来よりも樹脂密着性が改善されるものとなる。付加粗化層は、垂直粗化層と密着性が良い材料からなることが好ましく、例えば銅、銅合金、ニッケル、ニッケル合金、コバルト、コバルト合金、銀、銀合金などが挙げられる。中でも基体成分の拡散を防止するバリア層としての機能も付与できることから、ニッケル、ニッケル合金、コバルト、コバルト合金のうちいずれかが好ましい。なお、付加粗化層は、垂直粗化層とは異なる成分からなることが好ましい。銅合金、ニッケル合金、コバルト合金、銀合金としては、銅合金としては銅−錫合金、ニッケル合金としてはニッケル−亜鉛合金、コバルト合金としてはコバルト−錫合金、銀合金としては銀−錫合金などが挙げられる。
(Additional roughening layer)
Further, according to the present invention, an additional roughening layer composed of one or more layers is provided on the upper layer of the vertical roughening layer, and preferably one additional roughening layer is provided. Due to the presence of the additional roughening layer, it is possible to impart resin adhesion at a level that cannot be achieved only by the conventional uneven roughening (see, for example, FIG. 6). This additional roughening layer is a portion that is roughened on the upper layer of the vertical roughening layer so that the distance between the peaks is narrower (smaller) than that of the vertical roughening layer. The additional roughened layer is formed to give a wedge action to the resin. It is preferable that the additional roughened layer has a portion formed at an angle of ± 20 ° or more from the 90 ° perpendicular line of the substrate as much as possible. That is, it is preferable that the additional roughened layer is more inclined with respect to the 90 ° perpendicular line of the substrate. As a result, not only the anchor effect is further increased, but also the expansion and contraction of the resin due to the high temperature environment and the high humidity environment can be followed not only two-dimensionally but also three-dimensionally. Adhesion will be improved. The additional roughened layer is preferably made of a material having good adhesion to the vertical roughened layer, and examples thereof include copper, copper alloys, nickel, nickel alloys, cobalt, cobalt alloys, silver and silver alloys. Among them, any of nickel, nickel alloy, cobalt, and cobalt alloy is preferable because it can also provide a function as a barrier layer for preventing the diffusion of the substrate component. The additional roughening layer is preferably composed of a component different from that of the vertical roughening layer. Copper alloys, nickel alloys, cobalt alloys, silver alloys include copper-tin alloys as copper alloys, nickel-zinc alloys as nickel alloys, cobalt-tin alloys as cobalt alloys, silver-tin alloys as silver alloys, etc. Can be mentioned.

(付加粗化層の膜厚)
付加粗化層の厚みについては特に制限はないが、膜厚が大きければ大きいほど粗化による凹凸が大きくなる傾向にある。一方、厚すぎると垂直粗化層の凹凸を埋めてしまう懸念がある。このため、垂直粗化層被覆厚の1/10以上、好ましくは1/5以上あることが好ましい。一方、付加粗化層の上限被覆厚としては、最大でも垂直粗化層の被覆厚と同厚以下が好ましく、さらに垂直粗化層厚の2/3以下であることがより好ましい。
(Film thickness of additional roughened layer)
The thickness of the additional roughened layer is not particularly limited, but the larger the film thickness, the larger the unevenness due to roughening tends to be. On the other hand, if it is too thick, there is a concern that the unevenness of the vertical roughening layer will be filled. Therefore, it is preferably 1/10 or more, preferably 1/5 or more of the vertical roughened layer coating thickness. On the other hand, the upper limit coating thickness of the additional roughened layer is preferably at most the same thickness as the coating thickness of the vertical roughened layer, and more preferably 2/3 or less of the vertical roughened layer thickness.

(垂直粗化層と付加粗化層の形状(厚さ))
また、本発明で得られる粗化層の形状は、付加粗化層による楔作用を利用しているため、表面からの粗度測定ではその度合いを表現することができない。このため、断面から観察した時のすべての皮膜層(前記の各粗化層)形成後の最表層の断面の線分長さ(最表層の断面の線分長さの総長)を測定し、その導電性基体断面の線分長さに対する比率の値を長さ指標として利用することができる。最表層断面の線分長さ(最表層断面線分長さ)(A)の比率(A/B)の値は、導電性基体断面の線分長さ(B)を1とした時、好ましくは1.2倍以上、より好ましくは2倍以上である。これによって、比表面積が増大して樹脂との密着性が増大する。一方、導電性基体断面の線分長さ(B)を1とした時、最表層断面の線分長さ(A)の比(A/B)の値が4倍程度を超えると粉落ちしやすい懸念があることから、好ましくは4倍以下、より好ましくは3.5倍以下である。
本発明においては、垂直粗化層と付加粗化層で、封止材との樹脂密着性を改善することができる。
(Shape (thickness) of vertical roughening layer and additional roughening layer)
Further, since the shape of the roughened layer obtained in the present invention utilizes the wedge action of the additional roughened layer, the degree cannot be expressed by the roughness measurement from the surface. Therefore, the line segment length of the cross section of the outermost layer after the formation of all the film layers (each roughened layer described above) when observed from the cross section (total length of the line segment length of the cross section of the outermost layer) is measured. The value of the ratio of the cross section of the conductive substrate to the line segment length can be used as a length index. The value of the ratio (A / B) of the line segment length of the outermost layer cross section (the line segment length of the outermost layer cross section) (A) is preferably 1 when the line segment length (B) of the conductive substrate cross section is 1. Is 1.2 times or more, more preferably 2 times or more. As a result, the specific surface area is increased and the adhesion to the resin is increased. On the other hand, when the line segment length (B) of the cross section of the conductive substrate is set to 1, powder falls off when the value of the ratio (A / B) of the line segment length (A) of the outermost layer cross section exceeds about 4 times. It is preferably 4 times or less, and more preferably 3.5 times or less because there is an easy concern.
In the present invention, the vertical roughening layer and the additional roughening layer can improve the resin adhesion with the sealing material.

(各粗化層の形状)
なお、本発明では垂直粗化層と付加粗化層を形成するため、それぞれの凹凸については最表層からの測定のみでは把握できず、断面から観察することによって各粗化層の隣り合った凸部の頂点間隔(各粗化層の凹凸)を観察することが可能である。これは、例えば任意の粗化層断面をFocused Ion Beam:FIBにより加工後、Scanning Ion Mycroscope:SIM像により結晶粒径のコントラストから確認することができ、各粗化層の隣り合った凸部の頂点の間隔についてはスケールより判断することができる。各粗化層において、垂直粗化層および付加粗化層のそれぞれ隣り合う各凸部の頂点同士の平均間隔を「垂直粗化層の間隔(凸部の間隔)」および「付加粗化層の間隔(凸部の間隔)」というとき、垂直粗化層の間隔は付加粗化層のそれとは異なる。垂直粗化層の間隔の方が付加粗化層のそれよりも大きいことが好ましい。このことにより、垂直粗化層の間に樹脂が容易に入り込むため、樹脂密着性がより一層向上することができる。その間隔の比率としては、好ましくは付加粗化層の間隔が垂直粗化層の間隔の1/2以下、さらに好ましくは1/4以下である。一方1/20を超えると、付加粗化層が細かくなりすぎて密着力が低下しつつあるため、好ましくは1/20以上、さらに好ましくは1/15以上である。なお、垂直粗化層が複数層ある時は、その最大の間隔となっている垂直粗化層をその対象とし、また付加粗化層が複数層ある時は、その最表面に形成された付加粗化層をその対象とする。
直粗化層において、電流密度や被覆厚を変えることにより、粗化層の結晶粒径が変化して付加粗化層の凸凸間隔を制御することができる。異なる成分の粗化層をそれぞれ粗化めっきすることで、凸凸の間隔比が変わってくることを制御することができる。具体的には、各粗化層の厚さと平均間隔は、高電流密度ほど間隔を狭く、低電流密度ほど間隔を広く作り分けることができる。
(Shape of each roughened layer)
In the present invention, since the vertical roughening layer and the additional roughening layer are formed, the unevenness of each cannot be grasped only by the measurement from the outermost layer, and the adjacent convexities of each roughening layer can be observed by observing from the cross section. It is possible to observe the apex spacing of the portions (unevenness of each roughened layer). This can be confirmed from the contrast of the crystal grain size by, for example, after processing an arbitrary roughened layer cross section with Focused Ion Beam: FIB and then scanning Ion Mycroscop: SIM image, and the adjacent convex portions of each roughened layer. The spacing between vertices can be determined from the scale. In each roughened layer, the average spacing between the vertices of the convex portions adjacent to each of the vertical roughened layer and the additional roughened layer is defined as "the interval between the vertical roughened layers (the interval between the convex portions)" and "the interval between the additional roughened layers". When we say "spacing (spacing of convex parts)", the spacing of the vertical roughening layer is different from that of the additional roughening layer. It is preferable that the spacing between the vertical roughening layers is larger than that of the additional roughening layers. As a result, the resin easily penetrates between the vertical roughening layers, so that the resin adhesion can be further improved. As for the ratio of the intervals, the interval of the additional roughening layer is preferably 1/2 or less, more preferably 1/4 or less of the interval of the vertical roughening layer. On the other hand, if it exceeds 1/20, the additional roughened layer becomes too fine and the adhesion is decreasing, so that it is preferably 1/20 or more, more preferably 1/15 or more. When there are a plurality of vertical roughening layers, the vertical roughening layer having the maximum interval is the target, and when there are a plurality of additional roughening layers, the addition formed on the outermost surface thereof is targeted. you a rough layer and its target.
In vertical roughened layer, by changing the current density and coating thickness, it can be controlled groaning spacing of the additional roughened layer crystal grain size of the roughened layer is changed. By rough-plating the roughened layers of different components, it is possible to control the change in the convex-convex spacing ratio. Specifically, the thickness and average spacing of each roughened layer can be narrowed as the current density increases and wider as the current density decreases.

(導電性基体)
また、使用する金属基体(導電性基体)成分としては、銅または銅合金、鉄または鉄合金、アルミニウムまたはアルミニウム合金等が好ましく、中でも導電率の良い銅または銅合金が好ましい。
例えば銅合金の一例として、CDA(Copper Development Association)掲載合金である「C14410(Cu−0.15Sn、古河電気工業(株)製、商品名:EFTEC(登録商標)−3)」、「C19400(Cu−Fe系合金材料、Cu−2.3Fe−0.03P−0.15Zn)」、「C18045(Cu−0.3Cr−0.25Sn−0.5Zn、古河電気工業(株)製、商品名:EFTEC−64T)」等を用いることができる。なお、各元素の前の数字の単位は質量%である。これら銅合金基体はそれぞれ導電率や強度が異なるため、適宜要求特性により選定されて使用されるが、導電率が50%IACS以上の銅合金の条材とすることが好ましい。
また、鉄もしくは鉄合金としては、例えば、42アロイ(Fe−42mass%Ni)やステンレス鋼などが用いられる。これらの鉄合金基体は、導電率はそれほど高くないが、導電率をそれほど要求せず、電気信号の伝達を目的とするようなリードフレームには適用することができる。
また、アルミニウムもしくはアルミニウム合金としては、例えば、A5052などが用いられる。
基体の厚さには特に制限はないが、通常、0.05mm〜2mmであり、好ましくは、0.1mm〜1mmである。
(Conductive substrate)
Further, as the metal substrate (conductive substrate) component to be used, copper or copper alloy, iron or iron alloy, aluminum or aluminum alloy or the like is preferable, and copper or copper alloy having good conductivity is preferable.
For example, as an example of a copper alloy, "C14410 (Cu-0.15Sn, manufactured by Furukawa Denki Kogyo Co., Ltd., trade name: EFTEC (registered trademark) -3)", "C19400 (registered trademark)", which is an alloy published in CDA (Copper Development Association). Cu-Fe alloy material, Cu-2.3Fe-0.03P-0.15Zn) "," C18045 (Cu-0.3Cr-0.25Sn-0.5Zn, manufactured by Furukawa Denki Kogyo Co., Ltd., trade name) : EFTEC-64T) ”and the like can be used. The unit of the number before each element is mass%. Since these copper alloy substrates have different conductivity and strength, they are appropriately selected and used according to the required characteristics, but it is preferable to use a copper alloy strip having a conductivity of 50% IACS or more.
Further, as the iron or iron alloy, for example, 42 alloy (Fe-42 mass% Ni), stainless steel, or the like is used. These ferroalloy substrates are not very conductive, but do not require much conductivity and can be applied to lead frames for the purpose of transmitting electrical signals.
Further, as the aluminum or the aluminum alloy, for example, A5052 or the like is used.
The thickness of the substrate is not particularly limited, but is usually 0.05 mm to 2 mm, preferably 0.1 mm to 1 mm.

(粗化めっきの上層、表層)
また本発明によれば、付加粗化層のさらに上層(表層)に、リードフレームの半田濡れ性やワイヤボンディング性、ダイボンディング性などの特性を付与するため、パラジウム、パラジウム合金、ロジウム、ロジウム合金、ルテニウム、ルテニウム合金、白金、白金合金、イリジウム、イリジウム合金、金、金合金、銀、銀合金のうちいずれかからなる皮膜が、リードフレーム材料の全面あるいは部分的に、単層または複数層で形成されていてもよい。この内、代表的な層構成としては、粗化層側から表面へ順に、Pd/Au被覆、Pd/Ag/Au被覆、Pd/Rh/Au被覆、Ru/Pd/Au被覆などが挙げられる。これらの被覆厚に特に制限はないが、厚すぎると粗化層凹凸を埋めてしまい機能を果たさなくなる可能性があることや、貴金属を主としているためにコスト増の可能性がある。本書において、「貴金属を主としている」とは、構成成分の内、50質量%以上が貴金属であることをいう。これらから、総被覆厚は1μm以下が好ましい。パラジウム合金、ロジウム合金、ルテニウム合金、白金合金、イリジウム合金、金合金、銀合金としては、パラジウム合金としてはパラジウム−銀合金、ロジウム合金としてはロジウム−パラジウム合金、ルテニウム合金としてはルテニウム−イリジウム合金、白金合金としては白金−金合金、イリジウム合金としてはイリジウム−ルテニウム合金、金合金としては金−銀合金、銀合金としては銀−錫合金などが挙げられる。
(Upper layer and surface layer of roughened plating)
Further, according to the present invention, in order to impart properties such as solder wettability, wire bonding property, and die bonding property of the lead frame to the upper layer (surface layer) of the additional roughening layer, a palladium, palladium alloy, rhodium, and rhodium alloy are provided. , Luthenium, ruthenium alloy, platinum, platinum alloy, iridium, iridium alloy, gold, gold alloy, silver, silver alloy, all or part of the lead frame material, with a single layer or multiple layers. It may be formed. Among these, typical layer configurations include Pd / Au coating, Pd / Ag / Au coating, Pd / Rh / Au coating, Ru / Pd / Au coating, and the like in order from the roughened layer side to the surface. There is no particular limitation on the coating thickness, but if it is too thick, it may fill the unevenness of the roughened layer and fail to function, or it may increase the cost because it is mainly composed of precious metals. In this document, "mainly precious metal" means that 50% by mass or more of the constituents are precious metals. From these, the total coating thickness is preferably 1 μm or less. Palladium alloys, rhodium alloys, ruthenium alloys, platinum alloys, iridium alloys, gold alloys, as silver alloys, palladium-silver alloys as palladium alloys, rhodium-palladium alloys as rhodium alloys, ruthenium-iridium alloys as ruthenium alloys, Examples of the platinum alloy include a platinum-gold alloy, an iridium alloy includes an iridium-lutenium alloy, a gold alloy includes a gold-silver alloy, and a silver alloy includes a silver-tin alloy.

(粗化層の被覆部)
なお、本発明における粗化層の形成箇所は、樹脂モールドされる部分の少なくとも一部が形成されていればよい。例えばリードフレームが樹脂モールドされる部分の少なくとも1/5以上であることが好ましく、さらに好ましくは1/2以上の面積に形成されることで密着性向上効果を発揮する。樹脂モールドされる全面に施されているものが最も好ましい。この部分的に設けられる粗化層の形状としては、ストライプ状、スポット状、リング状など、様々な形態をとることが可能である。さらに、樹脂モールドが片面だけであるような製品においては、例えば片面のみ前記粗化層を形成することも可能である。
(Coating part of roughened layer)
The roughened layer may be formed in at least a part of the resin-molded portion in the present invention. For example, the lead frame is preferably formed in an area of at least 1/5 or more of the resin-molded portion, and more preferably in an area of 1/2 or more, thereby exhibiting an effect of improving adhesion. Most preferably, it is applied to the entire surface to be resin-molded. The shape of the partially provided roughened layer can take various forms such as a stripe shape, a spot shape, and a ring shape. Further, in a product in which the resin mold has only one side, for example, it is possible to form the roughened layer on only one side.

また本発明によれば、電流密度や攪拌により比較的容易に粗化めっきを制御することができ且つ簡便であることから、垂直粗化層および付加粗化層のうち、いずれかまたは双方とも形成する際には電気めっき法で形成することが好ましい。さらに双方を湿式めっきによって形成することが、生産性の観点からより好ましい。 Further, according to the present invention, since roughening plating can be controlled relatively easily by current density and stirring and is simple, either or both of the vertical roughening layer and the additional roughening layer are formed. It is preferable to form by an electroplating method. Further, it is more preferable to form both by wet plating from the viewpoint of productivity.

以下、本発明を、図面に基づいて詳細に説明する。
図1は、本発明の一形態における概略断面模式図である。導電性基体1の上層に、垂直粗化層2が形成されており、そのさらに上層に付加粗化層3が形成されている。付加粗化層3の上部は、樹脂モールドで覆われる(図示せず)。本態様のように、樹脂モールドが片面だけであるような製品(半導体パッケージ)においては、例えば片面のみ前記粗化層を形成することも可能であるし、もちろん両面に形成されていてもよい。
Hereinafter, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic cross-sectional schematic diagram according to an embodiment of the present invention. A vertical roughening layer 2 is formed on the upper layer of the conductive substrate 1, and an additional roughening layer 3 is formed on the upper layer thereof. The upper part of the additional roughening layer 3 is covered with a resin mold (not shown). In a product (semiconductor package) in which the resin mold has only one side as in this embodiment, for example, the roughened layer can be formed on only one side, or of course, it may be formed on both sides.

図2は、本発明の別の形態における概略断面模式図である。導電性基体1の上層に、垂直粗化層2が形成されており、そのさらに上層に付加粗化層3が形成され、さらにその表層にリードフレームの半田濡れ性やワイヤボンディング性、ダイボンディング性などの特性を付与するため、パラジウム、パラジウム合金、ロジウム、ロジウム合金、ルテニウム、ルテニウム合金、白金、白金合金、イリジウム、イリジウム合金、金、金合金、銀、銀合金のうちいずれかからなる皮膜層(表層)4が全面的に単層で形成されている。皮膜層4の上部は、樹脂モールドで覆われる(図示せず)。この皮膜層4は、リードフレームの半田濡れ性やワイヤボンディング性、ダイボンディング性などの特性を付与するために形成される層であり、例えば樹脂モールドされる部分に部分的に形成されていてもよい。その形状もストライプ状、スポット状、リング状などで形成されていてもよい。 FIG. 2 is a schematic cross-sectional schematic view of another embodiment of the present invention. A vertical roughening layer 2 is formed on the upper layer of the conductive substrate 1, an additional roughening layer 3 is formed on the upper layer thereof, and the solder wettability, wire bonding property, and die bonding property of the lead frame are further formed on the surface layer thereof. A film layer made of any of palladium, palladium alloy, rhodium, rhodium alloy, ruthenium, ruthenium alloy, platinum, platinum alloy, iridium, iridium alloy, gold, gold alloy, silver, and silver alloy in order to impart such properties. (Surface layer) 4 is entirely formed of a single layer. The upper part of the film layer 4 is covered with a resin mold (not shown). The film layer 4 is a layer formed to impart properties such as solder wettability, wire bonding property, and die bonding property of the lead frame, and even if it is partially formed on a resin-molded portion, for example. Good. The shape may also be striped, spot-shaped, ring-shaped or the like.

図3は、本発明のさらに別の形態における概略断面模式図である。導電性基体1の上層に、垂直粗化層2が形成されており、そのさらに上層に付加粗化層3が形成され、さらにその表層にリードフレームの半田濡れ性やワイヤボンディング性、ダイボンディング性などの特性を付与するため、パラジウム、パラジウム合金、ロジウム、ロジウム合金、ルテニウム、ルテニウム合金、白金、白金合金、イリジウム、イリジウム合金、金、金合金、銀、銀合金のうちいずれかからなる皮膜層4’(第一表層)および皮膜層5(第二表層)が2層で形成されている。皮膜層5の上部は、樹脂モールドで覆われる(図示せず)。このとき、皮膜層4’および5は異なる金属種から形成されている。例えば皮膜層4’はPd、Rh、Ru、Irなどが好ましく、皮膜層5はAu、Ag、Ptなどが好ましい。図3においては、皮膜層4’および5は全面的に形成されているが、貴金属使用量削減のため、皮膜層4’および5はワイヤボンディングやはんだ付け等の作用を必要とする部分にのみ形成することで、省貴金属化により環境にやさしく低コストな形態をとることも可能である。 FIG. 3 is a schematic cross-sectional schematic view of still another embodiment of the present invention. A vertical roughening layer 2 is formed on the upper layer of the conductive substrate 1, an additional roughening layer 3 is formed on the upper layer thereof, and the solder wettability, wire bonding property, and die bonding property of the lead frame are further formed on the surface layer thereof. A film layer made of any of palladium, palladium alloy, rhodium, rhodium alloy, ruthenium, ruthenium alloy, platinum, platinum alloy, iridium, iridium alloy, gold, gold alloy, silver, and silver alloy in order to impart such properties. 4'(first surface layer) and film layer 5 (second surface layer) are formed by two layers. The upper part of the film layer 5 is covered with a resin mold (not shown). At this time, the film layers 4'and 5 are formed from different metal species. For example, the film layer 4'is preferably Pd, Rh, Ru, Ir or the like, and the film layer 5 is preferably Au, Ag, Pt or the like. In FIG. 3, the film layers 4'and 5 are formed on the entire surface, but in order to reduce the amount of precious metal used, the film layers 4'and 5 are formed only on the parts that require actions such as wire bonding and soldering. By forming it, it is possible to take an environment-friendly and low-cost form by saving precious metals.

図4は、本発明の一形態における概略断面模式図の拡大図であり、導電性基体1の上層に、垂直粗化層2が形成されており、そのさらに上層に付加粗化層3が形成されているが、その垂直粗化層の間隔6と付加粗化層の間隔7を示す模式図である。このように、垂直粗化層2と付加粗化層3との間隔(それぞれ6および7)は、異なっている。また付加粗化層の間隔7の方が垂直粗化層の間隔6よりも小さい(狭い)ことが好ましい。これは、比較的大きな垂直粗化層2の間隙にモールドされる樹脂が入り込み、本発明により形成された付加粗化層3がその樹脂に対して楔作用を取ることにより、従来よりも強力に樹脂と密着し、その結果、高温高湿などの過酷な試験に対しても樹脂密着性を保持できることによる。 FIG. 4 is an enlarged view of a schematic cross-sectional view according to an embodiment of the present invention, in which a vertical roughening layer 2 is formed on an upper layer of a conductive substrate 1, and an additional roughening layer 3 is formed on the upper layer thereof. However, it is a schematic diagram which shows the interval 6 of the vertical roughening layer and the interval 7 of an additional roughening layer. As described above, the intervals (6 and 7 respectively) between the vertical roughening layer 2 and the additional roughening layer 3 are different. Further, it is preferable that the distance 7 between the additional roughening layers is smaller (narrower) than the distance 6 between the vertical roughening layers. This is because the resin to be molded enters the gap of the relatively large vertical roughening layer 2, and the additional roughening layer 3 formed by the present invention acts as a wedge against the resin, so that it is stronger than before. This is because it adheres to the resin, and as a result, the resin adhesion can be maintained even in harsh tests such as high temperature and high humidity.

図5は、本発明の、図4に示した前記一形態における概略断面模式図の拡大図であり、導電性基体1の上層に、垂直粗化層2が形成されており、そのさらに上層に付加粗化層3が形成されているが、その導電性基体断面線分長さ8(B)と最表層の断面線分長さ9(A)を示す模式図である。ここで、最表層の断面線分長さ9とは、図示したギザギザ状の長さの総長(図5に示したギザギザを引き延ばした長さ9a)をいう。本発明では、この最表層の断面線分長さの総長9a(A)を導電性基体断面線分長さ8(B)で除した値において、その比率(A/B)の値(最表層断面線分長さの総長9a(A)を導電性基体断面長さ8(B)で除した比の値)が好ましくは1.2以上、より好ましくは2以上であることで比表面積が増大して樹脂との密着性が増大する。一方、前記線分長さの比(A/B)の値が4程度を超えると粉落ちしやすい懸念があることから、この線分長さの比(A/B)の値は、好ましくは4以下、より好ましくは3.5倍以下である。 FIG. 5 is an enlarged view of a schematic cross-sectional schematic view of the above embodiment shown in FIG. 4 of the present invention, in which a vertical roughening layer 2 is formed on an upper layer of a conductive substrate 1, and a vertical roughening layer 2 is formed on the upper layer thereof. FIG. 3 is a schematic view showing the conductive substrate cross-sectional line segment length 8 (B) and the surface layer cross-sectional line segment length 9 (A) of which the additional roughened layer 3 is formed. Here, the cross-sectional line segment length 9 of the outermost layer means the total length of the illustrated jagged length (the length 9a obtained by extending the jaggedness shown in FIG. 5). In the present invention, the total length 9a (A) of the cross-sectional line segment length of the outermost layer is divided by the cross-sectional line segment length 8 (B) of the conductive substrate, and the value of the ratio (A / B) (outermost layer). The specific surface area is increased by preferably 1.2 or more, more preferably 2 or more (the value of the ratio obtained by dividing the total length of the cross-sectional line segment length 9a (A) by the cross-sectional length 8 (B) of the conductive substrate). As a result, the adhesion with the resin is increased. On the other hand, if the value of the ratio of line segment lengths (A / B) exceeds about 4, there is a concern that powder may easily fall off, so the value of this ratio of line segment lengths (A / B) is preferable. It is 4 or less, more preferably 3.5 times or less.

以下、本発明を実施例に基づきさらに詳細に説明するが、本発明はこれらに限定されるものではない。 Hereinafter, the present invention will be described in more detail based on examples, but the present invention is not limited thereto.

予め試験片サイズ40mm×40mmに切断した板厚0.2mmの表1に示す各種導電性基体を準備し、下記に示すカソード電解脱脂、酸洗工程の前処理を経たのち、発明例については垂直粗化層および付加粗化層を形成した。比較例としては垂直粗化層を形成後、通常Ni層を付加粗化層として形成した。さらに従来例としては、粗化層として粗化Ni層のみ形成したものを準備した。また、各試料のさらに上層として、付加粗化層の上層にPdめっきを0.02μm形成した後、さらにその上層にAuめっきを0.01μm形成して最表層とした。発明例1〜15は、図3に示した形態である。比較例1は、図6に示した形態においてCu下地めっき12を設けなかった形態である。従来例1は、図6に示した形態である。各粗化層の厚さと平均間隔は、高電流密度ほど間隔を狭く、低電流密度ほど間隔を広く作り分けることができた。
垂直粗化層において、電流密度や被覆厚を変えることにより、垂直粗化層の結晶粒径が変化して付加粗化層の凸凸間隔を制御した。異なる成分の層をそれぞれ粗化めっきすることで、凸凸の間隔が変わってくることによって、間隔(比率)を制御した。粗化厚さは処理時間で、平均間隔は電流密度で作り分けることができた。また、最表層断面線分長さ(最表層断面線分長さの総長)(A)と、導電性基体断面線分長さ(B)を測定し、その比率(最表層断面線分長さの総長9a(A)を導電性基体断面線分長さ8(B)で除した値)(A/B)の値を求めた。これを表中には「表層断面線分長さ比」として示す。
Various conductive substrates shown in Table 1 having a plate thickness of 0.2 mm cut into a test piece size of 40 mm × 40 mm were prepared in advance, and after undergoing the pretreatment of the cathode electrolytic degreasing and pickling steps shown below, the invention example is vertical. A roughened layer and an additional roughened layer were formed. As a comparative example, after the vertical roughening layer was formed, a Ni layer was usually formed as an additional roughening layer. Further, as a conventional example, a roughened layer having only a roughened Ni layer formed was prepared. Further, as a further upper layer of each sample, 0.02 μm of Pd plating was formed on the upper layer of the additional roughening layer, and then 0.01 μm of Au plating was further formed on the upper layer to form the outermost layer. Examples 1 to 15 are the forms shown in FIG. Comparative Example 1 is a form shown in FIG. 6 in which the Cu base plating 12 is not provided. Conventional example 1 is the form shown in FIG. As for the thickness and average spacing of each roughened layer, the higher the current density, the narrower the spacing, and the lower the current density, the wider the spacing.
In the vertical roughened layer, the crystal grain size of the vertical roughened layer was changed by changing the current density and the coating thickness, and the convex-convex spacing of the additional roughened layer was controlled. The spacing (ratio) was controlled by changing the spacing between the convex and convex by rough-plating the layers of different components. The roughening thickness could be determined by the processing time, and the average interval could be created by the current density. Further, the outermost layer cross-sectional line segment length (total length of the outermost layer cross-sectional line segment length) (A) and the conductive substrate cross-sectional line segment length (B) are measured and their ratios (outermost surface layer cross-sectional line segment length) are measured. The value of (A / B) was obtained by dividing the total length 9a (A) of the above by the conductive substrate cross-sectional line segment length 8 (B). This is shown in the table as "surface cross-sectional line segment length ratio".

(前処理条件)
[カソード電解脱脂]
脱脂液:NaOH 60g/リットル
脱脂条件:2.5A/dm、温度60℃、脱脂時間60秒
[酸洗]
酸洗液:10%硫酸
酸洗条件:30秒、浸漬、室温
(Pretreatment conditions)
[Cathode electrolytic degreasing]
Solventing liquid: NaOH 60 g / liter Degreasing conditions: 2.5 A / dm 2 , temperature 60 ° C, degreasing time 60 seconds [pickling]
Pickling solution: 10% Sulfate pickling conditions: 30 seconds, immersion, room temperature

(粗化めっき条件)
[粗化Cuめっき(垂直粗化層を形成)]
めっき液:硫酸銅:銅濃度として5〜10g/リットル、硫酸:30〜120g/リットル、モリブデン酸アンモニウム:Mo金属として0.1〜5.0g/リットル
めっき条件:浴温 20〜60℃、電流密度 10〜60A/dm
[粗化Niめっき(付化粗化層を形成)]
めっき液:株式会社ワールドメタル社製 WDB−321(商品名)
めっき条件:電流密度 8A/dm、 温度 70℃
(Roughened plating conditions)
[Roughened Cu plating (forms vertical roughened layer)]
Plating solution: Copper sulfate: Copper concentration 5-10 g / liter, Sulfate: 30-120 g / liter, Ammonium molybdate: 0.1-5.0 g / liter as Mo metal Plating conditions: Bath temperature 20-60 ° C, current Density 10-60A / dm 2
[Roughened Ni plating (forms roughened layer)]
Plating liquid: WDB-321 (trade name) manufactured by World Metal Co., Ltd.
Plating conditions: current density 8A / dm 2 , temperature 70 ° C

(通常中間めっき条件)
[Niめっき](通常Niめっき)
めっき液:Ni(SONH・4HO 500g/リットル、NiCl 30g/リットル、HBO 30g/リットル
めっき条件:電流密度 10A/dm、温度 50℃
(Normal intermediate plating conditions)
[Ni plating] (normally Ni plating)
Plating solution: Ni (SO 3 NH 2) 2 · 4H 2 O 500g / l, NiCl 2 30 g / l, H 3 BO 3 30g / l Plating Conditions: current density 10A / dm 2, temperature 50 ° C.

[Coめっき(付化粗化層を形成)]
めっき液:Co(SONH・4HO 500g/リットル、CoCl 30g/リットル、HBO 30g/リットル
めっき条件:電流密度 10A/dm、温度 50℃
[Co plating (forming a roughened layer)]
Plating solution: Co (SO 3 NH 2) 2 · 4H 2 O 500g / l, CoCl 2 30 g / l, H 3 BO 3 30g / l Plating Conditions: current density 10A / dm 2, temperature 50 ° C.

(Pdめっき条件)
[Pdめっき(第一表層を形成)]
めっき液:Pd(NHCl 45g/リットル、NHOH 90ミリリットル/リットル、(NHSO 50g/リットル、パラシグマ光沢剤(商品名、松田産業株式会社製) 10ミリリットル/リットル
めっき条件:電流密度 5A/dm、温度 60℃
(Pd plating conditions)
[Pd plating (forming the first surface layer)]
Plating solution: Pd (NH 3 ) 2 Cl 2 45 g / liter, NH 4 OH 90 ml / liter, (NH 4 ) 2 SO 4 50 g / liter, Parasigma brightener (trade name, manufactured by Matsuda Sangyo Co., Ltd.) 10 ml / Liter plating conditions: current density 5A / dm 2 , temperature 60 ° C

(Auめっき条件)
[Auめっき(第二表層を形成)]
めっき液:KAu(CN) 14.6g/リットル、C 150g/リットル、K 180g/リットル
めっき条件:温度 40℃
(Au plating conditions)
[Au plating (forming the second surface layer)]
Plating solution: KAu (CN) 2 14.6 g / liter, C 6 H 8 O 7 150 g / liter, K 2 C 6 H 4 O 7 180 g / liter Plating conditions: Temperature 40 ° C

それぞれ作成した発明例、比較例、従来例の試験片において、樹脂モールドをコータキ精機社製トランスファーモールド試験装置(製品名:Model FTS)にて接触面積4mmのプリン状試験片を形成した。その試験片を高温高湿試験(85℃、85%RH、168時間)に投入し、その試験片について、樹脂密着性評価などを実施した。結果を表1に示す。In the prepared test pieces of the invention example, the comparative example, and the conventional example, a pudding-like test piece having a contact area of 4 mm 2 was formed by using a transfer mold test device (product name: Model FTS) manufactured by Kotaki Seiki Co., Ltd. for the resin mold. The test piece was put into a high temperature and high humidity test (85 ° C., 85% RH, 168 hours), and the test piece was evaluated for resin adhesion and the like. The results are shown in Table 1.

(樹脂密着性評価)
評価樹脂:G630L、住友ベークライト社製(商品名)
評価条件:装置:4000Plus、ノードソン・アドバンスト・テクノロジー社製(商品名)、
ロードセル:50kg
測定レンジ:10kg
テストスピード:100μm/s
テスト高さ:10μm
「A」(優)は平均で10kgf/mm以上である場合、「B」(良)は平均で5kgf/mm以上10kgf/mm未満である場合、「D」(不可)は平均で0kgf/mm以上5kgf/mm未満である場合、と示した。
(Resin adhesion evaluation)
Evaluation resin: G630L, manufactured by Sumitomo Bakelite (trade name)
Evaluation conditions: Equipment: 4000Plus, manufactured by Nordson Advanced Technology (trade name),
Load cell: 50 kg
Measurement range: 10 kg
Test speed: 100 μm / s
Test height: 10 μm
"A" (excellent) if it is on average 10 kgf / mm 2 or more, "B" (good) if it is 10 kgf / mm less than 2 5 kgf / mm 2 or more on average, "D" (No) on average It is shown that the case is 0 kgf / mm 2 or more and less than 5 kgf / mm 2 .

(粉落ち性評価)
目視により感応評価した。「A」(優)は粉落ちが認められなかった場合、「B」(良)は粉落ちが少し発生した場合、「C」(可)は粉落ちが若干多く発生した場合、「D」(不可)は粉落ちが非常に多く発生した場合、と示した。A〜Cは実用に供するレベルである。
(Evaluation of powder removal property)
Sensitivity evaluation was performed visually. "A" (excellent) is "D" when no powder drop is observed, "B" (good) is when powder drop occurs a little, and "C" (possible) is when powder drop occurs a little more. (Impossible) indicates that when a large amount of powder falling occurs. A to C are levels for practical use.

(平均間隔の評価)
各粗化層の間隔の比としては、垂直断面から走査型電子顕微鏡(SEM)で観察した像において任意の各層の凸部を決め、そこから右方向に連続する10か所の隣り合う凸と凸の間隔(頂点間隔)を測定し、その平均値から比を求めた。また、間隔比(付化/垂直)とは、付化粗化層の間隔の垂直粗化層の間隔に対する比率を算出した値をいう。なお、各凸凸間隔の測定は、図4に示すように、前記垂直断面観察により確認された凸部頂点と隣の凸部頂点との間隔(垂直粗化層の間隔6、付化粗化層の間隔7)の平均値を取って、「平均間隔」を表1に示した。また、条のTD方向に略10等分した各箇所においてSEM観察を行い、得られたSEM像から最表層の断面の線分長さ(最表層の断面の線分長さの総長)(A)と、導電性基体断面の線分長さ(B)を測定し、その比率(最表層の断面の線分長さの総長9a(A)を導電性基体断面の線分長さ8(B)で除した値)(A/B)の値を求めた。これを表中には「表層断面線分長さ比」として示す。
(Evaluation of average interval)
As the ratio of the spacing between the roughened layers, a convex portion of any arbitrary layer is determined in an image observed with a scanning electron microscope (SEM) from a vertical cross section, and 10 adjacent convex portions continuous to the right are defined. The convex spacing (peak spacing) was measured, and the ratio was calculated from the average value. Further, the interval ratio (applied / vertical) means a value obtained by calculating the ratio of the interval of the attached roughened layer to the interval of the vertically roughened layer. As shown in FIG. 4, the measurement of each convex-convex interval is performed by measuring the interval between the convex apex confirmed by the vertical cross-sectional observation and the adjacent convex apex (vertical roughening layer interval 6, roughening roughening). The "average spacing" is shown in Table 1 by taking the average value of the layer spacing 7). In addition, SEM observation was performed at each location divided into approximately 10 equal parts in the TD direction of the strip, and from the obtained SEM image, the line segment length of the cross section of the outermost layer (total length of the line segment length of the cross section of the outermost layer) (A). ) And the line segment length (B) of the conductive substrate cross section, and the ratio (the total length 9a (A) of the line segment length of the outermost layer cross section is the line segment length 8 (B) of the conductive substrate cross section. ) Divided by) (A / B). This is shown in the table as "surface cross-sectional line segment length ratio".

Figure 0006789965
Figure 0006789965

1 導電性基体
2 垂直粗化層
3 付化粗化層
4 表層
4’ 第一表層
5 第二表層
6 垂直粗化層の間隔
7 付化粗化層の間隔
8 基体断面長さ
9 最表層断面長さ
9a 最表層断面長さの総長
11 導電性基体(銅、銅合金、鉄、鉄合金など)
12 銅下地めっき層
13 ニッケル粗化めっき層
14 表層(ニッケル粗化めっき層に沿って成長)
1 Conductive substrate 2 Vertical roughened layer 3 Attached roughened layer 4 Surface layer 4'First surface layer 5 Second surface layer 6 Vertical roughened layer spacing 7 Attached roughened layer spacing 8 Base cross-section length 9 Outermost surface layer cross section Length 9a Total length of outermost surface cross-sectional length 11 Conductive substrate (copper, copper alloy, iron, iron alloy, etc.)
12 Copper base plating layer 13 Nickel roughened plating layer 14 Surface layer (grown along the nickel roughened plating layer)

Claims (9)

導電性基体上に粗化層を有するリードフレーム材において、その粗化層は、複数層の粗化層からなり、前記粗化層が、導電性基体の垂直方向に少なくとも1層からなる垂直粗化層を有するとともに、さらにその垂直粗化層の上層に付加粗化層を少なくとも1層以上有し、前記垂直粗化層及び付加粗化層がそれぞれ有する凹凸の内、前記付加粗化層の隣り合う凸部の頂点の平均間隔が前記垂直粗化層の隣り合う凸部の頂点の平均間隔の1/20以上3/4以下であることを特徴とするリードフレーム材。 In a lead frame material having a roughened layer on a conductive substrate, the roughened layer is composed of a plurality of roughened layers, and the roughened layer is a vertical coarse layer composed of at least one layer in the vertical direction of the conductive substrate. and has a layer further has its top in the additional roughened layer of vertical roughened layer at least one layer, among irregularities the vertical roughened layer and additional roughened layer has each of the additional roughened layer A lead frame material characterized in that the average distance between the vertices of adjacent convex portions is 1/20 or more and 3/4 or less of the average distance between the vertices of adjacent convex portions of the vertical roughening layer . 最表層断面の線分長さ(A)と導電性基体断面の線分長さ(B)の比(A/B)の値が1.2以上4以下である請求項1に記載のリードフレーム材。 The lead frame according to claim 1, wherein the value of the ratio (A / B) of the line segment length (A) of the outermost layer cross section to the line segment length (B) of the conductive substrate cross section is 1.2 or more and 4 or less. Material. 前記導電性基体は、銅または銅合金、鉄または鉄合金、アルミニウムまたはアルミニウム合金であることを特徴とする、請求項1または2に記載のリードフレーム材。 The lead frame material according to claim 1 or 2, wherein the conductive substrate is copper or a copper alloy, iron or an iron alloy, or aluminum or an aluminum alloy. 前記複数の粗化層は2層からなり、導電性基体の垂直方向に粗化された第一の垂直粗化層と、その垂直粗化層の上層の第二の付加粗化層を有し、さらにその垂直粗化層と付加粗化層それぞれの成分が異なることを特徴とする、請求項1から3のいずれか1項に記載のリードフレーム材。 The plurality of roughened layers are composed of two layers, and have a first vertical roughened layer that is roughly roughened in the vertical direction of the conductive substrate, and a second additional roughened layer that is an upper layer of the vertical roughened layer. The lead frame material according to any one of claims 1 to 3, further characterized in that the components of the vertical roughening layer and the additional roughening layer are different. 前記垂直粗化層の成分が、銅または銅合金からなることを特徴とする、請求項1〜のいずれか1項に記載のリードフレーム材。 The lead frame material according to any one of claims 1 to 4 , wherein the component of the vertical roughening layer is made of copper or a copper alloy. 前記付加粗化層の成分が、ニッケル、ニッケル合金、コバルト、コバルト合金のうちのいずれかからなることを特徴とする、請求項1〜のいずれか1項に記載のリードフレーム材。 The lead frame material according to any one of claims 1 to 5 , wherein the component of the additional roughened layer is made of any one of nickel, a nickel alloy, cobalt, and a cobalt alloy. 前記導電性基体は、垂直方向に粗化された垂直粗化層を有するとともに、その垂直粗化層の上層として付加粗化層を有し、さらに付加粗化層の上層に、パラジウム、パラジウム合金、ロジウム、ロジウム合金、ルテニウム、ルテニウム合金、白金、白金合金、イリジウム、イリジウム合金、金、金合金、銀、銀合金のうちいずれかからなる表層を、リードフレーム材の全面あるいは部分的に、単層または複数層有することを特徴とする、請求項1〜のいずれか1項に記載のリードフレーム材。 The conductive substrate has a vertical roughened layer roughened in the vertical direction, an additional roughened layer as an upper layer of the vertical roughened layer, and a palladium-palladium alloy as an upper layer of the additional roughened layer. , Rhodium, rhodium alloy, ruthenium, ruthenium alloy, platinum, platinum alloy, iridium, iridium alloy, gold, gold alloy, silver, silver alloy on the surface layer of any of the following, all or part of the lead frame material. The lead frame material according to any one of claims 1 to 6 , wherein the lead frame material has one layer or a plurality of layers. 前記垂直粗化層および付加粗化層のうち、いずれかまたは双方とも電気めっきにより形成されることを特徴とする、請求項1〜のいずれか1項に記載のリードフレーム材の製造方法。 The method for producing a lead frame material according to any one of claims 1 to 7 , wherein either or both of the vertical roughening layer and the additional roughening layer are formed by electroplating. 前記請求項1〜のいずれか1項に記載のリードフレーム材を使用した、半導体パッケージ。 A semiconductor package using the lead frame material according to any one of claims 1 to 7 .
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