JP5387374B2 - Lead frame manufacturing method - Google Patents

Lead frame manufacturing method Download PDF

Info

Publication number
JP5387374B2
JP5387374B2 JP2009276774A JP2009276774A JP5387374B2 JP 5387374 B2 JP5387374 B2 JP 5387374B2 JP 2009276774 A JP2009276774 A JP 2009276774A JP 2009276774 A JP2009276774 A JP 2009276774A JP 5387374 B2 JP5387374 B2 JP 5387374B2
Authority
JP
Japan
Prior art keywords
metal plate
plating
lead frame
plating layer
plated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009276774A
Other languages
Japanese (ja)
Other versions
JP2010114451A (en
Inventor
順太郎 三上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP2009276774A priority Critical patent/JP5387374B2/en
Publication of JP2010114451A publication Critical patent/JP2010114451A/en
Application granted granted Critical
Publication of JP5387374B2 publication Critical patent/JP5387374B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

本発明は、半導体装置に使用されるリードフレームの製造方法に関し、特にSON(Small Outline Non-Leaded Package)やQFN(Quad Flat Non-Leaded Package)と呼ばれ、樹脂パッケージの裏面にリードが露出して外部接続端子となるタイプの半導体装置に用いられるリードフレームの製造方法に関する。   The present invention relates to a method of manufacturing a lead frame used in a semiconductor device, and is particularly called SON (Small Outline Non-Leaded Package) or QFN (Quad Flat Non-Leaded Package), and leads are exposed on the back surface of a resin package. The present invention relates to a method of manufacturing a lead frame used in a semiconductor device of a type that serves as an external connection terminal.

近年、基板への高密度実装化に伴い、基板に実装される半導体装置の小型化・薄型化が要求され、いわゆるCSP(Chip Size Package)と呼ばれる半導体装置の普及が急速に進んでいる。特に、リードフレームを用いた小型の半導体装置においては、図3に示すように、半導体素子7を搭載するリードフレームの上面を樹脂9で封止し、封止したパッケージの裏面側からリード3の下面が露出する片面封止タイプのSONやQFNと呼ばれる半導体装置15が開発されている。そして、このような半導体装置15には、全面にパラジウムめっきが施された図4に示すような態様のリードフレームを用いることが多い。   2. Description of the Related Art In recent years, with high-density mounting on a substrate, the semiconductor device mounted on the substrate is required to be reduced in size and thickness, and the so-called CSP (Chip Size Package) is rapidly spreading. In particular, in a small semiconductor device using a lead frame, as shown in FIG. 3, the top surface of the lead frame on which the semiconductor element 7 is mounted is sealed with resin 9, and the leads 3 are formed from the back side of the sealed package. A semiconductor device 15 called a single-side sealing type SON or QFN whose bottom surface is exposed has been developed. Such a semiconductor device 15 often uses a lead frame having a form as shown in FIG. 4 with palladium plating on the entire surface.

このSONやQFNタイプの半導体装置15は、リード3の上面と側面を樹脂9で封止し、リード3の下面を樹脂9から露出させ外部接続端子とする構造で、リード3と樹脂9との密着性が弱い。このため、樹脂9で封止した後にそれぞれの半導体装置15同士を形成する境界部をダイシングソーによって切断加工して個々の半導体装置15とする際、リード3がリード3の上面と側面を封止した樹脂9と離れ、抜け落ちやすい欠点を有している。   The SON or QFN type semiconductor device 15 has a structure in which the upper surface and side surface of the lead 3 are sealed with a resin 9 and the lower surface of the lead 3 is exposed from the resin 9 to serve as an external connection terminal. Adhesion is weak. For this reason, when the boundary portions that form the semiconductor devices 15 after being sealed with the resin 9 are cut by a dicing saw to form individual semiconductor devices 15, the leads 3 seal the upper surface and side surfaces of the leads 3. It has a defect that it is separated from the resin 9 and easily falls off.

一般的に樹脂との密着性は、銅、銀、パラジウム、金の順番に悪い。また、部分めっきより全面めっきの方が悪くなることが知られており、上記のようにSONやQFNタイプの半導体装置はリード3の上面と側面を樹脂9で封止した構造であり、個々の半導体装置15にする際、リード3とリード3の上面を封止した樹脂9とが離れて抜け落ちやすいという構造的な欠点だけでなく、全面にパラジウムめっきを施すリードフレームは、そもそも樹脂との密着性が悪い。また、通常パラジウムめっきを施す際には、ニッケルなどの下地めっき層の上にパラジウムをめっきし、更にワイヤーボンディング時の信頼性を向上させるために、パラジウムのめっき層の上に金をフラッシュめっきした3層構造となっている。そのため、更に樹脂との密着性は悪い。   In general, the adhesion with the resin is poor in the order of copper, silver, palladium, and gold. In addition, it is known that the whole surface plating is worse than the partial plating. As described above, the SON or QFN type semiconductor device has a structure in which the upper surface and the side surface of the lead 3 are sealed with the resin 9. When the semiconductor device 15 is formed, not only the structural defect that the lead 3 and the resin 9 sealing the upper surface of the lead 3 are separated and easily fall off, but also the lead frame on which the entire surface is plated with palladium is in close contact with the resin. The nature is bad. In addition, when palladium plating is usually applied, palladium is plated on an underplating layer such as nickel, and gold is flash-plated on the palladium plating layer in order to improve reliability during wire bonding. It has a three-layer structure. Therefore, the adhesiveness with the resin is further poor.

このような半導体装置のリードの抜け落ちの防止を目的とした技術が、例えば特許文献1乃至3に提案されている。   For example, Patent Documents 1 to 3 propose techniques for preventing such a semiconductor device lead from falling off.

そして、特許文献1には、プレス加工によってリード断面を逆台形形状にしてリードの抜け落ちを防止する技術が提案されている。   Patent Document 1 proposes a technique for preventing the lead from falling off by making the lead cross section into an inverted trapezoidal shape by press working.

また、特許文献2には、プレス加工やプラズマ加工によってリード表面を粗化する技術が提案されている。   Patent Document 2 proposes a technique of roughening the lead surface by press working or plasma processing.

また、特許文献3には、安価なリードフレームを提供することを目的としてパラジウムを部分めっきする技術によって、樹脂との密着性が悪いめっき面の面積を小さくでき、全面をめっきするよりも密着性が向上する技術が提案されている。   Further, Patent Document 3 discloses a technique for partially plating palladium for the purpose of providing an inexpensive lead frame, which can reduce the area of the plating surface with poor adhesion to the resin, and has better adhesion than plating the entire surface. There are proposals for techniques to improve this.

特開平11−260983号公報Japanese Patent Laid-Open No. 11-260983 特開2003−158234号公報JP 2003-158234 A 特開2003−78097号公報JP 2003-78097 A

しかし、特許文献1に記載の技術のように、リードフレームを逆台形形状に成形する場合やリードフレームの表面粗化のためにプレス加工を行った場合、リードフレームの片面側を加工する点については、加工歪による影響によってリードフレームに反りが生じ品質を劣化させる問題があった。   However, as in the technique described in Patent Document 1, when the lead frame is formed into an inverted trapezoidal shape or when press working is performed to roughen the surface of the lead frame, one side of the lead frame is processed. However, there is a problem that the lead frame is warped due to the influence of processing distortion and the quality is deteriorated.

また、特許文献2に記載の技術のように、リードフレームの表面粗化のために新たにプラズマ加工によってリードフレームを製造する工程を追加したのでは、製造コストがアップする問題があった。また、リードフレームの表面粗化のためにエッチング加工によってリードフレームを製造する工程でも、新たにプレス加工を工程に追加する必要があり、さらに製造コストがアップする問題があった。   Further, as in the technique described in Patent Document 2, if a process for manufacturing a lead frame by plasma processing is newly added to roughen the surface of the lead frame, there is a problem that the manufacturing cost increases. In addition, even in the process of manufacturing the lead frame by etching to roughen the surface of the lead frame, it is necessary to newly add press processing to the process, which further increases the manufacturing cost.

また、特許文献3に記載の技術のように、リードフレーム全面にパラジウム又はパラジウムの上に金がめっきされているリードフレームでは、パラジウム及び金と樹脂とはそもそも密着性が悪いので、リードフレーム全面にパラジウム又はパラジウムの上に金のめっきを施しているリードフレームは、樹脂との密着性は悪い。そのため、めっき面の表面にアンカー効果を求めた場合、表面の粗いめっき面にすると樹脂との密着性は向上するが、半田の濡れ性が悪くなる。一方、表面の平滑なめっき面にすると半田の濡れ性は向上するが、樹脂との密着性が乏しくなる。そのため、樹脂との密着性と半田の濡れ性について双方を満足できるめっき面が得られないという問題があった。   Further, in the lead frame in which palladium is plated on the entire surface of the lead frame or gold on the palladium as in the technique described in Patent Document 3, palladium, gold, and resin have poor adhesion in the first place. The lead frame having gold plated on palladium or palladium has poor adhesion to the resin. Therefore, when the anchor effect is obtained on the surface of the plating surface, if the surface is a rough plating surface, the adhesion with the resin is improved, but the wettability of the solder is deteriorated. On the other hand, when the plated surface is smooth, the wettability of the solder is improved, but the adhesion with the resin is poor. Therefore, there is a problem that a plated surface that satisfies both the adhesiveness to the resin and the wettability of the solder cannot be obtained.

そこで、本発明は、従来方法の有する上記のような課題に鑑みて成されたものである。その目的とするところは、リードフレームに加工歪を与えず、製造コストアップになること無く、めっき表面のアンカー効果を向上させることによって、リードと樹脂との密着性をより向上させることができ、樹脂からリードが抜け落ちないようにするリードフレームの製造方法を提供することである。   Therefore, the present invention has been made in view of the above-described problems of conventional methods. The aim is to improve the adhesion between the lead and the resin by improving the anchor effect of the plating surface without giving processing distortion to the lead frame and without increasing the manufacturing cost, It is an object of the present invention to provide a method for manufacturing a lead frame that prevents a lead from falling off from a resin.

上記目的を達成するために、本発明のリードフレームの製造方法は、金属板の両面にレジストを用いてめっきを施す部分を露出させたマスクを形成し、めっきを施した後、エッチング加工によってリードフレーム形状を形成する製造方法であって、金属板の上面に表面の粗いめっきを施すため金属板の上面用めっき槽でアノードを金属板の上面の側にのみ設置して金属板の上面めっきし、金属板の下面に表面の平滑なめっきを施すため金属板の下面用めっき槽でアノードを金属板の下面の側にのみ設置して金属板の下面めっきをすることで、金属板の上面と下面にそれぞれ異なる表面粗さのめっき層が形成されるようにしたことを特徴とする。 In order to achieve the above object, the lead frame manufacturing method of the present invention uses a resist on both sides of a metal plate to form a mask that exposes portions to be plated, and after plating, leads are etched. a manufacturing method of forming a frame shape, the anode in the plating bath for the upper surface of the metal plate for applying rough plating of the surface on the upper surface of the metal plate is installed only on the side of the upper surface of the metal plate on the upper surface of the metallic plate the plating, by plating on the lower surface of the anode at the lower surface for plating bath of a metal plate for applying a smooth plating surface to the lower surface of the metal plate is installed only on the side of the lower surface of the metal plate metallic plate, Plating layers having different surface roughnesses are formed on the upper surface and the lower surface of the metal plate, respectively.

また、上記目的を達成するために、本発明のリードフレームの製造方法は、金属板の両面にレジストを用いてめっきをしたい部分を露出させたマスクを形成し、金属板の上面に表面の粗いめっきを施すための上面用ニッケルめっき槽でアノードを金属板の上面の側にのみ設置し金属板の上面めっきし、金属板の下面に表面の平滑なめっきを施すため金属板の下面用ニッケルめっき槽でアノードを金属板の下面の側にのみ設置し金属板の下面めっきをすることで、金属板の上面と下面にそれぞれ異なる表面粗さのニッケルめっき層を形成した後、金属板の両面のめっき層の上に両面同時にパラジウムめっき層を形成し、次に金めっき層を形成することを特徴とする。 In addition, in order to achieve the above object, the lead frame manufacturing method of the present invention forms a mask that exposes a portion to be plated using a resist on both surfaces of a metal plate, and has a rough surface on the upper surface of the metal plate. In the nickel plating bath for the upper surface for plating, the anode is installed only on the upper surface side of the metal plate, the upper surface of the metal plate is plated , and the lower surface of the metal plate is used for smooth plating of the lower surface of the metal plate After forming the nickel plating layers with different surface roughness on the upper and lower surfaces of the metal plate by plating the lower surface of the metal plate by installing the anode only on the lower surface side of the metal plate in the nickel plating tank for It is characterized in that a palladium plating layer is formed on both surfaces of the metal plate at the same time, and then a gold plating layer is formed.

また、本発明のリードフレームの製造方法は、前記金属板の上面下面にそれぞれ異なる表面粗さのニッケルめっき層を形成する工程は、それぞれ異なる組成のニッケルめっき浴を用いることが好ましいA method of manufacturing a lead frame of the present invention, the step of forming a nickel plating layer having different surface roughness on the upper surface and the lower surface of the metal plate, it is preferable to use a nickel plating bath having different compositions.

本発明によるリードフレームの製造方法によれば、リードフレームに加工歪を与えず、製造コストアップになることもなく、樹脂との密着性を向上させることができる。   According to the lead frame manufacturing method of the present invention, adhesion to the resin can be improved without giving processing distortion to the lead frame and without increasing the manufacturing cost.

また、本発明の製造方法によって製作されるリードフレームは、リードフレームの必要部分のみをめっきする部分めっきとすることが可能であるため、パラジウムめっきを施しても樹脂との密着性が悪いめっき面の面積を最小限にすることができる。また、リードの上面であるワイヤーボンディング部をボンディングが可能で樹脂との密着性を向上させる粗さの表面を持つ粗面めっき層とすることが可能であるため、そのようにすることによって、リードの抜け落ちを防止できるようになる。また、リードの下面である外部接続端子部を、半田の濡れ性が良い平滑な表面を持つ平滑面めっき層とすることが可能であるため、そのようにすると、基板等への実装が好適に行えるようになる。   In addition, since the lead frame manufactured by the manufacturing method of the present invention can be a partial plating for plating only a necessary portion of the lead frame, the plating surface has poor adhesion to the resin even if palladium plating is performed. Can be minimized. In addition, since the wire bonding portion, which is the upper surface of the lead, can be formed into a rough plating layer having a rough surface that can be bonded and improves the adhesion to the resin, the lead can be obtained by doing so. It will be possible to prevent omission. In addition, the external connection terminal portion, which is the lower surface of the lead, can be a smooth surface plating layer having a smooth surface with good solder wettability. You can do it.

(a)は、本発明の実施例1に係るリードフレームの断面図であり、(b)は、リードの拡大断面図である。(A) is sectional drawing of the lead frame which concerns on Example 1 of this invention, (b) is an expanded sectional view of a lead. (a)〜(l)は、本発明の実施例1に係るリードフレームの製造方法を示す工程図である。(A)-(l) is process drawing which shows the manufacturing method of the lead frame which concerns on Example 1 of this invention. (a)は、半導体装置の断面図であり、(b)は、グランド用ボンディング部としてパッドの周囲にリング状にめっきを施した半導体装置の断面図である。(A) is sectional drawing of a semiconductor device, (b) is sectional drawing of the semiconductor device which plated to the circumference | surroundings of a pad as a bonding part for grounds. (a)は、リードフレームの平面図であり、(b)は、単位リードフレームを示す平面図である。(A) is a top view of a lead frame, (b) is a top view which shows a unit lead frame.

まず、本発明のリードフレームの作製手順について、図2を用いて説明する。
本発明は、図2(a)に示すように、金属板12を用い、前処理として、図2(b)に示すように、金属板12の両面にドライフィルムレジスト13を設け、図2(c)に示すように、金属板12の上面と下面のそれぞれの面で、めっきが必要な部分のドライフィルムレジスト13を剥離する。
First, the manufacturing procedure of the lead frame of the present invention will be described with reference to FIG.
As shown in FIG. 2 (a), the present invention uses a metal plate 12, and as a pretreatment, as shown in FIG. 2 (b), a dry film resist 13 is provided on both surfaces of the metal plate 12, and FIG. As shown in c), the dry film resist 13 is peeled off from the upper and lower surfaces of the metal plate 12 where plating is necessary.

めっきの前処理をした後、図2(d)に示すように、最初のニッケルめっき槽で、金属板12の上面のみにニッケルめっきを施す。次に、図2(e)に示すように、別のニッケルめっき槽で、金属板12の下面のみにニッケルめっきを施す。ここで、本発明に係るリードフレームの製造方法のように、最初のニッケルめっき槽で、金属板の一方の面側のみにアノードを設置しめっきを行えば、アノードのある金属板の面側のみにめっき層が形成される。この場合金属板のもう一方の面側は、金属板が境となってめっき層が形成されない。次に、別のニッケルめっき槽で、金属板のもう一方の面側のみにアノードを設置しめっきを行えば、金属板のもう一方の面側のみにめっき層が形成される。このように、本発明のリードフレームの製造方法によれば、金属板12の両面を独立させ、別々にめっき層を形成することができる。   After the pretreatment for plating, as shown in FIG. 2D, nickel plating is performed only on the upper surface of the metal plate 12 in the first nickel plating tank. Next, as shown in FIG. 2E, nickel plating is performed only on the lower surface of the metal plate 12 in another nickel plating tank. Here, as in the lead frame manufacturing method according to the present invention, in the first nickel plating tank, if the anode is installed only on one surface side of the metal plate and plating is performed, only the surface side of the metal plate with the anode is provided. A plating layer is formed on the substrate. In this case, the plating layer is not formed on the other surface side of the metal plate with the metal plate as a boundary. Next, in another nickel plating tank, if an anode is installed only on the other side of the metal plate and plating is performed, a plating layer is formed only on the other side of the metal plate. Thus, according to the lead frame manufacturing method of the present invention, both surfaces of the metal plate 12 can be made independent and the plating layers can be formed separately.

この2つのめっきでは、それぞれ所望の表面の粗さを有するめっき層が得られるようにめっき浴を設定する。例えば、図1(b)に示す表面の粗いニッケルめっきを施すにはワット浴の塩素濃度を通常の2倍以上に調整して用い、図1(b)に示す表面の平滑なニッケルめっきを施すにはスルファミン酸ニッケルめっき浴を用いることで、金属板12の一方の面側に図1(b)に示す表面の粗いニッケルめっき層を形成し、金属板12のもう一方の面側に図1(b)に示す表面の平滑なニッケルめっき層を形成した金属板12を得ることが可能となる。   In these two platings, the plating bath is set so that a plating layer having a desired surface roughness can be obtained. For example, in order to apply rough nickel plating as shown in FIG. 1 (b), the chlorine concentration of the Watt bath is adjusted to at least twice the normal concentration, and smooth nickel plating as shown in FIG. 1 (b) is applied. 1, a nickel plating layer having a rough surface shown in FIG. 1B is formed on one surface side of the metal plate 12 by using a nickel sulfamate plating bath, and FIG. 1 is formed on the other surface side of the metal plate 12. It becomes possible to obtain the metal plate 12 on which the nickel plating layer having a smooth surface shown in (b) is formed.

なお、これら2回のめっきにおいて、金属板12の一方の面のみにめっきをする際には、塩化ビニ―ル板等をセットして遮蔽するとさらに効果的である。   In these two platings, when plating only one surface of the metal plate 12, it is more effective to set and shield a vinyl chloride plate or the like.

次に、図2(f)に示すように、金属板12の両面にそれぞれ形成されたニッケルめっき層の上に同時にパラジウムめっき層を、更にその上に金めっき層を形成する。これにより、金属板12の両面に本発明のそれぞれ図1(b)に示す表面の粗さの異なる3層構造から成るめっき層5及び6が得られる。   Next, as shown in FIG. 2 (f), a palladium plating layer is simultaneously formed on the nickel plating layers formed on both surfaces of the metal plate 12, and a gold plating layer is further formed thereon. Thereby, plating layers 5 and 6 having a three-layer structure with different surface roughnesses shown in FIG. 1B of the present invention are obtained on both surfaces of the metal plate 12, respectively.

次に、図2(g)に示すように、上記めっき層5及び6が形成された金属板12からドライフィルムレジスト13を剥離する。次に、図2(h)に示すように、再び、上記めっき層5及び6が形成された金属板12の全面にドライフィルムレジスト13を設ける。次に、図2(i)に示すように、エッチング用パターンを形成し、エッチング処理を行い、図2(j)に示すように、所定のリードフレームの形状を形成する。次に、図2(k)に示すように、ドライフィルムレジスト13を剥離する。これにより、リードフレームが完成する。   Next, as shown in FIG. 2G, the dry film resist 13 is peeled from the metal plate 12 on which the plating layers 5 and 6 are formed. Next, as shown in FIG. 2 (h), the dry film resist 13 is again provided on the entire surface of the metal plate 12 on which the plating layers 5 and 6 are formed. Next, as shown in FIG. 2 (i), an etching pattern is formed and an etching process is performed to form a predetermined lead frame shape as shown in FIG. 2 (j). Next, as shown in FIG. 2 (k), the dry film resist 13 is peeled off. Thereby, the lead frame is completed.

例えば、上記めっき層5及び6は、厚さが約1μmのニッケルめっき層と、厚さが約0.1μmのパラジウムめっき層と、厚さが約0.05μmの金めっき層でそれぞれ形成する。   For example, the plating layers 5 and 6 are formed of a nickel plating layer having a thickness of about 1 μm, a palladium plating layer having a thickness of about 0.1 μm, and a gold plating layer having a thickness of about 0.05 μm, respectively.

形成された3層構造から成るめっき層のめっき面の表面粗さは、下地となる厚いニッケルめっき層のめっき面の表面の粗さをコントロールすることにより決定される。また、ニッケルめっきを施す際のニッケルめっき槽の浴組成をコントロールすることで、形成されるめっき層の表面の粗さをコントロールすることができる。   The surface roughness of the plated surface of the formed three-layered plating layer is determined by controlling the surface roughness of the plated surface of the thick nickel plated layer as a base. Moreover, the roughness of the surface of the plating layer formed is controllable by controlling the bath composition of the nickel plating tank at the time of performing nickel plating.

上記のように形成しためっき層のめっき面の表面粗さに対する、半田の濡れ性、樹脂との密着性、ボンディング性の評価結果を表1に示す。   Table 1 shows the evaluation results of solder wettability, resin adhesion, and bondability with respect to the surface roughness of the plating surface of the plating layer formed as described above.

表1

Figure 0005387374
Table 1
Figure 0005387374

表1において、半田の濡れ性は、ソルダーチェッカーを使用したメニスコグラフ法により測定し、230℃で溶融したH63S共晶はんだを含むるつぼの中に試料片を浸漬し、その時のゼロクロスタイム(ZCT)を測定すると共に試料片を引き上げた後に顕微鏡で濡れていない部分がないか半田の濡れ具合を確認することで評価した。この評価における○は濡れていない部分はなく、ZCTが1秒以内である場合、△は濡れていない部分はなく、ZCTが1〜3秒以内である場合、×は濡れていない部分はなく、ZCTが3秒以上である場合をそれぞれ表している。   In Table 1, the wettability of the solder is measured by a meniscograph method using a solder checker. A sample piece is immersed in a crucible containing H63S eutectic solder melted at 230 ° C., and the zero cross time (ZCT) at that time is measured. The measurement was performed and the sample piece was pulled up, and then evaluated by checking the wetness of the solder to see if there was any portion that was not wet with a microscope. In this evaluation, there is no portion that is not wet, and when ZCT is within 1 second, Δ is that there is no portion that is wet, and when ZCT is within 1 to 3 seconds, × is that there is no portion that is not wet, Each represents a case where ZCT is 3 seconds or more.

また、樹脂との密着性は、めっき面に2mm角のポッドを175℃×90秒で成形し、その後にポストモールドキュアを4時間行った。この成形した樹脂片を横方向からシェアツールで押し、樹脂がめっき面から引き剥がされるときの強度を測定することで評価した。この評価における○は平均で10kgf/4mm2以上である場合、△は平均で5〜10kgf/4mm2である場合、×は平均で0〜5kgf/4mm2である場合をそれぞれ表している。 The adhesiveness with the resin was obtained by forming a 2 mm square pod on the plated surface at 175 ° C. for 90 seconds and then performing post mold curing for 4 hours. This molded resin piece was evaluated by measuring the strength when the resin was peeled from the plated surface by pressing it with a shear tool from the side. In this evaluation, ◯ represents an average of 10 kgf / 4 mm 2 or more, Δ represents an average of 5 to 10 kgf / 4 mm 2 , and x represents an average of 0 to 5 kgf / 4 mm 2 .

また、ボンディング性は、Φ30μmの金線を用いてヒータブロック設定温度200℃でワイヤボンディングを行い、その後にボンディングされたワイヤの下にフックを入れ、下から上へ垂直にワイヤを引き上げる、いわゆるフックプル方式でプル強度を測定し、ワイヤが切れる時の強度を測定することで評価した。この評価における○はプル強度が平均で5gf以上であり、△は平均で5gf以下である場合をそれぞれ表している。   In addition, the bonding property is a so-called hook pull, in which wire bonding is performed at a heater block set temperature of 200 ° C. using a Φ30 μm gold wire, a hook is then placed under the bonded wire, and the wire is pulled up vertically from the bottom to the top. The pull strength was measured by a method and evaluated by measuring the strength when the wire was cut. In this evaluation, “◯” represents a case where the average pull strength is 5 gf or more, and “Δ” represents a case where the average is 5 gf or less.

表1に示すように、樹脂9と密着するボンディング面側となる表面の粗いめっき層5では、表面粗さ(Ra)は、0.20μm以上0.70μm以下が好ましい。また、パッケージの裏面から露出して外部接続端子となる側の表面の平滑なめっき層6では、表面粗さ(Ra)は、0.10μm以下が好ましい。   As shown in Table 1, the surface roughness (Ra) of the rough plating layer 5 on the bonding surface side in close contact with the resin 9 is preferably 0.20 μm or more and 0.70 μm or less. In the smooth plating layer 6 on the surface exposed from the back surface of the package and serving as the external connection terminal, the surface roughness (Ra) is preferably 0.10 μm or less.

図1及び図2は本発明の実施例に係るリードフレームの説明図であり、図1はリードフレームの断面図、図2(a)〜(l)はリードフレームの製造方法の工程を示す状態説明図である。   1 and 2 are explanatory views of a lead frame according to an embodiment of the present invention, FIG. 1 is a cross-sectional view of the lead frame, and FIGS. 2A to 2L show the steps of the lead frame manufacturing method. It is explanatory drawing.

まず、図2(a)に示すように、金属板12として銅合金を用い、図2(b)に示すように、両面にドライフィルムレジスト13を貼り付けた。その後、図2(c)に示すように,リードフレームの形状の中で上面として図1に示すめっき層5が必要な部分を遮光するガラスマスクと下面として図1に示すめっき層6が必要な部分を遮光するガラスマスクを位置合わせした状態で、ドライフィルムレジスト13付き銅合金の両面上に被せ、被せた両面のガラスマスクを介して紫外光で露光した。   First, as shown in FIG. 2 (a), a copper alloy was used as the metal plate 12, and as shown in FIG. 2 (b), a dry film resist 13 was attached to both surfaces. Thereafter, as shown in FIG. 2 (c), a glass mask that shields a portion of the lead frame that requires the plating layer 5 shown in FIG. 1 as the upper surface and the plating layer 6 shown in FIG. 1 as the lower surface is required. In a state where a glass mask that shields the portion was aligned, it was placed on both sides of the copper alloy with the dry film resist 13 and exposed to ultraviolet light through the covered glass masks on both sides.

露光後ガラスマスクを外し、ドライフィルムレジスト13付き銅合金を現像液に浸して現像することにより、紫外光が遮光された部分、即ちパッド部やワイヤーボンディング部、外部接続端子部などのめっきを施す必要のある部分のドライフィルムレジスト13のみを除去した。   After exposure, the glass mask is removed, and the copper alloy with the dry film resist 13 is dipped in a developing solution and developed, so that plating is performed on the portion where the ultraviolet light is shielded, that is, the pad portion, wire bonding portion, external connection terminal portion, etc. Only the necessary dry film resist 13 was removed.

次に、アルカリや酸で前処理をした後に、図2(d)に示すように,リードフレームの上面となる方にのみアノードを設置しためっき槽を用いて、ワット浴により電流密度2A/dm2で2分間めっきを施し、厚さが1μmの図1(b)に示す表面の粗いニッケルめっき層を形成した。次に、図2(e)に示すように、リードフレームの下面となる方にのみアノードを設置しためっき槽を用いて、スルファミン酸ニッケルめっき浴により電流密度2A/dm2で2分間めっきを施し、厚さが1μmの図1(b)に示す表面の平滑なニッケルめっき層を形成した。 Next, after pre-treatment with alkali or acid, as shown in FIG. 2 (d), a current density of 2 A / dm is applied by a watt bath using a plating tank in which an anode is installed only on the upper surface of the lead frame. 2 for 2 minutes to form a rough nickel plating layer having a thickness of 1 μm as shown in FIG. Next, as shown in FIG. 2 (e), using a plating tank having an anode only on the lower surface of the lead frame, plating is performed at a current density of 2 A / dm 2 for 2 minutes using a nickel sulfamate plating bath. A smooth nickel plating layer having a thickness of 1 μm as shown in FIG. 1B was formed.

次に、図2(f)に示すように、パラジウムを銅合金の両面にそれぞれ形成されたニッケルめっき層の上に同時に厚さが0.10μmのパラジウムめっき層を形成し、更に、その上に厚さが0.05μmの金めっき層を形成した。これにより、銅合金の両面にそれぞれ表面の粗さの異なる3層構造から成るめっき層5及び6を得た。次に、図2(g)に示すように、めっきが施されたドライフィルムレジスト13付き銅合金から、ドライフィルムレジスト13を剥離した。   Next, as shown in FIG. 2 (f), a palladium plating layer having a thickness of 0.10 μm is simultaneously formed on the nickel plating layers formed on both sides of the copper alloy, and further, A gold plating layer having a thickness of 0.05 μm was formed. Thereby, plating layers 5 and 6 each having a three-layer structure with different surface roughnesses were obtained on both surfaces of the copper alloy. Next, as shown in FIG. 2G, the dry film resist 13 was peeled from the plated copper alloy with the dry film resist 13.

次に、図2(h)に示すように、めっきが施された銅合金の両面の全面にフォトレジストとしての役目をするドライフィルムレジスト13を貼り付けた。次に、リードフレームの上面としてリードフレームの形状以外を遮光するガラスマスクとリードフレームの下面としてリードフレームの形状以外を遮光するガラスマスクを位置合わせした状態で、めっきが施されたドライフィルムレジスト13付き銅合金の両面の上に被せ、被せた両面のガラスマスクを介して紫外光で露光した。   Next, as shown in FIG. 2 (h), a dry film resist 13 serving as a photoresist was attached to the entire surface of both surfaces of the plated copper alloy. Next, the dry film resist 13 is plated in a state where the glass mask that shields light other than the shape of the lead frame as the upper surface of the lead frame and the glass mask that shields light other than the shape of the lead frame as the lower surface of the lead frame are aligned. The coated copper alloy was covered on both surfaces and exposed to ultraviolet light through the covered glass masks on both surfaces.

露光後、ガラスマスクを外し、めっきが施されたドライフィルムレジスト13付き銅合金を現像液に浸して現像することにより、紫外光が遮光された部分、即ちリードフレームの形状以外の部分のドライフィルムレジスト13を除去した。   After the exposure, the glass mask is removed, and the plated copper alloy with the dry film resist 13 is developed by immersing it in a developer to develop a portion where the ultraviolet light is shielded, that is, the portion other than the shape of the lead frame. The resist 13 was removed.

次に、図2(i)に示すように、めっきが施されたドライフィルムレジスト13付き銅合金の両面に、噴射ノズル14によりエッチング液を吹き付けてエッチング処理を行い、図2(j)に示すように、所定のリードフレームの形状を形成した。次に、図2(k)に示すように、ドライフィルムレジスト13を剥離して、めっき層付きリードフレームを作製した。   Next, as shown in FIG. 2 (i), an etching process is performed by spraying an etching solution onto the both surfaces of the plated copper alloy with the dry film resist 13 by using a spray nozzle 14, and the result is shown in FIG. 2 (j). Thus, a predetermined lead frame shape was formed. Next, as shown in FIG. 2 (k), the dry film resist 13 was peeled off to produce a lead frame with a plating layer.

このようにして作製したリードフレームの上面である金線ボンディング部のめっき表面の表面粗さ(Ra)は、0.21μm、下面である外部接続端子部のめっき表面の表面粗さ(Ra)は、0.06μmとなった。   The surface roughness (Ra) of the plating surface of the gold wire bonding portion, which is the upper surface of the lead frame thus fabricated, is 0.21 μm, and the surface roughness (Ra) of the plating surface of the external connection terminal portion, which is the lower surface, is 0.06 μm.

また、エッチング用ガラスマスクは、リード3の上面が下面より幅広になるように設計し、エッチング処理によってリードフレームのリード3を、上面が下面より広く形成した。   The glass mask for etching was designed so that the upper surface of the lead 3 was wider than the lower surface, and the lead 3 of the lead frame was formed wider than the lower surface by etching.

次に、個々の半導体装置15同士を形成する境界をハーフエッチングして樹脂9で封止し、後のダイシングソーによる個々の半導体装置15に切断する際に金属バリが低減できるよう、切断する金属部分が少なくなるようにした。   Next, a metal to be cut is cut so that a boundary between the individual semiconductor devices 15 is half-etched and sealed with a resin 9, and metal burrs can be reduced when cutting into individual semiconductor devices 15 by a subsequent dicing saw. I tried to reduce the number of parts.

1 パッド
2 吊りリード
3 リード
4 ダムバー
5 粗いめっき層
6 平滑なめっき層
7 半導体素子
8 ワイヤー(金線)
9 樹脂
10 ハーフエッチング
11 単位リードフレーム
12 金属板
13 ドライフィルムレジスト
14 噴射ノズル
15 半導体
DESCRIPTION OF SYMBOLS 1 Pad 2 Suspended lead 3 Lead 4 Dam bar 5 Rough plating layer 6 Smooth plating layer 7 Semiconductor element 8 Wire (gold wire)
9 Resin 10 Half etching 11 Unit lead frame 12 Metal plate 13 Dry film resist 14 Injection nozzle 15 Semiconductor

Claims (3)

金属板の両面にレジストを用いてめっきを施す部分を露出させたマスクを形成し、めっきを施した後、エッチング加工によってリードフレーム形状を形成する製造方法であって、金属板の上面に表面の粗いめっきを施すため金属板の上面用めっき槽でアノードを金属板の上面の側にのみ設置して金属板の上面めっきし、金属板の下面に表面の平滑なめっきを施すため金属板の下面用めっき槽でアノードを金属板の下面の側にのみ設置して金属板の下面めっきをすることで、金属板の上面と下面にそれぞれ異なる表面粗さのめっき層が形成されるようにしたことを特徴とするリードフレームの製造方法。 A method of forming a lead frame shape by etching after forming a mask that exposes portions to be plated using resist on both sides of a metal plate, and performing plating, wherein the surface of the metal plate is formed on the upper surface of the metal plate. metal for applying rough plating anodes in the upper surface for plating bath of a metal plate for applying installed only on the side of the upper surface of the metal plate is plated on the upper surface of the metallic plate, a smooth plating surface to the lower surface of the metal plate by it the anode in the lower surface for plating bath of the plate is installed only on the side of the lower surface of the metal plate to the plating on the lower surface of the metallic plate, plating layers of different surface roughness, respectively on the upper and lower surfaces of the metal plate is formed A method for manufacturing a lead frame, characterized in that: 金属板の両面にレジストを用いてめっきをしたい部分を露出させたマスクを形成し、金属板の上面に表面の粗いめっきを施すための上面用ニッケルめっき槽でアノードを金属板の上面の側にのみ設置し金属板の上面めっきし、金属板の下面に表面の平滑なめっきを施すため金属板の下面用ニッケルめっき槽でアノードを金属板の下面の側にのみ設置し金属板の下面めっきをすることで、金属板の上面と下面にそれぞれ異なる表面粗さのニッケルめっき層を形成した後、金属板の両面のめっき層の上に両面同時にパラジウムめっき層を形成し、次に金めっき層を形成することを特徴とするリードフレームの製造方法。 Using a resist on both sides of the metal plate, a mask exposing the part to be plated is formed, and the anode is placed on the upper surface side of the metal plate in a nickel plating bath for the upper surface to apply rough plating to the upper surface of the metal plate. only by installing the plating on the upper surface of the metal plate, the anode on the lower surface for nickel plating bath of a metal plate for applying a smooth plating surface to the lower surface of the metal plate is installed only on the side of the lower surface of the metal plate metal plate by the lower surface plating, after forming a nickel plating layer having different surface roughness on the upper surface and the lower surface of the metal plate, both sides at the same time to form a palladium plating layer on the plating layer of both sides of the metal plate, the following Forming a gold plating layer on the lead frame. 前記金属板の上面下面にそれぞれ異なる表面粗さのニッケルめっき層を形成する工程は、それぞれ異なる組成のニッケルめっき浴を用いることを特徴とする請求項2に記載のリードフレームの製造方法。 Forming a different surface roughness nickel plating layer on the upper surface and lower surface of the metal plate, the manufacturing method of lead frame according to claim 2, characterized by using a nickel plating bath having different compositions.
JP2009276774A 2009-12-04 2009-12-04 Lead frame manufacturing method Active JP5387374B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009276774A JP5387374B2 (en) 2009-12-04 2009-12-04 Lead frame manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009276774A JP5387374B2 (en) 2009-12-04 2009-12-04 Lead frame manufacturing method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2004279459A Division JP2006093559A (en) 2004-09-27 2004-09-27 Lead frame and its manufacturing method

Publications (2)

Publication Number Publication Date
JP2010114451A JP2010114451A (en) 2010-05-20
JP5387374B2 true JP5387374B2 (en) 2014-01-15

Family

ID=42302721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009276774A Active JP5387374B2 (en) 2009-12-04 2009-12-04 Lead frame manufacturing method

Country Status (1)

Country Link
JP (1) JP5387374B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102403282B (en) * 2011-11-22 2013-08-28 江苏长电科技股份有限公司 Packaging structure with basic islands and without pins at four sides and manufacturing method thereof
JP6362111B2 (en) * 2014-12-01 2018-07-25 大口マテリアル株式会社 Lead frame manufacturing method
CN108026657B (en) * 2015-11-05 2020-05-26 古河电气工业株式会社 Lead frame material and method for producing same
JP7029504B2 (en) * 2020-09-23 2022-03-03 Shプレシジョン株式会社 Manufacturing method of lead frame and power semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11229196A (en) * 1998-02-12 1999-08-24 Mitsubishi Shindoh Co Ltd Electroplating device and electroplating method
JP2003158234A (en) * 2001-11-21 2003-05-30 Hitachi Ltd Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
JP2010114451A (en) 2010-05-20

Similar Documents

Publication Publication Date Title
JP2006093559A (en) Lead frame and its manufacturing method
US6475646B2 (en) Lead frame and method of manufacturing the lead frame
US20020153596A1 (en) Lead frame and semiconductor package formed using it
JP6493952B2 (en) Lead frame and manufacturing method thereof
TWI462253B (en) Lead frame board, method of forming the same
TWI479626B (en) Lead frame board, method of forming the same, and semiconductor device
JP2004349497A (en) Packaging component and semiconductor package
JP4698708B2 (en) Package parts and semiconductor packages
JP6741356B1 (en) Lead frame
JP5387374B2 (en) Lead frame manufacturing method
JP2010080889A (en) Lead frame and method of manufacturing the same
JP2006303215A (en) Resin-sealed semiconductor device
TWI660068B (en) Lead-frame structure, lead-frame, surface mount electronic device and methods of producing same
JP2011108818A (en) Manufacturing method of lead frame and manufacturing method of semiconductor device
JP4628263B2 (en) Package component, manufacturing method thereof, and semiconductor package
JP6733940B1 (en) Lead frame
JPH11121673A (en) Lead frame
JP6693642B2 (en) Lead frame
JP5264939B2 (en) Package parts and semiconductor packages
JP5034913B2 (en) Semiconductor device manufacturing substrate and manufacturing method thereof
JP6744020B1 (en) Lead frame
JP5299411B2 (en) Lead frame manufacturing method
JP2017130522A (en) Resin-attached lead frame substrate
JP6736716B1 (en) Lead frame
KR100828490B1 (en) Method of manufactuning leadframe

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120924

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121016

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121217

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20121217

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20121227

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130910

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130923

R150 Certificate of patent or registration of utility model

Ref document number: 5387374

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313115

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350