TWI696273B - 具有輔助閘的快閃記憶體暨其製作方法 - Google Patents

具有輔助閘的快閃記憶體暨其製作方法 Download PDF

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TWI696273B
TWI696273B TW108116696A TW108116696A TWI696273B TW I696273 B TWI696273 B TW I696273B TW 108116696 A TW108116696 A TW 108116696A TW 108116696 A TW108116696 A TW 108116696A TW I696273 B TWI696273 B TW I696273B
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gate
gates
flash memory
auxiliary gate
floating gates
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TW202044551A (zh
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許漢杰
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力晶積成電子製造股份有限公司
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Priority to CN201910444569.XA priority patent/CN111952308A/zh
Priority to US16/520,305 priority patent/US10892341B2/en
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Abstract

一種具有輔助閘的快閃記憶體，其具有兩浮動閘設置在基底上、一絕緣層形成在該兩浮動閘以及該基底上、一輔助閘設置在該兩浮動閘之間，其中該輔助閘有部分包覆住該兩浮動閘、以及兩選擇閘，分別設置在該兩浮動閘外側且有部分與該浮動閘重疊。

Description

具有輔助閘的快閃記憶體暨其製作方法
本發明與一種快閃記憶體有關，更具體言之，其係關於一種具有輔助閘的快閃記憶體結構，可降低快閃記憶體所需的工作電壓。
快閃記憶體(flash memory)問世至今已有30餘年，有別於揮發性記憶體如動態隨機存取記憶體(DRAM)或是靜態隨機存取記憶體(SRAM)，快閃記憶體是一種非揮發性記憶體，其應用層面極為廣泛，特別是在消費性電子產品方面，包括個人電腦、行動通訊產品、數位相機等，皆需要具有體積小、容量大、低耗電、可修改等特性的記憶裝置，快閃記憶體無疑符合上述所有要求。
一般快閃記憶體寫入資料(program)的原理是利用熱電子注入(hot electron injection)或是源極側注入(source side injection)等方式來將電子寫進記憶單元的浮動閘極中，浮動閘極就像是位能井一樣將電子儲存於其中；而抹除資料通常則是利用反向的FN穿隧效應來達成。上述寫入或抹除狀態會決定浮動閘中電子的多寡，進而影響浮動閘下方的通道電場，故根據所讀出的電流大小就可以判定出該記憶單元的資料態。
在快閃記憶體的運作中，浮動閘的耦合率(coupling ratio)會影響到快閃記憶體的讀取/寫入速度，其與浮動閘和源極之間的重疊面積有關，重疊面積 越大，耦合率越好，儲存單元所需的工作電壓也可降低。然而，隨著製程技術的進步，現今浮動閘的尺寸不斷地微縮，已經來到了奈米尺度的級別。雖然浮動閘的單元尺寸持續的縮小，但是寫入與抹除動作所需的電壓並沒有按比例地縮小。在先進一代的製程工藝中，這樣的負擔越來越大，特別是對於嵌入式的非揮發性記憶體應用，其周邊電路相關的高壓電晶體製作變得越來越困難和昂貴，而如果採用加大浮動閘的尺寸來增加耦合率之作法，其無疑又增加了儲存單元的尺寸，違背電子元件尺寸微縮的發展前提。
有鑑於習知技術中的快閃記憶體需要高工作電壓且尺寸不易微縮，本發明特此提出了一種新穎的快閃記憶體結構，其具備一額外的輔助閘來分擔所需的工作電壓，進而能夠縮小記憶體單元的尺寸。
本發明的其一面向在於一種具有輔助閘的快閃記憶體，包含一基底、兩浮動閘，設置在該基底上、一絕緣層，共形地形成在該兩浮動閘以及該基底上、一輔助閘，設置在該兩浮動閘之間的該絕緣層上，其中該輔助閘有部分包覆住該兩浮動閘、以及兩選擇閘，分別設置在該兩浮動閘外側的該絕緣層上，其中該選擇閘有部分與該浮動閘重疊。
本發明的另一面向在於一種製作具有輔助閘的快閃記憶體的方法，包含提供一基底，該基底上依序具有一穿隧氧化層與一第一多晶矽層、進行一第一蝕刻製程蝕刻該多晶矽層以及該穿隧氧化層，以形成兩浮動閘、在該兩浮動閘以及該基底上形成一共形的絕緣層、在該絕緣層上形成一第二多晶矽層、以及進行一第二蝕刻製程蝕刻該第二多晶矽層，以形成一輔助閘與兩選擇閘，其中該輔助閘形成在該兩浮動閘之間的該絕緣層上，且該輔助閘有部分包覆住該兩浮動閘，該兩選擇閘分別形成在該兩浮動閘外側的該絕緣層上，且該選擇 閘有部分與該浮動閘重疊。
本發明的這類目的與其他目的在閱者讀過下文以多種圖示與繪圖來描述的較佳實施例細節說明後必然可變得更為明瞭顯見。
1:快閃記憶體
100:基底
102:浮動閘
102a:多晶矽層
102c:表面
104:穿隧氧化層
104a:氧化層
106:源極
108:絕緣層
110:輔助閘
112:選擇閘
114:汲極
116:尖端部位
118:氮化矽層
118a:開口
120:犧牲氧化層
122:多晶矽層
124:光阻
BL:位元線
OC:工作電壓控制電路
SLC:來源線電壓控制電路
WLC:字元線電壓控制電路
本說明書含有附圖併於文中構成了本說明書之一部分，俾使閱者對本發明實施例有進一步的瞭解。該些圖示係描繪了本發明一些實施例並連同本文描述一起說明了其原理。在該些圖示中：第1圖為根據本發明較佳實施例一示例性的快閃記憶體截面示意圖；以及第2-9圖為根據本發明較佳實施例第1圖所示快閃記憶體的製作流程的截面示意圖。
須注意本說明書中的所有圖示皆為圖例性質，為了清楚與方便圖示說明之故，圖示中的各部件在尺寸與比例上可能會被誇大或縮小地呈現，一般而言，圖中相同的參考符號會用來標示修改後或不同實施例中對應或類似的元件特徵。
現在下文將詳細說明本發明的示例性實施例，其會參照附圖示出所描述之特徵以便閱者理解並實現技術效果。閱者將可理解文中之描述僅透過例示之方式來進行，而非意欲要限制本案。本案的各種實施例和實施例中彼此不衝突的各種特徵可以以各種方式來加以組合或重新設置。在不脫離本發明的精神與範疇的情況下，對本案的修改、等同物或改進對於本領域技術人員來說是可以理解的，並且旨在包含在本案的範圍內。
閱者應能容易理解，本案中的「在…上」、「在…之上」和「在…上方」的含義應當以廣義的方式被解讀，以使得「在…上」不僅表示「直接在」某物「上」而且還包括在某物「上」且其間有居間特徵或層的含義，並且「在…之上」或「在…上方」不僅表示「在」某物「之上」或「上方」的含義，而且還可以包括其「在」某物「之上」或「上方」且其間沒有居間特徵或層(即，直接在某物上)的含義。
此外，諸如「在…之下」、「在…下方」、「下部」、「在…之上」、「上部」等空間相關術語在本文中為了描述方便可以用於描述一個元件或特徵與另一個或多個元件或特徵的關係，如在附圖中示出的。
如本文中使用的，術語「基底」是指向其上增加後續材料的材料。可以對基底自身進行圖案化。增加在基底的頂部上的材料可以被圖案化或可以保持不被圖案化。此外，基底可以包括廣泛的半導體材料，例如矽、鍺、砷化鎵、磷化銦等。或者，基底可以由諸如玻璃、塑膠或藍寶石晶圓的非導電材料製成。
如本文中使用的，術語「層」是指包括具有厚度的區域的材料部分。層可以在下方或上方結構的整體之上延伸，或者可以具有小於下方或上方結構範圍的範圍。此外，層可以是厚度小於連續結構的厚度的均質或非均質連續結構的區域。例如，層可以位於在連續結構的頂表面和底表面之間或在頂表面和底表面處的任何水平面對之間。層可以水準、豎直和/或沿傾斜表面延伸。基底可以是層，其中可以包括一個或多個層，和/或可以在其上、其上方和/或其下方具有一個或多個層。層可以包括多個層。例如，互連層可以包括一個或多個導體和接觸層(其中形成觸點、互連線和/或通孔)和一個或多個介電層。
此外，下述之方法與結構係著重在單一記憶體單元的形成與特徵，在實際製作中，會同時有一整個陣列的這些記憶體單元被形成在基底的記憶單 元區中。較佳來說，這些記憶體單元會形成在成欄的主動區域中，其由絕緣區域所分隔，這些主動區域與絕緣區域的形成都是習知技藝。
[記憶體結構]
現在請參照第1圖，其為根據本發明較佳實施例一示例性的快閃記憶體截面示意圖。快閃記憶體1可以建構在一半導體基底100中的記憶單元(cell)區的主動區域上。例如，半導體基底100可為一P型矽基底，其上具有複數個由淺溝渠隔離結構(shallow trench isolation,STI)或是場氧化結構(field oxide)所界定出來的主動區域，快閃記憶體1則形成在這些主動區域上。然而，應了解其他的半導體基底如矽覆絕緣層基底(silicon-on-insulator,SOI)或是磊晶基底也可應用在本發明中。
每個快閃記憶體1都包含兩個浮動閘102成對地設置在基底100上，呈現出鏡像單元組架構。兩浮動閘102之間彼此相隔一段距離，以提供用來設置輔助閘的空間，其與基底100之間形成有穿隧氧化層(tunnel oxide)104將浮動閘102與基底100彼此電性隔絕。浮動閘102可以多晶矽材料製成，穿隧氧化層104則可為氧化矽層。兩浮動閘102之間的基底100中形成有一源極106，源極106有部分區域會與兩浮動閘102重疊，以提供浮動閘102較佳的耦合率(coupling ratio)。
一絕緣層108共形地形成在兩浮動閘102以及基底100上。一輔助閘110設置在兩浮動閘102之間的絕緣層108上，其藉由絕緣層108而與兩浮動閘102電性隔絕。須注意在本實施例中，有部分的輔助閘110會嵌入兩浮動閘102之間的空間中，且有部分的輔助閘110會與兩浮動閘102重疊，使得輔助閘110會包覆住所鄰接部分的該兩浮動閘102，如此可藉由輔助閘110進一步增進浮動閘102的耦合率。
兩選擇閘112分別設置在兩浮動閘102外側的絕緣層108上，其中部分的選擇閘112會與浮動閘102重疊，以提供電子抹除路徑。兩汲極114分別形成在 兩選擇閘112外側的基底100中。輔助閘110與選擇閘112都可以多晶矽材料形成，且由於在同一道製程中形成的緣故，其頂面可能齊高。絕緣層108則可為氧化矽層，與穿隧氧化層104同樣具有穿隧特性。須注意在本實施例中，浮動閘102的外側角落會以特殊製程形成具有向上突起的尖端部位116。此尖端部位116會與選擇閘112重疊，其可促進快閃記憶體的抹除運作。
前述實施例為本發明快閃記憶體1的基本結構，其各部位還會進一步電性連接到其他的外部結構來達成讀取/寫入/抹除等運作。復參照第1圖，在本實施例中，快閃記憶體1的源極106即為一來源線(source line)，其會電性連接到一來源線電壓控制電路SLC，以控制來源線的電壓。快閃記憶體1的輔助閘110會電性連接到一工作電壓控制電路OC，以控制輔助閘110的電壓。在本實施例中，快閃記憶體1的選擇閘112即為字元線(word line)，每列記憶體單元的選擇閘112共同作為單一的字元線，其會電性連接到一字元線電壓控制電路WLC，以控制選擇閘112的電壓。快閃記憶體1的汲極114會電性連接到一位元線(bit line)BL，其可能設置在整個快閃記憶體1的上方，而每條位元線BL還會進一步連接到一位元線電壓控制電路(未示出)，以控制位元線BL以及其所連接的汲極114的電壓。
[運作方式]
在記憶體的寫入(program)運作中，當想要所選的記憶體單元被執行寫入，其汲極114會被施加0伏，選擇閘112會被施加一正壓，其接近選擇閘112所界定之MOS結構的臨界電壓，約為3.3伏。而源極106與輔助閘110都會被施加一正壓，約為6伏。從汲極114生成的電子會因為源極106與輔助閘110的正壓從汲極114經由選擇閘112下方的通道流向源極106。當電子來到浮動閘102下方的區域時，由於浮動閘102與帶有較高正壓的源極106以及輔助閘110具有較強的電容耦合，電子會被加速且會穿過穿隧氧化層104而被注入浮動閘102中，如此電子就被 儲存在所選擇的記憶體單元中，如第1圖中的路徑
Figure 108116696-A0305-02-0009-10
，此即源極測注入或熱電子注入原理。在此運作中，源極106與輔助閘110可分擔寫入浮動閘102所需的高正壓，故所需施加之正壓僅需習知技術的一半即可，約為6伏。如此，記憶體對於周邊高壓電路的需求就沒有那麼嚴格，儲存單元的尺寸也可進一步的縮小。
在記憶體的讀取運作中，源極106與輔助閘110會被接地，汲極114會被施加一讀取電壓，約為1伏，而選擇閘112會被施加裝置的供壓(Vcc)。在這樣的情況下，如果浮動閘102是帶正電的(即沒有電子儲存在浮動閘102中)，那浮動閘102下方的通道會被開路，選擇閘112下方的通道也會因為供壓的關係被開路，使得電子從源極106流到汲極114，如此記憶體會被測為“1”的資料態。另一方面，如果浮動閘102是帶負電的，那浮動閘102下方的通道會閉路，沒有電子會從源極106流到汲極114，如此記憶體會被測為“0”的資料態。
最後，在記憶體的抹除運作中，源極106與汲極114都會被接地，選擇閘112會被施加一正壓，約為6伏。較特別的是，輔助閘110會被施加一負壓，約為-5伏。選擇閘112的正壓以及輔助閘110的負壓會促使浮動閘102中的電子因為反向FN穿隧機制而穿過浮動閘102與選擇閘112之間的絕緣層，如第1圖中的路徑
Figure 108116696-A0305-02-0009-11
，使得浮動閘102中的電子被清空而帶正電。該處尖銳的浮動閘102尖端部位116可以增強此反向FN穿隧機制，使得抹除的速度更快。值得注意的是，輔助閘110在此運作中也如同寫入運作起到了分擔電壓的效果，有別於習知技術僅透過選擇閘或額外設置的抹除閘來施加高正壓(如10-12伏)抹除電子，本案的輔助閘110在另一側提供了一半的負壓推力，使得選擇閘112一側只要約一半的正壓(即6伏)即可達成FN穿隧，如此可以降低周邊高壓電路的需求並可進一步縮小儲存單元尺寸。
[製作方法]
現在請依序參照第2-9圖，其繪示出根據本發明較佳實施例第1圖所示之快閃記憶體1的製作流程的截面示意圖。首先請參照第2圖，提供一基底100，如P型矽基底或是其他的半導體基底如矽覆絕緣層基底或是磊晶基底，其上可具有複數個由淺溝渠隔離結構或是場氧化結構所界定出來的主動區域。由於上述的主動區域與隔離結構之製作並非本發明之重點，此處將省略其製作流程，圖中所示之基底一律為記憶單元區中的主動區域。一氧化層104a，如氧化矽，形成在基底100上。氧化層104a可使用氧化或沉積(如化學氣相沉積，CVD)等習知技術形成在基底100上。一多晶矽層102a形成在氧化層104a的頂面上。多晶矽層102a可使用低壓化學氣相沉積(LPCVD)等習知技術沉積在氧化層104a上。一氮化矽層118形成在多晶矽層102a的頂面上，其較佳使用CVD方式形成。在實施例中，氮化矽層118是用來界定浮動閘的，其上會使用光刻技術形成開口118a而裸露出下方的多晶矽層102a。
接下來請參照第3圖。進行一熱氧化製程，使得從開口118a裸露出的多晶矽層102a氧化成為犧牲氧化層120。此熱氧化步驟所形成之犧牲氧化層120會具有透鏡形狀的外型，其周圍接近氮化矽層118的部位會漸縮並稍微延伸到氮化矽層118的下方。因為犧牲氧化層120的形成，剩餘的多晶矽層102a會具有傾斜的表面102c。
接下來請參照第4圖。進行一選擇性蝕刻步驟移除氮化矽層118以及前述製程中形成的犧牲氧化層120，裸露出下方的多晶矽層102a。如此，多晶矽層102a會具有一從兩側向下凹的表面102c，即使得多晶矽層102a形成相對突出的部位。
接下來請參照第5圖。使用光阻進行一非等向性蝕刻製程來界定出浮動閘102。此非等向性蝕刻步驟會移除前述多晶矽層102a的下凹表面102c以外的部分以及下凹表面102c中間的部分，如此即能形成如第5圖所示鏡像成對、外側 具有尖銳的尖端部位116的浮動閘102。須注意此步驟同時也會移除多晶矽層102a下方部分的氧化層104a，形成浮動閘102與基底100之間的穿隧氧化層104。
接下來請參照第6圖。進行一離子佈植製程在兩浮動閘102之間的基底100中形成源極106(即來源線)，期間可搭配熱擴散製程使得摻雜的源極106擴散延伸至浮動閘102，使得部分的源極106會與兩浮動閘102重疊，以達到電容耦合。之後，在兩浮動閘102與基底100的表面上形成一層共形的絕緣層108。絕緣層108可使用熱氧化以及/或高溫氧化沉積等製程來形成。
接下來請參照第7圖。在絕緣層108形成另一厚的多晶矽層122，其可使用低壓化學氣相沉積方式形成，並在多晶矽層122上形成光阻124，其中光阻124會具有預定的輔助閘圖案與選擇閘圖案，其裸露出部分的多晶矽層122。
接下來請參照第8圖。以光阻124為遮罩進行一非等向性蝕刻製程移除裸露的多晶矽層122，如此即形成了如第8圖所示的輔助閘110以及選擇閘112。可以看到輔助閘110形成在兩浮動閘102之間，其藉由絕緣層108與兩浮動閘102電性隔絕。有部分的輔助閘110嵌入兩浮動閘102之間的空間中，且有部分的輔助閘110會與兩浮動閘102重疊，使得輔助閘110會包覆住所鄰接部分的兩浮動閘102，如此可藉由輔助閘110進一步增進浮動閘102的耦合率。兩選擇閘112則分別設置在兩浮動閘102外側的絕緣層108上，其中部分的選擇閘112會與浮動閘102重疊，以提供電子抹除路徑。由於在同一道製程中形成的緣故，輔助閘110與選擇閘112的頂面可能齊高。光阻124在輔助閘110與選擇閘112形成後可以加以移除。
最後請參照第9圖。在形成選擇閘112之後，進行另一離子佈植製程在兩選擇閘112外側的基底100中形成汲極114，如此即完成了本發明快閃記憶體1的基本結構。之後，還可進行如接觸結構以及金屬導線等互連結構之製作，來將源極106、汲極114、輔助閘110以及選擇閘112連接到所需的電壓控制電路如位元線BL、字元線電壓控制電路WLC、來源線電壓控制電路SLC、工作電壓控制 電路OC等，如此即完成了快閃記憶體1之製作。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1:快閃記憶體
100:基底
102:浮動閘
104:穿隧氧化層
106:源極
108:絕緣層
110:輔助閘
112:選擇閘
114:汲極
116:尖端部位
BL:位元線
OC:工作電壓控制電路
SLC:來源線電壓控制電路
WLC:字元線電壓控制電路

Claims (12)

  1. 一種具有輔助閘的快閃記憶體，包含：一基底；兩浮動閘，設置在該基底上；一絕緣層，共形地形成在該兩浮動閘以及該基底表面上；一輔助閘，設置在該兩浮動閘之間的該絕緣層上，其中該輔助閘有部分包覆住該兩浮動閘；兩選擇閘，分別設置在該兩浮動閘外側的該絕緣層上，其中部分該選擇閘與該基底之間設有該絕緣層與該浮動閘，其餘部分之該選擇閘與該基底之間僅設有該絕緣層。
  2. 如申請專利範圍第1項所述之具有輔助閘的快閃記憶體，更包含：一源極，形成在該兩浮動閘之間的該基底中，其中該源極有部分與該兩浮動閘重疊；以及兩汲極，分別形成在該兩選擇閘的外側該基底中。
  3. 如申請專利範圍第2項所述之具有輔助閘的快閃記憶體，其中該源極為來源線，該汲極連接到一位元線，該選擇閘為字元線，該輔助閘連接到一工作電壓控制電路。
  4. 如申請專利範圍第3項所述之具有輔助閘的快閃記憶體，其中在該快閃記憶體的寫入運作中，該輔助閘連接到該工作電壓控制電路所提供之正壓，而在該快閃記憶體的抹除運作中，該輔助閘連接到該工作電壓控制電路所提供之負壓。
  5. 如申請專利範圍第1項所述之具有輔助閘的快閃記憶體，更包含一穿隧氧化層形成在該兩浮動閘與該基底之間。
  6. 如申請專利範圍第1項所述之具有輔助閘的快閃記憶體，其中該浮動閘與該選擇閘重疊部分的角落具有向上突起的尖端部位。
  7. 如申請專利範圍第1項所述之具有輔助閘的快閃記憶體，其中該輔助閘與該兩選擇閘係由同一多晶矽層構成並且兩者的頂面齊高。
  8. 如申請專利範圍第1項所述之具有輔助閘的快閃記憶體，其中該浮動閘、該輔助閘以及該選擇閘的材料皆為多晶矽。
  9. 一種製作具有輔助閘的快閃記憶體的方法，包含：提供一基底，該基底上依序具有一穿隧氧化層與一第一多晶矽層；進行一第一蝕刻製程蝕刻該多晶矽層以及該穿隧氧化層，形成兩浮動閘；在該兩浮動閘以及該基底上形成一共形的絕緣層；在該絕緣層上形成一第二多晶矽層；以及進行一第二蝕刻製程蝕刻該第二多晶矽層，以形成一輔助閘與兩選擇閘，其中該輔助閘形成在該兩浮動閘之間的該絕緣層上，且該輔助閘有部分包覆住該兩浮動閘，該兩選擇閘分別形成在該兩浮動閘外側的該絕緣層上，且該選擇閘有部分與該浮動閘重疊。
  10. 如申請專利範圍第9項所述之製作具有輔助閘的快閃記憶體的方法， 其中形成該兩浮動閘的步驟更包含：在該第一多晶矽層上形成一氮化矽層，其中該氮化矽層具有開口裸露出該第一多晶矽層；進行一熱氧化製程，使從該開口裸露出的該第一多晶矽層氧化成犧牲氧化層；以及進行一選擇性蝕刻製程移除該氮化矽層以及該犧牲氧化層，使得該第一多晶矽層具有從兩側向下凹的表面。
  11. 如申請專利範圍第10項所述之製作具有輔助閘的快閃記憶體的方法，其中該第一蝕刻製程移除具有下凹表面的部分該第一多晶矽層，形成外側具有向上突起的尖端部位的該兩浮動閘。
  12. 如申請專利範圍第9項所述之製作具有輔助閘的快閃記憶體的方法，更包含：進行一第一離子佈植製程在該浮動閘之間的該基底中形成源極，其中該源極有部分與該兩浮動閘重疊；以及進行一第二離子佈植製程在該兩選擇閘的外側的該基底中分別形成一汲極。
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