TWI690978B - 保護圖案化介電金屬塗層之雙塗覆及剝離方法 - Google Patents

保護圖案化介電金屬塗層之雙塗覆及剝離方法 Download PDF

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TWI690978B
TWI690978B TW105111915A TW105111915A TWI690978B TW I690978 B TWI690978 B TW I690978B TW 105111915 A TW105111915 A TW 105111915A TW 105111915 A TW105111915 A TW 105111915A TW I690978 B TWI690978 B TW I690978B
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傑夫瑞 普爾
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B1/00—Optical elements characterised by the material of which they are made; Optical coatings for optical elements
    • G02B1/10—Optical coatings produced by application to, or surface treatment of, optical elements
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B1/00—Optical elements characterised by the material of which they are made; Optical coatings for optical elements
    • G02B1/10—Optical coatings produced by application to, or surface treatment of, optical elements
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Abstract

本發明揭示一種使用2層微影製程來保護圖案化介電質-金屬塗層之雙塗覆及剝離方法，該微影製程經暴露及顯影以形成底切結構，且隨後在用以不完全最終層結束之金屬/介電質濾光劑塗覆晶圓之後，剝離頂部微影層以暴露金屬層邊緣且將底部微影層完整留在晶圓上，使得可沈積最終濾光層以完成塗層且使暴露之金屬層邊緣鈍化。

Description

保護圖案化介電金屬塗層之雙塗覆及剝離方法
本發明屬於薄膜介電質-金屬塗層之領域。更特定言之，其為一種使用雙塗覆及剝離方法來保護圖案化介電質-金屬塗層之方法。
已知若干沈積及保護介電質-金屬塗層之先前技術方法，諸如頒予Buchsbaum等人之美國專利第7,648,808號中所描述的方法，其處理沈積在圖案化特徵之頂部上的最終毯覆式塗層。在Buchsbaum所揭示之方法中，使用剝離製程接著使用新穎最終毯覆式塗覆步驟來對特徵進行圖案化及沈積，該最終毯覆式塗覆步驟完成塗層堆疊且產生金屬層邊緣之鈍化。金屬層邊緣之鈍化防止金屬之氧化及腐蝕。最終毯覆層可為一組層，諸如最終空腔鏡面、抗反射層或單層材料。此等層可使用針對其耐腐蝕特性特異性選擇之材料。此先前技術與部分或完全填充之圖案化區域相容，但在經塗覆及未塗覆之圖案化區上方利用連續毯覆式塗覆。其不與具有接合墊或類似未塗覆區域需求之晶圓相容。
藉由使用本申請案中所揭示之2層製程，上文所描述之先前技術限制現在可得以解決。
本揭示案之發明內容為一種使用2層微影製程來保護圖案化介電 質-金屬塗層之雙塗覆及剝離方法，該微影製程經暴露及顯影以形成底切結構(undercut)，且隨後在用以不完全最終層結束之金屬/介電質濾光劑塗覆晶圓之後，剝離頂部微影層以暴露金屬層邊緣且將底部微影層完整留在晶圓上，使得可沈積最終毯覆層以完成塗層且使暴露之金屬層邊緣鈍化。
1:晶圓
2:LOR底層
3:抗蝕劑頂層
4:金屬/介電質濾光層
5:毯覆式塗層
為更完整理解本發明之性質及目標，應結合附圖參考以下【實施方式】，其中：圖1為展示本發明較佳實施例之步驟的圖示。
本方法之較佳實施例開始於在晶圓(1)上進行2層剝離微影製程，其由以下組成：沈積剝離抗蝕劑(lift-off resist，LOR)以形成LOR底層(2)，及沈積1822抗蝕劑(或其他材料，諸如蝕刻相容性金屬或可由熟習此項技術者在閱讀本發明之後確定的抗蝕劑)以形成抗蝕劑頂層(3)，該微影製程隨後經暴露及顯影以在該LOR底層(2)中形成1-4微米底切結構。接著，將晶圓(1)塗覆0.25-5微米金屬/介電質濾光層(4)，其形成未完成之最終塗層。接著，使用丙酮或等效物選擇性地剝離任何金屬/介電質濾光層(4)之過量塗層及該抗蝕劑頂層(3)，從而暴露所沈積之金屬/介電質濾光層(4)的金屬邊緣且將該LOR底層(2)完整留在晶圓(1)上。如此一來留下具有1-4微米大的圖案化周界的圖案化金屬/介電質濾光層(4)，此係基於該LOR底層中之原始底切結構之尺寸。隨後，沈積毯覆式塗層(5)以完成所沈積之金屬/介電質濾光層(4)且使金屬層邊緣鈍化。對於一些應用，毯覆式塗層(5)沈積亦可由多層堆疊組成。最後，剝離該LOR底層(2)及過量毯覆式塗層沈積，從而將圖案化特徵留在晶圓(1)上。
圖1展示本發明較佳實施例之雙層微影製程，其包含： 步驟1：形成圖案於晶圓上；步驟2：沈積介電質/金屬濾光層；步驟3：剝離抗蝕劑頂層，從而暴露介電質/金屬濾光層邊緣；步驟4：沈積毯覆式塗層；及步驟5：最終剝離。
圖1之雙層製程之步驟詳述如下：首先形成LOR底層(2)於晶圓(1)上及形成抗蝕劑頂層(3)(1822抗蝕劑或其他類似材料)於該LOR底層(2)上，並加工該抗蝕劑頂層(3)及該LOR底層(2)以形成圖案於該抗蝕劑頂層(3)及該LOR底層(2)中，從而暴露該晶圓(1)之經選擇區域，並在該LOR底層(2)中形成1-4微米底切結構。
接著，用蒸鍍或濺鍍製程來將介電質及金屬濾光層(4)沈積至該晶圓(1)所暴露的經選擇區域上。
隨後剝離該抗蝕劑頂層(3)及任何過量介電質及金屬濾光材料，將該LOR底層(2)留在晶圓(1)上，從而基於該晶圓(1)之每一暴露區域中該底切結構的存在，使該介電質及金屬濾光層(4)之金屬層邊緣暴露在該LOR底層(2)之放大區中。
隨後在該LOR底層(2)之放大區中沈積毯覆式塗層(5)以保護該介電質及金屬濾光層(4)之金屬塗層邊緣且完成塗層堆疊(4)及(5)。
隨後剝離該LOR底層(2)及任何過量毯覆式塗層，從而於該晶圓(1)上留下被該毯覆式塗層(5)所覆蓋之該介電質及金屬濾光層(4)的圖案化特徵。
因為可在不脫離本文所涉及之本發明範疇的情況下在上文所描述的保護圖案化介電質-金屬塗層之雙塗覆及剝離方法中進行某些變化，因此希望其實施方式中所含有或附圖中所示之所有主題應解釋為說明申請專利範圍而不具限制性意義。
1:晶圓
2:LOR底層
3:抗蝕劑頂層
4:金屬/介電質濾光層
5:毯覆式塗層

Claims (5)

  1. 一種使用雙層微影製程來保護圖案化介電質-金屬塗層之雙塗覆及剝離方法，包括：形成剝離抗蝕劑之底層於晶圓上，及形成抗蝕劑之頂層於該剝離抗蝕劑之底層上；加工該抗蝕劑之頂層及該剝離抗蝕劑之底層以形成圖案於該抗蝕劑之頂層及該剝離抗蝕劑之底層中，從而暴露該晶圓之經選擇區域，並於該剝離抗蝕劑之底層產生底切結構；接著使用蒸鍍或濺鍍製程來將介電質及金屬濾光層沈積至該晶圓所暴露的經選擇區域上；移除該抗蝕劑之頂層及任何過量沈積介電質及金屬濾光材料，將該剝離抗蝕劑之底層留在該晶圓上，從而基於該晶圓之每一暴露區域中該底切結構的存在，使該沈積之介電質及金屬濾光層的任何金屬層邊緣在該剝離抗蝕劑之底層中的放大區中暴露；隨後沈積一或多個毯覆式塗層在該剝離抗蝕劑之底層的放大區內以保護金屬層邊緣；及隨後剝離該剝離抗蝕劑之底層及任何過量毯覆式塗層，從而於該晶圓上留下被該一或多個毯覆式塗層所覆蓋之該介電質及金屬濾光層的圖案化特徵。
  2. 如請求項1之方法，其中該底切結構係1微米至4微米。
  3. 如請求項1之方法，其中該一或多個毯覆式塗層包含鏡面層。
  4. 如請求項1之方法，其中該一或多個毯覆式塗層包含抗反射層。
  5. 如請求項1之方法，其中該一或多個毯覆式塗層包含耐腐蝕材料。
TW105111915A 2015-04-15 2016-04-15 保護圖案化介電金屬塗層之雙塗覆及剝離方法 TWI690978B (zh)

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PCT/US2016/027190 WO2016168232A1 (en) 2015-04-15 2016-04-13 Dual coating and lift-off method for protecting patterned dielectric-metal coatings
US15/097,342 US9514939B2 (en) 2015-04-15 2016-04-13 Dual coating and lift-off method for protecting patterned dielectric-metal coatings
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4238559A (en) * 1978-08-24 1980-12-09 International Business Machines Corporation Two layer resist system
US20040209123A1 (en) * 2003-04-17 2004-10-21 Bajorek Christopher H. Method of fabricating a discrete track recording disk using a bilayer resist for metal lift-off
US20050153219A1 (en) * 2004-01-12 2005-07-14 Ocean Optics, Inc. Patterned coated dichroic filter
US20140168761A1 (en) * 2012-12-19 2014-06-19 Georg J. Ockenfuss Sensor device including one or more metal-dielectric optical filters

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050136648A1 (en) * 2003-12-23 2005-06-23 Mariah Sharma Method and system for forming a contact in a thin-film device
US20130252369A1 (en) * 2012-03-20 2013-09-26 Intersil Americas LLC Enhanced lift-off techniques for use when fabricating light sensors including dielectric optical coating filters
US8815102B2 (en) 2012-03-23 2014-08-26 United Microelectronics Corporation Method for fabricating patterned dichroic film
US9515217B2 (en) * 2012-11-05 2016-12-06 Solexel, Inc. Monolithically isled back contact back junction solar cells
JP2015090380A (ja) * 2013-11-05 2015-05-11 ソニー株式会社 ドライフィルムフォトレジスト、ドライフィルムフォトレジストの製造方法、金属パターン形成方法及び電子部品
CN106461833B (zh) * 2014-06-18 2019-09-17 唯亚威通讯技术有限公司 金属-电介质滤光器、传感器设备及制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4238559A (en) * 1978-08-24 1980-12-09 International Business Machines Corporation Two layer resist system
US20040209123A1 (en) * 2003-04-17 2004-10-21 Bajorek Christopher H. Method of fabricating a discrete track recording disk using a bilayer resist for metal lift-off
US20050153219A1 (en) * 2004-01-12 2005-07-14 Ocean Optics, Inc. Patterned coated dichroic filter
US7648808B2 (en) * 2004-01-12 2010-01-19 Ocean Thin Films, Inc. Patterned coated dichroic filter
US20140168761A1 (en) * 2012-12-19 2014-06-19 Georg J. Ockenfuss Sensor device including one or more metal-dielectric optical filters

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