TWI685848B - 用於在非揮發性記憶體陣列中管理峰值電力需求及雜訊的系統及方法 - Google Patents

用於在非揮發性記憶體陣列中管理峰值電力需求及雜訊的系統及方法 Download PDF

Info

Publication number
TWI685848B
TWI685848B TW108107677A TW108107677A TWI685848B TW I685848 B TWI685848 B TW I685848B TW 108107677 A TW108107677 A TW 108107677A TW 108107677 A TW108107677 A TW 108107677A TW I685848 B TWI685848 B TW I685848B
Authority
TW
Taiwan
Prior art keywords
time point
groups
bit line
line switches
word line
Prior art date
Application number
TW108107677A
Other languages
English (en)
Chinese (zh)
Other versions
TW201941210A (zh
Inventor
維平 蒂瓦里
曉萬 陳
恩漢 杜
馬克 萊坦
Original Assignee
美商超捷公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商超捷公司 filed Critical 美商超捷公司
Publication of TW201941210A publication Critical patent/TW201941210A/zh
Application granted granted Critical
Publication of TWI685848B publication Critical patent/TWI685848B/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW108107677A 2018-03-23 2019-03-07 用於在非揮發性記憶體陣列中管理峰值電力需求及雜訊的系統及方法 TWI685848B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201862647573P 2018-03-23 2018-03-23
US62/647,573 2018-03-23
US16/015,020 US10580491B2 (en) 2018-03-23 2018-06-21 System and method for managing peak power demand and noise in non-volatile memory array
US16/015,020 2018-06-21
PCT/US2019/015369 WO2019182684A2 (en) 2018-03-23 2019-01-28 System and method for managing peak power demand and noise in non-volatile memory array
WOPCT/US19/15369 2019-01-28

Publications (2)

Publication Number Publication Date
TW201941210A TW201941210A (zh) 2019-10-16
TWI685848B true TWI685848B (zh) 2020-02-21

Family

ID=67985589

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108107677A TWI685848B (zh) 2018-03-23 2019-03-07 用於在非揮發性記憶體陣列中管理峰值電力需求及雜訊的系統及方法

Country Status (7)

Country Link
US (1) US10580491B2 (cg-RX-API-DMAC7.html)
EP (1) EP3769307B1 (cg-RX-API-DMAC7.html)
JP (1) JP7093419B2 (cg-RX-API-DMAC7.html)
KR (1) KR102282580B1 (cg-RX-API-DMAC7.html)
CN (1) CN111919255A (cg-RX-API-DMAC7.html)
TW (1) TWI685848B (cg-RX-API-DMAC7.html)
WO (1) WO2019182684A2 (cg-RX-API-DMAC7.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021150497A (ja) 2020-03-19 2021-09-27 キオクシア株式会社 記憶装置
US12706160B2 (en) * 2022-12-28 2026-08-11 Anaflash Inc. Staggered triggering controller
US11943922B1 (en) * 2023-11-11 2024-03-26 Western Digital Technologies, Inc. Non-volatile memory with three dimensional stacked word line switches

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6363000B2 (en) * 2000-05-03 2002-03-26 Hewlett-Packard Company Write circuit for large MRAM arrays
US20020114181A1 (en) * 1996-05-24 2002-08-22 Uniram Technology, Inc. Multiple ports memory-cell structure
US20150348626A1 (en) * 2013-02-19 2015-12-03 Panasonic Intellectual Property Management Co., Ltd. Nonvolatile semiconductor storage device
US9672930B2 (en) * 2015-05-29 2017-06-06 Silicon Storage Technology, Inc. Low power operation for flash memory system

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029130A (en) 1990-01-22 1991-07-02 Silicon Storage Technology, Inc. Single transistor non-valatile electrically alterable semiconductor memory device
JP3337564B2 (ja) 1994-09-16 2002-10-21 松下電器産業株式会社 半導体記憶装置
US7315056B2 (en) 2004-06-07 2008-01-01 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with program/erase and select gates
JP2006004514A (ja) 2004-06-17 2006-01-05 Matsushita Electric Ind Co Ltd 半導体記憶装置
US20090039410A1 (en) 2007-08-06 2009-02-12 Xian Liu Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing
KR20100120517A (ko) 2009-05-06 2010-11-16 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 워드 라인 또는 비트 라인의 제어방법
US7868657B1 (en) * 2009-07-22 2011-01-11 Qualcomm, Incorporated High voltage logic circuits
JP5602941B2 (ja) * 2010-04-27 2014-10-08 コンバーサント・インテレクチュアル・プロパティ・マネジメント・インコーポレイテッド １つおきの選択を伴う相変化メモリアレイブロック
US8305808B2 (en) 2010-08-12 2012-11-06 Yield Microelectronics Corp. Low-voltage EEPROM array
JP2012069203A (ja) 2010-09-22 2012-04-05 Toshiba Corp 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の駆動方法
US8400864B1 (en) 2011-11-01 2013-03-19 Apple Inc. Mechanism for peak power management in a memory
US10541029B2 (en) * 2012-08-01 2020-01-21 Micron Technology, Inc. Partial block memory operations
JP2014170599A (ja) * 2013-03-01 2014-09-18 Toshiba Corp 半導体記憶装置
US20150155039A1 (en) * 2013-12-02 2015-06-04 Silicon Storage Technology, Inc. Three-Dimensional Flash NOR Memory System With Configurable Pins
JP6151203B2 (ja) 2014-03-04 2017-06-21 株式会社東芝 演算制御装置、それを備えたメモリシステム、および、情報処理装置
JP6271460B2 (ja) 2015-03-02 2018-01-31 東芝メモリ株式会社 半導体記憶装置
KR102469172B1 (ko) * 2016-03-14 2022-11-22 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 이의 검증 라이트 방법
JP6833873B2 (ja) 2016-05-17 2021-02-24 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 不揮発性メモリアレイを使用したディープラーニングニューラルネットワーク分類器
KR102493814B1 (ko) * 2016-06-29 2023-02-02 에스케이하이닉스 주식회사 메모리 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020114181A1 (en) * 1996-05-24 2002-08-22 Uniram Technology, Inc. Multiple ports memory-cell structure
US6363000B2 (en) * 2000-05-03 2002-03-26 Hewlett-Packard Company Write circuit for large MRAM arrays
US20150348626A1 (en) * 2013-02-19 2015-12-03 Panasonic Intellectual Property Management Co., Ltd. Nonvolatile semiconductor storage device
US9672930B2 (en) * 2015-05-29 2017-06-06 Silicon Storage Technology, Inc. Low power operation for flash memory system

Also Published As

Publication number Publication date
EP3769307A4 (en) 2021-11-03
CN111919255A (zh) 2020-11-10
US20190295647A1 (en) 2019-09-26
KR102282580B1 (ko) 2021-07-28
EP3769307A2 (en) 2021-01-27
TW201941210A (zh) 2019-10-16
KR20200102520A (ko) 2020-08-31
US10580491B2 (en) 2020-03-03
WO2019182684A3 (en) 2020-05-14
EP3769307B1 (en) 2023-11-08
JP7093419B2 (ja) 2022-06-29
JP2021518627A (ja) 2021-08-02
WO2019182684A2 (en) 2019-09-26

Similar Documents

Publication Publication Date Title
KR100692278B1 (ko) 비휘발성 반도체메모리장치
TWI682393B (zh) 用於在非揮發性記憶體中儲存多位元資料的系統及方法
TW202131337A (zh) 用於深度學習人工類神經網路中的類比類神經記憶體之解碼器
JP5915121B2 (ja) 抵抗変化型不揮発性メモリ
CN104835523B (zh) 电流检测电路及半导体存储装置
TW202016935A (zh) 具有電容耦合至浮動閘之閘極的記憶體單元之程式化
US9418744B2 (en) System and method to reduce disturbances during programming of flash memory cells
JP4278438B2 (ja) 不揮発性半導体記憶装置及びその制御方法
EP3172733A1 (en) System and method to inhibit erasing of portion of sector of split gate flash memory cells
TW201947596A (zh) 具有位元組抹除操作之分離閘快閃記憶體陣列
KR102282580B1 (ko) 비휘발성 메모리 어레이에서 피크 전력 요구 및 잡음을 관리하기 위한 시스템 및 방법
CN110462582B (zh) 基于非易失性存储器单元阵列生成随机数的系统和方法
TWI686808B (zh) 用於在非揮發性記憶體中使用電流乘數儲存並檢索多位元資料的系統及方法
TWI687928B (zh) 用於在快閃記憶體中程式化期間最小化浮閘對浮閘耦合效應之系統及方法
JP2012069203A (ja) 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の駆動方法
TW201931373A (zh) 用於藉由最佳化程式化操作來實施推理引擎的系統及方法
US12554423B2 (en) Accelerated programming of four gate, split-gate flash memory cells
WO2025122184A1 (en) Accelerated programming of four-gate, split-gate flash memory cells
WO2016014166A1 (en) System and method to inhibit erasing of portion of sector of split gate flash memory cells