TWI666728B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TWI666728B
TWI666728B TW106135769A TW106135769A TWI666728B TW I666728 B TWI666728 B TW I666728B TW 106135769 A TW106135769 A TW 106135769A TW 106135769 A TW106135769 A TW 106135769A TW I666728 B TWI666728 B TW I666728B
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Taiwan
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layer
source
epitaxial layer
drain
drain epitaxial
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TW106135769A
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TW201841304A (zh
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呂偉元
楊世海
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台灣積體電路製造股份有限公司
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Abstract

於製造半導體元件之方法中，一層間介電層形成於下方結構上。下方結構包含設置於鰭式結構之通道區域上之閘極結構，以及設置於鰭式結構之源極/汲極區域之第一源極/汲極磊晶層。藉由蝕刻部分之層間介電層以及第一源極/汲極磊晶層之上部，使第一開口形成於第一源極/汲極磊晶層上。第二源極/汲極磊晶層形成於被蝕刻之第一源極/汲極磊晶層上。導電材料係形成於第二源極/汲極磊晶層上。

Description

半導體元件及其製造方法
本揭露是有關於一種半導體元件之製造方法，尤其是有關於一種源極/汲極(S/D)接觸電阻縮減之半導體元件的結構及製造方法。
當半導體工業已進展至奈米技術製程節點以追求更高的元件密度、效能以及更低的成本，來自製造以及設計課題之挑戰造就了三維設計之發展，例如包含鰭式場效電晶體(fin field effect transistor,FinFET)之多閘極場效電晶體。在鰭式場效電晶體中，閘極電極係與通道區域之三個側表面以居於中間之閘極介電層相鄰。當鰭式場效電晶體之尺寸縮減，電極於源極/汲極之接觸面積亦縮減，因而增加了接觸電阻。當電晶體尺寸持續地被調降，則需要進一步的鰭式場效電晶體製程進展。
根據本揭露之一些實施方式，提出一種半導體元件形成方法，包含：形成層間介電(interlayer dielectric,ILD) 層於下層結構上；形成第一開口於第一源極/汲極磊晶層上；形成第二源極/汲極磊晶層於被蝕刻之第一源極/汲極磊晶層上以及形成導電材料於第二源極/汲極磊晶層上。其中上述之下層結構包含：閘極結構，設置於鰭式結構之通道區域；以及第一源極/汲極磊晶層，設置於鰭式結構之源極/汲極區域。而其中上述之第一開口係藉由蝕刻部分之層間介電層以及第一源極/汲極磊晶層之上部而形成。
根據本揭露之一些實施方式，提出一種半導體元件形成方法，包含：形成層間介電層於下層結構上；形成第一開口於第一源極/汲極磊晶層上；形成第二開口於第二源極/汲極磊晶層上以及形成第三源極/汲極磊晶層於被蝕刻之第一源極/汲極磊晶層，同時以第一覆蓋層覆蓋第二開口。其中上述之下層結構包含；第一導電型鰭式場效電晶體(FinFET)之第一閘極結構與第一源極/汲極磊晶層以及第二導電型鰭式場效電晶體之第二閘極結構與第二源極/汲極磊晶層。其中上述之第一開口係藉由蝕刻層間介電層之一部分以及第一源極/汲極磊晶層之上部而形成。其中上述之第二開口係藉由蝕刻層間介電層之一部分以及第二源極/汲極磊晶層之上部而形成。
根據本揭露之一些實施方式，提出一種半導體元件，包含：閘極結構、源極/汲極結構、蝕刻停止層以及導電接點。其中上述之閘極結構係設置於鰭式結構之通道區域。其中上述之源極/汲極結構係設置於鰭式結構之源極/汲極區域。其中上述之蝕刻停止層覆蓋源極/汲極結構之側面。其中上述之導電接點係設置於源極/汲極結構上，而其中源極/汲極 結構包含第一磊晶層以及設置於第一磊晶層上之第二磊晶層，且第二磊晶層係設置於蝕刻停止層之上部上。
5‧‧‧基材
10‧‧‧鰭式結構
10’‧‧‧鰭式結構
12‧‧‧井區
12’‧‧‧井區
14‧‧‧通道區
14’‧‧‧通道區
15‧‧‧隔離絕緣層
20、20N、20P‧‧‧下源極/汲極磊晶層
21‧‧‧橫向延伸部位
22‧‧‧鰭式側壁間隔物
24‧‧‧接觸蝕刻停止層
300‧‧‧基材
310‧‧‧鰭式結構
315‧‧‧通道區域
320‧‧‧隔離絕緣層
330‧‧‧金屬閘極結構
340‧‧‧蓋絕緣層
350‧‧‧側壁間隔物
360‧‧‧源極/汲極區域
370‧‧‧層間介電層
40‧‧‧金屬閘極結構
42‧‧‧閘極介電層
44‧‧‧金屬閘極電極層
441‧‧‧功函數調整層
442‧‧‧金屬材料
46‧‧‧側壁間隔物
50、50N、50P‧‧‧上源極/汲極磊晶層
55、55N、55P‧‧‧矽化物層
60‧‧‧源極/汲極接觸區
61‧‧‧接觸襯墊層
62‧‧‧黏著層
64‧‧‧體金屬層
70‧‧‧層間介電層
100‧‧‧第一遮罩層
101‧‧‧開口圖案
102‧‧‧接觸開口
105‧‧‧第一覆蓋層
110‧‧‧第二遮罩層
112‧‧‧開口
115‧‧‧第二覆蓋層
120‧‧‧第三遮罩層
122‧‧‧開口
130‧‧‧預先非晶化佈植
140‧‧‧重摻雜區域
145‧‧‧輕微摻雜汲極結構
155‧‧‧矽化物層
160‧‧‧源極/汲極磊晶層
H1、H2‧‧‧高度
D1、D2‧‧‧深度
為讓本揭露之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下：第1A圖為根據本揭露一些實施方式所繪示之半導體元件之剖面圖，第1B圖為繪示此半導體元件之另一剖面圖，第1C圖為繪示此半導體元件之一平面圖，且第1D圖為繪示此半導體元件之另一平面圖。第1E圖為根據本揭露一些實施方式所繪示之一半導體元件之閘極結構之剖面圖，且第1F圖為繪示此半導體元件之等角視圖。
第2A圖為根據本揭露一些其他實施方式所繪示之半導體元件之剖面圖，且第2B圖為繪示此半導體元件之另一剖面圖。
第3圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第4A圖、第4B圖以及第4C圖各為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第5圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第6圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第7A圖以及第7B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第8A圖以及第8B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第9A圖以及第9B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第10A圖以及第10B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第11A圖以及第11B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第12A圖以及第12B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第13A圖以及第13B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第14A圖以及第14B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第15A圖以及第15B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第16A圖以及第16B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第17A圖以及第17B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第18A圖以及第18B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第19A圖以及第19B圖為根據本揭露一些實施方式所繪示之半導體元件之序列製造步驟的不同階段中之一階段。
第20A圖為根據本揭露一些其他實施方式所繪示之半導體元件之剖面圖，且第20B圖為繪示此半導體元件之另一剖面圖，
以下將以圖式揭露本揭露之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本揭露。也就是說，在本揭露部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。並且，除非有其他表示，在不同圖式中相同之元件符號可視為相對應的元件。這些圖式之繪示是為了清楚表達這些實施方式中各元件之間的連接關係，並非繪示各元件的實際尺寸。
此外，相對空間詞彙，如『下方』、『下』、『底部』、『上』、以及『頂部』等，用來描述文中在圖式中所示的一元件與另一元件之關係。相對空間詞彙用來描述裝置在圖式中所描述之外的不同方位是可以被理解的。如果圖式中的元件被轉至不同方向(旋轉90度或轉至其他另一方向)，則元件將會根據圖示以不同之相對空間詞彙描述。除此之外，詞彙“組成”意指“包含”或是“由...所組成”。
由於閘極至閘極之空間(小於10奈米)日漸縮小，使得源極/汲極接觸區與源極/汲極磊晶層間之接觸電阻成為五奈米節點製程之問題。一般來說，源極/汲極磊晶層係形成於包含高介電常數介電層之金屬閘極結構之形成步驟之前，層間介電層(ILD)係形成於源極/汲極磊晶層以及金屬閘極結構之上方，接觸開口係形成於源極/汲極磊晶層之上方，且源極/汲極接觸區係形成於源極/汲極磊晶層上。於此製程中，源極/汲極磊晶層之一部分可於接續之蝕刻步驟中被蝕刻或失去，以形成接觸開口，造成緊縮的製程視窗以及較高的接觸電阻。除此之外，若欲以增加體積因應上述之失去，則緊縮的鰭節距阻止了體積之增加。
根據本揭露之一些實施方式，額外之磊晶層形成於接觸開口之形成步驟後，以擴大接觸著陸區域並縮減接觸電阻，因此進一步形成大體積之源極/汲極磊晶層為非必要。
第1A圖為根據第1C圖以及第1D圖中線段X1-X1所繪示之半導體元件X方向剖面圖。第1B圖為根據第1C圖以及第1D圖中線段Y1-Y1所繪示之半導體元件Y方向剖面圖。第1C圖為繪示了半導體元件之源極/汲極磊晶層之平面視圖，且第1D圖為繪示了半導體元件之源極/汲極接觸層之平面視圖。
於本揭露之一些實施方式中，運用了以閘極替代技術製造的鰭式場效電晶體。然而，接續之製造步驟可被應用於其他場效電晶體，例如，閘極環繞式(gate-all-around)場效電晶體、平面式場效電晶體或是先閘極(gate-first)技術。
請參照第1A圖以及第1B圖，鰭式結構10設置於基材5上方。鰭式結構10包含通道區14以及井區12。抗擊穿(anti-punch-through,APT)佈植執行於井區12，因此井區12具有不同於通道區14之摻雜濃度/特性。於一些實施方式中，如第1A圖、第1C圖以及第1D圖所繪示，鰭式結構10係由，例如矽，所組成且設置及延伸於X方向。於一些其他實施方式中，鰭式結構10係由鍺化矽(SiGe)、碳化矽(SiC)、鍺(Ge)或三五族半導體所組成。金屬閘極結構40延伸於Y方向而下源極/汲極磊晶層20係設置於相鄰之金屬閘極結構40之間。如第1C圖以及第1D圖所繪示，一金屬閘極結構40係設置於多個鰭式結構10(例如，四個)上方，且一下源極/汲極磊晶層20係設置於形成一結合之下源極/汲極磊晶層20之兩個鰭式結構10上方。然而，本揭露之一些實施方式並非侷限於此型態。鰭式結構10係設置於基材5上方且自一隔離絕緣層15突出(例如，淺溝槽隔離(STI))。
金屬閘極結構40包含閘極介電層42、金屬閘極電極層44以及出現於金屬閘極電極層44側壁上之側壁間隔物46。於一些實施方式中，側壁間隔物46在其底部之薄膜厚度係介於自約3奈米至約15奈米之範圍內，且於一些其他實施方式中係介於自約4奈米至約10奈米之範圍內。於一些實施方式中，一閘極蓋絕緣層係出現於金屬閘極電極層44之上方，且側壁間隔物46係出現於金屬閘極電極層44以及閘極蓋絕緣層之側壁上。金屬閘極結構40間之空間係以層間介電層70填充。層間介電層70包含一層或多層之矽氧化物、碳氧化矽(SiOC)、碳氮氧化矽(SiOCN)、或碳氮化矽(SiCN)、或其他 低介電常數之材料、或多孔性材料或其他合適之介電材料。層間介電層70可藉由低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)、電漿化學氣相沉積(plasma-CVD)、流動式化學氣相沉積(flowable CVD)或其他合適之薄膜形成方法而形成。
於本揭露中，源極與汲極可互換使用，且無實質上之結構差異。詞彙“一源極/汲極”(一S/D)係指一源極與一汲極中之一或兩者。
閘極蓋絕緣層包含一層或多層之絕緣材料，例如以氮矽為基底之材料，包含氮化矽(SiN)、氮氧化矽(SiON)、SiCN、SiOCN或是任何其他合適之介電材料。側壁間隔物46係由不同於閘極蓋絕緣層之材料所組成，包含一層或多層之絕緣材料，例如以氮矽為基底之材料，包含SiN、SiON、SiCN、SiOCN或是任何其他合適之介電材料。於第1A圖至第1D圖中所繪示而未於上述文中描述之多個元件將於下文中描述。
第1E圖為金屬閘極結構40之放大剖面圖。金屬閘極結構40包含一層或多層之金屬材料，例如鋁(Al)、銅(Cu)、鎢(W)、鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、鈦鋁(TiAl)、鋁鈦碳(TiAlC)、氮化鋁鈦(TiAlN)、氮化鉭(TaN)、矽化鎳(NiSi)以及矽化鈷(CoSi)，或是任意其他合適之導電材料。閘極介電層42係設置於鰭式結構10之通道區14與金屬閘極電極層44之間，且包含一層或多層之金屬氧化物，例如高介電常數之金屬氧化物。用於高介電常數介電層之金屬氧化物包含以下範例之氧化物：鋰(Li)、鈹(Be)、鎂(Mg)、鈣(Ca)、鍶(Sr)、鈧(Sc)、 釔(Y)、鋯(Zr)、鉿(Hf)、鋁(Al)、鑭(La)、鈰(Ce)、鐠(Pr)、釹(Nd)、釤(Sm)、銪(Eu)、釓(Gd)、鋱(Tb)、鏑(Dy)、鈥(Ho)、鉺(Er)、銩(Tm)、鐿(Yb)、鎦(Lu)，及/或上述之混和物，或是任意其他合適之介電材料。於一些實施方式中，由氧化矽(SiO2)組成且厚度為1至3奈米之一界面層，係形成於通道區14與高介電常數之閘極介電層42之間。
於一些實施方式中，一或多層之功函數調整層441係安插於閘極介電層42以及金屬材料442之間。功函數調整層441係由導電材料所組成，例如單層之TiN、TaN、鋁鉭碳(TaAlC)、碳化鈦(TiC)、碳化鉭(TaC)、鈷(Co)、Al、TiAl、鉿鈦(HfTi)、矽化鈦(TiSi)、矽化鉭(TaSi)或是鋁鈦氮，或是上述元素中兩種或多種之多層材料，或是任何其他合適之導電材料。於n型通道之場效電晶體中，係以一層或多層之TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi以及TaSi，或是任何其他合適之導電材料為功函數調整層441，於p型通道之場效電晶體中，係以一層或多層之TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC以及Co，或是任何其他合適之導電材料為功函數調整層441。
於一些實施方式中，下源極/汲極磊晶層20係形成於設置於鰭式結構10之源極/汲極區域之凹槽(由下源極/汲極磊晶層20與鰭式結構10之介面所定義)內及上方。如第1B圖所繪示，下源極/汲極磊晶層20之底部係內嵌在隔離絕緣層15內，而剩餘之上部係自隔離絕緣層15突出。此突出部分之底部具有鰭式側壁間隔物22。於一些實施方式中，鰭式側壁間隔物 22係由一層或多層之以氮矽為基底之材料所組成，例如，氮化矽、氮氧化矽或任何其他合適之絕緣材料。再者，於一些實施方式中，下源極/汲極磊晶層20之上部具有一橫向延伸部位21。於一些實施方式中，橫向延伸部位21係與其相鄰之下源極/汲極磊晶層20結合。
再者，如第1B圖所繪示，一接觸蝕刻停止層(CESL)24係形成於下源極/汲極磊晶層20之上部與鰭式側壁間隔物22之側面以及隔離絕緣層15之頂表面。於一些實施方式中，接觸蝕刻停止層24係由不同於閘極蓋絕緣層以及側壁間隔物46之材料所組成，並包含一層或多層之絕緣材料，例如，以氮矽為基底之材料，包含SiN、SiON、SiCN、SiOCN或是任何其他合適之介電材料。
於一些實施方式中，如第1A圖以及第1B圖所繪示，鰭式場效電晶體之源極/汲極結構進一步包含上源極/汲極磊晶層50。於一些實施方式中，如第1B圖所繪示，因上源極/汲極磊晶層50係形成於接觸開口形成於下源極/汲極磊晶層20上方之後，上源極/汲極磊晶層50具有設置於接觸蝕刻停止層24上部之橫向部位。於一些實施方式中，上源極/汲極磊晶層50之橫向部位係設置於相鄰兩鰭式結構間之層間介電層70上。
於一些實施方式中，矽化物層55係形成於上源極/汲極磊晶層50上方。矽化物層55係藉由加熱操作使一金屬材料與上源極/汲極磊晶層50之一材料反應而形成。於一些實施方式中，矽化物層55包含TiSi、NiSi、矽化鎢(Wsi)、CoSi 以及矽化鉬(MoSi)中之一或多者。於一些其他實施方式中，矽化物層55包含鍺或是由鍺化物所組成。
如第1A圖以及第1B圖所繪示，源極/汲極接觸區60係設置於矽化物層55上方。於一些實施方式中，源極/汲極接觸區60包含一黏著層62以及一體金屬層64。於一些實施方式中，黏著層62包含Ti、TiN、Ta及/或TaN。體金屬層64包含Co、Ni、Cu及/或W。於一些實施方式中，黏著層62係保形地形成於接觸開口內且與矽化物層55以及上源極/汲極磊晶層50直接接觸。於一些其他實施方式中，黏著層62只與矽化物層55接觸。再者，於一些實施方式中，由例如SiN、SiCN或是SiOCN所組成之接觸襯墊層61係形成於源極/汲極接觸區60之形成步驟前。
第1F圖為根據一些實施方式所繪示之鰭式場效電晶體結構之等角視圖。鰭式場效電晶體結構可依照以下之步驟製造。
首先，鰭式結構310係被製造於基材300上方。鰭式結構310可以任何合適之方法圖案化。例如，鰭式結構310可利用一次或多次之微影製程圖案化，包含雙重圖案化或多重圖案化製程。一般來說，雙重圖案化或多重圖案化製程結合微影以及自對準製程，使得擁有節距小於利用其他單一、直接之製程可得圖案之節距之圖案得以被製造。例如，於一實施方式中，一犧牲層係形成於基材300上方以及利用一微影製程圖案化。間隔物係利用自對準製程，沿著圖案化之犧牲層形成。犧牲層接著被移除，且剩餘之間隔物可被用以圖案化鰭式結構。
鰭式結構310包含一底部區以及一當作通道區域315之上部區。基材300為，例如，具有雜質濃度介於自約1×1015cm-3至約1×1019cm-3之範圍內之一p型矽基材，且於一些其他實施方式中，雜質濃度係介於自約1×1016cm-3至約1×1018cm-3之範圍內。於一些其他實施方式中，基材300為具有雜質濃度介於自約1×1015cm-3至約1×1019cm-3之範圍內之一n型矽基材，且於一些其他實施方式中，雜質濃度係介於自約1×1016cm-3至約1×1018cm-3之範圍內。可代替地，基材300可包含另一半導體元素，例如鍺；半導體化合物，包含四四族半導體化合物例如SiC以及SiGe，三五族半導體化合物例如砷化鎵(GaAs)、磷化鎵(GaP)、氮化鎵(GaN)、磷化銦(InP)、砷化銦(InAs)、銻化銦(InSb)、磷砷化鎵(GaAsP)、氮化鋁鎵(AlGaN)、砷化銦鋁(AlInAs)、鋁砷化鎵(AlGaAs)、砷化銦鎵(GaInAs)、磷化鎵銦(GaInP)及/或磷砷化銦鎵(GaInAsP)，或是任何其他合適之半導體材料；或是上述元素之組合。於一實施方式中，基材300為一絕緣層上矽基材(silicon-on-insulator)之矽層。
於形成鰭式結構310後，隔離絕緣層320係形成於鰭式結構310上方。隔離絕緣層320包含一層或多層之絕緣材料，例如，矽氧化物、氮矽氧化物或是氮化矽，藉由低壓化學氣相沉積、電漿化學氣相沉積或是流動式化學氣相沉積而形成。隔離絕緣層320可藉由一層或多層之旋塗式玻璃(SOG)、氧化矽(SiO)、SiON、SiOCN及/或氟矽玻璃(FSG)，或是任何其他合適之介電材料而形成。
於形成隔離絕緣層320於鰭式結構310上方後，執行平坦化操作以移除部分之隔離絕緣層320。平坦化操作可包含化學機械研磨(CMP)及/或回蝕刻製程。接著，隔離絕緣層320被進一步移除(凹陷)以曝露鰭式結構310之上部區。
虛設鰭式結構係形成於曝露之鰭式結構310上方。虛設鰭式結構包含由多晶矽組成之虛設閘極電極層以及虛設閘極介電層。包含一層或多層絕緣材料之側壁間隔物350亦形成於虛設閘極電極層之側壁上。於虛設閘極結構形成後，未被虛設閘極結構覆蓋之鰭式結構310被凹陷至低於隔離絕緣層320之上表面。接著，源極/汲極區域360藉由磊晶成長方法形成於凹陷之鰭式結構310上方。源極/汲極區域360可包含一應變材料以施加應力於通道區域315。
接著，層間介電層370形成於虛設閘極結構以及源極/汲極區域360上方。層間介電層370包含一層或多層之矽氧化物、SiOC、SiOCN、SiCN、或是其他低介電常數材料，或是多孔性材料或是任何其他合適之介電材料。於一平坦化操作後，虛設閘極結構被移除以製造閘極空間。接著，包含金屬閘極電極以及閘極介電層，例如高介電常數介電層，之金屬閘極結構330形成於閘極空間內。
再者，於一些實施方式中，一蓋絕緣層340係形成於金屬閘極結構330上方，以得到如第1F圖所繪示之鰭式場效電晶體結構。
請參照第1F圖，部分之金屬閘極結構330、蓋絕緣層340、側壁間隔物350以及層間介電層370被切割以繪示下 方結構。於一些實施方式中，相鄰之源極/汲極區域360彼此結合，且矽化物層係形成於結合之源極/汲極區域上。
第1F圖之金屬閘極結構330、蓋絕緣層340、側壁間隔物350、源極/汲極區域360以及層間介電層370，分別實質對應於第1A圖至第1E圖之閘極介電層42、金屬閘極電極層44、閘極蓋絕緣層、側壁間隔物46、下源極/汲極磊晶層20以及層間介電層70。
根據本揭露之一些實施方式，第2A圖繪示了半導體元件於X方向之剖面圖，第2B圖繪示了半導體元件於Y方向之剖面圖。與上述第1A圖至第1F圖所描述之實施方式中，相同或相似的材料、組態、維度及/或製程將於接續之實施方式中使用，而其詳盡之解釋將予以省略。
請參照第2A圖以及第2B圖，當源極/汲極接觸區60之接觸開口形成，下源極/汲極磊晶層20被蝕刻至相較於第1A圖以及第1B圖中更深之深度。於此例中，上源極/汲極磊晶層50係形成於被蝕刻之下源極/汲極磊晶層20之相對較寬廣之面積上。於一些實施方式中，如第2B圖所繪示，上源極/汲極磊晶層50橫向生長且與相鄰之上源極/汲極磊晶層50結合。再者，矽化物層55亦可形成為單一矽層。相似於第1B圖，如第2B圖所繪示，上源極/汲極磊晶層50具有設置於接觸蝕刻停止層24上部之橫向部位。於此一實施方式中，因上源極/汲極磊晶層50可以更大體積或面積形成，則有可能進一步減小源極/汲極接觸電阻。
第3圖至第19B圖為根據本揭露一些實施方式所繪示之半導體元件序列製造步驟中之不同階段。於第7A圖至 第19B圖中，“A”圖(第7A圖、第8A圖，...)繪示了n型通道之剖面圖，以及“B”圖(第7B圖、第8B圖，...)繪示了p型通道之剖面圖。應當瞭解，額外之步驟可提供於第3圖至第19B圖所繪示之過程之前、之中以及之後，且一些下文描述之步驟可於額外之實施方式中取代或取消。步驟/製程之順序可互相交換。與上述第1A圖至第2B圖所描述之實施方式中，相同或相似的材料、組態、維度及/或製程將於接續之實施方式中使用，而其詳盡之解釋將予以省略。
第3圖至第6圖之製造步驟對於n型通道鰭式場效電晶體以及p型通道鰭式場效電晶體係實質上通用。
如第3圖所繪示，於層間介電層70形成於包含金屬閘極結構(閘極介電層42、金屬閘極電極層44以及側壁間隔物46)以及下源極/汲極磊晶層20之下方結構上方後，具有開口圖案101之第一遮罩層100形成於層間介電層70上方。於一些實施方式中，第一遮罩層100為光阻圖案，且於一些其他實施方式中，第一遮罩層100為包含矽氧化物、氮化矽或任何其他合適材料之硬遮罩層。
如第4A圖所繪示，以第一遮罩層100為蝕刻遮罩，層間介電層70、接觸蝕刻停止層24以及下源極/汲極磊晶層20接續地被蝕刻，因而形成源極/汲極接觸開口102。
第4B圖以及第4C圖繪示了於接續半導體元件製造步驟中之一階段中，沿著Y方向之不同蝕刻深度之剖面圖。請參照第4B圖，高度H1為下源極/汲極磊晶層20於接觸開口102形成前之原始高度，且H2為鰭式側壁間隔物22之高度。深度D1、D2為下源極/汲極磊晶層20之蝕刻深度(量)。
於一些實施方式中，蝕刻深度D1、D2滿足0<D1，D2<(H1-H2)/2。請參照第4B圖，部分之層間介電層70保留於兩源極/汲極結構間之V型部分，且於第4C圖中，因較深之蝕刻深度，無層間介電層70保留於兩源極/汲極結構間。換句話說，無藉由接觸蝕刻停止層24形成之V型部分。當下源極/汲極磊晶層20之蝕刻停止於下源極/汲極磊晶層20於Y方向有最大寬度之水平面時，下源極/汲極磊晶層20被蝕刻之上表面具有最大面積。當鰭節距P係介於自約10奈米至約40奈米之範圍內時，較大之深度D1或是深度D2將造成較低之源極/汲極接觸電阻。
如第5圖所繪示，第一遮罩層100於源極/汲極接觸開口102形成後被移除。
接著，如第6圖所繪示，第一覆蓋層105係保形地形成於接觸開口102內以及層間介電層70之上表面上。第一覆蓋層105包含SiN、SiOC、SiOCN、SiCO中之一或多者或是任何合適之介電材料，於一些實施方式中，第一覆蓋層105之厚度係介於自約1奈米至約10奈米之範圍內，且於其他一些實施方式中，第一覆蓋層105之厚度可介於自約2奈米至約8奈米之範圍內。第一覆蓋層105可藉由化學氣相沉積或是原子層沉積而形成。
根據本揭露之一些實施方式中，第7A圖以及第7B圖繪示了接續半導體元件序列製造步驟中之一階段之剖面圖。第7A圖繪示了n型通道鰭式場效電晶體之剖面圖，而第7B圖繪示了p型通道鰭式場效電晶體之剖面圖。於一些實施方式中，n型通道鰭式場效電晶體包含下源極/汲極磊晶層20N而p型通道鰭式場效電晶體包含不同於下源極/汲極磊晶層20N之下源極/汲極磊晶層20P。
如第7B圖所繪示，第二遮罩層110係形成於第一覆蓋層105上方，且第一覆蓋層105係以第二遮罩層110為蝕刻遮罩而圖案化p型區域至形成開口112。然而如第7A圖所繪示，n型區域係被第二遮罩層110所覆蓋。於一些實施方式中，第二遮罩層110為一光阻圖案，且於一些其他實施方式中，第二遮罩層110為包含矽氧化物、氮化係、或任何其他合適之材料之硬遮罩層。
如第8A圖以及8B圖所繪示，第二遮罩層110於開口112形成後被移除。
接著，如第9B圖所繪示，p型通道鰭式場效電晶體之上源極/汲極磊晶層50P被形成，而如第9A圖所繪示，n型區域係被第一覆蓋層105所保護。上源極/汲極磊晶層50P可藉由金屬氧化物化學氣相沉積(MOCVD)、原子層沉積及/或原子束磊晶(MBE)而形成。
於一些實施方式中，p型通道鰭式場效電晶體之上源極/汲極磊晶層50P包含硼化矽(SiB)、矽鍺硼(SiBGe)或是砷化鎵。於一些其他實施方式中，下源極/汲極磊晶層20P以及上源極/汲極磊晶層50P包含鍺，且於一些實施方式中，上源極/汲極磊晶層50P之鍺濃度係高於下源極/汲極磊晶層20P之鍺濃度。於一些實施方式中，下源極/汲極磊晶層20P包含矽鍺化合物(Sil-xGex)，其中0.15x0.8，且上源極/汲極磊晶層50P包含矽鍺化合物(Si1-yGey)，其中0.2y1.0且x<y。再者，下源極/汲極磊晶層20P以及上源極/汲極磊晶層50P中之至少一者進一步包含硼(B)，且於一些實施方式中，硼濃度係介於自約1.0×1020cm-3至約6.0×1021cm-3之一範圍內，於一些其他實施方式中，硼濃度係介於自約5.0×1020cm-3至約1.0×1021cm-3之一範圍內。
接著，如第10A圖以及第10B圖所繪示，第一覆蓋層105係藉由適當之蝕刻及/或清洗製程移除。
隨後，如第11A圖以及第11B圖所繪示，第二覆蓋層115係保形地形成於n型通道區域與p型通道區域之接觸開口112內以及層間介電層70之上表面。第二覆蓋層115包含SiN、SiOC、SiOCN、SiCO中之一或多者或是任何合適之介電材料，於一些實施方式中，第二覆蓋層115之厚度係介於自約1奈米至約10奈米之範圍內，且於一些其他實施方式中，第二覆蓋層115之厚度可介於自約2奈米至約8奈米之範圍內。第二覆蓋層115可藉由化學氣相沉積或是原子層沉積而形成。
如第12A圖所繪示，第三遮罩層120係形成於第二覆蓋層115上方，且第二覆蓋層115係以第三遮罩層120為蝕刻遮罩而圖案化n型區域至形成開口122，然而如第12B圖所繪示，p型區域係被第三遮罩層120所覆蓋。於一些實施方式中，第三遮罩層120為一光阻圖案，且於一些其他實施方式中，第三遮罩層120為包含矽氧化物、氮化矽或任何其他合適之材料之硬遮罩層。
如第13A圖以及13B圖所繪示，第三遮罩層120 於開口112形成後被移除。
接著，如第14A圖所繪示，n型通道鰭式場效電晶體之上源極/汲極磊晶層50N被形成，而如第14B圖所繪示，p型區域係被第二覆蓋層115所保護。上源極/汲極磊晶層50N可藉由金屬氧化物化學氣相沉積(MOCVD)、原子層沉積及/或原子束磊晶(MBE)而形成。
於一些實施方式中，n型通道鰭式場效電晶體之上源極/汲極磊晶層50N包含SiP、InP、矽碳磷(SiCP)、SiC或是GaInP。於一些實施方式中，下源極/汲極磊晶層20N亦包含SiP、InP、SiCP、SiC或是GaInP，但可具有與上源極/汲極磊晶層50N不同之成分。“不同成分”意指，例如，不同材料、不同元素組成比例、不同摻雜濃度以及其他相似之因素。於一些實施方式中，下源極/汲極磊晶層20N為矽。於一些之實施方式中，下源極/汲極磊晶層20N以及上源極/汲極磊晶層50N含有磷(phosphorous)，且上源極/汲極磊晶層50N之磷濃度係高於下源極/汲極磊晶層20N之磷濃度。再者，當上源極/汲極磊晶層50N含有磷，於一些實施方式中，磷濃度係介於自約1.0×1020cm-3至約6.0×1021cm-3之一範圍內，於一些其他實施方式中，磷濃度可介於自約5.0×1020cm-3至約1.0×1021cm-3之一範圍內。
接著，如第15A圖以及第15B圖所繪示，第二覆蓋層115係藉由適當之蝕刻及/或清洗製程移除。
再者，如第16A圖以及第16B圖所繪示，一接觸襯墊層61係形成於開口內之上源極/汲極磊晶層50P、50N上方，以及層間介電層70之上表面上方。接觸襯墊層61可藉由化學氣相沉積或是原子層沉積而形成。接觸襯墊層61包含SiN、SiOC、SiOCN、SiCO中之一或多者或是任何合適之介電材料，於一些實施方式中，接觸襯墊層61之厚度係介於自約1奈米至約10奈米之範圍內，於一些其他實施方式中，接觸襯墊層61之厚度可介於自約2奈米至約8奈米之範圍內。
如第17A圖以及第17B圖所繪示，形成於上源極/汲極磊晶層50P、50N上方之接觸襯墊層61藉由圖案畫製程被移除。於一些實施方式中，預先非晶化佈植130係執行於曝露之上源極/汲極磊晶層50P、50N。於一些實施方式中，佈植鍺以使上源極/汲極磊晶層50P、50N之上部為非晶態。
接著，沉積一矽化物生成所需之金屬層(例如，W、Ni、Co、Ti及/或Mo)。金屬層可藉由化學氣相沉積、物理氣相沉積或是原子層沉積，或是任何其他合適之薄膜形成方法而形成。如第18A圖以及第18B圖所繪示，於金屬層形成後，熱操作，例如快速熱退火製程，係執行於約450℃至約1000℃，並以上源極/汲極磊晶層50N、50P之成分(例如，矽)以及金屬層之金屬(例如，W、Ni、Co、Ti及/或Mo)形成矽化物層55N、55P。於一些實施方式中，因矽化物層可於形成金屬層之步驟中形成，而無執行熱操作。
於形成矽化物層55N、55P後，形成導電材料層以填充接觸開口。於一些實施方式中，如第1A圖以及第1B圖所繪示，導電材料層包含黏著(膠水)層62之一毯覆層以及體金屬層64。黏著層62包含一層或多層之導電材料。於一些實施方式中，黏著層62包含形成於Ti層上之TiN層。任何其他合適之導電材料可被使用。於一些實施方式中，每一TiN層以及Ti層之厚度係介於自約1奈米至約5奈米之一範圍內，於一些其他實施方式中，每一TiN層以及Ti層之厚度可介於自約2奈米至約3奈米之一範圍內。黏著層62可藉由化學氣相沉積、物理氣相沉積、原子層沉積、電鍍或是上述製程之組合，或是其他合適之薄膜形成方法而形成。黏著層62係用於避免體金屬層64脫落。於一些實施方式中，無黏著層62被使用且體金屬層64係直接形成於接觸開口內。於此例子中，體金屬層64係與矽化物層55N、55P直接接觸。
於一些實施方式中，黏著層62之Ti層可當作形成矽化物層所需之金屬層。
於一些實施方式中，體金屬層64為Co、W、Mo以及Cu中之一，或是任何其他合適之導電材料。於一些實施方式中，Co被當作體金屬層64。體金屬層64可藉由化學氣相沉積、物理氣相沉積、原子層沉積、電鍍或是上述製程之組合，或是其他合適之薄膜形成方法而形成。如第19A圖以及第19B圖所繪示，於導電材料層形成後，執行平坦化製程，例如，化學機械研磨(CMP)或是回蝕刻製程，以移除多餘之材料，藉此形成源極/汲極接觸區60。
應當被瞭解到，第19A圖以及第19B圖所繪示之元件進一步經過互補金屬氧化物半導體製程以形成多種特徵，例如，互連金屬層、介電層、鈍化層等。
根據本揭露之一些實施方式，第20A圖繪示了一半導體元件之剖面圖，且第20B圖繪示了半導體元件之另一剖面圖。與上述第1A圖至第19B圖所描述之實施方式中，相同或相似的材料、組態、維度及/或製程將於接續之實施方式中使用，而其詳盡之解釋將予以省略。
於此實施方式中，鰭式結構10’，至少鰭式結構10’之上部，係由SiGe所組成。SiGe鰭式結構10’具有通道區域14’以及井區12’。抗擊穿佈植係於井區12’中執行，因此井區12’具有不同於通道區域14’之摻雜濃度/特性。
鰭式結構10’亦具有未被閘極結構所覆蓋之源極/汲極區域。額外之半導體層係保形地形成於源極/汲極區域中，以覆蓋SiGe鰭式結構10’之源極/汲極區域，藉此形成輕微摻雜汲極(LLD)結構145。除此之外，離子佈植操作係執行於源極/汲極區域，且源極/汲極區域包含重摻雜區域140。
於形成源極/汲極區域開口之蝕刻操作中，源極/汲極區域之上部未被蝕刻。因此，源極/汲極自源極/汲極區域接觸開口之底部突出。上源極/汲極磊晶層160以及矽化物層155於源極/汲極區域開口形成後形成。於一些實施方式中，上源極/汲極磊晶層160包含具有相較於源極/汲極鰭式結構較高鍺含量之SiGe。於一些實施方式中，上源極/汲極磊晶層160於形成矽化物層155時完全消耗，且不存在於最終結構中。
此處不同之實施方式以及實施例提供多種現有技藝中所欠缺之優勢。例如，藉由於源極/汲極接觸開口形成後形成上源極/汲極磊晶層，接觸著陸面積可被擴大，因而縮減了源極/汲極接觸電阻。再者，先形成大體積之下源極/汲極磊 晶層為非必要，因而能減小鰭節距。
而將被理解的是，並非所有優勢皆必須於上述文中被討論，非所有實施方式或實施例皆具有特定之優勢，其他實施方式或實施例可提供不同之優勢。
根據本揭露之一觀點，於製造半導體元件之方法中，層間介電層(ILD)形成於下方結構上方。下方結構包含設置於鰭式結構之通道區域上方之閘極結構，以及設置於鰭式結構之源極/汲極區域之第一源極/汲極磊晶層。藉由蝕刻層間介電層之一部分以及第一源極/汲極磊晶層之上部，使第一開口形成於第一源極/汲極磊晶層上方。第二源極/汲極磊晶層形成於被蝕刻之第一源極/汲極磊晶層上方。導電材料係形成於第二源極/汲極磊晶層上方。於一或多個上述或接續之實施方式中，下方結構進一步包含蝕刻停止層，且蝕刻停止層之一部分於形成第一開口之步驟中被蝕刻。於一或多個上述或接續之實施方式中，於形成第二源極/汲極磊晶層後，一金屬層形成於第二源極/汲極磊晶層上方，且矽化物層係藉由使金屬層以及第二源極/汲極磊晶層反應而形成。導電材料係形成於矽化物層上。於一或多個上述或接續之實施方式中，於形成金屬層前，一佈植操作執行於第二源極/汲極磊晶層上。於一或多個上述或接續之實施方式中，於第一開口形成後，覆蓋層形成於第一開口內以及層間介電層上，且覆蓋層被圖案化，藉此形成第二開口於覆蓋層內。第二源極/汲極磊晶層形成於第二開口內。於一或多個上述或接續之實施方式中，第一源極/汲極磊晶層具有不同於第二源極/汲極磊晶層之成分。於一或多個上 述或接續之實施方式中，第一源極/汲極磊晶層以及第二源極/汲極磊晶層含有鍺，且第二源極/汲極磊晶層之鍺濃度係大於第一源極/汲極磊晶層之鍺濃度。於一或多個上述或接續之實施方式中，第一源極/汲極磊晶層以及第二源極/汲極磊晶層中至少一者進一步含有硼。於一或多個上述或接續之實施方式中，第二源極/汲極磊晶層包含選自由SiP、InP以及GaInP所組成之群組中之一者。於一或多個上述或接續之實施方式中，第一源極/汲極磊晶層係形成於設置於鰭式結構內之凹槽內及上方。
根據本揭露之另一觀點，於製造半導體元件之方法中，層間介電層形成於下方結構上方。下方結構包含第一導電型鰭式場效電晶體之第一閘極結構以及第一源極/汲極磊晶層，以及第二導電型鰭式場效電晶體之第二閘極結構以及第二源極/汲極磊晶層。第一開口係藉由蝕刻層間介電層之一部分以及第一源極/汲極磊晶層之上部而形成於第一源極/汲極磊晶層上方，第二開口係藉由蝕刻層間介電層之一部分以及第二源極/汲極磊晶層之上部形成於第二源極/汲極磊晶層上方。第三源極/汲極磊晶層係形成於被蝕刻之第一源極/汲極磊晶層上方，並以第一覆蓋層覆蓋第二開口。於一或多個上述或接續之實施方式中，第一覆蓋層被移除，且第四源極/汲極磊晶層形成於被蝕刻之第二源極/汲極磊晶層上方，並以第二覆蓋層覆蓋第三源極/汲極磊晶層。於一或多個上述或接續之實施方式中，於形成第四源極/汲極磊晶層後，移除第二覆蓋層，形成金屬層於第三源極/汲極磊晶層以及第四源極/汲極磊晶層 上方，第一矽化物層藉由使金屬層與第三源極/汲極磊晶層反應而形成，第二矽化物層藉由使金屬層與第四源極/汲極磊晶層反應而形成，第一接觸層形成於第一矽化物層上且第二接觸層形成於第二矽化物層上。於一或多個上述或接續之實施方式中，第一覆蓋層形成於第一開口內以及層間介電層上方。再者，形成於第一開口內之第一覆蓋層被圖案化，藉此形成第三開口於第一覆蓋層內，且第三源極/汲極磊晶層係形成於第三開口內。於一或多個上述或接續之實施方式中，第二覆蓋層亦形成於第二開口內以及層間介電層上方。再者，形成於第二開口內之第二覆蓋層被圖案化，藉此形成第四開口於第二覆蓋層內，且第四源極/汲極磊晶層係形成於第四開口內。於一或多個上述或接續之實施方式中，第一源極/汲極磊晶層具有不同於第三源極/汲極磊晶層之成分，且第二源極/汲極磊晶層具有不同於第四源極/汲極磊晶層之成分。於一或多個上述或接續之實施方式中，第一導電型為p型，第一源極/汲極磊晶層以及第三源極/汲極磊晶層含有鍺，且第三源極/汲極磊晶層之鍺濃度係大於第一源極/汲極磊晶層之鍺濃度。於一或多個上述或接續之實施方式中，第一源極/汲極磊晶層以及第三源極/汲極磊晶層中至少一者進一步含有硼。於一或多個上述或接續之實施方式中，第一導電型為n型，且第三源極/汲極磊晶層包含選自由SiP、InP以及GaInP所組成之群組中之一者。
根據本揭露之另一觀點，於製造半導體元件之方法中，層間介電層形成於下方結構上。下方結構包含設置於第一鰭式結構之通道區域上之閘極結構以及第二鰭式結構之通道區域，設置於第一鰭式結構之源極/汲極區域之第一源極/汲極磊晶層，以及設置於第二鰭式結構之源極/汲極區域之第二源極/汲極磊晶層。第一開口藉由蝕刻層間介電層之一部分以及第一源極/汲極磊晶層及第二源極/汲極磊晶層之上部以形成於第一源極/汲極磊晶層及第二源極/汲極磊晶層上方。第三源極/汲極磊晶層係形成於被蝕刻之第一源極/汲極磊晶層及第二源極/汲極磊晶層上方。導電材料係形成於第三源極/汲極磊晶層上方。
根據本揭露之另一觀點，半導體元件包含設置於第一鰭式結構之通道區域上方之閘極結構，設置於鰭式結構之源極/汲極區域之源極/汲極結構，覆蓋源極/汲極結構之側面之蝕刻停止層以及設置於源極/汲極結構上方之導電接點。源極/汲極結構包含第一磊晶層以及設置於第一磊晶層上方之第二磊晶層。第二磊晶層設置於蝕刻停止層之上部上。於一或多個上述或接續之實施方式中，第二磊晶層係設置於形成於第一磊晶層內之凹槽內。於一或多個上述或接續之實施方式中，半導體元件進一步包含設置於第二磊晶層與導電接點間之矽化物層。於一或多個上述或接續之實施方式中，矽化物層包含TiSi。於一或多個上述或接續之實施方式中，第一磊晶層具有不同於第二磊晶層之成分。於一或多個上述或接續之實施方式中，第一磊晶層以及第二磊晶層含有鍺，且第二磊晶層之鍺濃度係高於第一磊晶層之鍺濃度。於一或多個上述或接續之實施方式中，第一源極/汲極磊晶層以及第二源極/汲極磊晶層中至少一者進一步含有硼。於一或多個上述或接續之實施方式中，硼濃度係介於自約1.0×1020cm-3至約6.0×1021cm-3之範圍內。於一或多個上述或接續之實施方式中，第一磊晶層包含矽鍺化合物(Sil-xGex)且第二磊晶層包含矽鍺化合物(Sil-yGey)，其中0.15x0.8、0.2y1.0且x<y。於一或多個上述或接續之實施方式中，第二磊晶層包含一選自由SiP、InP以及GaInP所組成之群組中之一者。於一或多個上述或接續之實施方式中，第二磊晶層之磷濃度係介於自約1.0×1020cm-3至約6.0×1021cm-3之範圍內。於一或多個上述或接續之實施方式中，第一磊晶層係形成於設置於鰭式結構內之凹槽內。
根據本揭露之另一觀點，半導體元件包含第一鰭式場效電晶體，其中包含設置於第一鰭式結構之第一通道區域上方之第一閘極結構、設置於第一鰭式結構之第一源極/汲極區域之第一源極/汲極結構以及覆蓋第一源極/汲極結構側表面之第一蝕刻停止層；以及第二鰭式場效電晶體，其中包含設置於第二鰭式結構之第二通道區域上方之第二閘極結構、設置於第二鰭式結構之第二源極/汲極區域之第二源極/汲極結構以及覆蓋第二源極/汲極結構側表面之第二蝕刻停止層。第一鰭式場效電晶體為第一導電型且第二鰭式場效電晶體為第二導電型。第一源極/汲極結構包含第一下磊晶層以及設置於第一下磊晶層上方之第一上磊晶層。第一上磊晶層係設置於第一蝕刻停止層之上部上。於一或多個上述或接續之實施方式中，半導體元件進一步包含設置於第一上磊晶層上之第一矽化物層，以及設置於第一矽化物層上之第一導電接點。於一或多個上述或接續之實施方式中，第二源極/汲極結構包含第二下磊 晶層以及設置於第二下磊晶層上方之第二上磊晶層，且第二上磊晶層係設置於第二蝕刻停止層之上部上。於一或多個上述或接續之實施方式中，半導體元件進一步包含設置於第一上磊晶層上之第一矽化物層，以及設置於第一矽化物層上之第一導電接點。於一或多個上述或接續之實施方式中，第二上磊晶層包含一選自由SiP、InP以及GaInP所組成之群組中之一者。於一或多個上述或接續之實施方式中，第一下磊晶層以及第一上磊晶層含有鍺，且第一上磊晶層之鍺濃度係大於第一下磊晶層之鍺濃度。於一或多個上述或接續之實施方式中，第一下磊晶層以及第一上磊晶層中至少一者進一步含有硼。
根據本揭露之另一觀點，半導體元件包含設置於第一鰭式結構之通道區域上方之閘極結構以及第二鰭式結構之通道區域、設置於第一鰭式結構之源極/汲極區域之第一磊晶層、設置於第二鰭式結構之源極/汲極區域之第二磊晶層、第三磊晶層以及覆蓋第一源極/汲極磊晶層與第二源極/汲極磊晶層之側面之蝕刻停止層。第三磊晶層係設置於蝕刻停止層之上部以及第一磊晶層與第二磊晶層上。
雖然本揭露已以實施方式揭露如上，然其並不用以限定本揭露，任何熟習此技藝者，在不脫離本揭露的精神和範圍內，當可作各種的更動與潤飾，因此本揭露的保護範圍當視後附的申請專利範圍所界定者為準。

Claims (10)

  1. 一種半導體元件製造方法，包含：形成一層間介電(interlayer dielectric(ILD))層於一下層結構上方，其中該下層結構包含：一閘極結構，設置於一鰭式結構之一通道區域上方；以及一第一源極/汲極磊晶層，設置於該鰭式結構之一源極/汲極區域；藉由蝕刻該層間介電層之一部分以及該第一源極/汲極磊晶層之一上部而形成一第一開口於該第一源極/汲極磊晶層上方；形成一第二源極/汲極磊晶層於被蝕刻之該第一源極/汲極磊晶層上方，其中該第一源極/汲極磊晶層以及該第二源極/汲極磊晶層含有鍺(Ge)，該第二源極/汲極磊晶層之一鍺濃度高於該第一源極/汲極磊晶層之一鍺濃度；以及形成一導電材料於該第二源極/汲極磊晶層上方。
  2. 如請求項第1項所述之半導體元件製造方法，進一步包含，於該形成該第二源極/汲極磊晶層之步驟後：形成一金屬層於該第二源極/汲極磊晶層上方；以及藉由使該金屬層與該第二源極/汲極磊晶層反應而形成一矽化物層，其中該導電材料係形成於該矽化物層上。
  3. 如請求項第2項所述之半導體元件製造方法，進一步包含，於該形成該金屬層之步驟前，執行一佈植操作於該第二源極/汲極磊晶層上。
  4. 如請求項第1項所述之半導體元件製造方法，進一步包含，於該形成該第一開口之步驟後：形成一覆蓋層於該第一開口內以及該層間介電層上方；以及圖案化該覆蓋層，藉此形成一第二開口於該覆蓋層，其中該第二源極/汲極磊晶層係形成於該第二開口內。
  5. 一種半導體元件製造方法，包含形成一層間介電(interlayer dielectric(ILD))層於一下層結構上方，其中該下層結構包含；一第一導電型鰭式場效電晶體(FinFET)之一第一閘極結構以及一第一源極/汲極磊晶層；以及一第二導電型鰭式場效電晶體之一第二閘極結構以及一第二源極/汲極磊晶層；藉由蝕刻該層間介電層之一部分以及該第一源極/汲極磊晶層之一上部而形成一第一開口於該第一源極/汲極磊晶層上方，以及藉由蝕刻該層間介電層之一部分以及該第二源極/汲極磊晶層之一上部而形成一第二開口於該第二源極/汲極磊晶層上方；以及形成一第三源極/汲極磊晶層於被蝕刻之該第一源極/汲極磊晶層上方，同時以一第一覆蓋層覆蓋該第二開口。
  6. 如請求項第5項所述之半導體元件製造方法，進一步包含：移除該第一覆蓋層；以及形成一第四源極/汲極磊晶層於被蝕刻之該第二源極/汲極磊晶層上方，同時以一第二覆蓋層覆蓋該第三源極/汲極磊晶層。
  7. 如請求項第6項所述之半導體元件製造方法，進一步包含，於該形成該第四源極/汲極磊晶層之步驟後：移除該第二覆蓋層；形成一金屬層於該第三源極/汲極磊晶層以及該第四源極/汲極磊晶層上方；藉由使該金屬層與該第三源極/汲極磊晶層反應而形成一第一矽化物層，以及藉由使該金屬層與該第四源極/汲極磊晶層反應而形成一第二矽化物層；以及形成一第一接觸層於該第一矽化物層上，以及形成一第二接觸層於該第二矽化物層上。
  8. 如請求項第6項所述之半導體元件製造方法，其中：該第一覆蓋層係形成於該第一開口內以及該層間介電層上方，該半導體元件形成方法進一步包含圖案化形成於該第一開口內之該第一覆蓋層，藉此形成一第三開口於該第一覆蓋層，以及該第三源極/汲極磊晶層係形成於該第三開口內。
  9. 如請求項第8項所述之半導體元件製造方法，其中：該第二覆蓋層係形成於該第二開口內以及該層間介電層上方，該半導體元件形成方法進一步包含圖案化形成於該第二開口內之該第二覆蓋層，藉此形成一第四開口於該第二覆蓋層，以及該第四源極/汲極磊晶層係形成於該第四開口內。
  10. 一種半導體元件，包含：一閘極結構，設置於一鰭式結構之一通道區域上方；一源極/汲極結構，設置於該鰭式結構之一源極/汲極區域；一蝕刻停止層，覆蓋於該源極/汲極結構之側面；以及一導電接點，設置於該源極/汲極結構上方，其中：該源極/汲極結構包含一第一磊晶層以及設置於該第一磊晶層上之一第二磊晶層，以及該第二磊晶層係設置於該蝕刻停止層之一上部上。
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