TWI664696B - 用於嵌入式半導體裝置封裝的電性互連結構及其製造方法 - Google Patents

用於嵌入式半導體裝置封裝的電性互連結構及其製造方法 Download PDF

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TWI664696B
TWI664696B TW104125946A TW104125946A TWI664696B TW I664696 B TWI664696 B TW I664696B TW 104125946 A TW104125946 A TW 104125946A TW 104125946 A TW104125946 A TW 104125946A TW I664696 B TWI664696 B TW I664696B
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layer
die
metallized
thickness
dielectric layer
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TW104125946A
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TW201620074A (zh
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保羅 麥可隆尼
艾倫 格達
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美商通用電機股份有限公司
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Abstract

一種電子封裝，包括具有形成穿過本身厚度之第一複數個孔的第一介電質基板、耦接至該第一介電質基板之頂表面的金屬化接觸層、以及定位於形成穿過該第一介電質基板之該厚度的第一晶粒開口中的第一晶粒。金屬化互連形成在該第一介電質基板之底表面且延伸穿過該第一複數個孔以接觸該金屬化接觸層。第二介電質基板係耦接至該第一介電質基板且具有形成穿過本身厚度之第二複數個孔。金屬化互連延伸穿過該第二複數個孔以接觸該第一複數個金屬化互連及該第一晶粒之接觸墊。第一導電元件電性地耦接該第一晶粒至該金屬化接觸層。

Description

用於嵌入式半導體裝置封裝的電性互連結構及其製造方法
本發明係有關於用於嵌入式半導體裝置封裝的電性互連結構及其製造方法。
本發明實施例大致是有關於嵌入式半導體裝置封裝或電子封裝，且更具體地是有關於結合電性互連結構或其中形成至晶粒(die)I/O連接及在電子封裝中的其它電性組件之功能性網路組件、同時相比於其中結合印刷電路板(printed circuit board，PCB)的先前技術裝置最小化電子封裝之整體厚度的半導體裝置封裝。
當半導體裝置封裝已經變的越來越小且產生更好的操作性能，封裝技術相應地從含鉛封裝演變至疊層狀球柵陣列(Ball Grid Array，BGA)封裝、至晶片級封裝(chip scale packaging，CSP)然後覆晶(flip-chip)封裝，而現在為埋入晶粒/嵌入式晶片堆疊(build-up)封裝。推動半導體晶片封裝技術的進步係透過不斷增加對於 實現更好的性能、更加地微小化及更高的可靠度的需求。新的封裝技術必須進一步提供用於大規模製造從而允許規模經濟並同時解決微小化需求之批量生產的可能性。
現有製造技術的挑戰係電子封裝的微小化，其中電子封裝結合不同類型之單獨封裝的半導體晶粒或功率裝置。單獨封裝的裝置通常安裝在多層印刷電路板(PCB)上，其中多層印刷電路板對於整體電子封裝的厚度增加相當多。
因此，需要一種用於製造嵌入式電子封裝的方法，其提供了具有增加互連數目及密度之雙面I/O系統、同時最小化電子封裝之整體厚度。
本發明實施例藉由提供用於嵌入式半導體裝置封裝之堆疊製程克服前面所提之缺點，嵌入式半導體裝置封裝開始於功能性網路組件之製造，其提供增加剛性至電子封裝以及用於在封裝中I/O連接至組件之頂和底表面的電性佈線層的雙重目的。
根據本發明一實施例，一種電子封裝，包括具有形成穿過本身厚度之第一複數個孔的第一介電質基板，耦接至該第一介電質基板之頂表面之金屬化接觸層，以及定位在形成穿過該第一介電質基板之該厚度的第一晶粒開口中之第一晶粒。第一複數個金屬化互連，其形成在該第一介電質基板之底表面上且延伸穿過該些第一複數個 孔以接觸該金屬化接觸層的至少一部份。第二介電質基板之頂表面耦接至該第一介電質基板之底表面的，該第二介電質基板具有形成穿過其厚度之第二複數個孔。第二複數個金屬化互連，其形成在該第二介電質基板之底表面上且延伸穿過該些第二複數個孔以接觸該些第一複數個金屬化互連及該第一晶粒之接觸墊。第一導電元件，其電性耦接該第一晶粒至該金屬化接觸層。
根據本發明另一實施例，一種製造電子封裝的方法，該方法包含：提供第一介電質層，在該第一介電質層之第一表面上形成金屬化接觸層，以及在該第一介電質層之相對於該第一表面之第二表面上形成第一複數個金屬化孔。該些第一複數個金屬化孔延伸穿過該第一介電質層之厚度以接觸該些複數個金屬化接觸層的至少一部分。該方法也包括形成穿過該第一介電質層之該厚度的第一電性組件開口，耦接第二介電質層之該第一介電質層之該第二表面，以及定位第一電性組件在該第一電性組件開口中。在該第二介電質層之底表面上形成第二複數個金屬化孔，該第二複數個金屬化孔延伸穿過該第二介電質層之厚度以耦接該金屬化接觸層至該第一電性組件。此外，該方法包括耦接第一導電組件在該第一電性組件及該金屬化接觸層之間。
根據本發明又一實施例，一種電子封裝包含功能性網路組件，其具有耦接至第一介電質層之金屬化接觸層，其中該金屬化接觸層之底表面大致與該第一介電質 層之頂表面共平面。該功能性網路組件也包括設置在該第一介電質層之底表面且延伸穿過形成在該第一介電質層內的孔以與該金屬化接觸層電性連接的第一複數個金屬互連，以黏著劑耦接至該第一介電質層的第二介電質層，以及設置在該第二介電質層之底表面且延伸穿過形成在該第二介電質層內的孔以與該些第一複數個金屬互連的至少一部分電性連接的第二複數個金屬互連。定位在形成穿過該第一介電質層之第一開口中且具有耦接至該黏著劑及該些第一複數個金屬互連之至少一金屬互連的第一表面的第一晶粒。電性連接該金屬化接觸層之第一部分及該第一晶粒之相對於該第一表面的第二表面的第一金屬橋。
這些和其它優點與特徵從提供在下面之結合圖式的本發明較佳實施之詳細敘述將可以更容易地理解。
10,32,168‧‧‧電子封裝
12‧‧‧印刷電路板
14,16,18‧‧‧分離組件
15,98,122,124,129,138,150,154,186,188‧‧‧厚度
20,30,68,70,72,180,182,84‧‧‧晶粒
21,31,80‧‧‧接觸墊
22‧‧‧電感器
23‧‧‧I/O墊
24,108a,108b,108c‧‧‧被動組件
25,35‧‧‧覆蓋成形組件
26‧‧‧電性接觸
27,37‧‧‧導線結合
28‧‧‧金屬化連接
29,39‧‧‧安裝平台
33‧‧‧I/O引線
34,136‧‧‧上介電質層
36‧‧‧可選擇框
38‧‧‧金屬晶種層
40,44,142‧‧‧頂表面
42,52‧‧‧金屬層
46‧‧‧可焊接塗層
47‧‧‧金屬塗層
48‧‧‧金屬化接觸層
49‧‧‧金屬接觸墊
50,82,148‧‧‧孔
51‧‧‧跡線
51a‧‧‧部分
54,86,88,102,146‧‧‧底表面
56‧‧‧金屬化孔或金屬互連
58‧‧‧晶粒開口
59‧‧‧側壁
60,178‧‧‧第一級功能性網路組件
62‧‧‧黏著層
64‧‧‧下介電層
74,76,78‧‧‧主動表面
84‧‧‧金屬化層
90‧‧‧可焊接金屬塗佈
92,144‧‧‧金屬化孔
94‧‧‧第二級功能性網路組件
96,134‧‧‧功能性網路組件
100‧‧‧焊錫遮罩
104,166‧‧‧下焊錫層
106‧‧‧焊錫層
108,110‧‧‧可焊接裝置
112,160‧‧‧上表面
114,116,118‧‧‧短路棒
120‧‧‧焊錫
126‧‧‧第一表面
128‧‧‧第二表面
130‧‧‧第二主動側
132‧‧‧封裝劑
140‧‧‧金屬化接觸
152‧‧‧結合厚度
156‧‧‧上焊錫遮罩
158‧‧‧下焊錫遮罩
162‧‧‧下表面
164‧‧‧上焊錫層
174‧‧‧上金屬化層
176‧‧‧金屬化互連
190‧‧‧非主動表面
192‧‧‧金屬接觸層
194‧‧‧金屬接觸互連
圖式示出目前預期用於實現本發明的實施例。
在圖式中：第1圖係先前技術之積體電路(IC)封裝之示意剖面側視圖。
第2-17圖係根據本發明實施例在製造/堆疊製程的各種階段期間之結合功能性網路結構的積體電路(IC)封裝之示意剖面側視圖。
第18圖係根據本發明實施例在第2-17圖之 製造/堆疊製程的可選擇階段期間之結合功能性網路結構的IC封裝之示意剖面側視圖。
第19及20圖分別係根據第2-16圖之製造/堆疊製程製造之IC封裝的示意底視及頂視圖。
第21圖係根據本發明替代實施例之結合功能性網路結構之IC封裝的示意剖面側視圖。
第22-27圖係根據本發明另一實施例之在製造/堆疊製程的各種階段期間之結合功能性網路結構的積體電路(IC)封裝之示意剖面側視圖。
本發明實施例提供用於形成嵌入式晶粒模組或電子封裝之方法。電子封裝被製造以包括功能性網路組件，其增加剛性至嵌入式晶粒封裝且提供多層之額外電性佈線(electrical routing)。如下面詳細敘述，實施例之功能性網路組件包括具有金屬化電性連接或互連在功能性網路組件兩側之介電質層以及定位其中金屬化孔。晶粒開口形成在功能性網路組件中，所述功能性網路組件允許方置相對於介電質層之晶片或電性組件。
本發明實施例是針對包括一或多個晶粒(即，晶片)嵌入在複數個圖案化功能性網路層之電子封裝之堆疊，其中功能性網路層在電子封裝中形成佈線層。而在下面第2-27圖實施例之嵌入在電子封裝之晶粒具體是作為晶粒，可以理解的是其它電性組件可以替代嵌入式 晶粒模組之晶粒，且因此本發明實施例不僅限制於電子封裝中的嵌入晶片/晶粒。也就是，下面敘述之在電子封裝實施例內所使用之晶粒/晶片也應可理解地包括其它電性組件，例如電阻(resistor)、電容(capacitor)、電感器(inductor)、濾波器(filter)或其它可以在電子裝置內提供之相似裝置。
先前技術電子封裝10之一般結構顯示於第1圖。用於IC封裝10之標準製造製程通常開始於一個具有厚度14大約為32密耳(mils)至64密耳之多層印刷電路板(PCB)12。例如晶粒封裝或封裝控制器的各種分離組件16、18，以及例如電感器22和被動組件24的其它電性組件可使用例如以球柵陣列(BGA)形式的焊錫球之金屬化連接28電性耦接至PCB 12電性接觸26。每一個分離組件16、18包括具有形成在主動表面之接觸墊21、31上的各別晶粒20、30。晶粒20、30設置在安裝平台29、39上且包覆在封裝劑或覆蓋成形(over-molding)組件25、35中。導線結合(wirebond)27、37形成直接金屬連接在各自晶粒20、30之主動表面和設置在或耦接至分離組件16、18之下表面的金屬化輸入/輸出(I/O)之間。在分離組件16之情形下，導線結合27形成晶粒20之接觸墊21至設置在分離組件16之底表面上之I/O墊23之間之電子連接。導線結合37電性耦接接觸墊31至I/O引線33。例如，其中晶粒30為二極體(diode)，導線結合37可接觸至晶粒30之第一表面上之陽極(anode)且 晶粒之第二表面可被焊接到引線框(leadframe)。I/O墊23及I/O引線33耦接至PCB 12之電性接觸26藉由金屬化連接28的方式。此種先前技術IC封裝之整體厚度15可在500μm-2000μm範圍內或更大。
現在參考第2-17圖，根據本發明一實施例之用於製造電子封裝32被闡述。單切的(singular)電子封裝堆疊製程之剖面在第2-17圖中每一圖示出是為了堆疊製程之視覺化，然而該技術領域中具通常知識者將意識到多電子封裝可以以在面板級之相似方式被製造且根據需要分割成單個電子封裝組件。此外，每一電子封裝可含有單一或多個晶粒/晶片/被動(passive)元件。
如第2圖所示，嵌入式晶粒模組32之製造開始於上介電質層34或耦接至可選擇框36之絕緣層(以虛像示出)。在一實施例中上介電質層34為Kapton® laminate flex，雖然其它例如Ultem®,polytetrafluoroethylene(PTFE)或例如液晶聚合物(liquid crystal polymer，LCP)或聚合物膜聚醯亞胺基板之其它聚合物膜也可以使用。在一實施例中，上介電質層34可具有大約10μm-50μm之厚度。金屬晶種層38(第3圖)形成在上介電質層34和金屬層42之頂表面40，例如銅應用於金屬晶種層38。在一實施例中，金屬晶種層38包含鈦-銅且使用濺鍍(sputter)技術形成以及金屬層42使用電鍍(electroplating)製程被應用。在另一實施例中，金屬層42直接應用於上介電質層34之頂表面40而 沒有晶種金屬。在又一實施例中，上介電質層34可以在附著至框36之前的銅批覆(clad)，其中銅可以為電沉積(electrodeposited)或層壓(laminated)的。金屬層42之厚度可以依據設計需求被選擇，例如晶粒厚度，將在下面更詳細敘述。在示範性實施例中，金屬層42可具有大約4μm-150μm之厚度。選擇性的鈦層(未示出)可應用於金屬層42之頂表面44。
參考第4圖，本發明一實施例之金屬層42的頂表面44可接著塗佈金屬塗層(coating)或可焊接塗層46，其接著被圖案化以形成在製造製程中後續步驟之被動元件焊接附著之焊錫墊。金屬塗層47包含可焊接金屬，例如鎳-金，作為一非限制範例，其促進焊接附著以及幫助防止焊錫從沿著金屬層42的整個頂表面44流動。然而，可以預期的是金屬塗層47在一些其中被動組件不被包括在設計中或金屬塗層不需要用於被動組件之焊接附著或其它如導電黏著劑被使用之替代實施例中可以被省略。金屬層42接著被圖案化。在結合金屬塗層46之實施例中，塗層46可被使用作為蝕刻遮罩(etching mask)。接著，金屬層42及金屬晶種層38被蝕刻以在上介電質層34之頂表面44上形成金屬化接觸層48。在替代實施例中，半添加電鍍製程可被使用以形成金屬化接觸層48。
如第5圖所示，金屬化接觸層48的一些部分可含有金屬塗層46而其它可能沒有。包括金屬塗層46之部分的金屬化接觸層48充當金屬接觸墊49至其中可使用 焊錫附著的電性組件。不包括金屬塗層46之部分的金屬化接觸層48充當電性跡線51以電性連接至設置在電子封裝中的各種組件，如第19圖中示出了另外的細節。因此，金屬化接觸層48被形成具有金屬化接觸墊49及跡線51。金屬化接觸層48之接觸墊49和跡線51之示範性配置在第19圖中示出另外的細節。
如第6圖所示，數個孔50在相應於圖案化的銅層42之位置形成穿過上介電質層34。例如，孔50可藉由UV雷射鑽孔或蝕刻形成。另外，也可以意識到孔50可以以其它方式包括電漿蝕刻(plasma etching)、光定義(photo-definition)、像二氧化碳(CO2)和準分子(excimer)雷射技術或機械鑽孔製程之方法被形成。在一實施例中，如第6圖所示，孔50被形成具有成角度側表面，其促進後續填充及金屬沉積。如第7圖所示，例如銅之金屬層52接著形成在介電質34之底表面54上。在一實施例中，選擇性的鈦-銅晶種層(未示出)被濺鍍塗佈至介電質34之底表面54且在沉積銅層52之前穿過孔50。如第8圖所示，在圖案化金屬層52之後，金屬層52和鈦-銅晶種層(如果使用)被蝕刻以在其中延伸穿過孔50之上介電質層34之底表面54上形成金屬化孔或金屬互連56之上層。另外，金屬互連56之圖案化可使用半添加電鍍製程建立。金屬化孔56之上層因此在上介電質層34之底表面54以及在上介電質層34之頂表面40上之金屬化接觸層48形成電性連接。
接著，如第9圖所示，一或多個晶粒開口58被形成穿過上介電質層34。晶粒開口58的尺寸比相應的晶粒稍大。在一非限制範例中，晶粒開口58的尺寸比相應的晶粒大約10μm。在一實施例中，晶粒開口58使用雷射形成，其中雷射可被使用來控制晶粒開口58之側壁59之角度。第9圖示出其中晶粒開口58被形成具有成角度的側壁59以促進晶粒安置在晶粒開口58內的一實施例。另外，晶粒開口58可被形成平直或垂直的側壁。
所得第一級功能性網路組件60包括具有金屬化接觸層48及金屬化孔56之上層形成其上的上介電質層34。可以預期的是金屬化接觸48和/或金屬化孔56之上層的厚度可基於設計規格變化。例如，金屬化接觸48和/或金屬化孔56之上層中的一者或兩者可被設計具有增加厚度以應付高電流應用。
為了增加互連密度及功能性網路組件60之佈線能力，附加金屬互連層可以在附著晶粒組件至功能性網路組件60之前，增加至第一級功能性網路組件60。例如，在製造製程的下一個步驟中，黏著層62可被應用於上介電質層34之底表面54及金屬化孔56之上層。根據一實施例，黏著層62首先應用到下介電層64，如第10圖所示其耦接至選擇性的過大的框66。根據各種實施例，作為非限制範例，黏著層62可使用例如旋轉塗佈(spin coating)或狹縫式晶粒塗佈(slot die coating)的塗佈技術而被應用，或可藉由噴墨列印(inkjet printing) 型裝置技術形式的可程式(programmable)分配(dispensing)工具被應用。在黏著層62應用在上介電質層34之後，進行耦合上介電質層34至下介電質層64的疊層技術。
參考第11圖，一或多個晶粒68、70、72被放置在形成於上介電質層34中的晶粒開口58。如第11圖所示晶粒68、70、72可以是不同厚度的，或在一替代實施例中是相同厚度的。在一非限制實施例中，具有厚度約50μm的薄晶粒可被放置在晶粒開口58中。如圖所示，晶粒68、70、72被定位使得包含接觸墊80之主動表面74、76、78被定位在黏著層62內。而沒有在實施例中顯示的，可以預期的是例如電阻、電容或電感器的被動元件，可以以相似於上面關於晶粒68、70、72敘述的方式，被放置在黏著層62中相應的晶粒開口58。
當晶粒68、70、72被定位在晶粒開口58中，部分的黏著層62向上行進至晶粒68、70、72之側邊以填充介電質層34和晶粒68、70、72之間的空間。無論是藉由黏著層62或晶粒68、70、72而保持未填充之晶粒開口58的任何部分可在後續製程步驟中填充有封裝劑132。在晶粒68、70、72被定位之後，黏著層62可以被完全固化，加熱或藉由熱或輻射的結合。適當的輻射包括UV光和/或微波。假如揮發物存在的話，部分真空和/或高於大氣壓力可在固化期間被使用以促進黏著劑中揮發物的去除。因為晶粒開口58的尺寸剛好稍大於晶粒68、 70、72(例如，約大於10μm)，晶粒68、70、72在介電質層34中自對準(self-align)。當黏著層62被完全固化時，晶粒開口58也防止晶粒68、70、72移動或游離開其位置。
接著，過大的框66被去除且孔82之第二層被形成穿過下介電質層64及黏著層62。如第12圖所示，孔82之第二層延伸至在金屬化孔56和晶粒68、70、72上的相應位置。可以預期的是孔82尺寸差異可取決於電流需求及晶粒墊尺寸變化。
如第13圖所示，在形成孔82之第二層之後，金屬化層84被應用以塗佈下介電質層64之底表面86且延伸穿過孔82之第二層。在一實施例中，例如鈦-銅晶種層(未示出)的金屬塗佈層在之金屬化層84應用之前被濺鍍沉積在下介電質層64之底表面86上。可選地，鈦層(未示出)可被應用至金屬化層84之底表面88。框36可接著被去除。
現在參考第14圖，例如鎳-金之可焊接金屬塗佈90可被應用至金屬化層84之底表面88上。接著，如第15圖所示，金屬化層84被圖案化及蝕刻以形成金屬化孔或金屬化互連92之下層。金屬化孔92之下層包含電性連接至晶粒68、70、72以及金屬化孔56之上層。在一替代實施例中，金屬化孔92之下層可使用半添加電鍍技術形成。總之，黏著層62、金屬化孔92之下層及可焊接金屬塗佈90形成第二級功能性網路組件94。
可以預期的是包含第一級功能性網路組件60及第二級功能性網路組件94的功能性網路組件96可被製造為具有或不具有晶粒68、70、72之預先製造的模組。在其中功能性網路組件96不具有晶粒68、70、72之實施例中，黏著層62可以以半固化狀態(partially cured state)被提供(例如，作為一個B-階段材料)這對於進一步的處理或傳輸是足夠穩定的。這將允許晶粒68、70、72在後續步驟中隨後附著至功能性網路組件96。在一實施例中，功能性網路組件具有厚度98約為5密耳。
根據本發明一實施例，應認識到介電質和金屬化孔之附加層可以在進一步功能性網路組件96之堆疊步驟期間可被添加超過第二級功能性網路組件94，其具有取決於最終封裝之設計考量而被應用之數個功能性網路之附加級。
在功能性網路組件96之級的應用之後，焊錫遮罩100可被應用至功能性網路組件96之最外底表面102。在示出的實施例中，焊錫遮罩100被應用至部分的下介電質層64之底表面86及金屬化孔92之下層且被圖案化如第16圖所示。而沒在第16圖示出，可以預期的是第二焊錫遮罩可根據應用的需要形成在選擇面朝上的表面金屬化接觸層48、上介電質層34及晶粒68、70、72上。接著焊錫遮罩100之應用，可以形成如圖所示之下焊錫層104。下焊錫層104提供I/O連接至功能性網路組件96之底表面102。在一實施例中，下焊錫層104被形成如 焊錫至焊錫遮罩100的球(例如，形成球柵陣列(BGA)之焊錫球)。然而，還可以預想被連接之I/O互連84的其它形式，例如電鍍凸塊(plated bumps)、支柱凸塊(pillar bumps)、金嵌柱凸塊(stud bumps)、金屬填充聚合物凸塊或導線結合連接/墊，使得電性連接在功能性網路組件96中的電性組件和例如母板或印刷電路板(PCB)的外部組件(未示出)之間被製成。
如第17圖所示，焊錫層106被使用以耦接被動組件108、110或其它可焊接裝置至各自的金屬化接觸層48之金屬化接觸墊49。在示出的實施例中，每一被動組件108、110被耦接至各自的金屬化接觸層48之一對金屬化接觸墊49之上表面112。嵌入式晶粒模組32之所得厚度129可根據應用及取決於結合至模組中的晶粒之相對薄度或厚度變化。在一非限制範例中，嵌入式晶粒模組32可根據本發明實施例被製造具有厚度129約175μm-270μm。
金屬橋、導電元件或短路棒114、116、118也被使用來電性耦接每一個晶粒68、70、72至各自的金屬化接觸墊49。在一實施例中焊錫120被使用以電性耦接短路棒114、116、118至晶粒68、70、72。另外，另一個例如燒結的銀之具有所需電性和熱導電特性之連接材料可被使用來取代焊錫。如在晶粒68和晶粒70的情況下所示，短路棒114、116和金屬化接觸48之間的焊錫120厚度可以考慮到晶粒68、70之不同厚度122、124變化。而 在第17圖所示之被提供於每一晶粒68、70、72之短路棒114、116、118，本領域具通常知識者將意識到對於僅具有一主動表面的晶粒，短路棒可以被省略。
另外，短路棒的幾何形狀可以依據不同晶粒厚度被改變。例如，短路棒118被提供具有如第17圖所示之L形剖面幾何，其具有與穿過焊錫120之金屬化接觸48接觸的短路棒118之第一表面126以及與穿過焊錫120之晶粒72的第二主動側130接觸的短路棒118之第二表面128。在一實施例中短路棒118可被加工為具有L形剖面，或在替代實施例中被建構具有以例如導電環氧樹脂(epoxy)之黏著劑連接在一起之一對矩形層板(slabs)。
如第18圖所示，任意地，晶粒68、70、72及被動組件108、110可塗覆有封裝劑132。例如，封裝劑132可在高電壓應用中被使用以防止晶粒和金屬組件之間拱起(arching)或提供剛性及易於處理。所得的電子封裝32(具有或不具有封裝劑132)然後可視需要被清潔、檢查及單切(singulated)。
第19和20圖分別示出根據第2-15圖之製造/堆疊製程製造的電子封裝之底和上視圖，且在短路棒114、116、118、焊錫遮罩100、焊錫層104、封裝劑132的應用之前。在第19圖之底或背側視圖，各種晶粒68、70、72、被動組件108、110、金屬化接觸層48及金屬互連56的示範性配置形成在介電質層34上。第20圖之上 或前視圖示出了形成在介電質層64上的金屬化互連92之相應的示範性配置。
如第19圖所示，金屬接觸層48被圖案化而在上介電質層34上建立佈線層以電性連接各種電性組件。例如，金屬接觸層48之部分51a在被動組件108a、108b和108c之間形成電性連接。金屬接觸層48之位置包括金屬塗料90形成至其中主動和被動組件使用焊錫耦接之接觸位置。因此，金屬接觸層48提供作為佈線層及作為用於電性組件附著之可焊接接觸層的雙重功能。
此外，相關於上面敘述之製造或堆疊技術的製程或方法步驟之順序和序列可以根據替代實施例變化。作為一非限制範例，可焊接金屬塗料90可被應用於下面的焊錫遮罩100。
可以預期的是金屬化接觸層48和/或金屬化孔56之上層的厚度可基於設計規格變化。例如，金屬化接觸層48及金屬化孔56之上層等兩者中之一或二者可被設計具有增加的厚度，以應付高電流應用。現在參考第21圖，功能性網路組件134根據本發明另一實施例示出。功能性網路組件134及功能性網路組件96(第15圖)擁有數個共同組件。功能性網路組件134及功能性網路組件96共同的元件和組件將相對以適當的相同元件編號進行討論。
如圖所示，功能性網路組件134包括具有形成穿過其厚度138之晶粒開口58的上介電質層136。金 屬化接觸140以相似於在上介電質層136的頂表面142上之金屬化接觸層48(第5圖)的方式形成。金屬化孔144之上層形成在上介電質層136之底表面146且延伸穿過被形成穿過上介電質層136的孔148，相似於金屬化孔56(第8圖)之上層。第二功能性網路組件94透過黏著層62耦接至上介電質層136。複數個晶粒150被定位在功能性網路組件134之相應的晶粒開口58。
上介電質層136之厚度138大於功能性網路組件96之上介電質層34的厚度。在一實施例中，如第21圖所示，上介電質層136和金屬化孔144之上層的結合厚度152大致等於晶粒150之厚度154。另外，上介電質層136可被提供具有厚度約等於晶粒150之厚度154。
上焊錫遮罩156及下焊錫遮罩158形成在功能性網路組件134各自的上和下表面160、162以允許上和下焊錫層164、166的形成。如圖所示，所得電子封裝168允許球柵陣列(BGA)附著到電子封裝168的兩側。此外，所得電子封裝168具有其允許多個電子封裝或模組堆疊之大致平面的結構。在第21圖所示之實施例中，金屬化接觸140被製造為功能性網路組件134之一部分且被製造在晶粒150置放之前。
現在參考第22-27圖，結合功能性網路組件172之用於製造電子封裝170之技術已根據本發明替代實施例被敘述。第22-27圖示出了在堆疊製程之各種步驟期間電子封裝170和/或功能性網路組件172之剖面視圖。 作為功能性網路組件172和功能性網路組件96(第15圖)擁有數個共同組件，這些共同組件將相對以適當的相同元件編號進行討論。
首先參考第22圖，根據各種具有或不具有晶種金屬層的實施例，上金屬化層174形成在上介電質層34之頂表面40。另外，上金屬化層174可在附著至框36之前被提供作為應用於上介電質層34之金屬批覆。如第23圖所示，此層174接著被圖案化及蝕刻以形成複數個金屬互連176。在以相對於第6圖所敘述之相似方式形成孔50之後，金屬化孔56之上層以相對於第7、8圖所敘述之相似方式形成在上介電質層34之底表面54上。在一替代實施例中孔50可在電鍍金屬在介電質層34之上和下表面之前形成。晶粒開口58接著形成穿過上介電質層34之厚度。所得第一級功能性網路組件178包括上介電質層34、複數個金屬互連176、金屬化孔56之上層及晶粒開口58。
如第24圖所示，下介電質層64接著使用黏著層62以相對於第10圖所敘述之方式耦接至第一級功能性網路組件178且一或多個晶粒180、182、184定位在晶粒開口中58。如圖所示，晶粒180、182、184具有厚度186大致等於上介電質層34之厚度188，使得上介電質層34之頂表面40及晶粒180、182、184之非主動表面190大致共平面。
如第25圖所示，金屬化孔或金屬化互連92 之第二層接著形成穿過下介電質層64及黏著層62。如圖所示，焊錫遮罩100可接著應用於下介電質層64之底表面86及金屬化孔92之下層。接著，如第26圖所示，金屬接觸層192形成在上介電質層34之頂表面40上且橫過晶粒180、182、184之非主動表面190。而在上面描述為分開步驟的金屬接觸層192及金屬化互連92，可以預期的是所述兩層92、192在一替代實施例中可以同時被沉積。
如第27圖所示，金屬接觸層192然後被圖案化及蝕刻以形成複數個金屬接觸互連194。金屬接觸互連194的功能相似於第17圖之藉由形成在晶粒180、182、184的非主動表面和金屬化孔56的上層之間的電性連接之短路棒114、116、118。
上焊錫遮罩156可接著接續上焊錫層164及下焊錫層166之形成後被形成在上介電質層34之頂表面40及部分的複數個金屬接觸互連194上。如果需要，所得電子封裝170然後可被清潔、檢查及單切。
因此，本發明實施例包括互連組件，在本文中稱為功能性網路組件，可以合併到電子封裝內以允許從多個晶粒和其它電性組件的輸入/輸出。
有利地，本發明實施例因此提供其中包括嵌入式晶粒及其它電性組件之電子封裝。提供在電子封裝中的功能性網路組件被製造以提供在電子封裝中之電性組件之頂和底表面之間所需電性互連，從而省去了在封裝中笨 重的多層PCB的需求。藉由在功能性網路組件中提供電性互連，電子封裝之整體體積可以減少約35%的同時相較於結合多層PCB之電子封裝增加了功率密度約50%。
另外，各種在功能性網路組件中的材料層之厚度可變化以容納各種晶粒尺寸及不同晶粒和電性組件之組合，同時最小化電子封裝整體厚度。
此外，因為功能性網路組件可以預先製造，互連在被結合至電子封裝內之前可以被測試，從而改善最終組裝之電子封裝的產量。
因此，根據本發明一實施例，一種電子封裝，包括具有形成穿過本身厚度之第一複數個孔的第一介電質基板，耦接至該第一介電質基板之頂表面之金屬化接觸層，以及定位在形成穿過該第一介電質基板之該厚度的第一晶粒開口中之第一晶粒。第一複數個金屬化互連，其形成在該第一介電質基板之底表面上且延伸穿過該些第一複數個孔以接觸該金屬化接觸層的至少一部份。第二介電質基板之頂表面耦接至該第一介電質基板之底表面的，該第二介電質基板具有形成穿過其厚度之第二複數個孔。第二複數個金屬化互連，其形成在該第二介電質基板之底表面上且延伸穿過該些第二複數個孔以接觸該些第一複數個金屬化互連及該第一晶粒之接觸墊。第一導電元件，其電性耦接該第一晶粒至該金屬化接觸層。
根據本發明另一實施例，一種製造電子封裝的方法，該方法包含：提供第一介電質層，在該第一介電 質層之第一表面上形成金屬化接觸層，以及在該第一介電質層之相對於該第一表面之第二表面上形成第一複數個金屬化孔。該些第一複數個金屬化孔延伸穿過該第一介電質層之厚度以接觸該些複數個金屬化接觸層的至少一部分。該方法也包括形成穿過該第一介電質層之該厚度的第一電性組件開口，耦接第二介電質層之該第一介電質層之該第二表面，以及定位第一電性組件在該第一電性組件開口中。在該第二介電質層之底表面上形成第二複數個金屬化孔，該第二複數個金屬化孔延伸穿過該第二介電質層之厚度以耦接該金屬化接觸層至該第一電性組件。此外，該方法包括耦接第一導電組件在該第一電性組件及該金屬化接觸層之間。
根據本發明又一實施例，一種電子封裝包含功能性網路組件，其具有耦接至第一介電質層之金屬化接觸層，其中該金屬化接觸層之底表面大致與該第一介電質層之頂表面共平面。該功能性網路組件也包括設置在該第一介電質層之底表面且延伸穿過形成在該第一介電質層內的孔以與該金屬化接觸層電性連接的第一複數個金屬互連，以黏著劑耦接至該第一介電質層的第二介電質層，以及設置在該第二介電質層之底表面且延伸穿過形成在該第二介電質層內的孔以與該些第一複數個金屬互連的至少一部分電性連接的第二複數個金屬互連。定位在形成穿過該第一介電質層之第一開口中且具有耦接至該黏著劑及該些第一複數個金屬互連之至少一金屬互連的第一表面的第一 晶粒。電性連接該金屬化接觸層之部分及該第一晶粒之相對於該第一表面的第二表面的第一金屬橋。
儘管本發明已僅以有限數量之實施例詳細敘述，但應當可理解的是本發明不限制於這些揭露的實施例。相反地，本發明可以以任何數目的變化、變更、替換或前面沒有描述的等效配置被修改，但其需與本發明的精神和範圍相稱。另外，儘管本發明的各種實施例已經敘述，但應當可理解本發明的方面可僅包括一些所敘述的實施例。因此，本發明不應該受前面描述的限制，而僅由所附之申請專利範圍所限制。

Claims (15)

  1. 一種電子封裝，包含：第一介電質基板，具有形成穿過其厚度之第一複數個孔；金屬化接觸層，其耦接至該第一介電質基板之頂表面；第一晶粒，其定位在形成於穿過該第一介電質基板之該厚度的第一晶粒開口中；第一複數個金屬化互連，其形成在該第一介電質基板之底表面上且延伸穿過該第一複數個孔以接觸該金屬化接觸層的至少一部份；第二介電質基板，其具有耦接至該第一介電質基板之底表面的頂表面，該第二介電質基板具有形成穿過其厚度之第二複數個孔；第二複數個金屬化互連，其形成在該第二介電質基板之底表面上且延伸穿過該第二複數個孔以接觸該第一複數個金屬化互連及該第一晶粒之接觸墊；以及第一導電元件，其電性耦接該第一晶粒至該金屬化接觸層，該第一導電元件包含耦接至該金屬化接觸層之金屬接觸墊的第一表面及耦接至第一晶粒的第二表面，其中該第一導電元件的該第一表面和該第二表面非共平面。
  2. 如申請專利範圍第1項所述之電子封裝，其中該金屬化接觸層包含複數個金屬接觸墊及跡線。
  3. 如申請專利範圍第2項所述之電子封裝，其中該第一導電元件電性耦接該第一晶粒至該金屬化接觸層之金屬接觸墊。
  4. 如申請專利範圍第1項所述之電子封裝，更包含：第二晶粒，其定位在形成於穿過該第一介電質基板之該厚度的第二晶粒開口中；以及第二導電元件，其電性耦接該第二晶粒至該金屬化接觸層。
  5. 如申請專利範圍第4項所述之電子封裝，其中該第二晶粒具有厚度大於該第一晶粒之厚度。
  6. 如申請專利範圍第5項所述之電子封裝，其中該第二導電元件包含耦接至該金屬化接觸層之第一部份以及耦接至該第二晶粒之第二部分；以及其中該第一部份具有厚度大於該第二部分之厚度。
  7. 如申請專利範圍第4項所述之電子封裝，其中該第二晶粒具有厚度大致等於該第一晶粒之厚度。
  8. 如申請專利範圍第1項所述之電子封裝，其中該第一介電質基板之該厚度大致等於該第一晶粒之厚度。
  9. 如申請專利範圍第1項所述之電子封裝，更包含耦接至該金屬化接觸層之一對金屬接觸墊的組件。
  10. 一種製造電子封裝的方法，該方法包含：提供第一介電質層；在該第一介電質層之第一表面上形成金屬化接觸層；在該第一介電質層之相對於該第一表面之第二表面上形成第一複數個金屬化孔，該第一複數個金屬化孔延伸穿過該第一介電質層之厚度以接觸該複數個金屬化接觸層的至少一部分；形成穿過該第一介電質層之該厚度的第一電性組件開口；耦接第二介電質層至該第一介電質層之該第二表面；定位第一電性組件在該第一電性組件開口中；在該第二介電質層之底表面上形成第二複數個金屬化孔，該第二複數個金屬化孔延伸穿過該第二介電質層之厚度以耦接該金屬化接觸層至該第一電性組件；以及耦接第一導電組件在該第一電性組件及該金屬化接觸層之間。
  11. 如申請專利範圍第10項所述之方法，更包含耦接該第一電性組件至該金屬化接觸層之金屬接觸墊。
  12. 如申請專利範圍第10項所述之方法，更包含：形成第二電性組件開口穿過第一介電質層之該厚度；定位第二電性組件在該第二電性組件開口中；以及耦接第二導電元件在該第二電性組件和該金屬化接觸層之間。
  13. 如申請專利範圍第12項所述之方法，更包含：耦接該第一導電元件之第一表面至該第一電性組件；耦接該第一導電元件之第二表面至該第一金屬接觸墊；以及其中該第一導電元件之該第一和第二表面非共平面。
  14. 如申請專利範圍第12項所述之方法，更包含：以具有第一厚度之第一焊錫層耦接該金屬化接觸層至該第一導電元件；以及以具有不同於該第一厚度之第二厚度的第二焊錫層耦接該金屬化接觸層至該第二導電元件。
  15. 如申請專利範圍第10項所述之方法，更包含以封裝劑封裝該第一電性組件及該金屬化接觸層。
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