TWI663756B - 晶圓接合互連結構及其製作方法 - Google Patents

晶圓接合互連結構及其製作方法 Download PDF

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TWI663756B
TWI663756B TW106113593A TW106113593A TWI663756B TW I663756 B TWI663756 B TW I663756B TW 106113593 A TW106113593 A TW 106113593A TW 106113593 A TW106113593 A TW 106113593A TW I663756 B TWI663756 B TW I663756B
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盧克 英格蘭
拉華爾 阿格瓦
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格羅方德半導體公司
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Abstract

本揭示內容係有關於半導體結構，且更特別的是，有關於晶圓接合互連結構及其製法。該結構包括：各自包含一接觸板的複數個子像素；以及在該接觸板之一背面上位於各子像素之相對角落的冗餘連接。

Description

晶圓接合互連結構及其製作方法
本揭示內容係有關於半導體結構，且更特別的是，有關於晶圓接合互連結構及製法。
無機發光二極體(ILED)為由半導體材料製成的發光二極體。有可能使用ILED產生各種不同色彩，包括紅、綠、黃及藍色。操作時，ILED在施加順向偏壓至半導體材料的P-N接面時發光。
4k ILED顯示系統由堆疊在控制晶粒上的LED晶粒構成。該4K ILED顯示器在晶粒之間需要間距在5微米以下的64密耳互連。在4k顯示像素陣列中，每個子像素都需要個別互連。不過，在這些尺寸很難得到高互連良率。
在本揭示內容之一方面，一種結構，包含：各自包含一接觸板的複數個子像素；以及在該接觸板之一背面上位於各子像素之相對角落的冗餘連接。
在本揭示內容之一方面，一種像素結構，包含：各自包含一接觸板的複數個子像素；以及在該接觸板之一背面上位於兩個相對角落且與在各子像素之該兩個相對角落之間延伸的一對角線“d”相交的接合墊結構。
在本揭示內容之一方面，一種方法，包含：在複數個子像素之一接觸板之一背面上的兩個相對角落形成接合墊結構，該接合墊結構與在各子像素之該兩個相對角落之間延伸的一對角線“d”相交。
10‧‧‧像素、結構、ILED驅動器晶圓
12‧‧‧接觸板、電極
14a-14d‧‧‧子像素
16‧‧‧奈米線
18‧‧‧接合墊結構
20‧‧‧子像素邊界
22‧‧‧像素邊界
24‧‧‧絕緣體材料、氧化物材料
30‧‧‧CMOS驅動器晶圓
40‧‧‧接合介面
50‧‧‧接合墊
b‧‧‧假想方盒
c‧‧‧中心點
c1‧‧‧角落
d‧‧‧對角線
x‧‧‧長度
A、B、C‧‧‧直線
以下說明詳述本揭示內容，其中參考多個附圖以不具限定性的方式舉例說明本揭示內容的示範具體實施例。
第1圖根據本揭示內容之數個方面圖示一像素設計。
第2A圖根據本揭示內容之數個方面圖示第1圖結構的背面及各個製程。
第2B圖根據本揭示內容之數個方面圖示第1圖結構的替代背面及各個製程。
第3圖根據本揭示內容之數個方面圖示一最佳接合墊佈置。
第4圖根據本揭示內容之數個方面圖示在ILED驅動器晶圓與CMOS驅動器晶圓之間的晶圓至晶圓連接。
本揭示內容係有關於半導體結構，且更特別的是，有關於晶圓互連結構及其製法。更特別的是，本 揭示內容有關於用於無機發光二極體(ILED)之晶圓接合墊結構的佈局圖案及其製法。在數個具體實施例中，該佈局圖案也可應用於任何可重複設計結構，例如記憶格陣列等等。有利的是，在特定佈局圖案中提供例如互連結構的晶圓接合墊結構，其提供互連冗餘同時維持高良率接合所需的大間距。此外，藉由實作描述於本文的佈局圖案，可在整個晶圓上以均勻的像素間距重複該接合墊圖案，同時也隨著像素大小及接合技術改善而縮放比例。
在數個具體實施例中，在特定互連佈局中提供該等晶圓接合墊結構，在此設計每個子像素有兩個冗餘接合墊(例如，互連)，以及冗餘連接駐留在子像素接觸板之背面的相對角落。再者，該特定佈局圖案不會違反子像素之間的最小可製造間距規則，同時也最大化用於晶圓接合技術的氧化物表面積。
可用使用許多不同工具的許多方法製造本揭示內容的晶圓接合墊結構。然而，通常該等方法及工具用來形成有微米及奈米級尺寸的結構。用來製造本揭示內容之晶圓接合墊結構的該等方法(即技術)係選自積體電路(IC)技術。例如，該等結構建立於晶圓上以及實現於在晶圓上面用光微影製程(photolithographic process)圖案化的材料膜中。特別是，該等晶圓接合墊結構的製造使用以下3個基本建造區塊：(i)沉積數個材料薄膜於基板上，(ii)用光微影成像法施加圖案化遮罩於薄膜上面，以及(iii)對於該遮罩選擇性地蝕刻薄膜。
第1圖根據本揭示內容之數個方面圖示一像素設計。本領域技術人員應瞭解，第1圖(及描述於本文的其他附圖)也可為用於例如記憶格陣列等等的任何可重複設計結構之佈局圖案。在第1圖中，像素10包含有4個子像素14a-14d的接觸板或電極12。在數個具體實施例中，該接觸板或電極12可為奈米線接觸與由例如金屬之不透光材料構成的反射板，例如，以最大化子像素14a-14d的發射光線。在數個具體實施例中，像素10有6.35微米×6.35微米的尺寸以及子像素14a-14d有3.175微米×3.175微米的尺寸；然而本文也設想其他尺寸。
仍參考第1圖，在一圖示實施例中，子像素14a-14d包含使用於無機發光二極體(ILED)的RGB像素設計。例如，各個子像素14a-14d可具有由不同材料構成、個數不同的奈米線16以發射某一色彩，例如，波長。以非限定性實施例說明，(i)子像素14a、14d的4條奈米線16可用於綠光(ii)子像素14b的9條奈米線16可用於藍光，以及(iii)子像素14c的4條奈米線16可用於紅光。儘管子像素14d圖示成為子像素14a的冗餘，然而應瞭解，子像素14d可為子像素14a-14c中之任一者的冗餘。替換地，子像素14d可空白，例如，沒有任何奈米線。
儘管對於本揭示內容的了解不重要，然而奈米線16可由不同材料構成以便提供不同的波長。例如，表1圖示可用於奈米線之半導體材料的示範組合。
第2A圖根據本揭示內容之數個方面圖示第1圖結構的背面及各個製程。如第2A圖所示，接合墊結構18(例如，互連)位在各子像素14a-14d的兩個相對角落。更特別的是，在圖示於第2A圖的具體實施例中，接合墊結構18會位於接觸板12背面在各子像素14a-14d的左下角及右上角上。可在整個晶圓上以均勻的像素間距重複此圖案。此外，接合墊結構18的各個集合會限制在子像素邊界20內而且子像素14a-14d會以像素邊界22為界。
在數個具體實施例中，製作接合墊結構18的尺寸會基於接合墊材料(例如，銅)與絕緣體材料(例如，氧化物材料24)的最佳比例。用一實施例說明，接合墊結 構18用於各子像素14a-14d的材料(例如，銅)最好約為或低於總表面積的30%，藉此最大化氧化物對氧化物接合(oxide to oxide bonding)。有利的是，儘管接合墊結構18的表面積已倍增，例如，兩個接合墊結構相較於習知設計的單一接合墊結構，使用此面積比配置因而會確保在ILED驅動器晶圓與CMOS驅動器晶圓之間有適當的氧化物對氧化物接合。
絕緣體材料24可為接觸板12背面上由習知沉積製程(例如，化學氣相沉積(CVD)製程)形成的任何氧化物材料，例如，二氧化矽。接合墊結構18(例如，互連)可用習知加成或減成法形成。例如，在加成法中，絕緣體材料24會沉積到某一厚度，通常使用習知化學氣相沉積(CVD)製程。在氧化物沉積後，使形成於絕緣體材料24上面的抗蝕劑暴露於能量(光線)以形成圖案(開口)。用選擇性化學物的蝕刻製程，例如，反應性離子蝕刻(RIE)，會通過抗蝕劑的開口用來在絕緣體材料24中形成一或更多溝槽。然後，抗蝕劑可用習知氧氣灰化法(oxygen ashing process)或其他習知去膜劑(stripant)移除。在移除抗蝕劑後，可用任何習知沉積製程(例如，CVD製程)沉積導電材料(例如，銅)以形成接合墊結構18。絕緣體材料表面上的任何殘餘材料可用習知化學機械研磨(CMP)製程移除。
第2B圖根據本揭示內容之數個方面圖示接合墊結構18的替代背面配置。與第2A圖所述說明類似，如第2B圖所示，接合墊結構18(例如，互連)位在各子像素 14a-14d的兩個相對角落。然而，在此配置中，接合墊結構18會位於在接觸板12背面上之各子像素14a-14d的左上角及右下角中。此外，在此配置中，接合墊結構18可具有在所有方向維持在適當位置之冗餘的間距。也可在整個晶圓上以均勻的像素間距重覆此圖案。此外，接合墊結構18的各個集合會限制在子像素邊界20內而且子像素14a-14d會以像素邊界22為界。
在圖示於第2A圖及第2B圖的配置中，接合墊結構18可具有在所有方向維持在適當位置之冗餘的間距。再者，這些佈局提供優於單一大墊間距的優點，因為此一大墊間距不提供任何冗餘。此外，已發現，冗餘方案佈局(例如，每子像素兩個以上的接合墊結構)導致太小的墊間距，接著，減少良率接合。亦即，使用太小的墊間距會無法維持高良率接合。而且，兩個以上的連接可能違反子像素之間的最小間距規則。
第3圖根據本揭示內容之數個方面圖示最佳接合墊佈置。更特別的是，接合墊結構18(例如，互連)的佈置可用簡單幾何規則界定用於使彼等在子像素對角線內及之間有相等間距。例如，如第3圖所示，該等接合墊結構18設在各子像素14a-14d的兩個相對角落，彼等與從子像素之相對對角角落以45度延伸的對角線“d”相交。應注意，子像素的每一邊有“x”的長度，每個接合墊結構18的中心點“c”會位在邊長為x/4及對角線長為d/4之假想方盒“b”的角落“c1”上。
藉由佈置子像素14a-14d於第2A圖或第2B圖及第3圖的配置中，在各個子像素14a-14d之中的各個接合墊結構18會沿著各自的對角線等距隔開。此對角線例如可為圖示於第2A圖與第2B圖的直線“A”、“B”或“C”。而且，藉由等距隔開，接合墊結構18會儘可能遠地互相隔開。此配置會提供接合墊結構的必要冗餘以最大化在ILED驅動器晶圓與CMOS驅動器晶圓之間用於連接的接觸面積，同時最大化高良率接合。
第4圖根據本揭示內容之數個方面圖示在ILED驅動器晶圓及CMOS驅動器晶圓之間的晶圓至晶圓連接。更特別的是，第4圖圖示用氧化物對氧化物接合技術接合至CMOS驅動器晶圓30的結構10，例如，ILED驅動器晶圓，如接合介面40所示。提供在橫截面圖中有子像素14a-14b的ILED驅動器晶圓10。子像素14a-14b用接合墊結構18連接至CMOS驅動器晶圓30的接合墊50。
上述該(等)方法係使用於積體電路晶片的製造。所得積體電路晶片可由製造者以原始晶圓形式(raw wafer form)(也就是具有多個未封裝晶片的單一晶圓)、作為裸晶粒(bare die)或已封裝的形式來銷售。在後一情形下，晶片裝在單晶片封裝體中(例如，塑膠載體(plastic carrier)，具有固定至主機板或其他更高層載體的引腳(lead))，或多晶片封裝體中(例如，具有表面互連件(surface interconnection)或內嵌互連件(buried interconnection)任一或兩者兼具的陶瓷載體)。然後，在任一情形下，晶片與其他晶片、離散電 路元件及/或其他信號處理裝置整合成為(a)中間產品(例如，主機板)，或(b)最終產品中之任一者的一部分。該最終產品可為包括積體電路晶片的任何產品，從玩具及其他低端應用到有顯示器、鍵盤或其他輸入裝置及中央處理器的先進電腦產品不等。
為了圖解說明已呈現本揭示內容之各種具體實施例的描述，但是並非旨在窮盡或限定於所揭示的具體實施例。本領域技術人員明白仍有許多修改及變體而不脫離所述具體實施例的範疇及精神。使用於本文的術語經選定成可最好地解釋具體實施例的原理、實際應用或優於在市場上可找到之技術的技術改善，或使得本領域技術人員能夠了解揭示於本文的具體實施例。

Claims (19)

  1. 一種半導體結構，包含：各自包含一接觸板的複數個子像素；以及在該接觸板之一背面上位於各子像素之相對角落的冗餘連接，其中，該子像素的每一邊有“x”的長度，對角線“d”以及各子像素之背面上的各接合墊結構的中心點“c”位在一假想方盒“b”的一角落“c1”上，該假想方盒“b”位在該子像素的相對對角角落上，具有邊長為x/4且對角線長為d/4，以使得各接合墊結構將沿著該子像素的對角線彼此等距隔開。
  2. 如申請專利範圍第1項所述之半導體結構，其中，該冗餘連接為每一子像素的兩個接合墊結構。
  3. 如申請專利範圍第2項所述之半導體結構，其中，在整個晶圓上以均勻的像素間距重複該冗餘連接。
  4. 如申請專利範圍第1項所述之半導體結構，其中，該冗餘連接包括在該接觸板之該背面上位於各子像素之左下角及右上角處的一接合墊結構。
  5. 如申請專利範圍第1項所述之半導體結構，其中，該冗餘連接包括在該接觸板之該背面上位於各子像素之左上角及右下角處的一接合墊結構。
  6. 如申請專利範圍第1項所述之半導體結構，其中，該冗餘連接為設在各子像素之兩個相對角落的接合墊結構，該接合墊結構與從該各子像素之相對角落以45度延伸的一對角線“d”相交。
  7. 如申請專利範圍第1項所述之半導體結構，其中，各接合墊結構沿著多個子像素的單一對角線等距隔開。
  8. 如申請專利範圍第1項所述之半導體結構，更包含在該接觸板之該背面上的氧化物材料，其中，該接合墊結構的表面積約為該接觸板之該背面之總表面積的30%或更少。
  9. 一種半導體結構，包含：各自包含一接觸板的複數個子像素；在該接觸板之一背面上位於各子像素之相對角落的冗餘連接；以及在該接觸板之該背面上的氧化物材料，其中，該子像素的每一邊有“x”的長度，以及各接合墊結構的中心點“c”位在邊長為x/4及對角線長為d/4之一假想方盒”b”的一角落“c1”上，其中，該接合墊結構的表面積約為該接觸板之該背面的總表面積的30%或更少，以及其中，該複數個子像素形成一無機發光二極體(ILED)驅動器晶圓的一像素，以及該ILED驅動器晶圓接合至一CMOS驅動器晶圓是透過該CMOS驅動器晶圓之氧化物材料與該氧化物材料的一氧化物對氧化物接合。
  10. 一種像素結構，包含：各自包含一接觸板的複數個子像素，其中，該複數個子像素形成一無機發光二極體(ILED)驅動器晶圓的一像素；以及在該接觸板之一背面上位於兩個相對角落且與在各子像素之該兩個相對角落之間延伸的一對角線“d”相交的接合墊結構。
  11. 如申請專利範圍第10項所述之像素結構，其中，該接合墊結構中之第一者在該接觸板之該背面上位於各子像素的左下角，以及該接合墊結構中之第二者位在各子像素的右上角。
  12. 如申請專利範圍第10項所述之像素結構，其中，該接合墊結構中之第一者在該接觸板之該背面上位於各子像素的左上角，以及該接合墊結構中之第二者位在各子像素的右下角。
  13. 如申請專利範圍第10項所述之像素結構，其中，該對角線“d”從該各子像素之相對角落以45度延伸。
  14. 如申請專利範圍第13項所述之像素結構，其中，該子像素的每一邊有“x”的長度，以及各接合墊結構的中心點“c”位在邊長為x/4及對角線長為d/4之一假想方盒”b”的一角落“c1”上。
  15. 如申請專利範圍第14項所述之像素結構，其中，各接合墊結構沿著多個子像素的單一對角線等距隔開。
  16. 如申請專利範圍第10項所述之像素結構，其中，該接合墊結構的表面積約為該接觸板之該背面之總表面積的30%或更少。
  17. 如申請專利範圍第16項所述之像素結構，更包含在該接觸板之該背面上的氧化物材料。
  18. 如申請專利範圍第17項所述之像素結構，其中，該ILED驅動器晶圓接合至一CMOS驅動器晶圓是透過該CMOS驅動器晶圓之氧化物材料與該氧化物材料的一氧化物對氧化物接合。
  19. 一種製作半導體結構的方法，包含：在複數個子像素之一接觸板之一背面上的兩個相對角落形成接合墊結構，該接合墊結構與在各子像素之該兩個相對角落之間延伸的一對角線“d”相交，其中，該複數個子像素形成一無機發光二極體(ILED)驅動器晶圓的一像素。
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