CN108231792A - 芯片键合互连结构 - Google Patents

芯片键合互连结构 Download PDF

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CN108231792A
CN108231792A CN201711354226.1A CN201711354226A CN108231792A CN 108231792 A CN108231792 A CN 108231792A CN 201711354226 A CN201711354226 A CN 201711354226A CN 108231792 A CN108231792 A CN 108231792A
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bonding
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CN108231792B (zh
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卢克·英格兰
拉华尔·阿格瓦
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GlobalFoundries US Inc
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GlobalFoundries Inc
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Abstract

本发明揭示芯片键合互连结构，其涉及半导体结构，且尤其涉及芯片键合互连结构及其制法。该结构包括：各自包含一接触板的多个子像素；以及在该接触板的一背面上位于各子像素的相对角落的冗余连接。

Description

芯片键合互连结构
技术领域
本揭示内容涉及半导体结构，且尤其涉及芯片键合互连结构及制法。
背景技术
无机发光二极管(ILED)为由半导体材料制成的发光二极管。有可能使用ILED产生各种不同色彩，包括红、绿、黄及蓝色。操作时，ILED在施加顺向偏压至半导体材料的P-N接面时发光。
4k ILED显示系统由堆栈在控制管芯上的LED管芯构成。该4K ILED显示器在管芯之间需要间距在5微米以下的64密耳互连。在4k显示像素数组中，每个子像素都需要个别互连。不过，在这些尺寸很难得到高互连良率。
发明内容
在本揭示内容之一方面，一种结构，包含：各自包含一接触板的多个子像素；以及在该接触板之一背面上位于各子像素之相对角落的冗余连接。
在本揭示内容之一方面，一种像素结构，包含：各自包含一接触板的多个子像素；以及在该接触板之一背面上位于两个相对角落且与在各子像素之该两个相对角落之间延伸的一对角线“d”相交的键合垫结构。
在本揭示内容之一方面，一种方法，包含：在多个子像素之一接触板之一背面上的两个相对角落形成键合垫结构，该键合垫结构与在各子像素之该两个相对角落之间延伸的一对角线“d”相交。
附图说明
以下说明详述本揭示内容，其中参考多个附图以不具限定性的方式举例说明本揭示内容的示范具体实施例。
图1根据本揭示内容之数个方面图示一像素设计。
图2A根据本揭示内容之数个方面图标图1结构的背面及各个制程。
图2B根据本揭示内容之数个方面图标图1结构的替代背面及各个制程。
图3根据本揭示内容之数个方面图示一最佳键合垫布置。
图4根据本揭示内容之数个方面图标在ILED驱动器芯片与CMOS驱动器芯片之间的芯片至芯片连接。
主要组件符号说明
10 像素、结构、ILED驱动器芯片
12 接触板、电极
14a-14d 子像素
16 纳米线
18 键合垫结构
20 子像素边界
22 像素边界
24 绝缘体材料、氧化物材料
30 CMOS驱动器芯片
40 键合接口
50 键合垫
A、B、C 直线
b 假想方盒
c 中心点
c1 角落
d 对角线
x 长度。
具体实施方式
本揭示内容涉及半导体结构，且尤其涉及芯片互连结构及其制法。更特别的是，本揭示内容涉及用于无机发光二极管(ILED)之芯片键合垫结构的布局图案及其制法。在数个具体实施例中，该布局图案也可应用于任何可重复设计结构，例如存储单元组等等。有利的是，在特定布局图案中提供例如互连结构的芯片键合垫结构，其提供互连冗余同时维持高良率键合所需的大间距。此外，藉由实作描述于本文的布局图案，可在整个芯片上以均匀的像素间距重复该键合垫图案，同时也随着像素大小及键合技术改善而缩放比例。
在数个具体实施例中，在特定互连布局中提供该等芯片键合垫结构，在此设计每个子像素有两个冗余键合垫(例如，互连)，以及冗余连接驻留在子像素接触板之背面的相对角落。再者，该特定布局图案不会违反子像素之间的最小可制造间距规则，同时也最大化用于芯片键合技术的氧化物表面积。
可用使用许多不同工具的许多方法制造本揭示内容的芯片键合垫结构。然而，通常该等方法及工具用来形成有微米及奈米级尺寸的结构。用来制造本揭示内容之芯片键合垫结构的该等方法(即技术)系选自集成电路(IC)技术。例如，该等结构建立于芯片上以及实现于在芯片上面用光刻制程(photolithographic process)图案化的材料膜中。特别是，该等芯片键合垫结构的制造使用以下3个基本建造区块：(i)沉积数个材料薄膜于基板上，(i i)用光刻成像法施加图案化掩模于薄膜上面，以及(iii)对于该掩模选择性地刻蚀薄膜。
图1根据本揭示内容之数个方面图示一像素设计。本领域技术人员应了解，图1(及描述于本文的其他附图)也可为用于例如存储单元数组等等的任何可重复设计结构之布局图案。在图1中，像素10包含有4个子像素14a-14d的接触板或电极12。在数个具体实施例中，该接触板或电极12可为纳米线接触与由例如金属之不透光材料构成的反射板，例如，以最大化子像素14a-14d的发射光线。在数个具体实施例中，像素10有6.35微米×6.35微米的尺寸以及子像素14a-14d有3.175微米×3.175微米的尺寸；然而本文也设想其他尺寸。
仍参考图1，在一图示实施例中，子像素14a-14d包含使用于无机发光二极管(ILED)的RGB像素设计。例如，各个子像素14a-14d可具有由不同材料构成、个数不同的纳米线16以发射某一色彩，例如，波长。以非限定性实施例说明，(i)子像素14a、14d的4条纳米线16b可用于绿光(i i)子像素14b的9条纳米线16可用于蓝光，以及(i ii)子像素14c的4条纳米线16可用于红光。尽管子像素14d图示成为子像素14a的冗余，然而应了解，子像素14d可为子像素14a-14c中之任一者的冗余。替换地，子像素14d可空白，例如，没有任何纳米线。
尽管对于本揭示内容的了解不重要，然而纳米线16可由不同材料构成以便提供不同的波长。例如，表1图示可用于纳米线之半导体材料的示范组合。
表1
图2A根据本揭示内容之数个方面图标图1结构的背面及各个制程。如图2A所示，键合垫结构18(例如，互连)位在各子像素14a-14d的两个相对角落。更特别的是，在图示于图2A的具体实施例中，键合垫结构18会位于接触板12背面在各子像素14a-14d的左下角及右上角上。可在整个芯片上以均匀的像素间距重复此图案。此外，键合垫结构18的各个集合会限制在子像素边界20内而且子像素14a-14d会以像素边界22为界。
在数个具体实施例中，制作键合垫结构18的尺寸会基于键合垫材料(例如，铜)与绝缘体材料(例如，氧化物材料24)的最佳比例。用一实施例说明，键合垫结构18用于各子像素14a-14d的材料(例如，铜)最好约为或低于总表面积的30％，藉此最大化氧化物对氧化物键合(oxide to oxide bonding)。有利的是，尽管键合垫结构18的表面积已倍增，例如，两个键合垫结构相较于习知设计的单一键合垫结构，使用此面积比配置因而会确保在ILED驱动器芯片与CMOS驱动器芯片之间有适当的氧化物对氧化物键合。
绝缘体材料24可为接触板12背面上由习知沉积制程(例如，化学气相沉积(CVD)制程)形成的任何氧化物材料，例如，二氧化硅。键合垫结构18(例如，互连)可用习知加成或减成法形成。例如，在加成法中，绝缘体材料24会沉积到某一厚度，通常使用习知化学气相沉积(CVD)制程。在氧化物沉积后，使形成于绝缘体材料24上面的抗蚀剂暴露于能量(光线)以形成图案(开口)。用选择性化学物的刻蚀制程，例如，反应性离子刻蚀(RIE)，会通过抗蚀剂的开口用来在绝缘体材料24中形成一或更多沟槽。然后，抗蚀剂可用习知氧气灰化法(oxygen ashing process)或其他习知去膜剂(stripant)移除。在移除抗蚀剂后，可用任何习知沉积制程(例如，CVD制程)沉积导电材料(例如，铜)以形成键合垫结构18。绝缘体材料表面上的任何残余材料可用习知化学机械研磨(CMP)制程移除。
图2B根据本揭示内容之数个方面图标键合垫结构18的替代背面配置。与图2A所述说明类似，如图2B所示，键合垫结构18(例如，互连)位在各子像素14a-14d的两个相对角落。然而，在此配置中，键合垫结构18会位于在接触板12背面上之各子像素14a-14d的左上角及右下角中。此外，在此配置中，键合垫结构18可具有在所有方向维持在适当位置之冗余的间距。也可在整个芯片上以均匀的像素间距重复此图案。此外，键合垫结构18的各个集合会限制在子像素边界20内而且子像素14a-14d会以像素边界22为界。
在图示于图2A及图2B的配置中，键合垫结构18可具有在所有方向维持在适当位置之冗余的间距。再者，这些布局提供优于单一大垫间距的优点，因为此一大垫间距不提供任何冗余。此外，已发现，冗余方案布局(例如，每子像素两个以上的键合垫结构)导致太小的垫间距，接着，减少良率键合。亦即，使用太小的垫间距会无法维持高良率键合。而且，两个以上的连接可能违反子像素之间的最小间距规则。
图3根据本揭示内容之数个方面图示最佳键合垫布置。更特别的是，键合垫结构18(例如，互连)的布置可用简单几何规则界定用于使彼等在子像素对角线内及之间有相等间距。例如，如图3所示，该等键合垫结构18设在各子像素14a-14d的两个相对角落，彼等与从子像素之相对对角角落以45度延伸的对角线“d”相交。应注意，子像素的每一边有“x”的长度，每个键合垫结构18的中心点“c”会位在边长为x/4及对角线长为d/4之假想方盒“b”的角落“c1”上。
藉由布置子像素14a-14d于图2A或图2B及图3的配置中，在各个子像素14a-14d之中的各个键合垫结构18会沿着各自的对角线等距隔开。此对角线例如可为图示于图2A与图2B的直线“A”、“B”或“C”。而且，藉由等距隔开，键合垫结构18会尽可能远地互相隔开。此配置会提供键合垫结构的必要冗余以最大化在ILED驱动器芯片与CMOS驱动器芯片之间用于连接的接触面积，同时最大化高良率键合。
图4根据本揭示内容之数个方面图标在ILED驱动器芯片及CMOS驱动器芯片之间的芯片至芯片连接。更特别的是，图4图示用氧化物对氧化物键合技术键合至CMOS驱动器芯片30的结构10，例如，ILED驱动器芯片，如键合接口40所示。提供在横截面图中有子像素14a-14b的ILED驱动器芯片10。子像素14a-14b用键合垫结构18连接至CMOS驱动器芯片30的键合垫50。
上述该(等)方法系使用于集成电路芯片的制造。所得集成电路芯片可由制造者以原始芯片形式(raw wafer form)(也就是具有多个未封装芯片的单一芯片)、作为裸管芯(bare die)或已封装的形式来销售。在后一情形下，芯片装在单芯片封装体中(例如，塑料载体(plastic carrier)，具有固定至母板或其他更高层载体的引脚(lead))，或多芯片封装体中(例如，具有表面互连件(surface interconnection)或内嵌互连件(buriedinterconnection)任一或两者兼具的陶瓷载体)。然后，在任一情形下，芯片与其他芯片、分立电路组件及/或其他信号处理装置整合成为(a)中间产品(例如，母板)，或(b)最终产品中之任一者的一部分。该最终产品可为包括集成电路芯片的任何产品，从玩具及其他低端应用到有显示器、键盘或其他输入设备及中央处理器的先进计算机产品不等。
为了图解说明已呈现本揭示内容之各种具体实施例的描述，但是并非旨在穷尽或限定于所揭示的具体实施例。本领域技术人员明白仍有许多修改及变体而不脱离所述具体实施例的范畴及精神。使用于本文的术语经选定成可最好地解释具体实施例的原理、实际应用或优于在市场上可找到之技术的技术改善，或使得本领域技术人员能够了解揭示于本文的具体实施例。

Claims (20)

1.一种结构，包含：
各自包含一接触板的多个子像素；以及
在该接触板的一背面上位于各子像素的相对角落的冗余连接。
2.如权利要求1所述的结构，其特征在于，该冗余连接为每一子像素的两个键合垫结构。
3.如权利要求2所述的结构，其特征在于，在整个芯片上以均匀的像素间距重复该冗余连接。
4.如权利要求1所述的结构，其特征在于，该冗余连接包括在该接触板的该背面上位于各子像素的左下角及右上角处的一键合垫结构。
5.如权利要求1所述的结构，其特征在于，该冗余连接包括在该接触板的该背面上位于各子像素的左上角及右下角处的一键合垫结构。
6.如权利要求1所述的结构，其特征在于，该冗余连接为设在各子像素的两个相对角落的键合垫结构，该键合垫结构与从该各子像素的相对角落以45度延伸的一对角线“d”相交。
7.如权利要求6所述的结构，其特征在于，该子像素的每一边有“x”的长度，以及各键合垫结构的中心点“c”位在边长为x/4及对角线长为d/4的一假想方盒”b”的一角落“c1”上。
8.如权利要求7所述的结构，其特征在于，各键合垫结构沿着多个子像素的单一对角线等距隔开。
9.如权利要求7所述的结构，其特征在于，还包含在该接触板的该背面上的氧化物材料，其中，该键合垫结构的表面积约为该接触板的该背面的总表面积的30％或更少。
10.如权利要求9所述的结构，其特征在于，该多个子像素形成一ILED驱动器芯片的一像素，该ILED驱动器芯片键合至一CMOS驱动器芯片是透过该CMOS驱动器芯片的氧化物材料与该氧化物材料的一氧化物对氧化物键合。
11.一种像素结构，包含：
各自包含一接触板的多个子像素；以及
在该接触板的一背面上位于两个相对角落且与在各子像素的该两个相对角落之间延伸的一对角线“d”相交的键合垫结构。
12.如权利要求11所述的像素结构，其特征在于，该键合垫结构中的第一者在该接触板的该背面上位于各子像素的左下角，以及该键合垫结构中的第二者位在各子像素的右上角。
13.如权利要求11所述的像素结构，其特征在于，该键合垫结构中的第一者在该接触板的该背面上位于各子像素的左上角，以及该键合垫结构中的第二者位在各子像素的右下角。
14.如权利要求11所述的像素结构，其中，该对角线“d”从该各子像素的相对角落以45度延伸。
15.如权利要求14所述的像素结构，其特征在于，该子像素的每一边有“x”的长度，以及各键合垫结构的中心点“c”位在边长为x/4及对角线长为d/4的一假想方盒”b”的一角落“c1”上。
16.如权利要求15所述的像素结构，其特征在于，各键合垫结构沿着多个子像素的单一对角线等距隔开。
17.如权利要求11所述的像素结构，其特征在于，该键合垫结构的表面积约为该接触板的该背面的总表面积的30％或更少。
18.如权利要求17所述的像素结构，其特征在于，还包含在该接触板的该背面上的氧化物材料。
19.如权利要求18所述的像素结构，其特征在于，该多个子像素形成一ILED驱动器芯片的一像素，该ILED驱动器芯片键合至一CMOS驱动器芯片是透过该CMOS驱动器芯片的氧化物材料与该氧化物材料的一氧化物对氧化物键合。
20.一种方法，包含：在多个子像素的一接触板的一背面上的两个相对角落形成键合垫结构，该键合垫结构与在各子像素的该两个相对角落之间延伸的一对角线“d”相交。
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