TWI662603B - 自對準之閘極隔離 - Google Patents
自對準之閘極隔離 Download PDFInfo
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- TWI662603B TWI662603B TW106143556A TW106143556A TWI662603B TW I662603 B TWI662603 B TW I662603B TW 106143556 A TW106143556 A TW 106143556A TW 106143556 A TW106143556 A TW 106143556A TW I662603 B TWI662603 B TW I662603B
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- Prior art keywords
- layer
- isolation layer
- gate
- isolation
- dielectric
- Prior art date
Links
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- 125000006850 spacer group Chemical group 0.000 claims abstract description 36
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
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- 238000001459 lithography Methods 0.000 abstract description 9
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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Abstract
鰭式場效電晶體(FinFET)及其製法包括自對準之閘極隔離層。一種形成FinFET之方法包括:形成犧牲間隔體於鰭片側壁上面,以及在犧牲間隔體之間的數個自對準位置處形成隔離層於毗鄰鰭片之間。形成例如犧牲閘極層的附加層於該隔離層上面,以及微影及蝕刻技術用來切斷或分段該附加層以在該隔離層上面界定一閘極切斷開口。用電介質材料回填該閘極切斷開口,以及回填的電介質與該隔離層合作以使相鄰犧牲閘極從而隨後形成與各個裝置關聯的功能閘極分離。
Description
本申請案大體有關於半導體裝置,且更特別的是,有關於鰭式場效電晶體的製造方法。
例如鰭式場效電晶體(FinFET)的全空乏裝置為致能縮小下一代閘極長度至14奈米及以下的候選者。鰭式場效電晶體(FinFET)為使電晶體通道在半導體基板表面上隆起而不是使通道位在或略低於該表面的三維架構。用隆起的通道,閘極可纏繞通道的側面,這提供裝置的改良靜電控制。
FinFET的製造通常利用自對準製程以使用選擇性蝕刻技術在基板表面上產生極薄的鰭片,例如,20奈米寬或更小。然後,沉積接觸各鰭片之複數個表面的閘極結構以形成多閘極架構。
使用閘極最先(gate-first)或閘極最後(gate-last)製造製程可形成該閘極結構。為了避免功能閘極材料暴露於與此類製程相關的熱預算,例如取代金屬閘極(RMG)製程的閘極最後製程使用在裝置激活之後通常被功能閘極取代的犧牲或虛擬閘極,亦即,在鰭片之源極/汲極
區的磊晶成長及/或摻雜物植入及相關驅入退火(drive-in anneal)之後。
在移除犧牲閘極及形成功能閘極之前,為了隔離毗鄰裝置,閘極切斷模組可用來切斷犧牲閘極層且在架構的選定區域內形成開口。與此一製程聯合,從開口移除的犧牲閘極層材料換成另一蝕刻選擇性電介質材料。不過,在先進節點,儘管近來的發展,在複數個密集排列的鰭片中界定具有所欲關鍵尺寸(s)及對準精確度的閘極切斷開口仍然是個挑戰。
因此,提供一種用於高度準確及精確地界定在關鍵尺寸之犧牲閘極結構的方法是有益的,特別是閘極結構,其致能形成在先進節點的功能取代金屬閘極而不改變設計規則或以其他方式犧牲建地(real estate)。
揭露一種閘極切斷方案,與取代金屬閘極(RMG)加工流程結合,可用於製造鰭式場效電晶體(FinFET),在此隔離層在毗鄰鰭片之間自對準以形成閘極切斷區。藉由形成自對準隔離層,可與習知微影關聯的限制無關地形成有所欲關鍵尺寸及對準的閘極切斷區。
根據本申請案的具體實施例,一種形成半導體結構的方法包括:形成複數個半導體鰭片於一半導體基板上面,形成一間隔體層於該複數個半導體鰭片的側壁上面,在毗鄰間隔體層之間的自對準位置處形成一隔離層,形成一第二層於該隔離層上面且於該半導體鰭片上
面,在該第二層中蝕刻一開口以暴露該隔離層的一頂面,以及在該開口內形成一電介質層。
一種示範半導體結構包括:配置在一半導體基板上面的複數個半導體鰭片,設置於該基板上面且於毗鄰鰭片之間的一隔離層,以及設置於該隔離層上面的一電介質層,其中該隔離層在該基板之一第一區內的一頂面低於鄰近該隔離層之半導體鰭片的一頂面,以及該隔離層在該基板之一第二區內的一頂面高於鄰近該隔離層之半導體鰭片的一頂面。
100‧‧‧半導體基板、基板
120‧‧‧鰭片
122‧‧‧子鰭區
124‧‧‧主動裝置區
140‧‧‧共形氧化物層
200‧‧‧淺溝槽隔離層、凹陷氧化物隔離層、STI、STI層
320‧‧‧硬遮罩、上覆硬遮罩
340‧‧‧上覆電介質層、電介質層
360‧‧‧犧牲側壁間隔體、毗鄰側壁間隔體、側壁間隔體
365a、365b‧‧‧開口
370‧‧‧隔離層、自對準隔離層、層
380‧‧‧犧牲填充層
410‧‧‧非晶矽層、非晶矽
415‧‧‧閘極切斷開口、開口
420‧‧‧閘極硬遮罩
470‧‧‧電介質層、層、電介質材料、氮化物電介質層
500‧‧‧取代金屬閘極架構、RMG架構
501‧‧‧共享閘極
502‧‧‧切斷閘極
510‧‧‧高k層、RMG層
520‧‧‧功函數金屬層、RMG層
530‧‧‧導電填充層
540‧‧‧共享源極/汲極接觸、源極/汲極接觸
570‧‧‧自對準覆蓋(SAC)層
610‧‧‧非晶矽共形層、非晶矽層、非晶矽、犧牲閘極層、共形非晶矽層、非晶矽側壁間隔體層
620‧‧‧電介質填充層
622‧‧‧凹部
630‧‧‧二氧化矽層、硬遮罩
700‧‧‧電介質堆疊
710‧‧‧第一氧化物層
720‧‧‧氮化物層
730‧‧‧第二氧化物層
770‧‧‧ILD層
810‧‧‧側壁間隔體
820‧‧‧源極/汲極區、磊晶層、磊晶源極/汲極區
840‧‧‧層間電介質、ILD層
850‧‧‧氮化物層
h1、h2‧‧‧厚度
A、B‧‧‧直線
閱讀時結合下列附圖可充分明白以下本申請案之特定具體實施例的詳細說明,其中類似的結構用相同的元件符號表示,以及其中:第1圖為FinFET裝置的示意俯視平面圖,其圖示共享閘極在直線A上的位置以及切斷閘極(cut gate)在直線B上的位置;第1A圖根據各種不同具體實施例圖示沿著第1圖共享閘極之尺寸的橫截面圖,它是在鰭片顯露蝕刻(fin revealing etch)以及形成間隔體層於鰭片側壁上面且於設置在鰭片上面之鰭片硬遮罩之側壁上面後的中間製造階段;第1B圖為沿著第1圖切斷閘極之尺寸繪出的橫截面圖,它是在鰭片顯露蝕刻以及形成間隔體層於鰭片側壁上面且於設置在鰭片上面之鰭片硬遮罩之側壁上面
後的中間製造階段;第2A圖根據各種不同具體實施例沿著共享閘極之尺寸圖示第1A圖的結構,它是在自對準沉積隔離層於毗鄰間隔體層之間且凹陷蝕刻(recess etch)隔離層之後;第2B圖沿著切斷閘極之尺寸圖示第1B圖的結構,它是在自對準沉積隔離層於毗鄰間隔體層之間且形成防止隔離層之凹陷蝕刻的犧牲填充層之後;第3A圖描繪根據各種不同具體實施例形成一層非晶矽於未凹陷隔離層上面以及形成閘極硬遮罩於該層非晶矽上面;第3B圖描繪沿著閘極切斷尺寸形成一層非晶矽於隔離層上面,接著是形成閘極硬遮罩於該層非晶矽上面,並且蝕刻閘極硬遮罩及該層非晶矽以形成用隔離層對準之一層蝕刻選擇性電介質材料回填的閘極切斷開口;第4A圖根據其他具體實施例圖示選擇性移除非晶矽層以及沿著共享閘極尺寸蝕刻隔離層;第4B圖圖示移除非晶矽層以及保留回填的蝕刻選擇性電介質材料與在沿著閘極切斷尺寸毗鄰的鰭片之間的隔離層;第5A圖根據另一具體實施例圖示沿著共享閘極尺寸繪出的橫截面圖,它是在形成包括高k層與在鰭片上面之功函數金屬層的取代金屬閘極(RMG)架構之一部份以及犧牲填充層於RMG架構上面之後;
第5B圖根據另一具體實施例圖示沿著切斷閘極尺寸繪出的橫截面圖,它是在形成取代金屬閘極(RMG)架構於鰭片上面之一部份以及犧牲填充層於RMG架構上面且蝕刻犧牲填充層以在隔離層上面形成用一層蝕刻選擇性電介質材料回填的閘極切斷開口之後;第6A圖根據又一具體實施例圖示沿著共享閘極尺寸繪出的橫截面圖,它是在形成取代金屬閘極(RMG)於複數個鰭片上面之後;第6B圖圖示沿著閘極切斷尺寸繪出的橫截面圖,它是在形成取代金屬閘極(RMG)於複數個鰭片上面以及蝕刻取代金屬閘極以在隔離層上面形成用一層蝕刻選擇性電介質材料回填的閘極切斷開口之後;第7圖圖示在形成自對準覆蓋層於取代金屬閘極之後的第6B圖結構;第8A圖根據另一具體實施例圖示FinFET結構沿著共享閘極尺寸繪出的橫截面圖,它是在鰭片顯露蝕刻且移除鰭片硬遮罩以及形成共形氧化物層於鰭片的暴露部份上面之後;第8B圖圖示FinFET結構沿著閘極切斷尺寸繪出的橫截面圖,它是在鰭片顯露蝕刻且移除鰭片硬遮罩以及形成共形氧化物層於鰭片的暴露部份上面之後;第9A圖圖示形成非晶矽共形層於第8A圖之結構上面,沉積及研磨在該層非晶矽上面的電介質填充層,以及隨後氧化該層非晶矽的暴露部份以原位形成二氧
化矽硬遮罩;第9B圖圖示形成非晶矽共形層於第8B圖之結構上面,沉積及研磨在該層非晶矽上面的電介質填充層,以及隨後氧化該層非晶矽的暴露部份以原位形成二氧化矽硬遮罩;第10A圖圖示選擇性移除第9A圖結構的電介質填充層以形成凹部,各向異性回蝕在凹部內的非晶矽層,以及沉積及平坦化隔離層到在毗鄰鰭片之間的自對準位置中;第10B圖圖示選擇性移除第9B圖結構的電介質填充層以形成凹部,各向異性回蝕在凹部內的非晶矽層,以及沉積及平坦化隔離層到在毗鄰鰭片之間的自對準位置中;第11A圖描繪沿著共享閘極尺寸形成一層非晶矽於隔離層上面以及形成閘極硬遮罩於該層非晶矽上面;第11B圖描繪沿著閘極切斷尺寸形成一層非晶矽於隔離層上面以及形成閘極硬遮罩於該層非晶矽上面;第12A圖的橫截面圖根據另一具體實施例圖示沿著共享閘極尺寸鰭片顯露後沉積(post-fin reveal deposition)非晶矽共形層於鰭片上面;第12B圖的橫截面圖根據另一具體實施例圖示沿著閘極切斷尺寸鰭片顯露後沉積非晶矽共形層於鰭
片上面;第12C圖為與鰭片長度平行地繪出的橫截面圖,其圖示鰭片顯露後沉積犧牲閘極於鰭片上面;第13A圖圖示第12A圖的結構,它是在回蝕犧牲閘極,沉積及平坦化在毗鄰鰭片之間之自對準隔離層,以及沉積電介質堆疊於隔離層上面之後;第13B圖圖示第12B圖的結構,它是在回蝕犧牲閘極,沉積及平坦化在毗鄰鰭片之間之自對準隔離層,以及沉積電介質堆疊於隔離層上面之後;第13C圖為與鰭片長度平行地繪出的橫截面圖,它是在沉積、圖案化及蝕刻電介質堆疊以形成犧牲閘極之後;第14A圖為沿著共享閘極尺寸繪出的橫截面結構,它是在移除電介質堆疊之一部份之後;第14B圖為沿著閘極切斷尺寸繪出的橫截面結構,它是在移除電介質堆疊之一部份之後;第14C圖圖示第13C圖橫截面結構,它是在形成側壁間隔體及磊晶層於鰭片之源極/汲極區上面以及凹陷蝕刻電介質堆疊之後;第15A圖為沿著共享閘極尺寸繪出的橫截面結構,它是在移除電介質堆疊之一部份之後;第15B圖為沿著閘極切斷尺寸繪出的橫截面結構,它是在移除電介質堆疊之一部份且隨後從電介質堆疊之其餘部份蝕刻電介質層以形成與隔離層對準且用一
層蝕刻選擇性電介質材料回填的閘極切斷開口之後;第15C圖圖示第14C圖的結構,它是在形成及平坦化在各磊晶層上面之凹部內的電介質填充層之後;第16A圖圖示電介質堆疊的移除以及隔離層沿著共享閘極尺寸的凹陷蝕刻;第16B圖圖示電介質堆疊的移除,以及隔離層之暴露部份沿著閘極切斷尺寸的凹陷蝕刻;第16C圖圖示電介質堆疊的移除,以及隔離層之暴露部份的凹陷蝕刻;第17A圖圖示在鰭片上面之犧牲閘極及共形氧化物層的移除,RMG架構的形成,以及覆蓋層在RMG架構上面的形成;第17B圖圖示在鰭片上面之犧牲閘極及共形氧化物層的移除,RMG架構的形成,以及自對準覆蓋層在RMG架構上面的形成;第17C圖圖示在鰭片上面之共形氧化物層的移除,RMG架構的形成,以及自對準覆蓋層的形成及平坦化;第18A圖根據各種不同具體實施例圖示沿著示範FinFET結構之共享閘極尺寸形成共享頂部源極/汲極接觸於源極/汲極區上面;以及第18B圖根據各種不同具體實施例圖示沿著示範FinFET結構之閘極切斷尺寸形成電氣隔離源極/汲
極接觸於毗鄰源極/汲極區上面。
此時參考本申請案之申請標的之各種具體實施例的更詳細細節,附圖圖示本發明的一些具體實施例。諸圖用相同的元件符號表示相同或類似的部件。
揭露的是FinFET裝置結構與製造FinFET裝置的方法,且更特別的是,分離毗鄰裝置的方法包括:形成犧牲間隔體於鰭片的側壁上面,以及在犧牲間隔體之間的數個自對準位置處形成隔離層於毗鄰鰭片之間。
例如犧牲閘極層的附加層形成於隔離層上面,以及微影及蝕刻技術用來切斷或分段該附加層以界定在隔離層上面的閘極切斷開口。根據各種不同具體實施例,用電介質材料回填該閘極切斷開口,致使回填的電介質與隔離層合作(cooperate)以使相鄰犧牲閘極從而隨後形成與各個裝置關聯的功能閘極隔離。獨立的電晶體可用局部互連法及/或直線金屬化層的後端連接以形成積體電路,例如SRAM裝置。
在不同的具體實施例中,自對準隔離層之側壁與毗鄰鰭片之間的距離(d)可小於20奈米,例如12、14、16或18奈米,包括在上述數值中之任一者之間的範圍。減少距離(d)有益地影響可實現的裝置密度。不過,減少毗鄰結構之間的距離(d)可能引進設計及加工挑戰。應瞭解,此類挑戰可包括功能閘極堆疊的沉積,其包括閘極電介質層、閘極導體層(例如,功函數金屬層)及在可用幾何
內的導電填充材料,例如,隔離層側壁與相鄰鰭片之間的空間。使用現在所揭露的方法,可形成隔離層側壁與毗鄰鰭片之間有受控一致之距離(d)的結構而不改變結構的設計規則。
請參考第1圖,FinFET裝置的簡化示意俯視平面圖圖示共享閘極501在直線A上的位置以及分段或切斷閘極502在直線B上的位置,其具有位在毗鄰鰭片120之間的閘極切斷區。亦即,單一共享閘極501可橫過複數個鰭片,同時切斷閘極502包括可用來形成獨立單獨受控之裝置的獨立閘極。在此參考第1A圖至第18B圖描述用於形成第1圖之裝置結構的示範製程。
第1A圖為沿著第1圖共享閘極之尺寸(直線A)繪出的橫截面圖,它是在鰭片顯露後形成複數個鰭片120於半導體基板100上面之後的中間製造階段。第1B圖圖示沿著第1圖閘極切斷之尺寸(直線B)繪出的對應橫截面圖。
半導體基板100可包括半導體材料,例如矽,例如單晶矽或多晶矽,或含矽材料。含矽材料包括但不限於:單晶矽鍺(SiGe)、多晶矽鍺、摻碳矽(Si:C)、非晶矽、以及由彼等組成的組合及多層。如本文所使用的,用語“單晶”表示晶形固體,其中整個固體的晶格實質連續且固體的邊緣實質不間斷且實質無晶界。
不過,基板100不限於含矽材料,因為基板100可包括其他半導體材料,包括鍺及化合物半導體,
包括III-V族化合物半導體,例如GaAs、InAs、GaN、GaP、InSb、ZnSe及ZnS,以及II-VI族化合物半導體,例如Cdse、CdS、CdTe、ZnSe、ZnS及ZnTe。
基板100可為塊狀基板或合成基板,例如絕緣體上半導體(SOI)基板,從下到上其包括握柄部、隔離層(例如,埋藏氧化物層)及半導體材料層。
基板100可具有本技藝常用的尺寸且可包括例如半導體晶圓。示範晶圓直徑包括但不限於:50、100、150、200、300及450毫米。總基板厚度可在250微米至1500微米之間,然而在特定具體實施例中,基板厚度在725至775微米的範圍內,其對應至常用於矽CMOS加工的厚度尺寸。例如,半導體基板100可包括(100)定向矽晶圓或(111)定向矽晶圓。
熟諳此藝者應瞭解,半導體鰭片120係平行地配置且藉由淺溝槽隔離層200在子鰭區(sub-fin region)122內互相橫向隔離。鰭片120在淺溝槽隔離(STI)層200上方延伸且形成主動裝置區124。
在不同的具體實施例中,鰭片120包括例如矽的半導體材料,且可藉由圖案化然後蝕刻半導體基板100(例如,半導體基板的頂部)形成。在數個具體實施例中,鰭片120從半導體基板100蝕刻而成且因而與其相接。例如,鰭片120可使用熟諳此藝者所習知的側壁影像轉印(SIT)製程形成。
在某些具體實施例中,鰭片120可具有5
奈米至20奈米的寬度,40奈米至150奈米的高度,以及20奈米至100奈米的間距,然而也可想到其他的尺寸。鰭片120可在基板上以規則的鰭間間隔或間距排成陣列。如本文所使用的,用語“間距”指鰭片寬度與相鄰鰭片之間隔的和。在示範具體實施例中,鰭片間距可在20至100奈米的範圍內,例如20、30、40、50、60、70、80、90或100奈米,包括在上述數值中之任一者之間的範圍,然而可使用更小及更大的間距值。在某些具體實施例中,可以不變或可變間距配置複數個鰭片。例如,可以第一間距配置對應至第一裝置的第一鰭片,同時可以第二間距配置對應至第二裝置的第二鰭片。
如圖示具體實施例所示,鰭片120的一部份可塗上薄共形氧化物層140,它可為犧牲氧化物層或併入有厚閘極電介質層的裝置。共形氧化物層140可包括二氧化矽,例如,且可形成於在主動裝置區124內的鰭片上面以及於鰭片硬遮罩上面。共形氧化物層140可具有2至3奈米的厚度。在製造FinFET裝置期間,可從鰭片的源極及汲極區及/或鰭片的通道區剝掉共形氧化物140。例如,被顯露的鰭片高度,亦即,在主動裝置區124內,可為30至60奈米,例如30、40、50或60奈米,包括在上述數值中之任一者之間的範圍。
淺溝槽隔離(STI)層200可用來按照被實作之電路(s)的需要提供鰭片120之間與毗鄰裝置之間的電氣隔離。FinFET裝置的STI製程涉及通過各向異性蝕刻製程
在半導體基板100中建立隔離溝槽。在各毗鄰鰭片之間的隔離溝槽可具有相對高的深寬比(例如,隔離溝槽的深度/寬度比)。例如二氧化矽的電介質填充材料沉積於隔離溝槽中,例如,使用增強式高深寬比製程(eHARP)以填充隔離溝槽。然後,沉積的電介質材料可用化學機械研磨(CMP)製程研磨移除多餘電介質材料以及凹陷蝕刻以建立有均勻厚度的平面STI結構。
用於本文的“平坦化(planarization)”及“平坦化(planarize)”係指至少運用例如磨擦媒介物之機械力以產生實質二維表面的材料移除製程。平坦化製程可包括化學機械研磨(CMP)或磨光。化學機械研磨(CMP)為使用化學反應及機械力兩者以移除材料及平坦化表面的材料移除製程。
在某些具體實施例中,回蝕經平坦化的STI氧化物以在鰭片120之間形成厚度均勻的凹陷氧化物隔離層200,在此可暴露鰭片120的上側壁供進一步加工。
請再參考第1A圖及第1B圖,包括硬遮罩320及上覆電介質層340的鰭片帽蓋(fin cap)設置在鰭片上面。硬遮罩320可包括SiCO、SiCN、SiOCN或氮化矽,例如,以及上覆電介質層340可包括二氧化矽。如本文所使用的,化合物二氧化矽及氮化矽有各自以SiO2及Si3N4之名義表示的組合物。用語氮化矽及二氧化矽不僅是指這些化學計量組合物,也指偏離該等化學計量組合物的氮化物及氧化物組合物。
使用共形沉積製程,接著是各向異性蝕刻,形成犧牲側壁間隔體360於鰭片120的側壁上面且於鰭片帽蓋上面,亦即,直接於共形氧化物層140及電介質層340上面。非晶元素矽(a-Si)的沉積可使用原子層沉積(ALD)或化學氣相沉積,例如溫度在450℃至700℃之間的低壓化學氣相沉積(LPCVD)。矽烷(SiH4)可用作CVD矽沉積的前驅物。毗鄰側壁間隔體360界定在相鄰鰭片之間的開口365a、365b。
請參考第2A圖及第2B圖,隔離層370沉積於在開口365a、365b裡的數個自對準位置內。隔離層370沿著鰭片的長度延伸。隔離層370可包括電介質材料,例如SiCO、SiCN、SiOCN及其類似者。根據各種不同具體實施例,隔離層370、每個側壁間隔體360及硬遮罩320由可互相選擇性地蝕刻的材料形成。隔離層370可使用共形沉積製程形成,以及在某些具體實施例中,在毗鄰側壁間隔體360之間可夾止(pinch off)。沉積隔離層後,可接著是有效暴露電介質層340之頂面的回蝕製程。
如本文所使用的,關於材料移除或蝕刻製程的用語“選擇性的”或“選擇性地”意指應用材料移除製程的結構中之第一材料的材料移除速率大於至少另一材料的移除率。例如,在某些具體實施例中,選擇性蝕刻可包括選擇性地對第二材料以2:1或更大的比率移除第一材料的蝕刻化學物,例如,5:1、10:1或20:1。
自對準隔離層370的高度可致使隔離層370
的頂面初始高於毗鄰鰭片120的頂面但是低於相鄰鰭片帽蓋的頂面,例如,低於硬遮罩320的頂面。在某些具體實施例中,隔離層370的高度不及在主動裝置區124內之鰭片的兩倍高度,亦即,小於或等於鰭片120在STI 200上方延伸之部份的兩倍高度。例如,初生(as-formed)的自對準隔離層370的頂面可高於相鄰鰭片之頂面10至50奈米,例如,高於相鄰鰭片之頂面25奈米。
在圖示具體實施例中,犧牲填充層380可形成於在閘極切斷尺寸(第2B圖)內的隔離層370上面,這防止蝕刻在閘極切斷尺寸內的隔離層370,同時至少部份移除在共享閘極尺寸(第2A圖)內的隔離層370。儘管第2A圖圖示凹陷蝕刻隔離層370例如到小於毗鄰鰭片120之高度的高度,然而應瞭解,蝕刻可完全移除在共享閘極尺寸內的隔離層370。示範犧牲填充層380例如可包括光學平坦化層(OPL)或一非晶碳層。
從包括碳化氫源與稀釋氣體的氣體混合物以200℃至700℃的沉積溫度,可形成包括非晶碳的犧牲填充層380。視需要,以大於200℃的固化溫度可固化剛沉積的(as-deposited)非晶碳(a-C)層,例如藉由暴露於紫外線輻射。
可包括在用來形成非晶碳層之碳化氫源中的示範碳化氫化合物可用公式CxHy描述,在此1x10且2y30。此類碳化氫化合物可包括但不限於烷烴,例如甲烷、乙烷、丙烷、丁烷及其異構體異丁烷,戊烷及其異構
體異戊烷,以及新戊烷、己烷及其異構體:2-甲基戊烷、3-甲基戊烷、2,3-二甲基丁烷、2,2-二甲基丁烷等等;烯烴,例如乙烯、丙烯、丁烯及其異構體,戊烯及其異構體等等;二烯,例如丁二烯、異戊二烯、戊二烯、己二烯等等,以及鹵化烯烴包括:單氟乙烯、二氟乙烯、三氟乙烯、四氟乙烯、單氯乙烯、二氯乙烯、三氯乙烯、四氯乙烯等等;以及炔烴,例如乙炔、丙炔、丁炔、乙烯基乙炔及其衍生物。其他碳化氫化合物包括芳香族分子,例如苯、苯乙烯、甲苯、二甲苯、乙苯、苯乙酮、苯甲酸甲酯、乙酸苯酯、苯酚、甲酚、呋喃等等,以及鹵化芳族化合物,包括單氟苯、二氟苯、四氟苯、六氟苯等等。
合適稀釋氣體可包括但不限於:氫(H2)、氦(He)、氬(Ar)、氨(NH3)、一氧化碳(CO)、二氧化碳(CO2)及彼等之混合物。
繼續參考第3A圖及第3B圖,其圖示在說明第2A圖及第2B圖時所述的結構之替代具體實施例。在圖示於第3A圖及第3B圖的具體實施例中,在製程的後期階段進行隔離層370沿著共享閘極尺寸(第3A圖)的凹陷蝕刻,致使在凹陷蝕刻隔離層370之前,移除上覆硬遮罩320之頂面及側壁表面的硬遮罩320及電介質層340,形成一層非晶矽410於隔離層370上面,形成閘極硬遮罩420於該層非晶矽上面,以及圖案化非晶矽410及閘極硬遮罩420以形成犧牲閘極。閘極硬遮罩420可包括例如氮化矽。
請參考第3B圖,閘極切斷開口415形成於
閘極硬遮罩420內且延伸穿過非晶矽層410以暴露隔離層370沿著閘極切斷尺寸的頂面。閘極切斷開口415可在形成閘極、間隔體、源極/汲極磊晶及形成ILD之後形成。
可使用熟諳此藝者所習知的圖案化及蝕刻製程形成閘極切斷開口415。該圖案化製程可包括微影,例如,其包括形成一層光阻材料(未圖示)於將會被圖案化的一或更多層上面。該光阻材料可包括正型(positive-tone)光阻組成物,負型(negative-tone)光阻組成物,或混合型(hybrid-tone)光阻組成物。可用例如旋轉塗佈(spin-on coating)的沉積製程形成一層光阻材料。
然後,沉積光阻經受一輻射圖案,且用習知阻劑顯影劑顯影露出的光阻材料。此後,用至少一圖案轉印蝕刻製程,將由帶圖案光阻材料所提供的圖案轉印到閘極硬遮罩420和非晶矽層410中。
根據各種不同具體實施例,除了一層光阻外,形成閘極切斷開口415的圖案化及蝕刻可包括形成微影堆疊(未圖示)於非晶矽層410上面。微影堆疊可包括光學平坦化層、蝕刻停止層、非晶碳層、黏附層、氧化物層及氮化物層中之一或更多。如熟諳此藝者所習知,可將該等層組配成可提供合適遮罩層以圖案化及蝕刻底下的層(s)。
該圖案轉印蝕刻製程通常為各向異性蝕刻。在某些具體實施例中,可使用乾蝕刻製程,例如反應性離子蝕刻(RIE)。在其他具體實施例中,可使用濕化學蝕
刻劑。又在其他具體實施例中,可使用乾蝕刻與濕蝕刻的組合。
閘極切斷開口415可具有分別在15至40奈米之間的面積尺寸(長度及寬度),然而可使用更小或更大的尺寸。根據各種不同具體實施例,初生的閘極切斷開口415的面積尺寸在用於形成此類結構的微影製程窗口內,且致能界定有實質垂直側壁的閘極切斷開口415。如本文所使用的,“實質垂直”側壁與基板主面的法線方向相差不到5°,例如0、1、2、3、4或5°,包括在上述數值中之任一者之間的範圍。在某些具體實施例中,閘極切斷開口415的寬度(w)小於20奈米,例如5、10或15奈米。
然後,用電介質層470回填閘極切斷開口415。電介質層470可包括氮化矽。CMP步驟可用來平坦化該結構。根據各種不同具體實施例,電介質層470由對於非晶矽與閘極硬遮罩兩者有蝕刻選擇性的材料形成,請參考第4A圖及第4B圖,這允許在後續加工期間移除非晶矽層410。在某些具體實施例中,隔離層370與電介質層470包括不同的材料。在某些具體實施例中,隔離層370與電介質層470包括相同的材料。
特別參考第4A圖,圖示結構為第2A圖結構的替代物,藉此在用來移除非晶矽層410的蝕刻製程期間或之後可凹陷(或移除)在共享閘極尺寸內的隔離層370(然而,在說明第2A圖時所述的製程中,在形成非晶矽層410之前用獨立的遮罩步驟移除在共享閘極尺寸內的
隔離層370)。由第4A圖及第4B圖可見,電介質層470可沿著閘極切斷尺寸(第4B圖)遮罩隔離層370,致使不實質蝕刻沿著閘極切斷尺寸的隔離層370。在圖示於第4B圖的具體實施例中,隔離層370與電介質層470形成合成結構且合作以使隨後形成位於層370、470之任一側的功能閘極電氣分離。
請參考第5A圖及第5B圖,根據另一具體實施例,在製程的更後期階段可進行閘極切斷模組。在圖示具體實施例中,包括高k層510及功函數金屬層520的取代金屬閘極(RMG)架構之一部份可形成於鰭片120上面且於隔離層370上面。在沉積高k層510及功函數金屬層520之前,可移除在鰭片上面的共形氧化物層140。然後,形成例如有機平坦化層或一非晶碳層的犧牲填充層380於RMG層上面,且在閘極切斷尺寸(第5B圖)中,圖案化及蝕刻穿過犧牲填充層380且穿過RMG層510、520的閘極切斷開口415以暴露隔離層370的頂面。用直接沉積隔離層370上面的一層蝕刻選擇性電介質材料470回填閘極切斷開口415。在圖示具體實施例中,在共享閘極尺寸(第5A圖)內,隔離層370的頂面低於鄰近隔離層之半導體鰭片的頂面,同時在閘極切斷尺寸(第5B圖)內,隔離層370的頂面高於鄰近隔離層之半導體鰭片的頂面。在某些具體實施例中,電介質層470的寬度可大於隔離層370的寬度。
根據另一具體實施例,參考第6A圖及第6B圖,在形成包括高k層510、功函數金屬層520及導電填
充層530的完全取代金屬閘極後,可蝕刻閘極切斷開口415以及用蝕刻選擇性電介質層回填。
圖示於第7圖的是在形成及平坦化在取代金屬閘極上面之自對準覆蓋(SAC)層570後的第6B圖結構。在圖示具體實施例中,在研磨SAC層570後,上覆隔離層370的SAC層570之厚度(h1)可大於直接上覆導電填充層530的SAC層570之厚度(h2)。
應瞭解,根據描述於本文的各種具體實施例,形成閘極切斷開口415的蝕刻只需延伸穿過犧牲填充層380(或導電填充層530)到隔離層370的頂面,其高於毗鄰鰭片120的頂面。相較於蝕刻形成延伸穿過犧牲填充層380(或導電填充層530)到STI 200之閘極切斷開口415的替代製程,相對淺的蝕刻深度導致一種方法及所產生之結構,在此開口415的關鍵尺寸與後續填充步驟各有寬廣的製程窗口且便於控制。例如,甚至在形成閘極切斷開口415的不對準蝕刻實施例中,如第3B圖、第5B圖及第6B圖所示意的,它可有大於隔離層370的CD,隔離層至鰭片的間隔(d)(在隔離層370的每側)係藉由隔離層370的自對準形成來固定,而不是藉由關鍵尺寸和與微影關聯的對準精確度。
特別參考第8圖至第11圖,描述用於形成自對準之閘極隔離的另一方法和所產生之結構。
第8A圖圖示FinFET結構沿著共享閘極尺寸繪出的橫截面圖,它是在鰭片顯露蝕刻且移除鰭片硬遮
罩以及形成共形氧化物層140於鰭片120的暴露部份之後。第8B圖為沿著閘極切斷尺寸繪出的對應橫截面圖。
請參考第9A圖及第9B圖,形成非晶矽共形層610於第8A圖及第8B圖的各個結構上面作為犧牲閘極。非晶矽共形層610可具有充分完全覆蓋鰭片及鰭片帽蓋的厚度。例如,非晶矽共形層610的厚度可在10至200奈米之間,例如10、15、20、50、75、100、125、150、175或200奈米,包括在上述數值中之任一者之間的範圍,然而可使用更小或更大的厚度。之後,沉積電介質填充層620於該層非晶矽上面且予以平坦化。在不同的具體實施例中,非晶矽層610用作平坦化製程的停止層,致使電介質填充層620的研磨暴露非晶矽的頂面。電介質填充層620可包括例如CVD或ALD氮化矽。然後,原位氧化非晶矽層610以形成包括一二氧化矽層630的硬遮罩。
請參考第10A圖及第10B圖,可移除用來模塑(template)硬遮罩630之原位形成的電介質填充層620以形成凹部622,例如,使用包括熱磷的濕蝕刻。
第10A圖及第10B圖描繪電介質填充層620的選擇性移除,接著是使用硬遮罩630作為蝕刻遮罩在凹部622內之非晶矽610的各向異性回蝕,且沉積及平坦化在毗鄰鰭片之間的凹部622內的自對準隔離層370。隔離層370直接形成於在凹部622之底部暴露的STI層200上面。
如第10A圖及第10B圖所示,化學機械研
磨步驟可用來在沉積隔離層370且產生平坦化結構之後移除過載體(overburden)。在移除多餘填充層材料期間,犧牲閘極層610可用作CMP蝕刻停止層。
請參考第11A圖及第11B圖,形成非晶矽410的附加層於共形非晶矽層610上面且於隔離層370上面,以及形成閘極硬遮罩420於該非晶矽410的附加層上面。從第11A圖及第11B圖的結構可見,可用蝕刻選擇性電介質層界定及回填閘極切斷開口(未圖示)以形成閘極切斷結構,如以上在說明第3A圖及第3B圖時所述。在此製程中,蝕刻形成延伸穿過非晶矽層410到在閘極切斷尺寸內之隔離層370頂面的閘極切斷開口。
參考第12圖至第18圖描述用於形成自對準之閘極隔離的另一方法以及所產生之結構。
請參考第12A圖及第12B圖,形成非晶矽共形層610於鰭片120上面且於鰭片帽蓋上面,亦即,直接於電介質層340上面以及直接於共形氧化物層140上面。第12C圖為與鰭片長度平行地繪出的橫截面圖,其圖示非晶矽層610在鰭片120上面的鰭片顯露後沉積。
請參考第13A圖及第13B圖,非晶矽層610的凹陷蝕刻用來暴露鰭片帽蓋的頂面和STI 200的頂面。在不同的具體實施例中,回蝕非晶矽層610致使非晶矽層610的頂面低於硬遮罩320的頂面。在回蝕後,非晶矽層610在鰭片120的側壁上面形成間隔體層。
沉積隔離層370於直接在STI 200上面在相
鄰非晶矽側壁間隔體層610之間的數個自對準位置內然後加以研磨以移除過載體且形成平坦化結構。硬遮罩320在研磨期間可用作CMP停止層,致使移除在硬遮罩320上面的電介質層340。如第13A圖至第13C圖所示,隨後在平坦化表面上面形成包括第一氧化物層710、氮化物層720及第二氧化物層730的電介質堆疊700。另一微影及蝕刻步驟用來圖案化電介質堆疊700於上覆鰭片120(第13C圖)的犧牲閘極中。該犧牲閘極上覆鰭片120的通道區。
請參考第14A圖至第14C圖,特別是第14C圖,形成側壁間隔體810於電介質堆疊700的側壁上面且於底下硬遮罩320的側壁上面,亦即,在圖示具體實施例中,直接於共形氧化物層140上面。側壁間隔體810的形成可藉由毯覆沉積間隔體材料(例如,使用原子層沉積),接著是定向蝕刻(directional etch),例如反應性離子蝕刻(RIE),以從水平表面移除間隔體材料。在某些具體實施例中,側壁間隔體810厚度為4至20奈米,例如4、10、15或20奈米,包括在上述數值中之任一者之間的範圍。示範側壁間隔體材料包括氮化矽與SiBCN。
如本文所使用的,“水平”係指大體沿著基板之主要表面的方向,以及“垂直”大體為與其正交的方向。此外,“垂直”與“水平”為大體互相垂直的方向而與基板在三維空間中的取向無關。
在移除在鰭片上面之共形氧化物層140的暴露部份後,可用離子植入或選擇性磊晶形成源極/汲極區
820,例如,使用側壁間隔體810作為對準遮罩。根據示範具體實施例,源極/汲極區820的形成可藉由凹陷半導體鰭片120,接著是從鰭片的暴露部份開始選擇性磊晶成長。
如本文所使用的,用語“磊晶(epitax)”、“磊晶(epitaxial)”及/或“磊晶成長及/或沉積”係指成長半導體材料層於半導體材料的沉積表面上,其中被成長的半導體材料層採取與沉積表面之半導體材料相同的結晶習性。例如,在磊晶沉積製程中,控制由氣體源所提供的化學反應物且設定系統參數使得沉積原子都落在沉積表面上且經由表面擴散仍然充分活躍以根據沉積表面中之原子的晶向來確定方向。因此,磊晶半導體材料會採取與形成於其上之沉積表面相同的結晶體特性。例如,沉積於(100)晶面上的磊晶半導體材料會有(100)取向。源極/汲極區820可包括矽、矽鍺、或另一合適半導體材料。
該選擇性磊晶製程沉積磊晶層直接於鄰近側壁間隔體810的鰭片120之暴露表面上。鰭片120的暴露表面可包括頂面以及鰭片側壁貼近頂面的上半部。在不同的具體實施例中,形成矽磊晶層而不沉積矽於暴露電介質表面上。使用適合選擇性磊晶的分子束磊晶或化學氣相沉積製程,可形成選擇性磊晶層。
用於形成頂部源極(或汲極)區的示範矽磊晶製程使用以600-800℃溫度沉積(例如,基板)包括氫與二氯矽烷(SiH2Cl2)的氣體混合物。矽磊晶的其他合適氣體源包括四氯化矽(SiCl4)、矽烷(SiH4)、三氯矽烷(SiHCl3),及
其他減氫氯矽烷(hydrogen-reduced chlorosilane,SiHxCl4-x)。
層間電介質840直接沉積於磊晶層820上面以填充在毗鄰側壁間隔體810之間的開口。層間電介質840可包括二氧化矽且可用化學氣相沉積形成。可用化學機械研磨法移除過載體,例如,使用作為CMP停止層的氮化物層720。由第14A圖及第14B圖可見,CMP步驟可移除在氮化物層720上面的第二氧化物層730。
在形成閘極切斷開口之前,選擇性蝕刻可用來凹陷ILD層840,且凹陷區可填滿氮化物層850(例如,氮化矽)以及再度研磨該結構,如第15C圖所示。請參考第15A圖至第15C圖,根據各種不同具體實施例,用來移除多餘氮化物層850的研磨步驟可在第一氧化物層710上停止。
如第15B圖所示,使用習知微影及蝕刻技術,在第一氧化物層710內形成閘極切斷開口415以暴露沿著閘極切斷尺寸之隔離層370的頂面。如在先前的具體實施例中,可用電介質層470回填閘極切斷開口415,以及CMP步驟可用來平坦化該結構。
形成第15B圖之閘極切斷開口415的蝕刻只需延伸穿過第一氧化物層710到隔離層370的頂面。與蝕刻形成將延伸穿過第一氧化物層710到STI 200之閘極切斷開口415的比較製程相比,相對淺的蝕刻深度導致一種方法及所產生之結構,在此開口415的關鍵尺寸及後續
填充步驟各有寬廣的製程窗口且便於控制。例如,甚至在形成閘極切斷開口415的不對準蝕刻實施例中,如第15B圖所示意的,隔離層至鰭片的間隔(d)(在隔離層370的每側)係藉由隔離層370的自對準形成來固定,而不是藉由與微影關聯的對準精確度。
請參考第16A圖、第16B圖及第16C圖,一或更多蝕刻製程可用來移除第一氧化物層710然後凹陷隔離層370的暴露部份。在不同的具體實施例中,對於氮化物電介質層470、非晶矽層610及SiCO隔離層370,可選擇性地移除第一氧化物層710。應瞭解,隔離層370在共享閘極尺寸(第16A圖)內凹陷,同時電介質層470在閘極切斷尺寸(第16B圖)內遮罩隔離層370,致使實質不蝕刻沿著閘極切斷尺寸的隔離層370。在鰭片120的通道區上面,在源極/汲極區820之間,第一氧化物層710的移除與閘極硬遮罩320的蝕刻暴露共形氧化物層140在鰭片上面的頂面。
例如含氬氟酸(BHF)蝕刻的各向同性濕蝕刻製程可用來蝕刻第一氧化物層710,接著是各向異性乾蝕刻製程以蝕刻閘極硬遮罩320及隔離層370。替換地,可使用濕化學蝕刻劑。又在其他具體實施例中,可使用乾蝕刻與濕蝕刻的組合。
可一起移除共形氧化物140與非晶矽層610的其餘部份。包括高k層、功函數金屬層及導電填充金屬(未個別圖示)的取代金屬閘極架構500可形成於鰭片上
面。可共形沉積該高k層及該功函數金屬層例如於隔離層370與相鄰鰭片120之間的間隙中。該導電填充層的凹陷蝕刻可用來控制它的厚度。
應瞭解,該導電填充層形成沿著共享閘極尺寸(第17A圖)的共享閘極,同時隔離層370與電介質層470合作以使該導電填充層的第一及第二部份沿著閘極切斷尺寸(第17B圖)電氣分離。
第17A圖至第17C圖描繪電介質堆疊700的移除,隔離層370之暴露部份的凹陷蝕刻,從鰭片上面移除犧牲閘極和共形氧化物層,RMG架構500的形成,以及自對準覆蓋層570的形成及平坦化。
第18A圖及第18B圖圖示穿過鰭片120之源極/汲極區的示範橫截面結構,在此設置自對準隔離層370於相鄰源極/汲極區820之間且提供彼等的電氣隔離。在第18A圖中,直接形成共享源極/汲極接觸540於合併的磊晶源極/汲極區820上面。源極/汲極接觸540可包括鎢且可使用化學氣相沉積形成於上覆隔離層370之ILD層770的開口中。該ILD層可包括二氧化矽。
第18A圖圖示共享頂部源極/汲極接觸540的形成,其係沿著示範FinFET結構的共享閘極尺寸延伸穿過ILD層770,以及第18B圖圖示沿著示範FinFET結構之閘極切斷尺寸在毗鄰源極/汲極區820上面之電氣隔離源極/汲極接觸540的形成。在不同的具體實施例中,自對準隔離層370可防止相鄰源極/汲極區820在彼等之磊晶
成長期間合併而不阻擋源極/汲極接觸540越過共享源極/汲極的合併。
應瞭解,描述於本文的閘極隔離方法及結構利用提供精確對準犧牲閘極之切斷區的自對準隔離層與上覆隔離層以微影界定之電介質層兩者的形成且與自對準隔離層一起提供有效的閘極隔離結構。藉由以自對準的方式在形成於毗鄰鰭片之側壁上面的犧牲側壁間隔體之間形成隔離層,可實現所欲關鍵尺寸(CD)與隔離層的對準。揭露的方法致能與單一閘極及共享閘極裝置兩者相容的結構。
根據各種不同具體實施例,包括前述諸層及結構之層或結構的形成或沉積可能涉及適用於被沉積之材料或層、或被形成之結構的一或更多技術。除了特意提及的技術或方法以外,各種不同的技術包括但不限於:化學氣相沉積(CVD)、低壓化學氣相沉積(LPCVD)、電漿增強式化學氣相沉積(PECVD)、微波電漿化學氣相沉積(MPCVD)、金屬有機CVD(MOCVD)、原子層沉積(ALD)、分子束磊晶(MBE)、電鍍、無電式電鍍、離子束沉積、旋轉塗佈(spin-on coating)、熱氧化、以及物理氣相(PVD)技術,例如濺鍍或蒸鍍。
如本文所使用的,單數形式“一(a)”、“一(an)”、及“該(the)”旨在也包括複數形式,除非上下文中另有明確指示。因此,例如,“層”的引用包括有兩個或更多此類“層”的實施例,除非上下文中另有明確指示。
除非另有明文規定,決非旨在提及於本文的任何方法被理解為它的步驟需要按照特定的順序執行。相應地,在方法請求項沒有實際列舉其步驟將會遵循的順序或請求項或說明中沒有另外特別說明該等步驟受限於特定順序時,決非旨在暗示任何特定順序。任一請求項中的任何列舉單一或複數個特徵或方面可與任何其他請求項或數個請求項中的任何其他列舉特徵或方面排列或組合。
應瞭解,當指例如層、區域或基板的元件形成、沉積或設置於另一元件“上”或“上面”時,它可直接在該另一元件上或者也可存在中介元件。相比之下,當指一元件“直接”在另一元件“上”或“上面”時,不存在中介元件。
儘管使用傳統片語“包含(comprising)”可揭示特定具體實施例的各種特徵、元件或步驟,然而應瞭解,替代具體實施例暗示包括可用傳統片言“由...組成(consisting)”或“實質由...組成(consisting essentially of)”描述者。因此,例如,包含鋯鈦酸鉛(lead zirconate titanate)之鐵電層的隱示替代具體實施例包括鐵電層實質由鋯鈦酸鉛組成的具體實施例與鐵電層由鋯鈦酸鉛組成的具體實施例。
熟諳此藝者明白,本發明可做出各種修改及變體而不脫離本發明的精神及範疇。由於熟諳此藝者可能想到體現本發明精神及主旨的修改、組合、次組合及變體,因此本發明應被視為涵蓋在隨附申請專利範圍及其均
等物之範疇內的任何事物。
Claims (17)
- 一種形成半導體結構之方法,其包含:形成複數個半導體鰭片於一半導體基板上面;形成一間隔體層於該複數個半導體鰭片的側壁上面;在毗鄰間隔體層之間的自對準位置處形成一隔離層;形成一非晶矽層於該隔離層上面且於該半導體鰭片上面;在該非晶矽層中蝕刻一開口以暴露該隔離層的一頂面;以及在該開口內形成一電介質層。
- 如申請專利範圍第1項所述之方法,其中,該間隔體層包含一非晶矽。
- 如申請專利範圍第1項所述之方法,其中,該隔離層包含從下列各物組成之群組選出的一電介質材料:SiCO、SiCN及SiOCN。
- 如申請專利範圍第1項所述之方法,更包含:蝕刻該隔離層,其中,經蝕刻之該隔離層在該基板之一第一區內的一頂面低於鄰近該隔離層之半導體鰭片的一頂面。
- 如申請專利範圍第1項所述之方法,其中,該隔離層在該基板之一第二區內的一頂面高於鄰近該隔離層之半導體鰭片的一頂面。
- 如申請專利範圍第1項所述之方法,更包含:在該半導體鰭片之間形成一淺溝槽隔離層於該半導體基板上面。
- 如申請專利範圍第6項所述之方法,其中,該隔離層直接形成於該淺溝槽隔離層上面。
- 如申請專利範圍第1項所述之方法,其中,該非晶矽層包含非晶矽。
- 如申請專利範圍第1項所述之方法,其中,該非晶矽層包含一導電層。
- 如申請專利範圍第1項所述之方法,其中,該非晶矽層包含上覆一導電層的一非晶碳層或一有機平坦化層(OPL)。
- 如申請專利範圍第1項所述之方法,其中,該電介質層的一寬度大於該隔離層的一寬度。
- 如申請專利範圍第1項所述之方法,更包含:在該電介質層與該隔離層的相對側壁上面形成一導電層。
- 一種半導體結構,其包含:複數個半導體鰭片,配置在一半導體基板上面;一隔離層,設置於該基板上面且於毗鄰鰭片之間;以及一電介質層,設置於該隔離層上面,其中,該隔離層在該基板之一第一區內的一頂面低於鄰近該隔離層之半導體鰭片的一頂面,以及該隔離層在該基板之一第二區內的一頂面高於鄰近該隔離層之半導體鰭片的一頂面。
- 如申請專利範圍第13項所述之半導體結構,其中,該電介質層包含氮化矽且該隔離層包含從下列各物組成之群組選出的一電介質材料:SiCO、SiCN及SiOCN。
- 如申請專利範圍第13項所述之半導體結構,更包含:在該半導體鰭片之間設置於該半導體基板上面的一淺溝槽隔離層,其中,該隔離層直接設置於該淺溝槽隔離層上面。
- 如申請專利範圍第13項所述之半導體結構,其中,該電介質層的一寬度大於該隔離層的一寬度。
- 如申請專利範圍第13項所述之半導體結構,更包含:設置在該電介質層及該隔離層之第一側壁上面的一第一導電層以及設置在該電介質層及該隔離層之第二側壁上面的一第二導電層。
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US11978774B2 (en) * | 2020-10-05 | 2024-05-07 | Sandisk Technologies Llc | High voltage field effect transistor with vertical current paths and method of making the same |
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US9236480B2 (en) * | 2013-10-02 | 2016-01-12 | Globalfoundries Inc. | Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices |
US9171752B1 (en) * | 2014-08-12 | 2015-10-27 | Globalfoundries Inc. | Product comprised of FinFET devices with single diffusion break isolation structures, and methods of making such a product |
KR102604564B1 (ko) * | 2016-07-01 | 2023-11-22 | 인텔 코포레이션 | 자기 정렬 게이트 에지 트라이게이트 및 finfet 디바이스들 |
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TW201717398A (zh) * | 2015-11-04 | 2017-05-16 | 台灣積體電路製造股份有限公司 | 半導體裝置及其製造方法 |
US20170222055A1 (en) * | 2016-01-28 | 2017-08-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
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US20190139830A1 (en) | 2019-05-09 |
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