TWI660483B - 電子裝置及其製造方法 - Google Patents
電子裝置及其製造方法 Download PDFInfo
- Publication number
- TWI660483B TWI660483B TW106114509A TW106114509A TWI660483B TW I660483 B TWI660483 B TW I660483B TW 106114509 A TW106114509 A TW 106114509A TW 106114509 A TW106114509 A TW 106114509A TW I660483 B TWI660483 B TW I660483B
- Authority
- TW
- Taiwan
- Prior art keywords
- conductive feature
- semiconductor die
- bumps
- electromagnetic radiation
- electronic device
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 106
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000005670 electromagnetic radiation Effects 0.000 claims description 64
- 238000000034 method Methods 0.000 claims description 10
- 239000002245 particle Substances 0.000 claims 1
- 230000008878 coupling Effects 0.000 description 16
- 238000010168 coupling process Methods 0.000 description 16
- 238000005859 coupling reaction Methods 0.000 description 16
- 239000011810 insulating material Substances 0.000 description 11
- 239000013078 crystal Substances 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
- H01L2224/1411—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
- H01L2224/17106—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area
- H01L2224/17107—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area the bump connectors connecting two common bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
- H01L2225/06537—Electromagnetic shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
電子裝置包含第一半導體晶粒、多個凸塊以及基材。第一半導體晶粒包含第一導電特徵。凸塊設置於第一半導體晶粒,並連接第一導電特徵。基材包含第二導電特徵。凸塊係電性連接於第二導電特徵。第一導電特徵、凸塊以及第二導電特徵係配置以形成至少一環狀結構。
Description
本案係關於一種可抑制環境中電磁輻射之耦合現象的電子裝置及其製造方法。
於積體電路中,耦合現象常發生於其內的電感與線路,諸如發生於電感與電感之間、線路與線路之間以及電感與線路之間。尤其在高頻領域中(如5GHz-10GHz),或是10GHz以上,其耦合現象更加明顯,嚴重影響積體電路之效能。
對於發生在電感與電感之間的耦合現象而言,由於積體電路之製程的發展方向漸趨微型化,致使積體電路內的電感與電感之間的距離越來越近,從而導致電感與電感之間的耦合現象愈加顯著。此外,於實際應用中,前述之電感可為變壓器(transformer)、傳輸線(transmission line)或金屬走線(metal trace)。
依據本揭露之一實施方式,一種電子裝置包含第一半導 體晶粒、多個凸塊以及基材。第一半導體晶粒包含第一導電特徵。凸塊設置於第一半導體晶粒,並連接第一導電特徵。基材包含第二導電特徵。凸塊係電性連接於第二導電特徵。
依據本揭露之另一實施方式,一種電子裝置的製造方法包含形成第一導電特徵以及多個凸塊於第一半導體晶粒,且第一導電特徵電性連接多個凸塊;以及將多個凸塊電性連接基材上之第二導電特徵。
1、2、3‧‧‧電子裝置
10‧‧‧第一半導體晶粒
12、22‧‧‧凸塊
13‧‧‧絕緣材料
14‧‧‧第二半導體晶粒
15‧‧‧環狀結構
16‧‧‧第三半導體晶粒
17‧‧‧空間
18‧‧‧第一電磁輻射源結構
19‧‧‧第二電磁輻射源結構
100、200‧‧‧第一導電特徵
140、240‧‧‧第二導電特徵
160‧‧‧導電接觸
162‧‧‧第三導電特徵
170、370、3700、3702‧‧‧子空間
1001~1006‧‧‧步驟
m1、m2‧‧‧曲線
A-A、B-B‧‧‧線段
第1圖繪示依據本案之一實施方式之電子裝置的立體圖,其中省略繪示絕緣材料以及第二半導體晶粒。
第2圖繪示沿著第1圖中線段A-A的剖視圖。
第3圖繪示依據本案之一實施方式之電子裝置的實驗數據圖。
第4圖繪示依據本案之一實施方式之電子裝置的立體圖。
第5圖繪示依據本案之一實施方式之電子裝置的立體圖,其中省略繪示絕緣材料、第二半導體晶粒以及第三半導體晶粒。
第6圖繪示沿著第5圖中線段B-B的剖視圖。
第7圖繪示依據本案之一實施方式之電子裝置之製造方法的流程圖。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解,製造商可能會用不同的名詞來稱呼同樣的元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式,而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語,故應解釋成「包含但不限定於」。另外,「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此,若文中描述一第一裝置耦接於一第二裝置,則代表該第一裝置可直接電氣連接於該第二裝置,或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
請參照第1圖及第2圖。第1圖繪示依據本案之一實施方式之電子裝置1的立體圖,其中省略繪示絕緣材料13以及第二半導體晶粒14(見第2圖)。第2圖繪示沿著第1圖中線段A-A的剖視圖。如圖所示,於本實施方式中,電子裝置1包含第一半導體晶粒10、多個凸塊12、第二半導體晶粒14(於本實施方式中亦可被稱為基材,見第2圖)、絕緣材料13(見第2圖)、第一電磁輻射源結構18以及第二電磁輻射源結構19。於本實施方式中,電子裝置1為積體電路。以下將詳細介紹各元件的結構、功能以及各元件之間的連接關係。
於本實施方式中,第一半導體晶粒10包含第一導電特徵100。第二半導體晶粒14包含第二導電特徵140。於其他實施方式中,第二半導體晶粒14可由印刷電路板(Printed Circuit Board,PCB)所取代。於本實施方式中,第一半導體 晶粒10的第一導電特徵100與第二半導體晶粒14的第二導電特徵140之間具有空間17。也就是說,第一半導體晶粒10的第一導電特徵100與第二半導體晶粒14的第二導電特徵140藉由空間17而相互分離。此外,本實施方式的第一半導體晶粒10與第二半導體晶粒14共同形成三維積體電路(3D IC)堆疊架構。
於第1圖中,多個凸塊12設置於第一半導體晶粒10,並連接第一半導體晶粒10的第一導電特徵100。凸塊12接合第二半導體晶粒14(見第2圖)的第二導電特徵140,因而電性連接於第二導電特徵140。也就是說,凸塊12設置於空間17中,以形成至少一子空間170(繪示為一個)。詳細而言,子空間170由兩個相鄰之凸塊12、第一半導體晶粒10的第一導電特徵100的一部位以及第二半導體晶粒14之第二導電特徵140的一部位環繞而形成。相對地,前述之兩個相鄰之凸塊12、第一導電特徵100的一部位以及第二導電特徵140的一部位環繞而形成封閉地環狀結構15。於本實施方式中,凸塊12為柱狀凸塊,但本案不以此為限。於其他實施方式中,凸塊12也可為球狀。舉例來說,多個凸塊12可為球柵式陣列(ball grid array,BGA)的形式。
於第2圖中,絕緣材料13位於第一半導體晶粒10與第二半導體晶粒14之間,且容置凸塊12。也就是說,第一半導體晶粒10與第二半導體晶粒14藉由凸塊12相互耦接,而其餘的空隙利用絕緣材料13填充。於本實施方式中,絕緣材料13為填充膠(filler),但本案不以此為限。
此外,本實施方式的第一半導體晶粒10的第一導電特徵100、多個凸塊12以及第二半導體晶粒14中的至少一者係接地或浮接。
於第1圖中,第一半導體晶粒10的第一導電特徵100位於第一電磁輻射源結構18與第二電磁輻射源結構19之間。此外,第二半導體晶粒14(見第2圖)的第二導電特徵140於第一半導體晶粒10上具有垂直投影,前述之垂直投影位於第一電磁輻射源結構18與第二電磁輻射源結構19之間。詳細而言,第一電磁輻射源結構18與第二電磁輻射源結構19分隔於第一半導體晶粒10之第一導電特徵100、該些凸塊12以及第二半導體晶粒14之第二導電特徵140的兩側。
於本實施方式中,第一電磁輻射源結構18以及第二電磁輻射源結構19分別為電感電容共振腔(LC tank),但本案不以此為限。於其他實施方式中,只要能產生電磁輻射的元件皆能應用於本揭露。舉例來說,第一電磁輻射源結構18以及第二電磁輻射源結構19也可為基於電感之轉換器。
於本實施方式中,第一電磁輻射源結構18以及第二電磁輻射源結構19設置於第一半導體晶粒10,但本案不限於此。於其他實施方式中,第一電磁輻射源結構18或第二電磁輻射源結構19之電感電容共振腔的電感部分與電容部分係分別設置於不同的晶粒,前述之不同的晶粒之間係相互耦接。舉例來說,前述之不同的晶粒可藉由直通矽晶穿孔導線(Through Silicon Via,TSV)及/或錫焊凸塊而彼此耦接,但本案不以此為限。
當第一電磁輻射源結構18或第二電磁輻射源結構19直接或是間接地產生電磁輻射,且此電磁輻射從環狀結構15的子空間170通過時,依據冷次定律(Lenz's law),環狀結構15會主動地在子空間170產生反向的感應磁場,以抑制第一電磁輻射源結構18或第二電磁輻射源結構19所產生的磁場通過子空間170,使通過子空間170內的整體磁場降低。藉由前述的結構配置,本實施方式可降低第一電磁輻射源結構18以及第二電磁輻射源結構19的電磁輻射,且可抑制第一電磁輻射源結構18以及第二電磁輻射源結構19的電磁輻射之間的耦合。
舉例來說,本實施方式之環狀結構15位於一平面上,前述之平面實質上垂直於第一半導體晶粒10。藉由上述結構配置,於電子裝置1運作時,第一半導體晶粒10上的第一電磁輻射源結構18與第二電磁輻射源結構19之間於垂直於前述之平面的方向上所產生的耦合會被環狀結構15所抑制。因此,第一電磁輻射源結構18與第二電磁輻射源結構19之間的耦合現象可被減弱,因而降低耦合現象對電子裝置1之效能的影響,藉此提升電子裝置1的運作效能。
請參照第3圖。第3圖繪示依據本案之一實施方式之電子裝置1的實驗數據圖。此實驗數據圖在於說明於不同頻率下,積體電路之電感之間的傳輸損耗(Insertion loss)。如第3圖所示,曲線m1為電子裝置1未採用環狀結構15的實驗數據。曲線m2為電子裝置1採用環狀結構15的驗證數據。由第3圖之實驗數據可知,曲線m2之耦合值較曲線m1之耦合值低,且曲線m1與曲線m2之間的耦合值可相差4dB。因此,藉由前 述之驗證數據可說明本案的電子裝置1可降低電感之間的耦合現象,並可降低電磁輻射之耦合現象對電子裝置1之效能的影響。然而,本案不以前述數值為限,任何習其技藝者可依據實際需求調整前述數值以達到最佳的效能。
請參照第4圖。第4圖繪示依據本案之一實施方式之電子裝置2的立體圖,其中省略繪示絕緣材料13以及第二半導體晶粒14。如第4圖所示,本實施方式之電子裝置2包含第一半導體晶粒10、多個凸塊22、第一電磁輻射源結構18以及第二電磁輻射源結構19。這些元件的結構、功能以及各元件之間的連接關係皆與第1圖及第2圖所示之電子裝置1大致相同,因此可參照前述相關說明,在此不再贅述。在此要說明的是,本實施方式與第1圖及第2圖所示之實施方式的差異之處,在於本實施方式中,電子裝置2的凸塊22數量繪示為四個,第一半導體晶粒10之第一導電特徵200連接凸塊22,且第二半導體晶粒14(圖未示)之第二導電特徵240連接凸塊22。因此,本實施方式以凸塊22、第一導電特徵200以及第二導電特徵240取代如第1圖及第2圖所示之凸塊12、第一導電特徵100以及第二導電特徵140。
於本實施方式中,多個凸塊22設置於空間17中,以形成多個子空間170(繪示為三個)。本實施方式的子空間170分別由多個凸塊22中相鄰之兩者、第一半導體晶粒10的第一導電特徵200的一部位以及第二半導體晶粒14的第二導電特徵240的一部位環繞而形成,且多個子空間170係彼此串連地排列。藉此,依據第一電磁輻射源結構18或第二電磁輻射源結 構19的電磁輻射範圍,多個子空間170可被串連以抑制第一電磁輻射源結構18與第二電磁輻射源結構19的電磁輻射之間的耦合。
請參照第5圖以及第6圖。第5圖繪示依據本案之一實施方式之電子裝置3的立體圖,其中省略繪示絕緣材料13、第二半導體晶粒14以及第三半導體晶粒16(見第6圖)。第6圖繪示沿著第5圖中線段B-B的剖視圖。如圖所示,本實施方式之電子裝置3包含第一半導體晶粒10、多個凸塊12、絕緣材料13(見第6圖)、第三半導體晶粒16(見第6圖)、第二半導體晶粒14(見第6圖)、第一電磁輻射源結構18以及第二電磁輻射源結構19。這些元件的結構、功能以及各元件之間的連接關係皆與第1圖及第2圖所示之電子裝置1大致相同,因此可參照前述相關說明,在此不再贅述。在此要說明的是,本實施方式與第1圖及第2圖所示之實施方式的差異之處,在於本實施方式中,電子裝置3更包含第三半導體晶粒16。
於本實施方式中,電子裝置3的第三半導體晶粒16位於第一半導體晶粒10與第二半導體晶粒14之間以形成三維堆疊架構,且包含多個導電接觸160以及第三導電特徵162。第三半導體晶粒16的第三導電特徵162連接導電接觸160。於其他實施方式中,第三導電特徵162可不配置於電子裝置3上。於一實施方式中,導電接觸160可為直通矽晶穿孔導線。然而,本案不限於半導體晶粒的個數或半導體晶粒的堆疊方式。舉例來說,本案的堆疊方式也可為二點五維積體電路(2.5D IC)堆疊架構。此外,於本實施方式中,不同的晶粒可由相同或不同的半導體製程所製造。
於第5圖以及第6圖中,多個凸塊12設置於第一半導體晶粒10,連接第一半導體晶粒10的第一導電特徵100,且分別接合第三半導體晶粒16的多個導電接觸160。也就是說,第一半導體晶粒10與第三半導體晶粒16藉由凸塊12相互耦接,而其餘的空隙利用絕緣材料13填充。此外,第三半導體晶粒16的導電接觸160電性連接第二半導體晶粒14的第二導電特徵140。因此,多個凸塊12分別經由第三半導體晶粒16的多個導電接觸160而電性連接第二半導體晶粒14的第二導電特徵140。
在前述結構配置下,至少一子空間370(繪示為一個)由第一半導體晶粒10的第一導電特徵100的一部位、兩個相鄰之凸塊12、第三半導體晶粒16的兩個相鄰之導電接觸160以及第二半導體晶粒14的第二導電特徵140的一部位環繞而形成。於本實施方式中,第三半導體晶粒16的第三導電特徵162與第一導電特徵100的一部位以及兩個相鄰之凸塊12環繞而形成子空間3700,而第三半導體晶粒16的第三導電特徵162與第二導電特徵140的一部位以及兩個相鄰之導電接觸160環繞而形成子空間3702。藉此,依據第一電磁輻射源結構18或第二電磁輻射源結構19的電磁輻射範圍,子空間370、3700以及3702可被設計以抑制第一電磁輻射源結構18與第二電磁輻射源結構19的電磁輻射之間的耦合。
請參照第7圖。第7圖繪示依據本案之一實施方式之電子裝置3之製造方法的流程圖。
儘管本文將所揭示電子裝置3的製造方法繪示及描述為一系列步驟或事件,但應瞭解到,並不以限制性意義解讀此類步驟或事件之所繪示次序。舉例而言,除本文繪示及/或描述之次序外,一些步驟可以不同次序發生及/或與其他步驟或事件同時發生。另外,實施本文描述之一或多個態樣或實施方式可並不需要全部繪示操作。進一步地,可在一或多個獨立步驟及/或階段中實施本文所描繪之步驟中的一或更多者。具體來說,電子裝置3的製造方法包含步驟1001至步驟1006。
於步驟1001中,形成至少一第一電磁輻射源結構18於第一半導體晶粒10上,且形成至少一第二電磁輻射源結構19於第一半導體晶粒10上。
於步驟1002中,形成第一導電特徵100於第一半導體晶粒10上。
於步驟1003中,形成多個凸塊12於第一半導體晶粒10,且第一導電特徵100電性連多個凸塊12。於本實施方式中,第一電磁輻射源結構18位於第一半導體晶粒10上之第一導電特徵100、多個凸塊12以及第二半導體晶粒14上之第二導電特徵140的一側。第二電磁輻射源結構19位於第一半導體晶粒10上之第一導電特徵100、多個凸塊12以及第二半導體晶粒14上之第二導電特徵140的另一側(見第5圖)。
於步驟1004中,將多個凸塊12分別電性連接第三半導體晶粒16上之多個導電接觸160。然而,於其他實施方式中,在未設置第三半導體晶粒16的情況下,可直接將多個凸塊12接合第二半導體晶粒14上之第二導電特徵140,以將凸塊12 電性連接第二導電特徵140。
於步驟1005中,將第三半導體晶粒16上多個導電接觸160電性連接至第二半導體晶粒14上之第二導電特徵140。
於步驟1006中,將第一半導體晶粒10上之第一導電特徵100、多個凸塊12、第二半導體晶粒14上之第二導電特徵140以及第三半導體晶粒16上多個導電接觸160中的至少一者接地或浮接。
上述關於本發明的觀念可以藉由半導體實現在任何積體電路中,包含射頻及/或同步時脈應用。例如可以將本發明實現在單獨的半導體設計中,或是實現在特定應用積體電路及/或任何其它子系統中。
雖然本發明已經結合一些實施例進行了說明,但本發明並不限定於此說明書中的特定形式闡述。相反地,本發明的範圍僅受到所附的權利要求限定。此外,雖然發明特徵可能係結合特定實施例來描述,但本領域的技術人員應當理解所描述的實施例的各種特徵可以根據本發明進行組合。
此外,特徵在權利要求中的順序並不意味著必須執行的任何特定順序,且方法權利要求中各個步驟的順序並不意味著這些步驟必須按照該順序來執行。相反地,可以以任何合適的順序來執行這些步驟。此外,單數引用不排除多個。因此,「一」、「第一」、「第二」等用語並不排除多個。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範 圍。
需注意的是,雖然「第一」、「第二」、「第三」等用語在文中用來描述各種元件,但這些被描述的元件不應被此類用語所限制。此類用語僅用於從一個元件區分另一個元件。因此,以下所討論之「第一」元件皆能被寫作「第二」元件,而不偏離本發明之教示。
Claims (10)
- 一種電子裝置,包含:一第一半導體晶粒,包含一第一導電特徵;複數個凸塊,設置於該第一半導體晶粒,並連接該第一導電特徵;以及一基材,包含一第二導電特徵,其中該些凸塊係電性連接於該第二導電特徵,且該第一導電特徵、該些凸塊以及該第二導電特徵係配置以形成至少一環狀結構。
- 如請求項1所述之電子裝置,其中該些凸塊係接合該第二導電特徵。
- 如請求項1所述之電子裝置,更包含一第三半導體晶粒,該第三半導體晶粒位於該第一半導體晶粒與該基材之間,且該些凸塊經由該第三半導體晶粒而電性連接該第二導電特徵。
- 如請求項3所述之電子裝置,其中該第三半導體晶粒包含複數個導電接觸,該些凸塊分別經由該些導電接觸電性連接該第二導電特徵。
- 如請求項1所述之電子裝置,其中該第一導電特徵與該第二導電特徵之間具有一空間,該些凸塊設置於該空間中以形成至少一子空間,該子空間由該些凸塊中相鄰的兩者、該第一導電特徵的一部位以及該第二導電特徵的一部位環繞而形成。
- 如請求項1所述之電子裝置,其中該第一導電特徵、該些凸塊以及該基材中的至少一者係接地。
- 如請求項1所述之電子裝置,更包含:一第一電磁輻射源結構,設置於該第一半導體晶粒;以及一第二電磁輻射源結構,設置於該第一半導體晶粒,其中該第一導電特徵位於該第一電磁輻射源結構與該第二電磁輻射源結構之間。
- 如請求項7所述之電子裝置,其中該第一電磁輻射源結構與該第二電磁輻射源結構分隔於該第一導電特徵與該些凸塊以及該第二導電特徵的兩側。
- 一種電子裝置的製造方法,包含:形成一第一導電特徵以及複數個凸塊於一第一半導體晶粒,且該第一導電特徵電性連接該些凸塊;以及將該些凸塊電性連接一基材上之一第二導電特徵,使得該第一導電特徵、該些凸塊以及該第二導電特徵形成至少一環狀結構。
- 如請求項9所述之電子裝置的製造方法,其中該將該些凸塊電性連接一基材上之一第二導電特徵包含:將該些凸塊分別電性連接一第三半導體晶粒上之複數個導電接觸;以及將該些導電接觸電性連接至該第二導電特徵。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW106114509A TWI660483B (zh) | 2017-05-02 | 2017-05-02 | 電子裝置及其製造方法 |
US15/925,792 US10504853B2 (en) | 2017-05-02 | 2018-03-20 | Electronic device capable of suppressing electromagnetic radiation and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW106114509A TWI660483B (zh) | 2017-05-02 | 2017-05-02 | 電子裝置及其製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201843797A TW201843797A (zh) | 2018-12-16 |
TWI660483B true TWI660483B (zh) | 2019-05-21 |
Family
ID=64014222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW106114509A TWI660483B (zh) | 2017-05-02 | 2017-05-02 | 電子裝置及其製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10504853B2 (zh) |
TW (1) | TWI660483B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111199926B (zh) * | 2019-10-29 | 2021-08-17 | 浙江大学 | 一种带有微隔腔的半导体封装结构 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130049826A1 (en) * | 2011-08-25 | 2013-02-28 | International Business Machines Corporation | 3d chip stack skew reduction with resonant clock and inductive coupling |
TW201715706A (zh) * | 2015-10-30 | 2017-05-01 | 瑞昱半導體股份有限公司 | 積體電路 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9213797B2 (en) * | 2013-11-15 | 2015-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method, system and computer program product for designing semiconductor device |
TWI524658B (zh) * | 2014-06-30 | 2016-03-01 | 瑞昱半導體股份有限公司 | 能抑制自身電磁輻射的電感電容共振腔及其製造方法 |
TWI575695B (zh) | 2014-10-21 | 2017-03-21 | 瑞昱半導體股份有限公司 | 電子裝置和電磁輻射抑制方法 |
TWI690043B (zh) * | 2016-02-17 | 2020-04-01 | 瑞昱半導體股份有限公司 | 積體電路裝置 |
US10381541B2 (en) * | 2016-10-11 | 2019-08-13 | Massachusetts Institute Of Technology | Cryogenic electronic packages and methods for fabricating cryogenic electronic packages |
-
2017
- 2017-05-02 TW TW106114509A patent/TWI660483B/zh active
-
2018
- 2018-03-20 US US15/925,792 patent/US10504853B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130049826A1 (en) * | 2011-08-25 | 2013-02-28 | International Business Machines Corporation | 3d chip stack skew reduction with resonant clock and inductive coupling |
TW201715706A (zh) * | 2015-10-30 | 2017-05-01 | 瑞昱半導體股份有限公司 | 積體電路 |
Also Published As
Publication number | Publication date |
---|---|
TW201843797A (zh) | 2018-12-16 |
US10504853B2 (en) | 2019-12-10 |
US20180323154A1 (en) | 2018-11-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9693461B2 (en) | Magnetic-core three-dimensional (3D) inductors and packaging integration | |
US10256286B2 (en) | Integrated inductor for integrated circuit devices | |
TWI611437B (zh) | 無基板個別耦合電感器結構、電感器結構設備及用於提供電感器結構之方法 | |
JP6476132B2 (ja) | 基板内結合インダクタ構造 | |
US20170092594A1 (en) | Low profile package with passive device | |
TWI646649B (zh) | 具有電感的組件及其封裝結構 | |
US20190004571A1 (en) | Device comprising compressed thermal interface material (tim) and electromagnetic (emi) shield comprising flexible portion | |
JP2017510075A (ja) | 半導体パッケージにおけるはんだボール接続でのフェースアップ基板集積化 | |
TWI575695B (zh) | 電子裝置和電磁輻射抑制方法 | |
TWI660483B (zh) | 電子裝置及其製造方法 | |
US20150137342A1 (en) | Inductor/transformer outside of silicon wafer | |
JP6306707B2 (ja) | 基板上の集積受動デバイス(ipd) | |
TWI499011B (zh) | 封裝結構及其製作方法 | |
CN108878399B (zh) | 电子装置及其制造方法 | |
US20160300660A1 (en) | Electronic device | |
JP2007299887A (ja) | 半導体集積回路素子搭載用基板および半導体装置 | |
TWI828378B (zh) | 電源設計架構 | |
JP6083143B2 (ja) | チップインダクタ内蔵配線基板 | |
WO2020155478A1 (zh) | 集成电感结构和集成电路 | |
CN105555108B (zh) | 电子装置和电磁辐射抑制方法 | |
US20150243574A1 (en) | Semiconductor package and fabrication method thereof | |
JP2016119322A (ja) | 半導体装置 | |
TW201541604A (zh) | 具有線路式電子元件的封裝結構及其製造方法 |