CN111199926B - 一种带有微隔腔的半导体封装结构 - Google Patents
一种带有微隔腔的半导体封装结构 Download PDFInfo
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- CN111199926B CN111199926B CN201911036792.7A CN201911036792A CN111199926B CN 111199926 B CN111199926 B CN 111199926B CN 201911036792 A CN201911036792 A CN 201911036792A CN 111199926 B CN111199926 B CN 111199926B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Materials Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
Claims (3)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911036792.7A CN111199926B (zh) | 2019-10-29 | 2019-10-29 | 一种带有微隔腔的半导体封装结构 |
PCT/CN2020/100509 WO2021082510A1 (zh) | 2019-10-29 | 2020-07-07 | 一种带有微隔腔的半导体封装结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911036792.7A CN111199926B (zh) | 2019-10-29 | 2019-10-29 | 一种带有微隔腔的半导体封装结构 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111199926A CN111199926A (zh) | 2020-05-26 |
CN111199926B true CN111199926B (zh) | 2021-08-17 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201911036792.7A Active CN111199926B (zh) | 2019-10-29 | 2019-10-29 | 一种带有微隔腔的半导体封装结构 |
Country Status (2)
Country | Link |
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CN (1) | CN111199926B (zh) |
WO (1) | WO2021082510A1 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111199926B (zh) * | 2019-10-29 | 2021-08-17 | 浙江大学 | 一种带有微隔腔的半导体封装结构 |
CN112838366B (zh) * | 2020-12-31 | 2024-02-20 | 中国电子科技集团公司第四十三研究所 | 一种多通道表贴式t/r组件 |
CN113224033A (zh) * | 2021-04-23 | 2021-08-06 | 中国电子科技集团公司第二十九研究所 | 一种基于bga封装的收发模块 |
CN114373741B (zh) * | 2022-03-08 | 2023-07-18 | 荣耀终端有限公司 | 模组、晶粒、晶圆和晶粒的制造方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6931723B1 (en) * | 2000-09-19 | 2005-08-23 | International Business Machines Corporation | Organic dielectric electronic interconnect structures and method for making |
US7173498B2 (en) * | 2004-09-28 | 2007-02-06 | Texas Instruments Incorporated | Reducing the coupling between LC-oscillator-based phase-locked loops in flip-chip ASICs |
US20070023203A1 (en) * | 2005-07-26 | 2007-02-01 | Leizerovich Gustavo D | Method and system for customized radio frequency shielding using solder bumps |
CN100555628C (zh) * | 2007-10-30 | 2009-10-28 | 日月光半导体制造股份有限公司 | 具有电磁屏蔽功能的半导体封装结构 |
US9368457B2 (en) * | 2012-03-07 | 2016-06-14 | Mitsubishi Electric Corporation | High-frequency package |
CN103137609B (zh) * | 2013-03-04 | 2015-12-09 | 华进半导体封装先导技术研发中心有限公司 | 带有电磁屏蔽结构的集成电路封装结构 |
TWI619234B (zh) * | 2015-10-30 | 2018-03-21 | 瑞昱半導體股份有限公司 | 積體電路 |
US10396036B2 (en) * | 2015-12-26 | 2019-08-27 | Intel Corporation | Rlink-ground shielding attachment structures and shadow voiding for data signal contacts of package devices; vertical ground shielding structures and shield fencing of vertical data signal interconnects of package devices; and ground shielding for electro optical module connector data signal contacts and contact pins of package devices |
CN106169428B (zh) * | 2016-08-31 | 2018-08-31 | 华天科技(昆山)电子有限公司 | 用于减缓电磁干扰的芯片封装结构及封装方法 |
CN106783847A (zh) * | 2016-12-21 | 2017-05-31 | 中国电子科技集团公司第五十五研究所 | 针对射频微系统器件的三维键合堆叠互连集成制造方法 |
TWI660483B (zh) * | 2017-05-02 | 2019-05-21 | 瑞昱半導體股份有限公司 | 電子裝置及其製造方法 |
CN110012596A (zh) * | 2019-05-09 | 2019-07-12 | 苏州浪潮智能科技有限公司 | 一种基于电磁能隙ebg结构的印刷电路板及其设计方法 |
CN111199926B (zh) * | 2019-10-29 | 2021-08-17 | 浙江大学 | 一种带有微隔腔的半导体封装结构 |
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2019
- 2019-10-29 CN CN201911036792.7A patent/CN111199926B/zh active Active
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2020
- 2020-07-07 WO PCT/CN2020/100509 patent/WO2021082510A1/zh active Application Filing
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CN111199926A (zh) | 2020-05-26 |
WO2021082510A1 (zh) | 2021-05-06 |
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Inventor after: Xu Zhiwei Inventor after: Gao Huiyan Inventor after: Li Min Inventor after: Li Nayu Inventor after: Zhang Zijiang Inventor after: Wang Shaogang Inventor after: Song Chunyi Inventor before: Xu Zhiwei Inventor before: Gao Huiyan Inventor before: Li Min Inventor before: Li Nayu Inventor before: Zhang Zijiang Inventor before: Wang Shaogang |
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Effective date of registration: 20230307 Address after: 316000 Room 202, 11 Baichuan Road, Lincheng street, Dinghai District, Zhoushan City, Zhejiang Province (centralized office) Patentee after: ZHEJIANG JISU HEXIN TECHNOLOGY CO.,LTD. Address before: 310058 Yuhang Tang Road, Xihu District, Hangzhou, Zhejiang 866 Patentee before: ZHEJIANG University |
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Effective date of registration: 20230703 Address after: Plant 1, No. 13, Guiyang Avenue, Yantai Economic and Technological Development Zone, Shandong Province, 264000 Patentee after: Yantai Xin Yang Ju Array Microelectronics Co.,Ltd. Address before: 316000 Room 202, 11 Baichuan Road, Lincheng street, Dinghai District, Zhoushan City, Zhejiang Province (centralized office) Patentee before: ZHEJIANG JISU HEXIN TECHNOLOGY CO.,LTD. |
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