CN111199926B - 一种带有微隔腔的半导体封装结构 - Google Patents

一种带有微隔腔的半导体封装结构 Download PDF

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CN111199926B
CN111199926B CN201911036792.7A CN201911036792A CN111199926B CN 111199926 B CN111199926 B CN 111199926B CN 201911036792 A CN201911036792 A CN 201911036792A CN 111199926 B CN111199926 B CN 111199926B
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徐志伟
高会言
厉敏
李娜雨
张梓江
王绍刚
宋春毅
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Yantai Xin Yang Ju Array Microelectronics Co ltd
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Abstract

本发明公开一种带有微隔腔的半导体封装结构,包括多通道或多模块的半导体芯片、导热基板、固定填充物、金属焊球、金属布线层、介质层、过孔。导热基板上有略大于芯片的凹槽,芯片以倒片摆放的方式放入凹槽并与导热基板粘接,芯片焊盘通过金属焊球与下方层压电路板连接。层压电路板有多层金属布线层,金属布线层由介质层隔开,不同金属布线层之间使用过孔互连。芯片按照通道或模块划分成不同的区域,每个区域的周围边界上紧密排布金属焊球,由芯片、金属焊球和层压电路板形成有效降低通道间或模块间电磁耦合的微隔腔结构。本发明减小封装的体积,降低信号在互连线上的传输损耗,有效提高芯片通道或模块间的隔离度,提升了系统的性能。

Description

一种带有微隔腔的半导体封装结构
技术领域
本发明涉及集成电路封装技术领域,具体涉及一种带有微隔腔的半导体封装结构。
背景技术
相控阵列技术是通信领域中提升频谱效率、增加传输速率、提高可靠性的关键技术。为了支持阵列化天线应用,射频收发芯片集成了多个通道,每个射频收发通道会受到同一芯片上其他通道电磁干扰的影响。具体而言,射频集成电路的接收电路容易受到外界电磁信号的干扰,如低噪声放大器对外部电磁波和衬底串扰非常敏感;发射电路则会产生电磁干扰信号,如功率驱动器会向外发射不需要的电磁波并向衬底注入串扰信号;部分射频电路既对外界的电磁串扰信号敏感,又会产生电磁干扰信号,如压控振荡器。过去的系统通常采用电磁屏蔽罩增加隔离度,但这只适用于芯片间的隔离,无法增加芯片内通道间的隔离度,同时这种方案也增加了系统的复杂度和重量。
半导体芯片内通道间隔离度还会受到封装工艺的影响。目前常用的高性能芯片封装工艺包括引线键合封装、球栅阵列封装等。引线键合封装技术通过金属棒线连接芯片焊盘和封装基板,但是较长的棒线会增加信号的衰减,降低系统集成度,引入的寄生效应会使芯片的性能大打折扣。在多通道射频收发芯片中,相邻通道射频信号棒线之间的电磁耦合效应会降低通道间隔离度,恶化系统性能。另一种常见封装技术,球栅阵列封装,具有体积小、引脚密度高、电性能好的优点,主要应用于输入输出引脚密集的数字和模拟集成电路。随着集成度的提高,射频收发芯片的引脚数量也逐渐增加,但采用传统封装技术难以保证片内通道间隔离度。针对高集成度多通道或多模块射频芯片,改进现有封装工艺改善隔离度的需求显的尤为迫切。
发明内容
针对现有技术的不足,本发明提出一种带有微隔腔的半导体封装结构,该结构引脚密度高、封装寄生小、通道间隔离度高。
本发明的目的通过如下技术方案来实现:
一种带有微隔腔的半导体封装结构,其特征在于,所述的半导体封装结构包括多通道或多模块的半导体芯片、导热基板、固定填充物、金属焊球、层压电路板,所述的导热基板上形成略大于芯片的长方形凹槽,在其侧壁和顶面加入固定填充物用于半导体芯片和导热基板的粘接,所述的半导体芯片采用倒片摆放的方式粘接在所述的导热基板的腔体中,所述的半导体芯片焊盘方向向下连接所述的金属焊球,所述的金属焊球另一侧连接层压电路板,所述的层压电路板包括金属布线层M1、M2、……、Mn、介质层IMD1、IMD2、……、IMD(n-1)、连接不同金属布线层的过孔,相邻的金属布线层由介质层隔开,任意两层或多层金属布线层之间均通过过孔相连;
所述的多通道或多模块芯片的焊盘连接金属焊球,并与层压电路顶层的金属布线层M1相连;在芯片上按照通道或模块的不同划分成不同的区域,形成通道或模块1、通道或模块2、……、通道或模块n等;在每个区域的周围边界上紧密排布金属焊球,由此芯片、金属焊球和层压电路板形成有效降低通道间或模块间电磁耦合的微隔腔结构。
进一步地,所述的介质层由两种不同材料的介质层组成,由介质一形成的介质层和由介质二形成的介质层相间排列,层压电路板的顶层和底层的材料为介质一,在由介质一形成的介质层内部或表面形成金属布线层,在由介质二形成的介质层内部不形成金属布线层。
进一步地,所述的金属布线层材料为铜,所述的金属焊球材料为铜锡银合金。
本发明的有益效果如下:
本发明将倒放芯片通过金属焊球与层压电路板连接,提高引脚密度,缩小封装尺寸,减轻整体重量,降低互连线的传输损耗,改善射频系统的性能。在通道或模块边界紧密排列的金属焊球、芯片和层压电路板形成了微隔腔结构,将所述通道电路产生的电、磁干扰信号限制在微隔腔内部,从而减少芯片各模块间的耦合和串扰,提高了通道间隔离度。
附图说明
图1为本发明的一种带有微隔腔的半导体封装结构的剖面结构示意图。
图2为本发明的一种带有微隔腔的半导体封装结构的芯片仰视图。
具体实施方式
下面根据附图和优选实施例详细描述本发明,本发明的目的和效果将变得更加明白,通过结合附图和实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
如图1所示,本发明的一种带有微隔腔的半导体封装结构的剖面结构示意图,所述的倒片封装微隔腔结构包括导热基板、固定填充物、集成电路芯片、金属焊球、金属布线层M1、M2、……、Mn、介质层IMD1、IMD2、……、IMD(n-1)、连接不同金属布线层的过孔。在导热基板下面形成大小略大于芯片的长方形凹槽,在其侧壁和顶面加入固定填充物用于芯片和基板的粘接,集成电路芯片采用倒片摆放的方式粘接在导热基板的腔体中。芯片焊盘方向向下连接金属焊球,金属焊球另一侧连接层压电路板的金属布线层M1,芯片下方层压了n-1层介质层,每层介质层上下两侧均连接有金属布线层,形成了总共n层金属布线层。任意两层或多层金属布线层之间均通过过孔相连。
优选地,层压电路板的介质层由两种不同材料的介质层组成,由介质一形成的介质层和由介质二形成的介质层相间排列。层压电路板的顶层和底层的材料为介质一,在由介质一形成的介质层内部或表面形成金属布线层;在由介质二形成的介质层内部不形成金属布线层。
图2为本发明的一种带有微隔腔的半导体封装结构的芯片仰视图。多通道或多模块芯片的焊盘上连接金属焊球,并与层压电路顶层的金属布线层M1相连。在芯片上按照通道或模块的不同划分成不同的区域,形成通道或模块1、通道或模块2、……、通道或模块n等。在每个区域的周围边界上紧密排布金属焊球,由此芯片、金属焊球和层压电路板形成了可以有效降低通道间或模块间电磁耦合的微隔腔结构。
优选地,所述的金属布线层材料为铜,所述的金属焊球材料为铜锡银合金。
本领域普通技术人员可以理解,以上所述仅为发明的优选实例而已,并不用于限制发明,尽管参照前述实例对发明进行了详细的说明,对于本领域的技术人员来说,其依然可以对前述各实例记载的技术方案进行修改,或者对其中部分技术特征进行等同替换。凡在发明的精神和原则之内,所做的修改、等同替换等均应包含在发明的保护范围之内。

Claims (3)

1.一种带有微隔腔的半导体封装结构,其特征在于,所述的半导体封装结构包括多通道或多模块的半导体芯片、导热基板、固定填充物、金属焊球、层压电路板,所述的导热基板上形成略大于芯片的长方形凹槽,在其侧壁和顶面加入固定填充物用于半导体芯片和导热基板的粘接,所述的半导体芯片采用倒片摆放的方式粘接在所述的导热基板的腔体中,所述的半导体芯片焊盘方向向下连接所述的金属焊球,所述的金属焊球另一侧连接层压电路板,所述的层压电路板包括金属布线层M1、M2、……、Mn、介质层IMD1、IMD2、……、IMD(n-1)、连接不同金属布线层的过孔,相邻的金属布线层由介质层隔开,任意两层或多层金属布线层之间均通过过孔相连;
所述的多通道或多模块芯片的焊盘连接金属焊球,并与层压电路顶层的金属布线层M1相连;在芯片上按照通道或模块的不同划分成不同的区域,形成通道或模块1、通道或模块2、……、通道或模块n;在每个区域的周围边界上紧密排布金属焊球,由此芯片、金属焊球和层压电路板形成有效降低通道间或模块间电磁耦合的微隔腔结构。
2.根据权利要求1所述的一种带有微隔腔的半导体封装结构,其特征在于,所述的介质层由两种不同材料的介质层组成,由介质一形成的介质层和由介质二形成的介质层相间排列,层压电路板的顶层和底层的材料为介质一,在由介质一形成的介质层内部或表面形成金属布线层,在由介质二形成的介质层内部不形成金属布线层。
3.根据权利要求1所述的一种带有微隔腔的半导体封装结构,其特征在于,所述的金属布线层材料为铜,所述的金属焊球材料为铜锡银合金。
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CN111199926B (zh) * 2019-10-29 2021-08-17 浙江大学 一种带有微隔腔的半导体封装结构
CN112838366B (zh) * 2020-12-31 2024-02-20 中国电子科技集团公司第四十三研究所 一种多通道表贴式t/r组件
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Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6931723B1 (en) * 2000-09-19 2005-08-23 International Business Machines Corporation Organic dielectric electronic interconnect structures and method for making
US7173498B2 (en) * 2004-09-28 2007-02-06 Texas Instruments Incorporated Reducing the coupling between LC-oscillator-based phase-locked loops in flip-chip ASICs
US20070023203A1 (en) * 2005-07-26 2007-02-01 Leizerovich Gustavo D Method and system for customized radio frequency shielding using solder bumps
CN100555628C (zh) * 2007-10-30 2009-10-28 日月光半导体制造股份有限公司 具有电磁屏蔽功能的半导体封装结构
US9368457B2 (en) * 2012-03-07 2016-06-14 Mitsubishi Electric Corporation High-frequency package
CN103137609B (zh) * 2013-03-04 2015-12-09 华进半导体封装先导技术研发中心有限公司 带有电磁屏蔽结构的集成电路封装结构
TWI619234B (zh) * 2015-10-30 2018-03-21 瑞昱半導體股份有限公司 積體電路
US10396036B2 (en) * 2015-12-26 2019-08-27 Intel Corporation Rlink-ground shielding attachment structures and shadow voiding for data signal contacts of package devices; vertical ground shielding structures and shield fencing of vertical data signal interconnects of package devices; and ground shielding for electro optical module connector data signal contacts and contact pins of package devices
CN106169428B (zh) * 2016-08-31 2018-08-31 华天科技(昆山)电子有限公司 用于减缓电磁干扰的芯片封装结构及封装方法
CN106783847A (zh) * 2016-12-21 2017-05-31 中国电子科技集团公司第五十五研究所 针对射频微系统器件的三维键合堆叠互连集成制造方法
TWI660483B (zh) * 2017-05-02 2019-05-21 瑞昱半導體股份有限公司 電子裝置及其製造方法
CN110012596A (zh) * 2019-05-09 2019-07-12 苏州浪潮智能科技有限公司 一种基于电磁能隙ebg结构的印刷电路板及其设计方法
CN111199926B (zh) * 2019-10-29 2021-08-17 浙江大学 一种带有微隔腔的半导体封装结构

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