TWI499011B - 封裝結構及其製作方法 - Google Patents

封裝結構及其製作方法 Download PDF

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TWI499011B
TWI499011B TW100104395A TW100104395A TWI499011B TW I499011 B TWI499011 B TW I499011B TW 100104395 A TW100104395 A TW 100104395A TW 100104395 A TW100104395 A TW 100104395A TW I499011 B TWI499011 B TW I499011B
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Taiwan
Prior art keywords
package structure
connection pads
wafer unit
wafer
electrically connected
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TW100104395A
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English (en)
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TW201234541A (en
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Yuan Tai Lai
Jeng Gong Duh
Yu Huei Lee
Ke Horng Chen
Kang Sheng
Tsung Chan Wu
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Nat Univ Tsing Hua
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Priority to TW100104395A priority Critical patent/TWI499011B/zh
Priority to US13/111,383 priority patent/US20120205778A1/en
Publication of TW201234541A publication Critical patent/TW201234541A/zh
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Publication of TWI499011B publication Critical patent/TWI499011B/zh

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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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Description

封裝結構及其製作方法
本發明係關於一種封裝結構及其製作方法，尤指一種薄型化之堆疊式之三維封裝結構，俾能改善被動元件於封裝時佔據電路板過多的面積，降低電路板使用面積，提升封裝密度。
拜科技所賜，電子產品日新月異，例如平面電腦，智慧型手機等消費性電子產品無不推陳出新，一種電子產品通常需具備多種功能以滿足消費者不同的需求。
為滿足消費者不同的需求，電子產品內部的電路板上便需要整合更多的晶片來完成不同的功能。例如，為滿足消費者無線上網的需求，則電路板上即需設置負責無線網路功能的晶片，而若需要視訊功能方面的產品，則電路板上即需設置負責視訊功能的晶片等。而除了必需將各種不同功能的晶片整合於電路板外，電路板上更無法缺少必要的被動元件，如電阻，電感，或電容。
以往，業界常用表面黏著式封裝技術(Surface Mounted Technology)將一被動元件(如電阻，電感，或電容)直接黏著於電路板上。，然而，目前電子產品皆朝向微小化(電子產品趨向輕、薄、短、小)的趨勢，而以表面黏著式封裝技術將被動元件直接黏著於電路板上確往往在電路板上常佔據相當大的面積，一但被動元件的封裝量上升，勢必佔用 更多的電路板面積，使得電子產品整體的大小無法適度的縮小，與目前電子產品日趨微小化的趨勢背道而馳，因而迫使業界必須對現有的封裝技術做出改善。
本發明之主要目的係在提供一種封裝結構，係將原本設置於電路板上之一被動元件，直接堆疊於晶片上(利用晶片背面之空間將被動元件與晶片整合)，如此可改善被動元件佔據電路板過多面積的問題，俾能大幅節省電路板之使用面積，並再藉由適當的調整，以克服將被動元件直接堆疊於晶片所產生之問題。
為達成上述目的，本發明之封裝結構，包括：一電路板，係具有一第一表面，該第一表面上係設置有複數個第一連接墊；一晶片單元，具有一主動面及一非主動面，該主動面設置有複數個第二連接墊及複數個電極墊，該非主動面設置有複數個第三連接墊，該晶片單元具有複數個導電孔，該些導電孔係貫穿該晶片單元且分別與該些第二連接墊及該些第三連接墊電性連接；複數個焊球，係電性連接該些第一連接墊及該些第二連接墊；以及一被動元件，係設置於該晶片單元之非主動面上，且與該晶片單元之該些第三連接墊電性連接；其中，該被動元件係透過該些第三連接墊、該些導電孔、該些電極墊與該晶片單元電性連接，該晶片單元係透過該些第二連接墊、該些焊球、該些第一連接墊與該電路板電性連接。
首先，如記載於先前技術中之說明，以往晶片單元與電路板之間係以磅線連接，其中磅線所形成之線弧高度約為10至15密爾(mil)，再者，晶片單元上連接有磅線之表面的面積亦較小，若直接將被動元件以一三維封裝方式直接堆疊於晶片單元上，容易將磅線壓斷或使磅線損毀，造成信號傳導上的阻礙，故若欲將被動元件直接堆疊於晶片單元上亦存在著電性連接的困難。
為此，為改善習知磅線斷線之問題，本發明之封裝結構係利用矽穿孔(Through-Silicon Via)封裝技術取代原有之磅線連接，於晶片單元上直接形成穿孔並貫穿晶片單元，形成穿孔之方法並無限制，其可為雷射鑽孔(Laser Drill)Bosch、深反應性離子蝕刻(Bosch DRIE)、或低温型深反應性離子蝕刻(Cryogenic DRIE)。並再配合球格陣列(Ball Grid Array)技術，以焊球連接晶片單元與電路板。如此，藉由矽穿孔封裝技術與球格陣列技術的使用，堆疊於晶片單元上之被動元件可與晶片單元電性連接，而晶片單元可與電路板電性連接。
再者，本發明之封裝結構中，被動元件並無限制為何種電路元件，其可為電感、電阻、亦或是電容。任何被動元件皆更適用於本發明之封裝結構中，直接以堆疊之方式整合於晶片上。
此外，本發明之封裝結構中之晶片單元係為一電力轉換晶片，例如一直流-直流(DC-to-DC)轉換晶片、一交流- 直流(AC-to-DC)轉換晶片、一直流-交流(DC-to-AC)轉換晶片、或一交流-交流(AC-to-AC)轉換晶片。
若本發明之封裝結構中之被動元件為一電感元件，其電感元件之形式並無任何限制，較佳可為一鐵氧體功率電感。鐵氧體功率電感因電感特性而於電感外部產生磁場，即產生漏磁，若將鐵氧體功率電感直接堆疊於晶片上，其產生之外部磁場即有可能對晶片產干擾，對晶片產生相當大的雜訊，在高密度封裝結構下，此一磁場將對晶片產生相當巨大的影響。本發明之封裝結構係針對此一問題做堆疊方式之改良，並再將鐵氧體功率電感填充一磁性材料或樹脂，以磁性材料或樹脂之特性導引外部磁場，縮減磁通分佈範圍。上述之磁性材料並無限制，其可為鐵磁性物質或亞鐵磁性物質所構成之磁性材料。
由上述可知，本發明之封裝結構係為一堆疊結構，由下至上係為：電路板，第一連接墊，焊球，第二連接墊，晶片，被動元件。於本發明之封裝結構中，此一堆疊高度係因應薄型封裝之趨勢，其堆疊高係介於1公厘到2公厘之間。
再者，本發明之封裝結構中，焊球之材料較佳係由錫所構成。此外，本發明之封裝結構中，導電孔係因其內填充有導電材料或設置有其他導電裝置而具有導電功能。導電材料係由銅、多晶矽、或鎢所組成。
此外，本發明之封裝結構中，被動元件可為一薄膜式被動元件，其形成方法可直接以微影製程技術於晶片單元 之非主動面上形成一薄膜式被動元件，例如以黃光微影製程技術(Photolithography Process)，將光罩薄膜式被動元件之圖形轉移至晶片單元之非主動面上，此一薄膜式被動元件可更縮減本發明之封裝結構的堆疊高度。再者，此一薄膜式被動元件可為薄膜電感、薄膜電容、或薄膜電阻，其較佳為一薄膜電感。需注意的是，薄膜式被動元件可與上述之第三連接墊電性連接，或不透過第三連接墊，而直接與上述之導電孔電性連接(即非之動面上不需設置第三連接墊)。
本發明更提供一種封裝結構之製作方法，係包括：(A)提供一電路板，其具有一第一表面，該第一表面上係設置有複數個第一連接墊；(B)提供一晶片單元，其具有一主動面及一非主動面，該主動面設置有複數個第二連接墊及複數個電極墊，該非主動面設置有複數個第三連接墊，該晶片單元具有複數個導電孔，而該些導電孔係貫穿該晶片單元且分別與該些第二連接墊及該些第三連接墊電性連接；(C)以焊球電性連接該第一連接墊及該第二連接墊；以及(D)提供一被動元件，係設置於該晶片單元之非主動面上，且與該晶片單元之該些第三連接墊上電性連接。
首先，如記載於先前技術中之說明，以往晶片單元與電路板之間係以磅線連接，其中磅線所形成之線弧高度約為10至15密爾(mil)，再者，晶片單元上連接有磅線之表面的面積亦較小，若直接將被動元件以三維封裝方式直接堆疊於晶片單元上，容易將磅線壓斷或使磅線損毀，造成 信號傳導上的阻礙，故若欲將被動元件直接堆疊於晶片單元上亦存在著電性連接的困難。
為此，本發明提供之封裝結構之製作方法係利用矽穿孔(Through-Silicon Via)封裝技術取代原有之磅線，於晶片單元上直接穿孔並貫穿晶片單元，並再配合球格陣列(ball grid array)技術，以焊球連接晶片單元與電路板。堆疊於晶片單元上之被動元件可與晶片單元電性連接。
再者，於上述步驟(D)中，該被動元件並無限制為何種電路元件，其可為電感、電阻、亦或是電容。任何被動元件皆更適用於本發明之封裝結構中，直接以堆疊之方式整合於晶片上。
此外，於上述步驟(C)中，晶片單元係為一電力轉換晶片，例如一直流-直流(DC-to-DC)轉換晶片、一交流-直流(AC-to-DC)轉換晶片、一直流-交流(DC-to-AC)轉換晶片、或一交流-交流(AC-to-AC)轉換晶片。
再者，若本發明之封裝結構之製作方法中，被動元件為一電感元件，其電感元件之形式並無任何限制，較佳可為一鐵氧體功率電感。鐵氧體功率電感因電感特性而於電感外部產生磁場，即產生漏磁，若鐵氧體功率電感直接堆疊於晶片上，其產生之外部磁場即有可能對晶片產干擾，對晶片產生相當的雜訊，在高密度封裝結構下，此一磁場將對晶片產生相當巨大的影響。本發明之封裝結構係針對此一問題做堆疊方式之改良，並再將鐵氧體功率電感填充一磁性材料或樹脂，以磁性材料或樹脂之特性導引外部磁 場，縮減磁通分佈範圍。上述之磁性材料並無限制，其可為鐵磁性物質或亞鐵磁性物質所構成之磁性材料。
由上述封裝結構之製作方法可知，本發明之封裝結構係為一堆疊結構，由下至上係為：電路板，第一連接墊，焊球，第二連接墊，晶片，被動元件。於本發明之封裝結構中，此一堆疊高度係因應薄型封裝之趨勢，其堆疊高係介於1公厘到2公厘之間。
再者，於上述封裝結構之製作方法中，焊球之材料較佳係由錫所構成。此外，本發明之封裝結構中，導電孔係因其內填充有導電材料或設置有其他導電裝置而具有導電功能。導電材料係由銅、多晶矽、或鎢所組成。
以下係藉由特定的具體實施例說明本發明之實施方式，熟習此技藝之人士可由本說明書所揭示之內容輕易地了解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實施例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。
本發明之封裝結構於實現上所面臨的問題，將一併在實施方式中詳細說明其改善方法，以說明本發明確實能有效改善三維封裝所面臨的問題，提供業界一種有效的封裝結構。而在說明本發明之發明之前，請對照先前技術中所 記載之內容，本發明之主要目的係在提供一種封裝結構以節省電路板的使用面積。
改變封裝方式為最直接且大幅改善現有缺失的因應對策，例如將被動元件直接整合於電力轉換晶片上，以減少被動元件在電路板上所佔據的面積，上述之將被動元件直接整合於電力轉換晶片上之概念即為將被動元件直接堆疊於電力轉換晶片上，因此，本發明即因此一三維式的封裝方法因應而生。然而，在實現將一被動元件直接堆疊於電力轉換晶片上的三維式的封裝方法確也衍生出許多問題，以下將搭配圖示說明。
請參閱圖1A，圖1A係三維封裝結構第一缺陷示意圖。如圖1A所示，一晶片單元11以表面黏著式封裝技術設置於一電路板12上，再者，晶片單元11以磅線13與電路板12電性連接，此時，若將一被動元件14直接堆疊的方式以整合於晶片單元11上時，因被動元件14的體積過大，堆疊在晶片單元11上時會有電性連接的困難，再者，被動元件14也容易壓斷用以連晶片單元11與電路板12的磅線13，即使磅線13不被壓斷也容易造成磅線13的損毀。因此，欲完成本發明之構想，被動元件不能直接堆疊於晶片單元上。
請參閱圖1B，圖1B係三維封裝結構第二缺陷示意圖，其缺陷係在於當如圖1A中所示之當被動元件為一電感元件時，其所衍生出之另一缺陷。圖1B中與圖1A相同之元件將使用相同的元件符號以方便說明與理解。
如圖1B所示，係將一電感元件141堆疊於晶片單元11上，而如圖1B所示，電感元件141因電感特性而於電感元件141外部產生一磁場，即產生漏磁，如圖1B中所示，電感元件141外部形成一磁力線E，磁力線E的分佈即如圖1B中所示。然而，電感元件141下方之磁力線係因電感元件141直接堆疊於晶片晶片單元11上，故下方的磁力線E會對晶片單元11造成干擾，對晶片單元11上產生相當的雜訊。目前製程晶片多為奈米數量級製程，在微觀的環境下，此一漏磁現象將會對晶片單元11造成巨大的干擾，影響晶片單元11而無法正常運作。
請參閱圖1C，圖1C係三維封裝結構第三缺陷示意圖。其缺陷在於，若直接將被動元件堆疊在晶片單元上，雖可節省電路板的使用面積，但對整體堆疊過後的垂直結構而言，會有厚度過厚的問題，與現今封裝產業與科技產品追求薄型化的訴求大相徑庭。
上述圖1A、圖1B、圖1C中所述之缺陷，俾在下列各個實例中以加以說明如何克服。
實施例1-使用矽穿孔(Through-Silicon Via)封裝技術與球格格陣列(ball grid array)技術
請先參閱圖1A，圖1A係三維封裝結構第一缺陷示意圖。如圖1A所示，一晶片單元11以表面黏著式封裝技術設置於一電路板12上，再者，晶片單元11以磅線13與電路板12電性連接，此時，若將一被動元件14直接堆疊的方式以整合於晶片單元11上時，因被動元件14的體積過大，堆疊 在晶片單元11上時會有電性連接的困難，再者，被動元件14也容易壓斷用以連晶片單元11與電路板12的磅線13，即使磅線13不被壓斷也容易造成磅線13的損毀。
欲解決上述之缺陷，請參閱圖2，圖2係本發明之封裝結構第一實施例之示意圖，如圖2所示，本發明之封裝結構包括：一電路板21、一晶片單元22、複數個焊球25、及一被動元件24。其中，電路板21係具有一第一表面211，第一表面211上係設置有複數個第一連接墊2111；晶片單元22具有一主動面222及一非主動面221，主動面222上設置有複數個第二連接墊2221及複數個電極墊2222，非主動面221上係設置有複數個第三連接墊2211；晶片單元22上係開設有複數個導電孔23，並貫穿該晶片單元22；複數個焊球25係電性連接第一連接墊2111及第二連接墊2221；被動元件24係設置於晶片單元22之非主動面221之該些第三連接墊2211上。
其中，該些導電孔23係填充有導電材料，被動元件24係透過該些第三連接墊2211、該些導電孔23、該些電極墊2222與晶片單元22電性連接。晶片單元22係透過該些第二連接墊2221、該些焊球25、該些第一連接墊2111與電路板21電性連接。
對照圖1A與圖2，於圖1A中所示之磅線斷裂之問題係可以如圖2所示之球格陣列(ball grid array)裝結構取代磅線，俾能解決磅線斷裂或損毀之缺失。
實施例2-被動元件為電感元件
請先參閱1B，圖1B係三維封裝結構第二缺陷示意圖。如圖1B所示，係將一電感元件141堆疊於晶片單元11上，而如圖1B所示，電感元件141因電感特性而於電感元件141外部產生一磁場，即產生漏磁，如圖1B中所示，電感元件141外部形成一磁力線E，磁力線E的分佈即如圖1B中所示。然而，電感元件141下方之磁力線係因電感元件141直接堆疊於晶片晶片單元11上，故下方的磁力線E會對晶片單元22造成干擾，對晶片單元22上產生相當的雜訊。目前製程晶片多為奈米數量級製程，在微觀的環境下，此一漏磁現象將會對晶片單元22造成巨大的干擾，影響晶片單元22而無法正常運作。
欲解決上述之缺陷，請參閱圖3，圖3係本發明之封裝結構之第二示意圖，如圖3所示，其係將圖1B中所示之電感元件141之堆疊方向轉置，如此一來，使電感元件141外部所產生之磁場位於左右兩側(如圖3中所示之磁力線E之分佈)，如此，磁力線E對晶片單元22上的干擾便可大幅降低。
此外，本發明之封裝結構更針對，在電感元件內填充一磁性材料35或樹脂，以磁性材料35或樹脂導引外部磁場，縮減磁力線E的分佈。磁性材料並無限制，其可為鐵磁性物質或亞鐵磁性物質所構成之磁性材料。
對照圖1B與圖3，漏磁現象對晶片單元所產生的干擾便可透過此一改良獲得改善。
實施例3-使用薄型化元件
請先參閱圖1C，圖1C係三維封裝結構第三缺陷示意圖。其缺陷在於，若直接將被動元件堆疊在晶片單元上，雖可節省電路板的使用面積，但對整體堆疊過後的垂直結構而言，會有厚度過厚的問題，與現今封裝產業與科技產品追求薄型化的訴求大相徑庭。
欲解決上述之缺陷，請參閱圖4，圖4係本發明之封裝結構之第三示意圖。如圖4所示，一電感元件141如第二實施例中所述之方式，堆疊於一晶片單元22上，然而，其電感元件141係使用一薄型化之電感元件，以降低整體堆疊的高度。為因應現行業界封裝結構薄型化的趨勢，本實施例所使用之薄型化電感元件，此一薄型化電感元件之厚度可縮減至1公厘以下，使整體封裝結構大幅降低，其封裝後的高度係介於1公厘到2公厘之間。
實施例4-使用微影製程之薄膜電感
請參閱圖5A及圖5B，圖5A及圖5B係本發明之封裝結構第四實施例之示意圖，而圖5B即從圖5A之晶片單元之上方之上視圖。
本實施例係從實施例2及實施例3延續，將本發明之封裝結構之厚度更薄化。如圖5B所示，係直接以微影製程技術於圖5A中所示之晶片單元22之非主動面221上形成一薄膜電感51。本實施例係使用黃光微影製程技術(Photolithography Process)，將薄膜電感的光罩圖形直接轉移至晶片單元22之非主動面221上。
以黃光微影製程技術所形成之薄膜電感，其厚度小於0.3mm。如此一來，因本實施例之薄膜電感的厚度可更薄於實施例2及實施例3中所使用之電感元件，如此可更縮減本發明之封裝結構的堆疊高度。需注意的是，薄膜電感可與前述實施例中之第三連接墊電性連接，或不透過第三連接墊，而直接與上述之導電孔電性連接(即非之動面上不需設置第三連接墊)。
再者，於晶片單元之非主動面上形成一薄膜電感的方式並無限制使用本實例中所使用之黃光微影製程技術，其他可製作薄膜電感之微影技術皆可適用於本發明中。
製作方法
有關本發明之封裝結構之製作方法，請參考圖6A-圖6D。其係顯示本發明一較佳實施例之一種封裝結構之製作方法。
如圖6A所示，首先步驟(A)提供一電路板21，電路板21具有一第一表面211，並於第一表面211上設置複數個第一連接墊2111。
接著，如圖6B所示，步驟(B)提供一晶片單元22，其具有一主動面222及一非主動面221，該主動面222設置有複數個第二連接墊2221及複數個電極墊2222，該非主動221面設置有複數個第三連接墊2211，該晶片單元22具有複數個導電孔223，而該些導電孔223係貫穿該晶片單元22且分別與該些第三連接墊2211及該些電極墊2222電性連接。
接著，如圖6C所示，步驟(C)以焊球25電性連接該第一連接墊2111及該第二連接墊2221。
最後，如圖6D所示，步驟(D)提供一被動元件24，係設置於晶片單元22之非主動面221之該些第三連接墊2211上。
如記載於先前技術中之說明，以往晶片單元與電路板之間係以磅線連接，其中磅線所形成之線弧高度約為10至15密爾(mil)，再者，晶片單元上連接有磅線之表面的面積亦較小，若直接將被動元件以三維封裝方式直接堆疊於晶片單元上，容易將磅線壓斷或使磅線損毀，造成信號傳導上的阻礙，故若欲將被動元件直接堆疊於晶片單元上亦存在著電性連接的困難。
為此，本發明提供之封裝結構之製作方法係利用矽穿孔(Through-Silicon Via)封裝技術取代原有之磅線，於晶片單元上直接穿孔並貫穿晶片單元，並再配合球格陣列(ball grid array)技術，以焊球連接晶片單元與電路板。堆疊於晶片單元上之被動元件可與晶片單元電性連接。
再者，於上述步驟(D)中，該被動元件並無限制為何種電路元件，其可為電感、電阻、亦或是電容。任何被動元件皆更適用於本發明之封裝結構中，直接以堆疊之方式整合於晶片上。
此外，於上述步驟(B)中，晶片單元係為一電力轉換晶片，例如一直流-直流(DC-to-DC)轉換晶片、一交流-直流 (AC-to-DC)轉換晶片、一直流-交流(DC-to-AC)轉換晶片、或一交流-交流(AC-to-AC)轉換晶片。
再者，若本發明之封裝結構之製作方法中，被動元件為一電感元件，其電感元件之形式並無任何限制，較佳可為一鐵氧體功率電感。鐵氧體功率電感因電感特性而於電感外部產生磁場，即產生漏磁，若鐵氧體功率電感直接堆疊於晶片上，其產生之外部磁場即有可能對晶片產干擾，對晶片產生相當的雜訊，在高密度封裝結構下，此一磁場將對晶片產生相當巨大的影響。本發明之封裝結構係針對此一問題做堆疊方式之改良，並再將鐵氧體功率電感填充一磁性材料或樹脂，以磁性材料或樹脂之特性導引外部磁場，縮減磁通分佈範圍。上述之磁性材料並無限制，其可為鐵磁性物質或亞鐵磁性物質所構成之磁性材料。
由上述封裝結構之製作方法可知，本發明之封裝結構係為一堆疊結構，由下至上係為：電路板，第一連接墊，焊球，第二連接墊，晶片，被動元件。於本發明之封裝結構中，此一堆疊高度係因應薄型封裝之趨勢，其堆疊高係介於1公厘到2公厘之間。
再者，於上述封裝結構之製作方法中，焊球之材料較佳係由錫所構成。此外，本發明之封裝結構中，導電孔係因其內填充有導電材料或設置有其他導電裝置而具有導電功能。導電材料係由銅、多晶矽、或鎢所組成。
上述實施例僅係為了方便說明而舉例而已，本發明所主張之權利範圍自應以申請專利範圍所述為準，而非僅限於上述實施例。
11‧‧‧晶片單元
12‧‧‧電路板
13‧‧‧磅線
14‧‧‧被動元件
21‧‧‧電路板
22‧‧‧晶片單元
223‧‧‧導電孔
24‧‧‧被動元件
25‧‧‧焊球
211‧‧‧第一表面
222‧‧‧主動面
221‧‧‧非主動面(晶片背面)
2111‧‧‧第一連接墊
2221‧‧‧第二連接墊
2211‧‧‧第三連接墊
141‧‧‧電感元件
35‧‧‧磁性材料
2222‧‧‧電極墊
51‧‧‧薄膜電感
圖1A係三維封裝結構第一缺陷示意圖。
圖1B係三維封裝結構第二缺陷示意圖。
圖1C係三維封裝結構第三缺陷示意圖。
圖2係本發明之封裝結構第一實施例之示意圖。
圖3係本發明之封裝結構第二實施例之示意圖。
圖4係本發明之封裝結構第三實施例之示意圖。
圖5A及圖5B係本發明之封裝結構第四實施例之示意圖。
圖6A-圖6D係本發明之封裝結構之製作方法之流程圖。
21‧‧‧電路板
22‧‧‧晶片單元
23‧‧‧導電孔
24‧‧‧被動元件
25‧‧‧焊球
211‧‧‧第一表面
222‧‧‧主動面
221‧‧‧非主動面
2111‧‧‧第一連接墊
2221‧‧‧第二連接墊
2211‧‧‧第三連接墊
2222‧‧‧電極墊

Claims (16)

  1. 一種封裝結構，包括：一電路板，係具有一第一表面，該第一表面上係設置有複數個第一連接墊；一晶片單元，具有一主動面及一非主動面，該主動面設置有複數個第二連接墊及複數個電極墊，該非主動面設置有複數個第三連接墊，該晶片單元具有複數個導電孔，該些導電孔係貫穿該晶片單元且分別與該些第二連接墊及該些第三連接墊電性連接；複數個焊球，係電性連接該些第一連接墊及該些第二連接墊；以及一被動元件，係設置於該晶片單元之非主動面上，且與該晶片單元之該些第三連接墊電性連接，其中，該被動元件係一鐵氧體功率電感；其中，該被動元件係透過該些第三連接墊、該些導電孔、該些電極墊與該晶片單元電性連接，該晶片單元係透過該些第二連接墊、該些焊球、該些第一連接墊與該電路板電性連接。
  2. 如申請專利範圍第1項所述之封裝結構，其中，該鐵氧體功率電感係填充有一磁性材料或樹脂。
  3. 如申請專利範圍第2項所述之封裝結構，其中，該磁性材料係由鐵磁性物質或陶鐵磁性物質所構成。
  4. 如申請專利範圍第1項所述之封裝結構，其中，該晶片單元係為一電力轉換晶片，該電力轉換晶片係為 直流-直流轉換晶片、交流-直流轉換晶片、直流-交流轉換晶片、或交流-交流轉換晶片。
  5. 如申請專利範圍第1項所述之封裝結構，其中，該些焊球之材料係由錫、或其他金屬所構成。
  6. 如申請專利範圍第1項所述之封裝結構，其中，該封裝結構之高度係介於1公厘到2公厘之間。
  7. 如申請專利範圍第1項所述之封裝結構，其中，該導電孔係以矽穿孔(Through-Silicon Via)封裝技術形成。
  8. 一種封裝結構之製作方法，係包括：(A)提供一電路板，其具有一第一表面，該第一表面上係設置有複數個第一連接墊；(B)提供一晶片單元，其具有一主動面及一非主動面，該主動面設置有複數個第二連接墊及複數個電極墊，該非主動面設置有複數個第三連接墊，該晶片單元具有複數個導電孔，而該些導電孔係貫穿該晶片單元且分別與該些第三連接墊與該些電極墊電性連接；(C)以焊球電性連接該第一連接墊及該第二連接墊；以及(D)提供一被動元件，係設置於該晶片單元之非主動面上，且與該晶片單元之該些第三連接墊上電性連接，其中，該被動元件係一鐵氧體功率電感。
  9. 如申請專利範圍第8項所述之封裝結構之製作方法，其中，該鐵氧體功率電感係填充有一磁性材料或樹脂。
  10. 如申請專利範圍第9項所述之封裝結構之製作方法，其中，該磁性材料係由鐵磁性物質或亞鐵磁性物質所構成。
  11. 如申請專利範圍第8項所述之封裝結構之製作方法，其步驟(B)中，該晶片單元係為一電力轉換晶片，該電力轉換晶片係為直流-直流轉換晶片、交流-直流轉換晶片、直流-交流轉換晶片、或交流-交流轉換晶片。
  12. 如申請專利範圍第8項所述之封裝結構之製作方法，其中，該些焊球之材料係由錫、或其他金屬所構成。
  13. 如申請專利範圍第8項所述之封裝結構之製作方法，其中，該封裝結構之高度係介於1公厘到2公厘之間。
  14. 如申請專利範圍第8項所述之封裝結構之製作方法，其步驟(B)中，該導電孔係以矽穿孔(Through-Silicon Via)封裝技術形成。
  15. 一種封裝結構，包括：一電路板，係具有一第一表面，該第一表面上係設置有複數個第一連接墊；一晶片單元，具有一主動面及一非主動面，該主動面設置有複數個第二連接墊及複數個電極墊，該晶片單元具有複數個導電孔，該些導電孔係貫穿該晶片單元；複數個焊球，係電性連接該些第一連接墊及該些第二連接墊；以及一薄膜電感，係形成於該晶片單元之該非主動面上，且與該晶片單元之該些導電孔電性連接； 其中，該薄膜電感係透過該些導電孔、該些電極墊與該晶片單元電性連接，該晶片單元係透過該些第二連接墊、該些焊球、該些第一連接墊與該電路板電性連接。
  16. 如申請專利範圍第15項所述之封裝結構，其中，該薄膜電感係由鐵氧體材料所構成。
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