TWI659611B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI659611B
TWI659611B TW107104863A TW107104863A TWI659611B TW I659611 B TWI659611 B TW I659611B TW 107104863 A TW107104863 A TW 107104863A TW 107104863 A TW107104863 A TW 107104863A TW I659611 B TWI659611 B TW I659611B
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TW
Taiwan
Prior art keywords
region
sensing
electrode
main electrode
resistance layer
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TW107104863A
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English (en)
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TW201836272A (zh
Inventor
妹尾賢
宮田征典
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日商豐田自動車股份有限公司
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Publication of TW201836272A publication Critical patent/TW201836272A/zh
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    • H01L27/0203—Particular design considerations for integrated circuits
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    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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Abstract

[課題] 抑制對感測二極體施加過電壓。 　　[解決手段] 一種半導體裝置，具有：半導體基板；配置在前述半導體基板的上部的上部主電極；配置在前述半導體基板的上部的感測陽極電極；第1電阻層；以及配置在前述半導體基板的下部的下部主電極。前述第1電阻層配置在前述半導體基板的上部，具有比前述上部主電極以及前述感測陽極電極還高的電阻率，並連接前述上部主電極和前述感測陽極電極。前述半導體基板具有切換元件和感測二極體。前述切換元件連接在前述上部主電極和前述下部主電極之間。前述感測二極體具有：p型的第1陽極區域，其係與前述感測陽極電極連接；以及n型的第1陰極區域，其係與前述下部主電極連接。

Description

半導體裝置
本說明書公開的技術有關半導體裝置。
專利文獻1中公開了一種在共通的半導體基板上設置切換元件和保護二極體的半導體裝置。保護二極體的陰極電極與切換元件的一個端子連接。保護二極體的陽極電極與外部電路連接。保護二極體的陽極電極的電位根據切換元件的前述一個端子的電位而變化。專利文獻1的技術中，根據保護二極體的陽極電極的電位，判定與切換元件並列連接的續流二極體是否導通。外部電路在續流二極體處於關閉狀態時允許切換元件接通。 [先前技術文獻] [專利文獻]
[專利文獻1] 日本特開2016-149715號專利公報
[發明欲解決之課題]
如專利文獻1的保護二極體那樣，將二極體的陰極電極連接至切換元件的一個端子時，二極體的陽極電極的電位根據該端子的電位而變化。這種二極體在專利文獻1的使用方法(即，續流二極體的導通的判定)以外的方法中，還能用於根據切換元件的端子的電位判定切換元件的動作狀態。以下，將這種二極體(包含專利文獻1的保護二極體)稱為感測二極體。
將感測二極體和切換元件設置在單個半導體基板上時，可以在半導體基板的上表面設置上部主電極和感測陽極電極，在半導體基板的下表面設置下部主電極。感測二極體的p型陽極層與感測陽極電極連接，感測二極體的n型陰極層與下部主電極連接。切換元件連接在上部主電極和下部主電極之間。即，下部主電極上連接有切換元件和感測二極體。即，下部主電極既是切換元件的一個端子，同時也是感測二極體的陰極電極。配置在半導體基板的上部的上部主電極和感測陽極電極之間存在寄生電容。另外，配置在半導體基板的上部的感測陽極電極和配置在半導體基板的下部的下部主電極之間也存在寄生電容。
圖12將該半導體裝置的電路圖作為示例示出。圖12示出了切換元件100、感測二極體110、上部主電極120、下部主電極130、感測陽極電極140、寄生電容150以及寄生電容160。另外，圖12中，作為切換元件100而示出了IGBT，但是切換元件100也可以是MOSFET、雙極性電晶體等其他的切換元件。如圖12所示，切換元件100連接在上部主電極120和下部主電極130之間。感測二極體110的陰極層與下部主電極130連接，感測二極體110的陽極層與感測陽極電極140連接。感測陽極電極140和上部主電極120之間存在寄生電容150。感測陽極電極140和下部主電極130之間存在寄生電容160。
圖12的半導體裝置在切換元件100的動作過程中，由於寄生電容150或寄生電容160產生的電容耦合，會有不期望的感測陽極電極140的電位上升的情況。由於電容耦合導致的感測陽極電極140的電位上升，會有感測二極體110被施加過電壓的情況。
因此，本發明提供一種能夠抑制對感測二極體施加過電壓的技術。 [解決課題之手段]
本說明書公開的半導體裝置具有：半導體基板；上部主電極，其係配置在前述半導體基板的上部；感測陽極電極，其係配置在前述半導體基板的上部；第1電阻層；以及下部主電極，其係配置在前述半導體基板的下部。前述第1電阻層配置在前述半導體基板的上部，具有比前述上部主電極以及前述感測陽極電極還高的電阻率，並連接前述上部主電極和前述感測陽極電極。前述半導體基板具有切換元件和感測二極體。前述切換元件連接在前述上部主電極和前述下部主電極之間。前述感測二極體具有：p型的第1陽極區域，其係與前述感測陽極電極連接；以及n型的第1陰極區域，其係與前述下部主電極連接。
該半導體裝置中，感測陽極電極透過第1電阻層與上部主電極連接。因此，由於電容耦合而感測陽極電極的電位上升時，電流透過第1電阻層從感測陽極電極流至上部主電極。因此，能夠抑制感測陽極電極的電位進一步上升。因此，能夠抑制過電壓被施加至感測二極體。另外，假設感測陽極電極和上部主電極之間的電阻極小，則感測陽極電極的電位固定在上部主電極的電位。對此，該半導體裝置中，連接感測陽極電極和上部主電極的第1電阻層具有大於上部主電極以及感測陽極電極的電阻率。因此，感測陽極電極的電位不固定在上部主電極的電位，感測陽極電極的電位能夠變化。因此，根據感測陽極電極的電位能夠判斷切換元件的動作狀態。因此，根據該半導體裝置，能夠適當地控制切換元件。
圖1至3示出了實施方式的半導體裝置10。半導體裝置10具有半導體基板12。半導體基板12是矽製成的基板。如圖1所示，半導體基板12的上部配置有上部主電極14和感測陽極電極50。上部主電極14的下部的半導體基板12上設置有元件區域18。元件區域18內設置有IGBT和續流二極體，之後會詳細說明。另外，感測陽極電極50的下部的半導體基板12上設置有感測區域70。感測區域70內設置有感測二極體，之後會詳細說明。元件區域18的面積遠遠大於感測區域70的面積。另外，在以下說明中，以半導體基板12的厚度方向為z方向，以與半導體基板12的上表面平行的一個方向(與z方向正交的一個方向)為x方向，以與z方向和x方向都正交的方向為y方向。
如圖2所示，感測區域70內的半導體基板12的上表面被層間絕緣膜36覆蓋。另外，感測區域70的上部配置有感測陽極電極50、第2電阻層52以及配線層54。
第2電阻層52利用摻雜有雜質的多晶矽構成。第2電阻層52具有大於感測陽極電極50以及配線層54的電阻率。第2電阻層52配置在層間絕緣膜36上。第2電阻層52的下部的層間絕緣膜36上設置有接觸孔36c。接觸孔36c內配置有配線層54。配線層54由Al(鋁)或AlSi(鋁和矽的合金)構成。配線層54與第2電阻層52接觸。配線層54與半導體基板12的上表面接觸。即，第2電阻層52透過配線層54與半導體基板12連接。感測陽極電極50利用Al或AlSi構成。感測陽極電極50配置在第2電阻層52上。感測陽極電極50覆蓋第2電阻層52的整個上表面。感測陽極電極50的上表面是焊墊。導線17的端部被接合到感測陽極電極50的上表面。導線17的另一端與外部電路連接。
透過第2電阻層52和配線層54構成連接感測陽極電極50和半導體基板12(更詳細而言是後述的陽極區域60)的電流路徑。如上述，第2電阻層52的電阻率大於感測陽極電極50的電阻率以及配線層54的電阻率。因此，在從焊墊到半導體基板12的電流路徑中，第2電阻層52的電阻大於感測陽極電極50的電阻以及配線層54的電阻。
上部主電極14利用Al或AlSi構成。如圖2、3所示，上部主電極14在元件區域18內與半導體基板12的上表面接觸。如圖2所示，上部主電極14和感測陽極電極50之間設置有間隔。
如圖2所示，位於元件區域18和感測區域70之間的半導體基板12的上表面被層間絕緣膜36覆蓋。該部分的層間絕緣膜36上配置有第1電阻層51。第1電阻層51利用摻雜有雜質的多晶矽構成。第1電阻層51的上表面被層間絕緣膜36覆蓋。第1電阻層51上的層間絕緣膜36上設置有接觸孔36a、36b。感測陽極電極50延伸至接觸孔36b。感測陽極電極50在接觸孔36b內覆蓋第1電阻層51。上部主電極14延伸至接觸孔36a。上部主電極14在接觸孔36a內覆蓋第1電阻層51。感測陽極電極50透過第1電阻層51與上部主電極14連接。
如圖2、3所示，半導體基板12的下表面配置有下部主電極16。下部主電極16與半導體基板12的下表面的大致整個區域接觸。
如圖2所示，感測區域70內配置有陽極區域60、漂移區域27以及陰極區域62。
陽極區域60是p型區域。陽極區域60配置在露出於半導體基板12的上表面的範圍。陽極區域60配置在配線層54之下。陽極區域60與配線層54接觸。陽極區域60透過配線層54以及第2電阻層52與感測陽極電極50連接。
漂移區域27是n型雜質濃度低的n型區域。漂移區域27配置在陽極區域60之下。理想上，第2電阻層52的電阻率大於沒有產生電導率調變現象時的漂移區域27的電阻率。
陰極區域62是n型雜質濃度高於漂移區域27的n型區域。陰極區域62配置在陽極區域60下部的漂移區域27之下。陰極區域62配置在露出於半導體基板12的下表面的範圍。陰極區域62與下部主電極16接觸。
感測區域70內，透過陽極區域60、漂移區域27以及陰極區域62而設置了感測二極體。
如圖3所示，元件區域18具有設置有IGBT的IGBT範圍20和設置有續流二極體的二極體範圍40。IGBT範圍20和二極體範圍40相鄰。元件區域18內，IGBT範圍20和二極體範圍40在y方向上交替反復地配置。
元件區域18內的半導體基板12的上表面設置有多個溝槽38。在半導體基板12的上表面，多個溝槽38沿x方向平行延伸。如圖3所示的截面上，各溝槽38從半導體基板12的上表面沿z方向延伸。IGBT範圍20和二極體範圍40分別設置有多個溝槽38。各溝槽38的內表面被閘極絕緣膜32覆蓋。各溝槽38內配置有閘極電極34。各閘極電極34透過閘極絕緣膜32與半導體基板12絕緣。各閘極電極34的上表面被層間絕緣膜36覆蓋。各閘極電極34透過層間絕緣膜36與上部主電極14絕緣。IGBT範圍20內的各閘極電極34與未圖示的閘極配線連接。二極體範圍40的各閘極電極34可以與閘極配線連接，也可以是與上部主電極14等連接的虛擬電極。
在被夾於2個溝槽38的各範圍內配置有射極區域22和p型區域24。IGBT範圍20內以及二極體範圍40內配置有射極區域22和p型區域24。射極區域22是n型區域。射極區域22配置在露出於半導體基板12的上表面的範圍。射極區域22與上部主電極14接觸。射極區域22在溝槽38的上端部與閘極絕緣膜32接觸。p型區域24具有高濃度區域24a和低濃度區域24b。高濃度區域24a具有高於低濃度區域24b的p型雜質濃度。高濃度區域24a配置在露出於半導體基板12的上表面的範圍。高濃度區域24a與上部主電極14接觸。低濃度區域24b配置在高濃度區域24a和射極區域22之下。低濃度區域24b在射極區域22的下方與閘極絕緣膜32接觸。IGBT範圍20內的p型區域24作為IGBT的體區域發揮作用。另外，二極體範圍40內的p型區域24作為續流二極體的陽極區域發揮作用。另外，圖3中二極體範圍40內配置有射極區域22，但也可以是二極體範圍40內不配置有射極區域22。
IGBT範圍20以及二極體範圍40內的p形區域24之下配置有漂移區域27。即，漂移區域27橫跨分布在感測區域70、IGBT範圍20以及二極體範圍40。漂移區域27在p型區域24之下與閘極絕緣膜32接觸。漂移區域27透過p型區域24從射極區域22分隔開。
IGBT範圍20內的漂移區域27下配置有集極區域30。集極區域30是p型區域。集極區域30配置在露出於半導體基板12的下表面的範圍。集極區域30與下部主電極16接觸。集極區域30透過漂移區域27從p型區域24分隔開。
二極體範圍40內的漂移區域27下配置有陰極區域44。陰極區域44是n型雜質濃度高於漂移區域27的n型區域。陰極區域44配置在露出於半導體基板12的下表面的範圍。陰極區域44與下部主電極16接觸。
IGBT範圍20內，利用射極區域22、p型區域24(即、體區域)、漂移區域27、集極區域30、閘極電極34以及閘極絕緣膜32等構成IGBT。作為IGBT進行動作時，上部主電極14作為射極電極發揮作用，下部主電極16作為集極電極發揮作用。
二極體範圍40內，利用p型區域24(即，陽極區域)、漂移區域27、陰極區域44等構成續流二極體。作為續流二極體發揮作用時，上部主電極14作為陽極電極發揮作用，下部主電極16作為陰極電極發揮作用。
如圖2所示，元件區域18和感測區域70之間分布有漂移區域27。p型區域24(體區域)透過漂移區域27從陽極區域60分隔開。以下，是有將位於p型區域24和陽極區域60之間的漂移區域27稱為分隔區域27a之情況。理想上，第1電阻層51的電阻率小於分隔區域27a的電阻率。
圖4示出了半導體裝置10的內部電路。圖4中，IGBT 82表示設置在IGBT範圍20內的IGBT，續流二極體84表示設置在二極體範圍40內的續流二極體，感測二極體80表示設置在感測區域70內的感測二極體。IGBT 82的集極與下部主電極16連接，IGBT 82的射極與上部主電極14連接。續流二極體84的陽極與上部主電極14連接，續流二極體84的陰極與下部主電極16連接。即，續流二極體84與IGBT 82反向並聯連接。感測二極體80的陰極與下部主電極16連接。另外，感測二極體80的陽極與感測陽極電極50連接。感測陽極電極50透過導線17(參閱圖1)與外部電路90連接。外部電路90根據感測陽極電極50的電位控制IGBT 82的閘極電極的電位。感測陽極電極50的電位根據下部主電極16的電位而變化。下部主電極16的電位為規定值以下時，感測二極體80導通，感測陽極電極50的電位變為與下部主電極16大致相同的電位(更詳細地，是比下部主電極16的電位僅高出感測二極體80的正向壓降大小的電位)。另外，下部主電極16的電位高於規定值時，感測二極體80關閉。此時，感測陽極電極50是獨立於下部主電極16的電位的電位(例如，在外部電路90的內部規定的電位)。因此，外部電路90能夠透過檢測感測陽極電極50的電位來檢測IGBT 82的動作狀態。因此，外部電路90能夠適當地控制IGBT 82。另外，如圖1、2所示，感測陽極電極50配置在上部主電極14的附近。因此，感測陽極電極50和上部主電極14之間存在有寄生電容。圖4中，將該寄生電容表示為電容86。另外，如圖2所示，感測陽極電極50和下部主電極16隔著半導體基板12相對配置。因此，感測陽極電極50和下部主電極16之間存在有寄生電容。圖4中，將該寄生電容表示為電容88。另外，感測陽極電極50透過第1電阻層51與上部主電極14連接。圖4中，將第1電阻層51表示為電阻51。
感測陽極電極50的電位會有由於透過寄生電容86、88的電容耦合而變化的情況。例如，上部主電極14的電位急劇變化時，感測陽極電極50的電位會由於透過寄生電容88的電容耦合而變化。另外，下部主電極16的電位急劇變化時，感測陽極電極50的電位會由於透過寄生電容86的電容耦合而變化。感測陽極電極50的電位由於電容耦合而變化時，會對感測二極體80施加較高的負載。例如，感測陽極電極50的電位由於電容耦合而過度上升時，會對感測二極體80施加正向過電壓。因此，過電流正向流過感測二極體80。另外，由於感測陽極電極50的電位的上升而電流正向流過感測二極體80的期間，空穴從陽極區域60注入到漂移區域27。然後感測陽極電極50的電位下降時，施加於感測二極體80的電壓從正向電壓切換為反向電壓。於是，存在於漂移區域27內的空穴被排出至感測陽極電極50。因此，恢復電流流過感測二極體80。正向電流越大，之後流過的恢復電流就越大，對感測二極體80施加的負載越大。另外，感測陽極電極50的電位過度上升時，會有感測陽極電極50和上部主電極14之間的絕緣膜的絕緣性變差的情況。
對此，本實施方式的半導體裝置10中，透過第1電阻層51和第2電阻層52減輕對感測二極體80施加的負載。以下，詳細說明之。
如上述，第1電阻層51連接感測陽極電極50和上部主電極14。感測陽極電極50的電位因電容耦合而上升時，微小電流透過第1電阻層51從感測陽極電極50流向上部主電極14。由此，能夠抑制感測陽極電極50的電位再上升。因此，能夠抑制對感測二極體80施加過電壓。另外，能夠抑制感測陽極電極50和上部主電極14之間的絕緣膜的絕緣性變差。另外，第1電阻層51的電阻過低時，感測陽極電極50的電位固定在上部主電極14的電位，外部電路90不能正常動作。對此，本實施方式中，第1電阻層51具有比較大的電阻。因此，感測陽極電極50的電位能夠在一定程度上獨立於上部主電極14的電位地變動。因此，外部電路90能夠根據感測陽極電極50的電位適當地控制IGBT 82。另外，從感測陽極電極50流向上部主電極14的微小電流，不流過半導體基板12的內部而是流過第1電阻層51。因此，能夠抑制半導體基板12的發熱，能夠減輕對半導體基板12施加的壓力。
另外，如上述，電阻較大的第2電阻層52配置在感測陽極電極50和陽極區域60之間。因此，感測二極體80的正向壓降較大。因此，施加正向電壓時，正向電流不容易流過感測二極體80。由此，能夠抑制過電流流過感測二極體80。另外，由於正向電流不容易流過感測二極體，所以施加於感測二極體80的電壓從正向電壓切換為反向電壓時，恢復電流不容易流過感測二極體80。
如以上說明，本實施方式的半導體裝置10中，不容易對感測二極體80施加過電壓。另外，本實施方式的半導體裝置10中，過電流以及恢復電流不容易流過感測二極體80。因此，能夠減輕施加於感測二極體80的負載，提高感測二極體80的可靠性。
另外，以下舉例說明構成半導體裝置10的各構件的構成。漂移區域27可以包含作為雜質的磷，具有40～100Ωcm的電阻率，具有80～165μm的厚度。上部主電極14可以具有層疊在利用Al或AlSi構成的層的上表面的鈦層、鎳層以及金(Au)層，具有3～30μm的厚度。下部主電極16可以具有層疊在利用Al或AlSi構成的層的下表面的鈦層、鎳層和金層。或者也可以是下部主電極16利用鈦層、鎳層和金層構成。下部主電極16可以具有1～30μm的厚度。p型區域24可以包含作為雜質的硼，具有1×1016 ～1×1019 cm-3 峰值雜質濃度，具有0.2～5.0μm的厚度。射極區域22可以包含作為雜質的砷或磷，具有1×1018 ～1×1021 cm-3 峰值雜質濃度，具有0.2～1.5μm的厚度。陰極區域44可以包含作為雜質的磷，具有1×1018 ～1×1021 cm-3 峰值雜質濃度，具有0.2～3.0μm的厚度。集極區域30可以包含作為雜質的硼，具有1×1015 ～1×1019 cm-3 峰值雜質濃度，具有0.2～3.0μm的厚度。溝槽38可以具有4～7μm的深度。第1電阻層51具有500～2000nm的厚度，具有1×108 ～1×1018 Ωcm的電阻率。
另外，第1電阻層51的電阻過高時，電容耦合的影響變大，另一方面，第1電阻層51的電阻過低時，感測陽極電極50的電位被固定。因此，需要將第1電阻層51的電阻設定為適當的值。例如，可以調節第1電阻層51的厚度，從而調節第1電阻層51的電阻。另外，為了調節第1電阻層51的電阻，可以採用圖5～8的構成。
圖5的構成中，第1電阻層51被分割為多個。圖5的構成與圖1的構成相比，第1電阻層51的電流路徑變窄。因此，能夠增大第1電阻層51的電阻。
圖6的構成中，第1電阻層51為蜿蜒狀，在其兩端與感測陽極電極50和上部主電極14連接。圖6的構成與圖1的構成相比，第1電阻層51的電流路徑變窄並且變長。因此，能夠增大第1電阻層51的電阻。
圖7的構成中，上部主電極14在感測陽極電極50的輪廓的2個邊上與感測陽極電極50相鄰。在這2個邊上，第1電阻層51連接感測陽極電極50和上部主電極14。圖7的構成與圖1的構成相比，第1電阻層51的電流路徑變寬。因此，能夠減小第1電阻層51的電阻。
圖8的構成中，感測陽極電極50被上部主電極14包圍。第1電阻層51在感測陽極電極50的整個周圍連接感測陽極電極50和上部主電極14。圖8的構成與圖1的構成相比，第1電阻層51的電流路徑變寬。因此，能夠減小第1電阻層51的電阻。另外，圖8中省略了導線17的圖示。
另外，上述實施方式中，上部主電極14覆蓋第1電阻層51的上表面的一部分(接觸孔36a的部分)，感測陽極電極50覆蓋第1電阻層51的上表面的一部分(接觸孔36b的部分)。但是，也可以是如圖9所示，第1電阻層51覆蓋上部主電極14的上表面的一部分和感測陽極電極50的上表面的一部分。
另外，上述實施方式中，陽極區域60配置在焊墊(即，感測陽極電極50)的下部。但是，也可以是如圖10所示，陽極區域60不配置在焊墊的下部，而是配置在焊墊的外側。這種情況下，第2電阻層52可以具有位於焊墊的下部的部分52a和從該部分52a延伸至焊墊的外側的部分52b。也可以是陽極區域60透過第2電阻層52的部分52b與感測陽極電極50連接。根據該構成，導線接合時的衝擊不容易施加到陽極區域60。由此，能夠抑制陽極區域60產生缺陷等。因此，能夠抑制感測二極體80的洩漏電流等。另外，由於焊墊的下部配置有利用多晶矽構成的第2電阻層52，所以能夠在導線接合時透過多晶矽層保護半導體基板12。由此，能夠在導線接合時減輕對半導體基板12造成的損傷。
另外，上述實施方式中，第2電阻層52透過配線層54與半導體基板12(即，陽極區域60)連接。但是，也可以是如圖11所示，第2電阻層52直接與半導體基板12連接。這種情況下，尤其是利用多晶矽構成第2電阻層52者為佳。圖11所示的構成中，利用多晶矽構成第2電阻層52，則感測二極體80被施加反向電壓時，空穴從陽極區域60流入第2電阻層52。多晶矽中的載流子壽命很短。因此，空穴在第2電阻層52內流動時，很多空穴由於再結合而消失。由此，能夠進一步減少恢復電流。
另外，上述實施方式中，第1電阻層51和第2電阻層52利用多晶矽構成。透過調節多晶矽中的雜質濃度，能夠容易調節多晶矽的電阻率。因此，容易將第1電阻層51和第2電阻層52的電阻率調節至所期望的電阻率。另外，第1電阻層51也可以是利用SInSiN(semi-insulating silicon nitride)膜(半絕緣氮化矽膜)構成。SInSiN膜有時作為用於半導體基板的表面保護和半導體基板內部的電場穩定的保護膜而設置在半導體基板的上表面。第1電阻層51是SInSiN膜時，可以在形成作為保護膜的SInSiN膜的同時，形成第1電阻層51。如圖9所示，上部主電極14和感測陽極電極50的上部配置有第1電阻層51，第1電阻層51是SInSiN膜時，可以如下地製造半導體裝置10。首先，形成上部主電極14和感測陽極電極50。接下來，在半導體基板的表面形成SInSiN膜。接下來，使SInSiN膜圖案化。此時，在需要作為保護膜以及第1電阻層51的地方保留SInSiN膜。根據該方法，能夠同時形成保護膜和第1電阻層51。
另外，第1電阻層51和第2電阻層52，可以由相同的材料構成，也可以由不同的材料形成。但是，第1電阻層51和第2電阻層52為相同材料時，能夠在製造工程中同時形成第1電阻層51和第2電阻層52。這種情況下，第1電阻層51和第2電阻52的電阻率大致相等。
另外，上述實施方式中，元件區域18內設置有IGBT，但也可以是元件區域18內設置有MOSFET等其他的切換元件以替代IGBT。
另外，上述實施方式中，感測陽極電極50的整個上表面是焊墊，但也可以是感測陽極電極50的上表面的一部分是焊墊。
接下來對上述實施方式的構成要素和請求項的構成要素的關係進行說明。實施方式的陽極區域60是請求項的第1陽極區域的一個示例。實施方式的陰極區域62是請求項的第1陰極區域的一個示例。實施方式的二極體範圍40內的p型區域24是請求項的第2陽極區域的一個示例。實施方式的陰極區域44是請求項的第2陰極區域的一個示例。
以下，列舉關於本說明書所揭示的技術要素。另外，以下的各個技術要素是各自獨立且有用的要素。
本說明書公開的一個例的半導體裝置中，切換元件也可以具有與上部主電極連接的p型體區域。另外，半導體基板也可以具有將體區域從第1陽極區域分隔開的n型分隔區域。第1電阻層的電阻率也可以小於分隔區域的電阻率。
根據該構成，能夠減小感測陽極電極和上部主電極之間的電阻。由此，能夠更有效地抑制對感測陽極電極施加過電壓。
本說明書公開的一個例的半導體裝置中，也可以是第1電阻層覆蓋上部主電極的上表面的一部分和感測陽極電極的上表面的一部分。
本說明書公開的另一例的半導體裝置中，也可以是上部主電極覆蓋第1電阻層的上表面的一部分。另外，也可以感測陽極電極覆蓋第1電阻層的上表面的一部分。
本說明書公開的一個例的半導體裝置中，第1電阻層也可以利用多晶矽構成。
根據該構成，能夠透過調節多晶矽中的雜質濃度來調節第1電阻層的電阻率。
本說明書公開的一個例的半導體裝置還可以具有配置在半導體基板的上部並具有大於感測陽極電極的電阻率的第2電阻層。第1陽極區域也可以透過第2電阻層與前述感測陽極電極連接。
根據該構成，電流不容易流至感測二極體。因此，能夠抑制感測二極體的正向電流以及恢復電流。
具有第2電阻層的一個例的半導體裝置中，感測陽極電極可以具有與導線接合的焊墊。也可以第2電阻層具有在焊墊的下部並與感測陽極電極連接的第1部分、和從第1部分延伸至焊墊的外側的第2部分。第1陽極區域也可以不配置在焊墊的下部，而是透過第2部分與感測陽極電極連接。
根據該構成，導線接合時的衝擊不容易被施加到第1陽極區域，能夠抑制第1陽極區域產生缺陷。
在第2電阻層配置在焊墊的下部的構成中，第2電阻層也可以利用多晶矽形成。
透過將耐衝擊的多晶矽配置在焊墊之下，能夠保護半導體基板免受導線接合時的衝擊。
具有第2電阻層的一個例的半導體裝置還可以具有配置在半導體基板的上部、具有小於第2電阻層的電阻率、並且與第1陽極區域接觸的配線層。第1陽極區域也可以透過配線層與第2電阻層連接。
另外，具有第2電阻層的另一例的半導體裝置中，也可以第1陽極區域與第2電阻層接觸。這種情況下，第2電阻層也可以利用多晶矽構成。
多晶矽中的載流子壽命很短。該構成中，反向電壓施加在感測二極體時從半導體基板排出至感測陽極電極的空穴透過利用多晶矽構成的第2電阻層。因此，第2電阻層中，空穴容易由於再結合而消失。因此，能夠進一步抑制恢復電流。
另外，具有第2電阻層的一個例的構成中，半導體基板也可以具有配置在第1陽極區域和第1陰極區域之間、並且n型雜質濃度低於前述第1陰極區域的n型漂移區域。第2電阻層的電阻率可以大於漂移區域的電阻率。
根據該構成，能夠進一步抑制感測二極體的恢復電流。
另外，本發明公開的一個例的構成中，半導體基板還可以具有續流二極體。也可以續流二極體具有與上部主電極連接的p型的第2陽極區域和與下部主電極連接的n型的第2陰極區域。
以上，雖然對實施方式進行了詳細說明，但這些只不過是示例，其並不對申請專利範圍進行限定。在申請專利範圍所記載的技術中，包含對以上所例示的具體例進行了各種變形、變更的內容。在本說明書或附圖中所說明的技術要素以單獨或各種組合的方式來發揮技術上的有用性，其並不限定申請專利範圍於申請時所記載的組合。此外，本說明書或圖面所例示的技術能夠同時實現複數個目的，並且實現其中一個目的的本身也具有技術上的有用性。
10‧‧‧半導體裝置
12‧‧‧半導體基板
14‧‧‧上部主電極
16‧‧‧下部主電極
18‧‧‧元件區域
20‧‧‧IGBT範圍
22‧‧‧射極區域
24‧‧‧p型區域
27‧‧‧漂移區域
30‧‧‧集極區域
32‧‧‧閘極絕緣膜
34‧‧‧閘極電極
36‧‧‧層間絕緣膜
38‧‧‧溝槽
40‧‧‧二極體範圍
44‧‧‧陰極區域
50‧‧‧感測陽極電極
51‧‧‧第1電阻層
52‧‧‧第2電阻層
54‧‧‧配線層
60‧‧‧陽極區域
62‧‧‧陰極區域
70‧‧‧感測區域
[圖1] 是實施方式的半導體裝置的俯視圖。 　　[圖2] 是沿著圖1的II-II線的半導體裝置的剖視圖。 　　[圖3] 是半導體裝置的元件區域18的剖視圖。 　　[圖4] 是實施方式的半導體裝置的電路圖。 　　[圖5] 是變形例的半導體裝置的與圖1對應的俯視圖。 　　[圖6] 是變形例的半導體裝置的與圖1對應的俯視圖。 　　[圖7] 是變形例的半導體裝置的與圖1對應的俯視圖。 　　[圖8] 是變形例的半導體裝置的與圖1對應的俯視圖。 　　[圖9] 是變形例的半導體裝置的與圖2對應的剖視圖。 　　[圖10] 是變形例的半導體裝置的與圖2對應的剖視圖。 　　[圖11] 是變形例的半導體裝置的與圖2對應的剖視圖。 　　[圖12] 是具有感測二極體的半導體裝置的電路圖。

Claims (13)

  1. 一種半導體裝置，具有：半導體基板；上部主電極，其係配置在前述半導體基板的上部；感測陽極電極，其係配置在前述半導體基板的上部；第1電阻層，其係配置在前述半導體基板的上部，具有比前述上部主電極和前述感測陽極電極還高的電阻率，並連接前述上部主電極和前述感測陽極電極；以及下部主電極，其係配置在前述半導體基板的下部；前述半導體基板具有切換元件和感測二極體；前述切換元件連接在前述上部主電極和前述下部主電極之間；前述感測二極體具有：p型的第1陽極區域，其係與前述感測陽極電極連接；以及n型的第1陰極區域，其係與前述下部主電極連接。
  2. 如請求項1的半導體裝置，其中，前述切換元件具有與上部主電極連接的p型的體區域；前述半導體基板具有將前述體區域從前述第1陽極區域分隔開的n型的分隔區域；前述第1電阻層的電阻率小於前述分隔區域的電阻率。
  3. 如請求項1或2的半導體裝置，其中，前述第1電阻層覆蓋前述上部主電極的上表面的一部分和前述感測陽極電極的上表面的一部分。
  4. 如請求項1或2的半導體裝置，其中，前述上部主電極覆蓋前述第1電阻層的上表面的一部分，前述感測陽極電極覆蓋前述第1電阻層的上表面的一部分。
  5. 如請求項1或2的半導體裝置，其中，前述第1電阻層利用多晶矽構成。
  6. 如請求項1或2的半導體裝置，其中，還具有第2電阻層，其係配置在前述半導體基板的上部，並具有比前述感測陽極電極還高的電阻率；前述第1陽極區域透過前述第2電阻層與前述感測陽極電極連接。
  7. 如請求項6的半導體裝置，其中，前述感測陽極電極具有與導線接合的焊墊；前述第2電阻層具有：第1部分，其係在前述焊墊的下部與前述感測陽極電極連接；以及第2部分，其係從前述第1部分延伸至前述焊墊的外側；前述第1陽極區域不配置在前述焊墊的下部，而是透過前述第2部分與前述感測陽極電極連接。
  8. 如請求項7的半導體裝置，其中，前述第2電阻層利用多晶矽構成。
  9. 如請求項6的半導體裝置，其中，還具有配線層，其係配置在前述半導體基板的上部，具有小於前述第2電阻層的電阻率，並與前述第1陽極區域接觸；前述第1陽極區域透過前述配線層與前述第2電阻層連接。
  10. 如請求項6的半導體裝置，其中，前述第1陽極區域與前述第2電阻層接觸。
  11. 如請求項10的半導體裝置，其中，前述第2電阻層利用多晶矽構成。
  12. 如請求項6的半導體裝置，其中，前述半導體基板具有n型的漂移區域，該n型的漂移區域配置在前述第1陽極區域和前述第1陰極區域之間，並且比起前述第1陰極區域，其n型雜質濃度為低；前述第2電阻層的電阻率大於前述漂移區域的電阻率。
  13. 如請求項1或2的半導體裝置，其中，前述半導體基板還具有續流二極體；前述續流二極體具有：p型的第2陽極區域，其係與前述上部主電極連接；以及n型的第2陰極區域，其係與前述下部主電極連接。
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