TWI648832B - 電子構件封裝及其製造方法 - Google Patents

電子構件封裝及其製造方法 Download PDF

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Publication number
TWI648832B
TWI648832B TW105121662A TW105121662A TWI648832B TW I648832 B TWI648832 B TW I648832B TW 105121662 A TW105121662 A TW 105121662A TW 105121662 A TW105121662 A TW 105121662A TW I648832 B TWI648832 B TW I648832B
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TW
Taiwan
Prior art keywords
electronic component
wiring portion
frame
conductive pattern
component package
Prior art date
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TW105121662A
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English (en)
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TW201724421A (zh
Inventor
Young Gwan Ko
高永寬
Sung Won Jeong
鄭丞洹
Original Assignee
Samsung Electronics Co., Ltd.
南韓商三星電子股份有限公司
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Application filed by Samsung Electronics Co., Ltd., 南韓商三星電子股份有限公司 filed Critical Samsung Electronics Co., Ltd.
Publication of TW201724421A publication Critical patent/TW201724421A/zh
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Publication of TWI648832B publication Critical patent/TWI648832B/zh

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    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract

一種電子構件封裝包括：配線部，所述配線部包括絕緣層、形成於所述絕緣層上的導電圖案、以及經由所述絕緣層而連接至所述導電圖案的導電通路；電子構件，安置於所述配線部上；框架，安置於所述配線部上且具有容置所述電子構件的貫穿孔；黏合層，將所述配線部與所述框架彼此結合；以及囊封劑，填充所述貫穿孔的至少一部分。

Description

電子構件封裝及其製造方法 [相關申請案的交叉參考]
本申請案主張於2015年12月21日在韓國智慧財產局提出申請的韓國專利申請案第10-2015-0183172號的優先權，所述韓國專利申請案的揭露內容併入本案供參考。
本發明是有關於一種電子構件封裝及其製造方法。
電子構件封裝是指將電子構件電性連接至例如電子裝置的主板等印刷電路板(printed circuit board，PCB)、並保護電子構件不受外部影響的封裝技術。近來，關於電子構件的技術開發的一個主流是減小構件的尺寸，且因此，在封裝領域，需要提供在保持多個引腳(pin)的同時尺寸減小的電子構件來滿足對小型化電子構件的快速增長的需求。
已提出一種晶圓級封裝(wafer level package，WLP)技術來作為滿足上述技術需求的封裝技術，所述晶圓級封裝技術使用在晶圓上形成的電子構件的電極焊墊(electrode pad)的重新分配線(redistribution line，RDL)。所述晶圓級封裝包括扇入式晶 圓級封裝(fan-in WLP)及扇出式晶圓級封裝(fan-out WLP)，且具體而言，近年來，尺寸減小且有利於達成多個引腳的扇出式晶圓級封裝已得到積極開發。
同時，在製造此種封裝時需要進行電性測試來判斷封裝是否存在缺陷。傳統上，所述電性測試一般是在將例如積體電路(integrated circuit，IC)晶片等電子構件安裝於封裝中之後進行。然而，在其中對安裝於封裝中的電子構件進行電性測試並確定所述封裝存在缺陷的情形中，除捨棄形成所述封裝的配線層以外，甚至可能必須捨棄所述電子構件，從而對製造商造成重大損失。
本發明的態樣可提供一種電子構件封裝，所述電子構件封裝具有緊湊的結構且容許在將電子構件安裝至配線部之前進行電子構件封裝的配線部的電性檢驗，因此使製造效率得到顯著提高。
本發明的態樣亦可提供一種有效地製造上述電子構件封裝的方法。
根據本發明的態樣，一種電子構件封裝可包括：配線部，包括絕緣層、形成於所述絕緣層上的導電圖案、以及經由所述絕緣層而連接至所述導電圖案的導電通路；電子構件，安置於所述配線部上；框架，安置於所述配線部上且具有容置所述電子構件的貫穿孔；黏合層，將所述配線部與所述框架彼此結合；以及囊封劑，填充所述貫穿孔的至少一部分。
根據本發明的另一態樣，一種製造電子構件封裝的方法可包括：製備配線部，所述配線部包括絕緣層、形成於所述絕緣層上的導電圖案、以及經由所述絕緣層而連接至所述導電圖案的導電通路；將電子構件安置於所述配線部上；製備具有貫穿孔的框架，並藉由黏合層而將所述框架結合至所述配線部的上表面；以及形成囊封劑，以填充所述貫穿孔的至少一部分。
根據本發明的另一態樣，一種電子構件封裝可包括：配線部，包括絕緣層、形成於所述絕緣層上的導電圖案、以及經由所述絕緣層而連接至所述導電圖案的導電通路；電子構件，安置於所述配線部上且具有電極焊墊，所述電極焊墊藉由安置於所述電極焊墊與所述導電圖案之間的導電結構而電性連接至所述導電圖案；框架，安置於所述配線部上且具有容置所述電子構件的貫穿孔；黏合層，將所述配線部與所述框架彼此結合；以及囊封劑，填充所述貫穿孔的至少一部分。所述導電結構的熔融溫度低於所述配線部的所述導電圖案的熔融溫度及所述電子構件的所述電極焊墊的熔融溫度。
100‧‧‧電子構件封裝
110‧‧‧配線部
111‧‧‧絕緣層
112、133‧‧‧導電圖案
113、132‧‧‧導電通路
120‧‧‧電子構件
121‧‧‧電極焊墊
122‧‧‧黏合性電子連接部
123‧‧‧黏合部
124‧‧‧導電凸塊
125‧‧‧填充樹脂
130‧‧‧框架
131‧‧‧黏合層
140‧‧‧囊封劑
150‧‧‧外部層
160‧‧‧支撐體
1000‧‧‧電子裝置
1010‧‧‧主板
1020‧‧‧晶片相關構件
1030‧‧‧網路相關構件
1040‧‧‧其他構件
1050、1130‧‧‧照相機
1060‧‧‧天線
1070‧‧‧顯示器
1080‧‧‧電池
1090‧‧‧訊號線
1100‧‧‧智慧型電話
1101‧‧‧主體
1110‧‧‧主板
1120‧‧‧電子構件
藉由結合附圖閱讀以下詳細說明，將更清楚地理解本發明的以上及其他態樣、特徵、及優點，在附圖中：圖1是示意性說明電子裝置系統的實例的方塊圖。
圖2是示意性說明應用至電子裝置的電子構件封裝的實例的視圖。
圖3是示意性說明電子構件封裝的實例的剖視圖。
圖4至圖8是示意性說明根據本發明示例性實施例的製造電子構件封裝的方法的剖視圖。
圖9至圖13是示意性說明根據本發明另一示例性實施例的製造電子構件封裝的方法的剖視圖。
在下文中，將參照附圖對本發明概念的實施例進行如下闡述。
然而，本發明概念可被示例成諸多不同的形式，而不應被視為僅限於本文中所述的具體實施例。確切而言，提供該些實施例是為了使此揭露內容將透徹及完整，並將向熟習此項技術者充分傳達本發明的範圍。
在本說明書通篇中，應理解，當稱一元件(例如，層、區、或晶圓(基板))位於另一元件「上」、「連接至」、或「耦合至」另一元件時，所述元件可直接位於所述另一元件「上」、直接「連接至」、或直接「耦合至」所述另一元件、或其間可存在其他中間元件。相比之下，當稱一元件「直接位於」另一元件「上」、「直接連接至」、或「直接耦合至」另一元件時，則其間可不存在中間元件或層。在通篇中相同的編號指代相同的元件。本文中所使用的用語「及/或」包含相關列出項其中一或多個項的任意及所有組合。
將顯而易見，儘管本文中可能使用「第一」、「第二」、「第 三」等用語來闡述各種部件、構件、區、層、及/或區段，然而該些部件、構件、區、層、及/或區段不應受限於該些用語。該些用語僅用於區分各個部件、構件、區、層、或區段。因此，在不背離示例性實施例的教示內容的條件下，以下所論述的第一部件、構件、區、層、或區段可被稱為第二部件、構件、區、層、或區段。
在本文中，為便於說明，可使用例如「在…之上(above)」、「上方的(upper)」、「在…之下(below)」、及「下方的(lower)」等空間相對性用語來闡述圖中所示一個元件相對於另一(其他)元件的關係。應理解，該些空間相對性用語旨在除圖中所示定向以外亦囊括裝置在使用或操作中的不同定向。舉例而言，若圖中的裝置被翻轉，則被闡述為在其他元件「之上」或「上方」的元件此時將被定向為在其他元件「之下」或「下方」。
電子裝置
圖1是示意性說明電子裝置系統的實例的方塊圖。參照圖1，電子裝置1000包括主板1010(或母板)。晶片相關構件1020、網路相關構件1030、及其他構件1040物理地及/或電性地連接至主板1010。該些構件亦耦合至下文所闡述的其他構件以形成各種訊號線1090。
晶片相關構件1020包括：記憶體晶片，例如揮發性記憶體(舉例而言，動態隨機存取記憶體(dynamic random access memory，DRAM))、非揮發性記憶體(舉例而言，唯讀記憶體 (read-only memory，ROM))、或快閃記憶體；應用處理器晶片，例如中央處理器(舉例而言，中央處理單元(central processing unit，CPU))、圖形處理器(舉例而言，圖形處理單元(graphics processing unit，GPU))、數位訊號處理器、密碼學處理器(cryptographic processor)、微處理器、或微控制器；以及邏輯晶片，例如類比-數位轉換器(analog-to-digital，ADC)或應用專用積體電路(application-specific integrated circuit，ASIC)。然而晶片相關構件1020並非僅限於此，而是可包括任何其他類型的晶片相關構件。此外，該些晶片相關構件1020可彼此組合。
網路相關構件1030可包括Wi-Fi(電氣及電子工程師學會(Institute of Electrical and Electronics Engineers，IEEE)802.11家族等)、全球互通微波存取(worldwide interoperability for microwave access，WiMAX)(IEEE 802.16家族等)、IEEE 802.20、長期演進(long term evolution，LTE)、僅支援資料的演進(evolution data only，Ev-DO)、高速封包存取+(high speed packet access +，HSPA+)、高速下行封包存取+(high speed downlink packet access +，HSDPA+)、高速上行封包存取+(high speed uplink packet access +，HSUPA+)、增強型資料GSM環境(enhanced data GSM environment，EDGE)、全球行動通訊系統(global system for mobile communication，GSM)、全球定位系統(global positioning system，GPS)、通用封包無線電服務(general packet radio service，GPRS)、分碼多重存取(code division multiple access，CDMA)、分時多重 存取(time division multiple access，TDMA)、數位增強型無線電訊(digital enhanced cordless telecommunications，DECT)、藍芽、3G、4G、5G、及下文所指定的某些其他無線協定/有線協定。然而，網路相關構件1030並非僅限於此，而是可包括任何其他無線/有線標準或協定。此外，該些網路相關構件1030亦可與上述晶片相關構件1020組合於一起。
其他構件1040可包括高頻(high frequency，HF)電感器、鐵氧體電感器(ferrite inductor)、功率電感器、鐵氧體珠粒、低溫共燒陶瓷(low temperature co-firing ceramic，LTCC)、電磁干擾(electro-magnetic interference，EMI)濾波器、多層陶瓷電容器(multilayer ceramic condenser，MLCC)等。然而，其他構件1040並非僅限於此，而是可包括用於各種其他用途的被動式構件等。此外，該些其他構件1040可與上述晶體相關構件1020及/或網路相關構件1030組合於一起。
根據電子裝置1000的類型而定，電子裝置1000可包括可物理地及/或電性地連接至主板1010或可不物理地及/或不電性地連接至主板1010的其他構件。該些構件包括照相機1050、天線1060、顯示器1070、電池1080、音訊編解碼器(圖中未示出)、視訊編解碼器(圖中未示出)、功率放大器(圖中未示出)、羅盤(圖中未示出)、加速度計(圖中未示出)、陀螺儀(圖中未示出)、揚聲器(圖中未示出)、大容量儲存裝置(例如，硬碟驅動機)(圖中未示出)、光碟(compact disk)(圖中未示出)、數位多功能光 碟(digital versatile disk)(圖中未示出)等。然而，所述任何其他構件並非僅限於此，且根據電子裝置1000的類型而定可包括用於各種用途的其他構件。
電子裝置1000可為智慧型電話、個人數位助理(personal digital assistant，PDA)、數位攝影機(digital video camera)、數位照相機(digital still camera)、網路系統、電腦、監視器、平板電腦(tablet)、膝上型電腦、隨身型易網機(netbook)、電視、視訊遊戲機(video game console)、或智慧型手錶等。然而，電子裝置1000並非僅限於此，而是亦可為處理資料的任何其他某些電子裝置。
圖2是示意性說明應用至電子裝置的電子構件封裝的實例的視圖。所述電子構件封裝應用至如上所述用於各種用途的各種電子裝置1000中。舉例而言，主板1110容置於智慧型電話1100的主體1101內，且各種電子構件1120可物理地及/或電性地連接至主板1110。此外，可物理地及/或電性地連接至主板1110或可不物理地及/或可不電性地連接至主板1110的另一構件(例如，照相機1130)可容置於主體1101內。此處，電子構件1120中的某些電子構件可為如上所述的晶片相關構件，且電子構件封裝100可為例如應用處理器，但其並非僅限於此。
電子構件封裝及其製造方法
圖3是示意性說明電子構件封裝的實例的剖視圖。根據示例性實施例的電子構件封裝100可包括配線部110、電子構件 120、框架130、黏合層131、及囊封劑140作為主要構件。
配線部110可被提供作為電子構件120的安裝區，並電性連接至電子構件120。配線部110可包括絕緣層111、導電圖案112、以及導電通路113，且可用於重新分配電子構件120的配線結構。在圖3的實例中，雖然所示配線部110具有多層式結構，但視需要，配線部110可形成為單層式結構。此外，根據設計細節而定，配線部110可具有更大數量的層。
作為可包含於絕緣層111中的絕緣材料，可使用熱固性樹脂(例如，環氧樹脂)、熱塑性樹脂(例如，聚醯亞胺)、藉由在熱固性樹脂或熱塑性樹脂中充注增強材料(例如，玻璃纖維或無機填料)而獲得的樹脂(例如，預浸體(pre-preg)、味之素增層膜(Ajinomoto build-up film，ABF)、FR-4、雙馬來醯亞胺三嗪(bismaleimide triazine，BT)樹脂等)。此外，在其中使用可光固化材料(photocurable material，PID)作為絕緣材料的情形中，絕緣層111可被形成得更薄且可更輕易地達成微圖案。分別形成配線部110的相應層的各個絕緣層111可由相同的材料形成，且可視需要由不同的材料形成。絕緣層111的厚度並無特別限制。舉例而言，除導電圖案112以外的每一層的厚度可介於約5微米至20微米範圍內，且包含導電圖案112在內的每一層的厚度可介於約15微米至70微米的範圍內。
導電圖案112可用作配線圖案及/或焊墊圖案，且可由例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、 鉛(Pd)、或其合金等電性導電材料形成。導電圖案112可根據對應層的設計而執行各種功能。舉例而言，導電圖案112可用作接地(GND)圖案、功率(PWR)圖案、訊號(S)圖案、或重新分配圖案。此處，除接地(GND)圖案及功率(PWR)圖案以外，訊號(S)圖案包括各種訊號，例如資料訊號等。此外，導電圖案112可用作通路焊墊(via pad)或外部連接端子焊墊而作為焊墊圖案。導電圖案112的厚度並無特別限制，且舉例而言，可介於10微米至50微米範圍內。
表面處理層可形成於被定位成暴露於絕緣層111外部的導電圖案112上，舉例而言，視需要連接至電子構件120的導電圖案上。對表面處理層並無特別限制，只要其為此項技術中已知的即可，且可藉由電解鍍金、無電鍍金、有機可焊性保護(organic solderability preservative，OSP)或無電鍍錫、無電鍍銀、無電鍍鎳/浸金鍍覆、直接浸金(direct immersion gold，DIG)鍍覆、熱空氣焊料均塗(hot air solder leveling，HASL)等來形成所述表面處理層。
在本示例性實施例中，位於配線部110的與上面安置有電子構件120的表面相對的表面上(亦即，安置於圖3中配線部110的下表面上)的導電圖案112可用作連接焊墊，所述連接焊墊成為與另一板或裝置的連接路徑，且如下文所述，導電圖案112可藉由使用支撐體的製程而被嵌入絕緣層111中。
導電通路113可將形成於不同層上的導電圖案112等電 性連接至彼此，且因此可在電子構件封裝100內形成電路徑，亦可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金等導電材料作為導電通路113的形成材料。導電通路113可被完全填充以導電材料，或導電材料可形成於所述通路的壁上。導電通路113可具有此項技術中已知的任意形狀，例如直徑朝其下表面減小的錐形形狀、直徑朝其下表面增大的倒錐形形狀、圓柱形狀。
安置於配線部110上以支撐封裝100的框架130可保持剛性並確保厚度均勻性。框架130可具有用於安置電子構件120的貫穿孔，且此種貫穿孔可由環繞電子構件120的內壁形成。電子構件120可位於所述貫穿孔內。根據示例性實施例，其中安置有電子構件120的區可具有溝槽形狀，而非具有所述貫穿孔的形狀。
用以形成框架130的材料並無特別限制，且可使用成型樹脂或預浸體，較佳的是金屬或陶瓷材料。舉例而言，如下文所述，在孔形成於預浸體中之後，框架130可結合至配線部110，且為此，可將黏合層131夾置於框架130與配線部110之間。
在本示例性實施例中，可在框架130中形成穿透過框架130並用作上部部分的及下部部分的電性導電結構的導電通路132。舉例而言，如圖3所示，框架130的導電通路132可被設置成使導電通路132可連接至配線部110的導電圖案112及形成於框架130的上部部分的導電圖案。導電圖案133-其是形成於囊封 劑140上且電性連接至框架130的導電通路132的元件-可連接至可安置於其上部部分上的附加電子構件。在此種情形中，導電通路132可藉由在框架130中形成孔(hole)並藉由例如鍍覆等方法填充所述孔而形成，或可被形成為導電柱。
電子構件120可為各種主動式構件(例如二極體、真空管、電晶體等)或被動式構件(例如電感器、電容器、電阻器等)。此外，電子構件120可為其中將數百至數百萬個或更多個元件整合於一起的單個晶片形式的積體電路(integrated circuit，IC)晶片。若需要，電子構件120可為其中將積體電路封裝成倒裝晶片(flipchip)形式的電子構件。所述積體電路晶片可為，舉例而言，例如中央處理器(例如中央處理單元)等應用處理器晶片、圖形處理器(例如圖形處理單元)、數位訊號處理器、密碼學處理器、微處理器、或微控制器，但並非僅限於此。此處，在圖3中示出其中一個電子構件120安裝於配線部110上的構造，但亦可使用二或更多個構件。
電子構件120可包括一或多個電性連接至配線部110的電極焊墊121，且如圖3中的實例所示，電子構件120可在其中電子構件120的電極焊墊121面對配線部110的狀態下安裝。電子構件120可被配線部110重新分配，且為此，可將配線部110的導電圖案112及例如焊料等黏合性電子連接部122夾置於電子構件120與配線部110之間。此外，為了穩定地安裝電子構件20，可將由絕緣黏合層等形成的黏合部123夾置於電子構件120與配 線部110之間。此處，根據示例性實施例，黏合部123可加以適當修改或被去除。舉例而言，黏合部123可為被形成為暴露出電子構件120的電極焊墊121的阻焊劑。電子構件120在其橫截面中的厚度並無特別限制，且根據電子構件120的類型而定可有所變化。舉例而言，在其中電子構件120為積體電路晶片的情形中，電子構件120在其橫截面中的厚度可介於約100微米至480微米的範圍內，但並非僅限於此。
用於保護電子構件120的囊封劑140覆蓋電子構件120且填充框架130的貫穿孔的至少一部分。此外，如圖3所示，囊封劑140可被形成為覆蓋框架130的上部部分。在此種情形中，形成於框架130的上部部分上的囊封劑140的對應部分可暴露出與框架130的導電通路132對應的區，且藉由此種構造，可將附加電子構件等安裝於所述上部部分上。
用於形成囊封劑140的材料並無特別限制，只要囊封劑140可執行保護電子構件的功能即可。舉例而言，囊封劑140可由以下材料形成：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺；藉由在熱固性樹脂或熱塑性樹脂中充注增強材料(例如玻璃纖維或無機填料)而獲得的樹脂，例如預浸體、ABF、FR-4、BT、PID樹脂等。此外，可藉由在配線部110及框架130上堆疊未固化的樹脂膜並固化所述樹脂膜來獲得囊封劑140，且除此方法以外，可藉由使用例如環氧模製化合物(epoxy molding compound，EMC)等已知的模製方案來獲得囊封劑140。
為阻擋電磁波，囊封劑140可視需要含有導電顆粒。可由任意材料形成任意導電顆粒，只要所述材料能夠阻擋電磁波即可。舉例而言，所述導電顆粒可由銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或焊料形成，但並非僅限於此。
黏合層131安置於配線部110與框架130之間以結合配線部110與框架130，且用以如在下文中針對製程所述將經適當處理的框架130結合至配線部110。舉例而言，黏合層131可由例如預浸體或阻焊劑等未固化材料形成，且可除使用電性絕緣材料以外亦使用電性導電材料而電性連接至導電圖案等。當處於未固化狀態的黏合層131被按壓時，黏合層131可向上延伸至框架130的貫穿孔(請參照區域A)。此處，如圖3所示，在已向上流至框架130的貫穿孔的狀態下固化的黏合層131可與填充所述貫穿孔的囊封劑140接觸。亦即，黏合層131的一部分可形成於貫穿孔的內表面與電子構件120之間。可藉由配線部110與框架130的結合製程而獲得黏合層131的此種形狀，從而為封裝100提供結構穩定性。
外部層150可形成於配線部110的下部部分及框架130的上部部分中，以保護配線部110與框架130不受外部物理影響或化學影響。在此種情形中，外部層150可具有暴露出導電圖案112及導電圖案133的至少一部分的開口。對外部層150的材料並無特別限制，且例如可使用阻焊劑。此外，可使用與配線部110 的絕緣層111的材料相同的材料。外部層150一般為單層的，但可視需要被構造成多層的。
儘管圖中未示出，然而可在電子構件封裝100的最下部分中提供連接端子。所述連接端子是將電子構件封裝100物理地及/或電性地連接至外部的構件。舉例而言，電子構件封裝100藉由所述連接端子而安裝於電子裝置的主板上。所述連接端子經由形成於外部層150中的開口而連接至導電圖案112，且亦經由導電圖案112及導電通路113而電性連接至電子構件120。所述連接端子可由例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或焊料等導電材料形成，但所述連接端子的材料並非僅限於此。所述連接端子可為焊盤(land)、球、或引腳。所述連接端子可被形成為多層或單層的。當所述連接端子被形成為多層的時，所述連接端子可包括銅柱及焊料，且當連接端子被形成為單層的時，所述連接端子可包括例如錫-銀焊料或銅，但所述連接端子並非僅限於此。
外部連接端子的一部分可安置於扇出區中。所述扇出區是指處於其中安置有電子構件的區的外部的區。亦即，根據示例性實施例的電子構件封裝100為扇出式封裝。所述扇出式封裝相較於扇入式封裝具有優異的可靠性，達成多個輸入/輸出(I/O)端子，且易於形成三維(3D)互連。此外，相較於球柵陣列(ball grid array，BGA)封裝或焊盤柵陣列(land grid array，LGA)封裝，扇出式封裝無需單獨的板便能夠安裝於電子裝置上，此使得其厚 度減小且具有優異的價格競爭力。
由於上述電子構件封裝100不包括例如插板(interposer)等板，因而其可被形成為具有緊密的尺寸，且此外，電子構件封裝100可具有適合於在電子構件安裝於電子構件封裝100中之前進行局部電性測試的結構。因此，可減少所述封裝的各構件中價格相對高的電子構件120的不必要浪費。亦即，當在電子構件120安裝之後進行電性測試時，即使配線部存在缺陷而非電子構件存在缺陷，電子構件120亦變得不可用。在下文中，將闡述本發明中製造具有上述結構的電子構件封裝的方法。藉由對所述製造方法的說明，可更清晰地理解根據上述示例性實施例或根據經修改的實例的封裝結構。
圖4至圖8是示意性說明根據本發明示例性實施例的一種製造電子構件封裝的方法的剖視圖。
首先，如圖4所示，配線部110形成於支撐體160之上。支撐體160用於應對相對薄的配線部110，且用於形成支撐體160的材料並無限制，只要其可用於支撐配線部110即可。支撐體160可具有多層式結構，且可包括脫膜層或金屬層以使支撐體160在隨後的製程中可相對於配線部110輕易地移除。在本示例性實施例中，如下文所述，可在其中支撐體160結合至配線部110的狀態下對配線部110進行電性測試。
為了達成配線部110，絕緣層111、導電圖案112及導電通路113可被形成為具有預期的形狀，且絕緣層111、導電圖案 112、以及導電通路113可重複地形成達所期望的次數。詳言之，絕緣層111可藉由已知的方法形成。舉例而言，可藉由對材料進行層合併隨後進行固化的方法、或對材料進行塗佈及固化的方法形成絕緣層111。
作為層合方法，舉例而言，可使用如下方法：在熱壓機中在高溫下對材料進行壓製達預定時間週期並將所述材料減壓並冷卻至室溫，隨後在冷壓機中冷卻所述材料並分離工具。作為塗佈方法，可使用以刮漿板(squeegee)應用墨水的絲網印刷方法、或以噴霧方式應用墨水的噴霧印刷方法。此處，固化可為以使得材料不完全固化的方式進行乾燥，以使用光刻製程作為後製程。
在本示例性實施例中，在電子構件120安裝之前可在此階段進行電性測試。詳言之，判斷配線部110在電性連接方面是否存在缺陷。舉例而言，可將測試夾具在配線部110的上部部分中連接至導電圖案112。藉由所述電性測試，可提前確定配線部110是否存在缺陷，從而最小化電子構件的不必要的浪費。亦即，當在測試中確定配線部110存在缺陷時，則配線部110可被捨棄或被回收用於另一用途，且不進行隨後的製程以減少製程成本。配線部110可具有例如用於電性測試的菊錬(daisy chain)等附加結構，且因此，即使在其中支撐體160結合至配線部110的下表面的狀態下，亦可對配線部110的上表面進行電性測試。
在對配線部110進行電性測試之後，如圖5所示，將電子構件120安裝於配線部110上，且在此種情形中，電子構件120 可被安置成使電極焊墊121面對配線部110。為了穩定地安裝電子構件120，在安裝電子構件120之前，可在配線部110上形成例如焊料等黏合性電子連接部122以及由例如絕緣黏合層、阻焊劑等形成的黏合部123。
此後，如圖6所示，製備具有貫穿孔的框架130並將其結合至配線部110，且為此，將黏合層131夾置於框架130與配線部110之間。在結合製程之前，藉由雷射束加工或機械加工而在與電子構件120對應的位置處在框架130中形成貫穿孔。在此種情形中，形成框架130的材料並無特別限制，且可使用處於固化狀態的預浸體。作為另外一種選擇，可使用任意黏合層131，只要其提供穩定的結合功能即可。舉例而言，可使用處於非固化狀態的預浸體或阻焊劑。藉由此結合製程，黏合層131可如上所述在其中黏合層131向上流至貫穿孔的狀態下被固化。
在本示例性實施例中，闡述了其中在安裝電子構件120之後結合框架130的方案，但可改變所述次序。亦即，在對配線部110進行電性測試之後，可首先結合框架130且可接著結合電子構件120。在此種情形中，可在框架130結合之前或之後形成貫穿孔。
在框架130結合之後或在框架130結合時，形成囊封劑140以覆蓋電子構件120。為形成囊封劑140，舉例而言，可使用在配線部110及框架130上堆疊處於非固化狀態的樹脂膜(例如，ABF等)並隨後固化所述樹脂膜的方法。圖7說明包括一直到形 成囊封劑140為止的構造。此處，儘管圖中未示出，然而在框架130形成之後，支撐體160可自配線部110移除。可利用在此項技術中使用的蝕刻法或除污法(desmear method)恰當地移除在支撐體160分離之後剩餘的材料。然而，支撐體160可不必在此階段中移除，並亦可在隨後的製程中移除。
此後，如圖8所示，在框架130中形成導電通路132及導電圖案133。藉由雷射束加工或機械加工在框架130及囊封劑140中形成孔，並藉由鍍覆等對所述孔填充導電材料。此後，形成例如阻焊劑等外部層，所述外部層被形成為在其上表面及下表面上具有恰當的圖案，由此獲得如圖3所示的封裝結構。此處，如在下文所述的示例性實施例中一般，在框架130結合至配線部110之前，可藉由恰當地處理框架130並將金屬薄膜圖案化的方法來提前獲得導電通路132及導電圖案133。此外，可將附加電子構件堆疊並安裝於其上表面上，藉此可獲得所謂的堆疊式封裝(package-on-package，POP)結構且可形成保護附加電子構件的附加囊封劑。
圖9至圖13是根據本發明另一示例性實施例示意性地說明一種製造電子構件封裝的方法的剖視圖。
首先，如圖9的實例中所示，在支撐體160上形成配線部110，且將最上絕緣層111構造成暴露出導電圖案112的一部分。此後，形成導電凸塊124以連接至所暴露出的導電圖案112。導電凸塊124用於與電子構件120及框架130的導電通路132形 成穩定的耦合結構。在此種情形中，如上所述，在形成導電凸塊124之前可對配線部110進行電性測試。
此後，如圖10的實例中所示，將電子構件120安置於並安裝於配線部110上，且可利用例如回流等製程將電極焊墊121直接連接至導電凸塊124。在安裝電子構件120之後，可在配線部110上及電子構件120上提供底部填充樹脂125(其是一種電性絕緣材料)以獲得如圖11所示的更穩定的安裝結構。
此後，如圖12的實例中所示，利用黏合層131將具有貫穿孔的框架130結合至配線部110。在本示例性實施例中，框架130可在其中在框架130中提前形成導電通路132及導電圖案133的狀態下結合至配線部110。在具體實例中，可使用敷銅積層板(copper clad laminate，CCL)作為框架130的基本結構，且框架130可藉由執行在敷銅積層板上進行孔加工並對所述孔填充導電材料的製程、以及將金屬薄膜恰當地圖案化等製程而獲得。
在以與上述製程相同的方式結合框架130之後或在以與上述製程相同的方式結合框架130時，形成覆蓋電子構件120的囊封劑140，且此後，如在圖13所示的實例中一般，利用雷射束加工或機械加工在囊封劑140中形成開放區域，且因此，可暴露出導電圖案133等。此後，可形成例如阻焊劑等外部層，以在所述外部層的上表面及下表面上具有恰當的圖案以獲得封裝結構，且在此種情形中，如上所述，支撐體160可在框架130結合後的恰當的時間被移除。
如上所述，使用根據本發明示例性實施例提出的電子構件封裝可減小封裝的尺寸，且甚至在使用多個電子構件時亦具有高的利用率。由於在安裝電子構件之前對電子構件封裝的配線部進行電性測試，製造效率可大幅提高。此外，利用根據本發明示例性實施例的製造方法，可有效地製造上述電子構件封裝。
儘管以上已示出並闡述了示例性實施例，然而對於熟習此項技術者將顯而易見，在不背離由隨附申請專利範圍界定的本發明的範圍的條件下，可作出各種潤飾及變化。

Claims (21)

  1. 一種電子構件封裝，包括：配線部，包括絕緣層、形成於所述絕緣層上的導電圖案、以及經由所述絕緣層而連接至所述導電圖案的導電通路；電子構件，安置於所述配線部上；框架，為電性絕緣且安置於所述配線部上且具有容置所述電子構件的貫穿孔；黏合層，將所述配線部與所述框架彼此結合；以及囊封劑，填充所述貫穿孔的至少一部分且覆蓋所述電子構件的上表面，其中所述黏合層的一部分形成於所述貫穿孔的內表面與所述電子構件之間且接觸所述囊封劑。
  2. 如申請專利範圍第1項所述的電子構件封裝，其中所述黏合層是預浸體。
  3. 如申請專利範圍第1項所述的電子構件封裝，其中所述黏合層是阻焊劑。
  4. 如申請專利範圍第1項所述的電子構件封裝，其中包含於所述配線部中的所述絕緣層包含可光固化材料。
  5. 如申請專利範圍第1項所述的電子構件封裝，更包括穿透所述框架的導電通路。
  6. 如申請專利範圍第5項所述的電子構件封裝，其中所述囊封劑覆蓋所述框架並暴露出與所述框架的所述導電通路對應的區。
  7. 如申請專利範圍第5項所述的電子構件封裝，更包括形成於所述囊封劑上並電性連接至所述框架的所述導電通路的導電圖案。
  8. 如申請專利範圍第1項所述的電子構件封裝，更包括形成於所述配線部上並暴露出與所述電子構件連接的電極焊墊的阻焊劑。
  9. 如申請專利範圍第1項所述的電子構件封裝，更包括嵌於所述絕緣層中並位於所述配線部的與上面安置有所述電子構件的表面相對的表面上的導電圖案。
  10. 如申請專利範圍第1項所述的電子構件封裝，其中所述電子構件藉由焊料而電性連接至所述配線部。
  11. 一種製造電子構件封裝的方法，所述製造電子構件封裝的方法包括：製備配線部，所述配線部包括絕緣層、形成於所述絕緣層上的導電圖案、以及經由所述絕緣層而連接至所述導電圖案的導電通路；將電子構件安置於所述配線部上；製備具有貫穿孔的框架，並藉由黏合層而將所述框架結合至所述配線部的上表面，其中所述框架為電性絕緣；以及形成囊封劑，以填充所述貫穿孔的至少一部分且覆蓋所述電子構件的上表面，且在所述貫穿孔之區中，所述黏合層接觸所述囊封劑。
  12. 如申請專利範圍第11項所述的製造電子構件封裝的方法，更包括：在將所述電子構件安置於所述配線部上之前，藉由對安置於所述配線部的所述上表面上的所述導電圖案施加電性訊號而對所述配線部執行電性測試。
  13. 如申請專利範圍第12項所述的製造電子構件封裝的方法，其中製備所述配線部包括在支撐體上形成所述絕緣層、所述導電圖案、及所述導電通路，且所述電性測試是在其中所述支撐體耦合至所述配線部的狀態下執行。
  14. 如申請專利範圍第11項所述的製造電子構件封裝的方法，其中在將所述電子構件安置於所述配線部上之後，將所述框架結合至所述配線部。
  15. 如申請專利範圍第11項所述的製造電子構件封裝的方法，更包括：在將所述框架結合至所述配線部的所述上表面之前，形成穿透所述框架的導電通路。
  16. 如申請專利範圍第11項所述的製造電子構件封裝的方法，更包括在將所述框架結合至所述配線部的所述上表面之後，形成穿透所述框架的導電通路。
  17. 一種電子構件封裝，包括：配線部，包括絕緣層、形成於所述絕緣層上的導電圖案、以及經由所述絕緣層而連接至所述導電圖案的導電通路；電子構件，安置於所述配線部上並具有電極焊墊，所述電極焊墊經由安置於所述電極焊墊與所述導電圖案之間的導電結構而電性連接至所述導電圖案；框架，為電性絕緣且安置於所述配線部上並具有容置所述電子構件的貫穿孔；黏合層，將所述配線部與所述框架彼此結合；以及囊封劑，填充所述貫穿孔的至少一部分且覆蓋所述電子構件的上表面，其中所述導電結構的熔融溫度低於所述配線部的所述導電圖案的熔融溫度及所述電子構件的所述電極焊墊的熔融溫度，以及其中所述黏合層的一部分形成於所述貫穿孔的內表面與所述電子構件之間且接觸所述囊封劑。
  18. 如申請專利範圍第17項所述的電子構件封裝，更包括穿透所述框架並電性連接至所述配線部的所述導電圖案的導電通路。
  19. 如申請專利範圍第18項所述的電子構件封裝，其中所述囊封劑覆蓋所述框架並暴露出與所述框架的所述導電通路對應的區。
  20. 如申請專利範圍第17項所述的電子構件封裝，更包括位於所述電子構件與所述配線部之間的阻焊劑。
  21. 如申請專利範圍第17項所述的電子構件封裝，更包括位於所述電子構件與所述配線部之間的底部填充樹脂。
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