TWI627722B - 三層式基板上覆晶圓上覆晶片結構 - Google Patents

三層式基板上覆晶圓上覆晶片結構 Download PDF

Info

Publication number
TWI627722B
TWI627722B TW105124585A TW105124585A TWI627722B TW I627722 B TWI627722 B TW I627722B TW 105124585 A TW105124585 A TW 105124585A TW 105124585 A TW105124585 A TW 105124585A TW I627722 B TWI627722 B TW I627722B
Authority
TW
Taiwan
Prior art keywords
die
ivr
package
encapsulating material
electrically coupled
Prior art date
Application number
TW105124585A
Other languages
English (en)
Other versions
TW201733068A (zh
Inventor
余振華
侯上勇
李雲漢
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201733068A publication Critical patent/TW201733068A/zh
Application granted granted Critical
Publication of TWI627722B publication Critical patent/TWI627722B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1026—Forming openings in dielectrics for dual damascene structures the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本發明揭示一種封裝，其包含一整合式電壓調節器(IVR)晶粒，其中該IVR晶粒包含第一IVR晶粒之一頂面處之金屬柱。該封裝進一步包含將該第一IVR晶粒囊封於其內之一第一囊封材料，其中該第一囊封材料具有與該等金屬柱之頂面共面之一頂面。複數個重佈線位於該第一囊封材料及該IVR晶粒上方。該複數個重佈線電耦合至該等金屬柱。一核心晶片與該複數個重佈線重疊且接合至該複數個重佈線。一第二囊封材料將該核心晶片囊封於其內，其中該第一囊封材料之邊緣及該第二囊封材料之各自邊緣彼此垂直對準。一中介層或一封裝基板位於該IVR晶粒下方且接合至該IVR晶粒。

Description

三層式基板上覆晶圓上覆晶片結構
本發明關於一種半導體元件。
中央處理單元(CPU)對輸入/輸出(I/O)及由CPU消耗之功率具有高要求。例如，一CPU可包含複數個核心，且需要消耗大量功率。另一方面，對提供功率之要求亦很高。例如，電源供應電壓需要非常穩定。據此，複數個電壓調節器可連接至相同CPU晶片來提供功率。
根據本揭露之一些實施例，一種封裝包含一IVR晶粒，其中該IVR晶粒包含第一IVR晶粒之一頂面處之金屬柱。該封裝進一步包含將該第一IVR晶粒囊封於其內之一第一囊封材料，其中該第一囊封材料具有與該等金屬柱之頂面共面之一頂面。複數個重佈線位於該第一囊封材料及該IVR晶粒上方。該複數個重佈線電耦合至該等金屬柱。一核心晶片與該複數個重佈線重疊且接合至該複數個重佈線。一第二囊封材料將該核心晶片囊封於其內，其中該第一囊封材料之邊緣及該第二囊封材料之各自邊緣彼此垂直對準。一中介層或一封裝基板位於該IVR晶粒下方且接合至該IVR晶粒。
根據本揭露之一些實施例，一種封裝包含一第一IVR晶粒及一第二IVR晶粒，其等各包含：金屬柱；電壓調節器電路，其等電耦合至該等金屬柱；及一電感器，其電耦合至該等電壓調節器電路。一第一 囊封材料將該第一IVR晶粒及該第二IVR晶粒囊封於其內。該第一囊封材料具有與該第一IVR晶粒及該第二IVR晶粒中之該等金屬柱之頂面共面之一頂面。一介電層與該第一IVR晶粒、該第二IVR晶粒及該第一囊封材料重疊。複數個重佈線包含該介電層中之部分。該複數個重佈線電耦合至該第一IVR晶粒及該第二IVR晶粒。一第一CPU晶片及一第二CPU晶片分別與該第一IVR晶粒及該第二IVR晶粒重疊且分別電耦合至該第一IVR晶粒及該第二IVR晶粒。一第二囊封材料將該第一CPU晶片及該第二CPU晶片囊封於其內。
根據本揭露之一些實施例，一種封裝包含一第一裝置晶粒，其包含：一半導體基板；一第一貫穿導通孔及一第二貫穿導通孔，其等穿過該半導體基板；一主動電路，其位於該半導體基板之一表面處；一第一金屬柱，其位於該第一裝置晶粒之一頂面處；及一第二金屬柱，其位於該第一裝置晶粒之一頂面處。該第一金屬柱電耦合至該主動電路及該第一貫穿導通孔。該第二金屬柱電耦合至該第二貫穿導通孔且不與該第一裝置晶粒中之全部主動電路電耦合。該封裝進一步包含：一第一囊封材料，其將該第一裝置晶粒囊封於其內；及一第二裝置晶粒，其與該第一裝置晶粒重疊且電耦合至該第一裝置晶粒。一封裝組件位於該裝置晶粒下方且接合至該裝置晶粒。該第二貫穿導通孔及該第二金屬柱將該封裝組件電耦合至該第二裝置晶粒。
20‧‧‧載體
22‧‧‧黏著層
24A‧‧‧裝置晶粒
24B‧‧‧裝置晶粒
24C‧‧‧裝置晶粒
24D‧‧‧裝置晶粒
24E‧‧‧裝置晶粒
26‧‧‧整合式電壓調節器(IVR)電路
28‧‧‧半導體基板
30‧‧‧電感器
32‧‧‧互連結構
34‧‧‧介電層
36A‧‧‧貫穿導通孔
36B‧‧‧貫穿導通孔
38‧‧‧導電路徑
40A‧‧‧金屬柱
40B‧‧‧金屬柱
44‧‧‧囊封材料
46‧‧‧介電層
48‧‧‧重佈線(RDL)/金屬墊
50‧‧‧開口
52A‧‧‧裝置晶粒/核心晶片
52B‧‧‧裝置晶粒
52C‧‧‧裝置晶粒/輸入/輸出(IO)晶粒/輸入/輸出(IO)晶片
54‧‧‧積體電路裝置/積體電路
56‧‧‧焊接區
58‧‧‧半導體基板
60‧‧‧重佈線(RDL)
64‧‧‧囊封材料
66‧‧‧封裝
68‧‧‧封裝
70‧‧‧中介層
71‧‧‧焊接區
72‧‧‧半導體基板
73‧‧‧底部填膠
74‧‧‧互連結構
76‧‧‧導通孔
78‧‧‧貫穿導通孔
80‧‧‧封裝基板
82‧‧‧焊接區
84‧‧‧互連結構
200‧‧‧製程流程
202‧‧‧步驟
204‧‧‧步驟
206‧‧‧步驟
208‧‧‧步驟
210‧‧‧步驟
212‧‧‧步驟
214‧‧‧步驟
216‧‧‧步驟
218‧‧‧步驟
220‧‧‧步驟
自結合附圖來閱讀之以下詳細描述最佳地理解本揭露之態樣。應注意，根據業界之通行做法，各種構件未按比例繪製。事實上，為使論述清楚，可任意增大或減小各種構件之尺寸。
圖1至圖9繪示根據一些實施例之包含整合式電壓調節器之一封裝之形成中之中間階段之剖面圖；圖10繪示根據一些實施例之包含整合式電壓調節器之一封裝之 剖面圖。
圖11繪示根據一些實施例之用於形成一封裝之一製程流程。
以下揭露提供用於實施本發明之不同特徵之諸多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等僅為實例且不意欲具限制性。例如，在以下描述中，使一第一構件形成於一第二構件上方或形成於一第二構件上可包含其中形成直接接觸之該第一構件及該第二構件之實施例，且亦可包含其中可使額外構件形成於該第一構件與該第二構件之間使得該第一構件及該第二構件可不直接接觸之實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複係為了簡化及清楚且其本身不指示所論述之各種實施例及/或組態之間之一關係。
此外，為易於描述，本文可使用空間相關術語(諸如「下方」、「下面」、「下」、「上覆」、「上」及其類似者)來描述一元件或構件與另一元件或構件之關係，如圖中所繪示。空間相關術語除涵蓋圖中所繪繪之定向之外，亦意欲涵蓋裝置在使用或操作中之不同定向。設備可以其他方式定向(旋轉90度或呈其他定向)，據此，可同樣地解譯本文所使用之空間相關描述符。
根據各種例示性實施例來提供一多階層封裝及其形成方法。可使用一基板上覆晶圓上覆晶片(CoWoS)製程來形成該多階層封裝。圖中繪示形成該封裝之中間階段。本文論述一些實施例之一些變動。在全部各種視圖及繪示性實施例中，相同元件符號用於標示相同元件。
圖1至圖9繪示根據一些實施例之一多階層封裝之形成中之中間階段之剖面圖。亦在圖11中所展示之製程流程200中示意性地繪示圖1至圖9中所展示之步驟。
參考圖1，提供載體20，且將黏著層22放置於載體20上方。載體 20可為一坯料玻璃載體、一坯料陶瓷載體、一有機載體或其類似者，且可具有一半導體晶圓(其具有一俯視圓形形狀)之一形狀。載體20有時指稱一載體晶圓。黏著層22可由(例如)一光熱轉換(LTHC)材料形成，且亦可使用其他類型之黏著劑。根據本揭露之一些實施例，黏著層22能夠在光之加熱下分解，且因此可使載體20脫離形成於其上之結構。
參考圖2，將裝置晶粒24(其包含24A、24B、24C、24D及24E)安置於黏著層22上方。將各自步驟展示為圖11中所展示之製程流程中之步驟202。在本描述中，裝置晶粒24亦指稱階層1晶粒。應瞭解，在晶圓級處執行隨後將論述之製程步驟。據此，存在相同於包含裝置晶粒24A、24B、24C、24D及24E之晶粒群組的複數個晶粒群組。複數個晶粒群組可經配置為包含複數個列及複數個行之一陣列。裝置晶粒24可彼此相同或彼此不同。例如，裝置晶粒24A、24B、24C及24D可彼此相同，且不同於裝置晶粒24E。
根據本揭露之一些實施例，裝置晶粒24係整合式電壓調節器(IVR)晶粒，其包含用於調節上覆晶粒之電壓供應之電壓調節器。將IVR中之電路示意性地繪示為26，該等電路形成於半導體基板28上。根據本揭露之替代實施例，裝置晶粒24包含邏輯晶粒或記憶體晶粒，諸如靜態隨機存取記憶體(SRAM)晶粒、動態隨機存取記憶體(DRAM)晶粒或其類似者。
IVR電路26可包含類比泵電路、數位控制區塊及用於調節電壓之其他電路。類比泵電路用於將電流泵浦至(例如)上覆邏輯晶粒中。數位控制區塊具有判定類比電路何時需要泵浦電流之功能。當數位控制區塊用於先進IVR中時，其可判定需要啟動類比泵之多少個相位來最佳化輸出至上覆裝置晶粒之電流。另外，裝置晶粒24亦可包含電耦合至類比泵電路及數位控制區塊之電感器30。IVR電路亦可包含駐留於 裝置晶粒52(其包含圖9之52A、52B及52C)中之電壓降偵測電路。由上覆裝置晶粒52(圖8)使用電壓降偵測電路來偵測電壓降、數位化及至裝置晶粒24中之類比泵電路之回饋。
根據本揭露之一些實施例，裝置晶粒24係獨立IVR晶粒，其中除由電壓調節器電路使用之電路之外，無其他邏輯電路建置於裝置晶粒24中。根據替代實施例，一些邏輯電路或記憶體電路與電壓調節器電路一起建置於裝置晶粒24內。
裝置晶粒24包含半導體基板28，其可為矽基板、矽碳基板、III-V族化合物半導體基板或其類似者。裝置晶粒24亦包含互連結構32。根據本揭露之一些實施例，互連結構32包含複數個介電層34及介電層34中之金屬線及導通孔(圖中未展示)。介電層34可包含金屬間介電(IMD)層，其可由具有(例如)低於約3.5、低於約3.0或低於約2.5之介電常數(k值)之低介電係數材料形成。此外，在裝置晶粒24之頂面附近，可存在非低介電係數鈍化層，諸如氮化矽層、氧化矽層、無摻雜矽酸鹽玻璃(USG)層及/或聚合物層。此外，在互連結構32之表面處，將金屬柱40(其包含40A及40B)駐留於一表面介電層34中。金屬柱40可為含銅墊、含鋁墊或其類似者。根據一些實施例，介電層34之最上者之頂面與金屬柱40之頂面共面。根據一些實施例，表面介電層34之一部分覆蓋金屬柱40。表面介電層34可為可由(例如)聚苯并噁唑形成之一聚合物層。
電感器30嵌入於互連結構32中，且亦為電壓調節器電路之部件。可使用經連接以具有一螺旋形狀之金屬線及導通孔來形成電感器30。據此，根據本揭露之一些實施例，電感器30係整合於相同於IVR電路之晶片中之晶片上電感器。根據本揭露之替代實施例，電感器30作為獨立電感器形成於IVR晶粒24外。
裝置晶粒24亦包含貫穿導通孔(替代地，指稱貫穿矽導通孔或貫 穿基板導通孔)36(其包含36A及36B)。應瞭解，儘管在圖2中將貫穿導通孔36繪示為穿過半導體基板28，但在將裝置晶粒24安置於載體20上方時，貫穿導通孔36可不延伸至半導體基板28之底面。確切而言，貫穿導通孔36延伸至半導體基板28之頂面與底面之間之一中間層級，且如圖7中所繪示，將在一隨後背面研磨步驟中顯露貫穿導通孔36之底端。由環繞各自貫穿導通孔36之一介電層(圖中未展示)使貫穿導通孔36之各者與各自半導體基板28電絕緣。
貫穿導通孔36A及36B用於將半導體基板28上方之導電構件連接至各自半導體基板28下方之導電構件。貫穿導通孔36B電耦合至各自裝置晶粒24內之裝置(諸如IVR電路、導線、電感器30等等)。貫穿導通孔36B亦可電耦合至金屬柱40B。另一方面，一裝置晶粒24中之貫穿導通孔36A僅用於將各自裝置晶粒24上方之導電構件(諸如，在圖8中之裝置晶粒52中)連接至裝置晶粒24下方之導電構件(諸如圖8中之中介層70中之金屬墊)。貫穿導通孔36A未連接至裝置晶粒24內之任何其他電路(其包含諸如電晶體及二極體之主動裝置及諸如電容器、電感器、電阻器等等之被動裝置)。據此，貫穿導通孔36A用於使裝置晶粒24外之構件互連，且未用於內部連接至裝置晶粒24內之電路。換言之，貫穿導通孔36A具有相同於貫穿成型導通孔(圖中未展示)(其可以其他方式建置於裝置晶粒24外且穿過囊封材料44(圖8))之功能。然而，在裝置晶粒24內形成貫穿導通孔36A不會有額外製造成本，此係因為與貫穿成型導通孔不同，貫穿導通孔36A係與貫穿導通孔36B同時形成的。另外，因為使用形成裝置晶粒之技術來形成貫穿導通孔36A，所以貫穿導通孔36可具有比貫穿成型導通孔高很多之密度及小很多之大小，且貫穿導通孔36A之總計數可比貫穿成型導通孔之總計數高很多。
如圖2中所展示，貫穿導通孔36A之各者連接至導電路徑38之一 者，導電路徑38將各自貫穿導通孔36A電耦合至一金屬柱40A。導電路徑38可為不具有分支/叉路之一單路線路徑，且不連接至各自裝置晶粒24中之任何其他金屬柱40B、電感器、電阻器、電容器、電晶體、二極體等等。據此，儘管貫穿導通孔36A駐留於裝置晶粒24中，但其不涉及與電壓調節相關之電壓/訊號轉移。此外，儘管將導電路徑38繪示為筆直路徑，但導電路徑38可包含水平金屬線。使用貫穿導通孔36A(及導電路徑38)來替換貫穿成型導通孔之一有利特徵在於：導電路徑38具有重設路線功能，且金屬柱40A不必與各自貫穿導通孔36A重疊，但貫穿成型導通孔係筆直及垂直的，且無法重設路線。
參考圖3，將囊封材料44囊封於裝置晶粒24上。將各自步驟展示為圖11中所展示之製程流程中之步驟204。施配囊封材料44且接著(例如)在一熱固化製程中固化囊封材料44。囊封材料44填充裝置晶粒24之間之間隙，且可與黏著層22接觸。囊封材料44可包含一成型化合物、一成型底部填膠、一環氧樹脂及/或一樹脂。在囊封製程之後，囊封材料44之頂面高於金屬柱40之頂端。
接著，一平坦化步驟(諸如一化學機械拋光(CMP)步驟或一研磨步驟)經執行以使囊封材料44平坦化，直至暴露裝置晶粒24之金屬柱40。將各自步驟展示為圖11中所展示之製程流程中之步驟206。圖3中展示所得結構。歸因於平坦化，金屬柱40之頂面實質上與囊封材料44之頂面齊平(共面)。
參考圖4，使介電層46之一或多個層及各自重佈線(RDL)48形成於囊封材料44及裝置晶粒24上方。將各自步驟展示為圖11中所展示之製程流程中之步驟208。根據本揭露之一些實施例，介電層46由一(或若干)聚合物(諸如PBO、聚醯亞胺或其類似者)形成。根據本揭露之替代實施例，介電層46由一(或若干)無機介電材料(諸如氮化矽、氧化矽、氮氧化矽或其類似者)形成。
RDL 48經形成以電耦合至金屬柱40。RDL 48可包含金屬跡線(金屬線)及位於各自金屬跡線下方且連接至各自金屬跡線之導通孔。根據本揭露之一些實施例，透過鍍覆製程來形成RDL 48，其中RDL 48之各者包含一晶種層(圖中未展示)及該晶種層上方之一鍍覆金屬材料。該晶種層及該鍍覆金屬材料可由相同材料或不同材料形成。
在RDL 48之形成期間，介電層46經圖案化以形成導通孔開口(由RDL 48佔用)，且上層RDL 48延伸至導通孔開口中以接觸下層RDL 48或金屬柱40。另外，RDL 48之部分可使裝置晶粒24電互連。頂部介電層46可經圖案化(例如，使用雷射)以在其內形成開口50，使得RDL 48中之一些金屬墊被暴露。
圖5繪示裝置晶粒52(其包含52A、52B及52C)至RDL 48中之暴露金屬墊上之接合。將各自步驟展示為圖11中所展示之製程流程中之步驟210。在本描述中，裝置晶粒52亦指稱階層2晶粒。裝置晶粒52可透過焊接區56來接合至金屬墊48。裝置晶粒52之各者可包含具有使其後表面朝上之半導體基板58。裝置晶粒52進一步包含半導體基板58之前表面(朝下表面)處之積體電路裝置54(諸如主動裝置(圖中未展示)，其包含(例如)電晶體)。裝置晶粒52A及52B可包含邏輯晶粒，諸如中央處理單元(CPU)晶粒、圖形處理單元(GPU)晶粒、行動應用晶粒或其類似者。裝置晶粒52A及52B可彼此相同。裝置晶粒52C可為一(高速)輸入/輸出(IO)晶粒，其用於裝置晶粒52A及52B之輸入/輸出。使用一虛線來繪示之RDL 60表示裝置晶粒52A及52B至IO晶粒52C之間之電連接。
根據其中裝置晶粒52A及52B係CPU晶粒之一些實施例，積體電路54可包含複數個功能電路，諸如一控制單元、記憶體組件、時脈電路、墊收發器電路、一邏輯閘胞庫等等。控制單元控制CPU之資料路徑。記憶體組件包含暫存器檔案、快取記憶體(SRAM胞)等等。時脈 電路包含時脈驅動器、鎖相迴路(PLL)、時脈分配網路或其類似者。邏輯閘胞庫用於實施邏輯。
裝置晶粒52A電連接至裝置晶粒24A及24B。另外，裝置晶粒24A及24B調節用於裝置晶粒52A之電壓供應。裝置晶粒52B連接至裝置晶粒24C及24D。另外，裝置晶粒24C及24D調節用於裝置晶粒52B之電壓供應。裝置晶粒52A及52B之各者可包含複數個核心，且裝置晶粒52A及52B代以指稱核心晶片。裝置晶粒52C(其可為一IO晶片)連接至裝置晶粒24E，其中裝置晶粒24E調節用於IO晶片52C之電壓。根據本揭露之一些實施例，裝置晶粒52A與裝置晶粒24A及24B完全重疊。裝置晶粒52A亦可橫向地延伸超過裝置晶粒24A及24B之邊緣。裝置晶粒52B與裝置晶粒24C及24D完全重疊。裝置晶粒52B亦可橫向地延伸超過裝置晶粒24C及24D之邊緣。
參考圖6，將囊封材料64囊封於裝置晶粒52上。將各自步驟展示為圖11中所展示之製程流程中之步驟212。囊封材料64可包含一成型化合物、一成型底部填膠、一環氧樹脂或一樹脂。囊封材料64之底面實體地接觸頂部介電層46之頂面。在施配之後，(例如)在一熱固化製程中固化囊封材料64。根據本揭露之一些實施例，一平坦化步驟經執行以使囊封材料64平坦化，直至囊封材料64之頂面與裝置晶粒52之頂面共面。將各自步驟展示為圖11中所展示之製程流程中之步驟214。根據本揭露之替代實施例，不執行平坦化，且在最終結構中，囊封材料64包含與裝置晶粒52重疊之一些部分。在本描述中，覆於層22上方之結構指稱封裝66，其包含複數個封裝，該複數個封裝各包含裝置晶粒24A、24B、24C、24D、24E及52A、52B及52C。
接著，自載體20剝離封裝66。將各自步驟展示為圖11中所展示之製程流程中之步驟216。圖7中展示所得結構。例如，藉由將一UV光或一雷射投射於黏著層22上來執行自載體20剝離封裝66。例如，當黏 著層22由LTHC形成時，由UV光或雷射產生之熱引起LTHC分解且因此使載體20與封裝66分離。一背面研磨經執行以研磨裝置晶粒24及囊封材料44之底部部分。執行背面研磨，直至暴露貫穿導通孔36A及36B之底端。根據一些實施例，使金屬墊及/或金屬跡線(圖中未展示)形成於裝置晶粒24之底部處以電連接至貫穿導通孔36A及36B。根據替代實施例，無金屬墊及/或金屬跡線形成於裝置晶粒24之底部處。
在一隨後步驟中，晶粒鋸切經執行以將封裝66鋸切成彼此相同之離散封裝68，且圖8中繪示離散封裝68之一者。亦將各自步驟展示為圖11中所展示之製程流程中之步驟216。
因為自封裝66鋸切封裝68，所以囊封材料44之邊緣垂直地對準於囊封材料64之各自邊緣。此外，囊封材料44之邊緣亦垂直地對準於介電層46之各自邊緣。
進一步參考圖8，將封裝68接合至中介層70。根據一些例示性實施例，透過焊接區71來執行接合。根據替代實施例，可使用諸如混合接合之其他接合方法。將各自步驟展示為圖11中所展示之製程流程中之步驟218。接合可為一晶圓上覆晶片(CoW)接合，其中複數個封裝(晶片)68接合至包含相同於所繪示中介層70之複數個中介層之中介層晶圓。根據本揭露之一些實施例，可使基本上相同於圖10中之互連結構84之一互連結構(圖中未展示)形成於封裝68之底部處，其中該互連結構中之RDL電耦合至貫穿導通孔36A及36B。中介層70可包含半導體基板72(其可為一矽基板)及半導體基板72上方之互連結構74。使金屬線及導通孔76形成於互連結構74中。使貫穿導通孔78形成於半導體基板72中。中介層70不具有諸如電晶體及二極體之主動裝置。中介層70可不具有或可包含諸如電阻器、電感器、電容器或其類似者之被動裝置(圖中未展示)。可將底部填膠73施配於封裝68與中介層70之間。接著，可將中介層晶圓鋸切成各包含中介層70及上覆裝置晶粒24及52 之複數個封裝。
參考圖9，(例如)透過焊接區82來將中介層70接合至封裝基板80。將各自步驟展示為圖11中所展示之製程流程中之步驟220。封裝基板80可為一層疊基板(無核心)或可具有核心。封裝基板80中之導電跡線及/或核心(圖中未展示)電連接至焊接區82。封裝基板80可具有大於上覆中介層70之俯視面積的一俯視面積。
圖10繪示根據替代實施例之封裝。除未使用中介層且封裝68直接接合至封裝基板80之外，此等實施例類似於圖9中之實施例。根據本揭露之一些實施例，封裝68包含形成於裝置晶粒24及囊封材料44之底面處之互連結構84。可使用形成介電層46及RDL 48之基本上相同方法及材料來形成互連結構，且因此不再重複細節。
本揭露之實施例具有一些有利特徵。如圖9或圖10中所展示，裝置晶粒52A可具有大於裝置晶粒24A及24B之總俯視面積的一俯視面積。據此，可將裝置晶粒24A及24B直接安置於各自核心晶片52A下方，且裝置晶粒24A、24B及52A之總俯視面積基本上為裝置晶粒52A之俯視面積。藉由將IVR晶粒(諸如24A及24B)直接安置於其對應核心裝置晶粒(諸如52A)下方來最小化自核心裝置晶粒至其電壓調節器之距離。類似地，藉由將IVR晶粒24E直接安置於裝置晶粒52C下方來最小化自裝置晶粒52C至IVR晶粒24E中之其電壓調節器之距離。因此，改良功率效率。作為一比較，若將IVR晶粒安置於核心晶片旁邊，則佈局係不平衡的，此係因為IVR晶粒更靠近於核心晶片中之核心之部分且更遠離核心晶片中之其他核心。藉由將IVR晶粒24直接安置於IVR晶粒24為其服務之核心晶片下方來使佈局平衡。
另外，因為裝置晶粒24較小，可由貫穿導通孔36A替換所以將以其他方式形成(若不使用本揭露之實施例)以將中介層70/封裝基板80連接至裝置晶粒52的貫穿成型導通孔。此消除用於形成貫穿成型導通孔 之成本，同時基本上不存在用於形成貫穿導通孔36A之生產成本(此係因為貫穿導通孔36A與貫穿導通孔36B係同時形成的)。此外，IVR晶粒24在其互連結構中通常具有一低密度之金屬線及導通孔。據此，IVR晶粒之互連結構可用於形成嵌入式電感器。
根據本揭露之一些實施例，一種封裝包含一IVR晶粒，其中該IVR晶粒包含第一IVR晶粒之一頂面處之金屬柱。該封裝進一步包含將該第一IVR晶粒囊封於其內之一第一囊封材料，其中該第一囊封材料具有與該等金屬柱之頂面共面之一頂面。複數個重佈線位於該第一囊封材料及該IVR晶粒上方。該複數個重佈線電耦合至該等金屬柱。一核心晶片與該複數個重佈線重疊且接合至該複數個重佈線。一第二囊封材料將該核心晶片囊封於其內，其中該第一囊封材料之邊緣及該第二囊封材料之各自邊緣彼此垂直對準。一中介層或一封裝基板位於該IVR晶粒下方且接合至該IVR晶粒。
根據本揭露之一些實施例，一種封裝包含一第一IVR晶粒及一第二IVR晶粒，其等各包含：金屬柱；電壓調節器電路，其等電耦合至該等金屬柱；及一電感器，其電耦合至該等電壓調節器電路。一第一囊封材料將該第一IVR晶粒及該第二IVR晶粒囊封於其內。該第一囊封材料具有與該第一IVR晶粒及該第二IVR晶粒中之該等金屬柱之頂面共面之一頂面。一介電層與該第一IVR晶粒、該第二IVR晶粒及該第一囊封材料重疊。複數個重佈線包含該介電層中之部分。該複數個重佈線電耦合至該第一IVR晶粒及該第二IVR晶粒。一第一CPU晶片及一第二CPU晶片分別與該第一IVR晶粒及該第二IVR晶粒重疊且分別電耦合至該第一IVR晶粒及該第二IVR晶粒。一第二囊封材料將該第一CPU晶片及該第二CPU晶片囊封於其內。
根據本揭露之一些實施例，一種封裝包含一第一裝置晶粒，其包含：一半導體基板；一第一貫穿導通孔及一第二貫穿導通孔，其等 穿過該半導體基板；一主動電路，其位於該半導體基板之一表面處；一第一金屬柱，其位於該第一裝置晶粒之一頂面處；及一第二金屬柱，其位於該第一裝置晶粒之一頂面處。該第一金屬柱電耦合至該主動電路及該第一貫穿導通孔。該第二金屬柱電耦合至該第二貫穿導通孔且不與該第一裝置晶粒中之全部主動電路電耦合。該封裝進一步包含：一第一囊封材料，其將該第一裝置晶粒囊封於其內；及一第二裝置晶粒，其與該第一裝置晶粒重疊且電耦合至該第一裝置晶粒。一封裝組件位於該裝置晶粒下方且接合至該裝置晶粒。該第二貫穿導通孔及該第二金屬柱將該封裝組件電耦合至該第二裝置晶粒。
上述內容概述若干實施例之特徵，使得熟悉此項技術者可較佳地理解本揭露之態樣。熟悉此項技術者應瞭解，其可容易地使用本揭露作為設計或修改用於實施相同目的及/或達成本文所引入之實施例之相同優點之其他製程及結構之一基礎。熟悉此項技術者亦應認識到，此等等效構造不背離本揭露之精神及範疇，且其可在不背離本揭露之精神及範疇之情況下對本文作出各種改變、代替及變更。

Claims (10)

  1. 一種封裝，其包括：一第一整合式電壓調節器(IVR)晶粒，其中該第一IVR晶粒包括：金屬柱，其等位於該第一IVR晶粒之一頂面處；一第一囊封材料，其將該第一IVR晶粒囊封於其內，其中該第一囊封材料具有與該等金屬柱之頂面共面之一頂面；複數個重佈線，其等位於該第一囊封材料及該第一IVR晶粒上方，其中該複數個重佈線電耦合至該等金屬柱；一第一核心晶片，其與該複數個重佈線重疊且接合至該複數個重佈線；一第二囊封材料，其將該第一核心晶片囊封於其內，其中該第一囊封材料之邊緣及該第二囊封材料之各自邊緣彼此垂直對準；及一中介層或一封裝基板，其位於該第一IVR晶粒下方且接合至該第一IVR晶粒。
  2. 如請求項1之封裝，其中該第一IVR晶粒包括：一半導體基板；及一貫穿導通孔，其位於該半導體基板中，其中該貫穿導通孔將該第一核心晶片電耦合至該中介層或該封裝基板且未電耦合至該第一IVR晶粒中之電路。
  3. 如請求項1之封裝，其中該第一IVR晶粒包括：一半導體基板；一互連結構，其覆於該半導體基板上方；及一內建電感器，其位於該互連結構中。
  4. 如請求項1之封裝，其進一步包括相同於該第一IVR晶粒之一第二IVR晶粒，其中將該第二IVR晶粒囊封於該第一囊封材料中，其中該第二IVR晶粒與該第一核心晶片重疊且電耦合至該第一核心晶片。
  5. 如請求項1之封裝，其進一步包括：一第三IVR晶粒，其囊封於該第一囊封材料中；及一輸入/輸出晶粒，其囊封於該第二囊封材料中，其中該輸入/輸出晶粒與該第三IVR晶粒重疊且電耦合至該第三IVR晶粒。
  6. 如請求項1之封裝，其進一步包括：一第四IVR晶粒及一第五IVR晶粒，其等囊封於該第一囊封材料中，其中該第四IVR晶粒及該第五IVR晶粒相同於該第一IVR晶粒；及一第二核心晶片，其與該第四IVR晶粒及該第五IVR晶粒重疊且電耦合至該第四IVR晶粒及該第五IVR晶粒。
  7. 一種封裝，其包括：一第一整合式電壓調節器(IVR)晶粒及一第二IVR晶粒，其等各包括：金屬柱；電壓調節器電路，其等電耦合至該等金屬柱；及一電感器，其電耦合至該等電壓調節器電路；一第一囊封材料，其將該第一IVR晶粒及該第二IVR晶粒囊封於其內，其中該第一囊封材料具有與該第一IVR晶粒及該第二IVR晶粒中之該等金屬柱之頂面共面之一頂面；一介電層，其與該第一IVR晶粒、該第二IVR晶粒及該第一囊封材料重疊；複數個重佈線，其等具有該介電層中之部分，其中該複數個 重佈線電耦合至該第一IVR晶粒及該第二IVR晶粒；一第一中央處理單元(CPU)晶片及一第二CPU晶片，其等分別與該第一IVR晶粒及該第二IVR晶粒重疊且分別電耦合至該第一IVR晶粒及該第二IVR晶粒；及一第二囊封材料，其將該第一CPU晶片及該第二CPU晶片囊封於其內。
  8. 如請求項7之封裝，其中該第一囊封材料之邊緣垂直地對準於該第二囊封材料之各自邊緣。
  9. 一種封裝，其包括：一第一裝置晶粒，其包括：一半導體基板；一第一貫穿導通孔及一第二貫穿導通孔，其等穿過該半導體基板；一主動電路，其位於該半導體基板之一表面處；一第一金屬柱，其位於該第一裝置晶粒之一頂面處，其中該第一金屬柱電耦合至該主動電路及該第一貫穿導通孔；及一第二金屬柱，其位於該第一裝置晶粒之一頂面處，其中該第二金屬柱電耦合至該第二貫穿導通孔且不與該第一裝置晶粒中之全部主動電路電耦合；一第一囊封材料，其將該第一裝置晶粒囊封於其內；一第二裝置晶粒，其與該第一裝置晶粒重疊且電耦合至該第一裝置晶粒；及一封裝組件，其位於該第一裝置晶粒下方且接合至該第一裝置晶粒，其中該第二貫穿導通孔及該第二金屬柱將該封裝組件電耦合至該第二裝置晶粒。
  10. 如請求項9之封裝，其中該第一裝置晶粒包括一整合式電壓調節 器(IVR)晶粒，該IVR晶粒內包括一IVR電路及一電感器，且該第二裝置晶粒包括一中央處理單元(CPU)晶粒。
TW105124585A 2015-11-30 2016-08-03 三層式基板上覆晶圓上覆晶片結構 TWI627722B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562260832P 2015-11-30 2015-11-30
US62/260,832 2015-11-30
US15/007,714 2016-01-27
US15/007,714 US9627365B1 (en) 2015-11-30 2016-01-27 Tri-layer CoWoS structure

Publications (2)

Publication Number Publication Date
TW201733068A TW201733068A (zh) 2017-09-16
TWI627722B true TWI627722B (zh) 2018-06-21

Family

ID=58692990

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105124585A TWI627722B (zh) 2015-11-30 2016-08-03 三層式基板上覆晶圓上覆晶片結構

Country Status (5)

Country Link
US (4) US9627365B1 (zh)
KR (1) KR101917418B1 (zh)
CN (1) CN107026153B (zh)
DE (1) DE102016102108B4 (zh)
TW (1) TWI627722B (zh)

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9768145B2 (en) * 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
US9627365B1 (en) 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US9831148B2 (en) 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US9659911B1 (en) * 2016-04-20 2017-05-23 Powertech Technology Inc. Package structure and manufacturing method thereof
CN109075151B (zh) 2016-04-26 2023-06-27 亚德诺半导体国际无限责任公司 用于组件封装电路的机械配合、和电及热传导的引线框架
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
TW202404049A (zh) 2016-12-14 2024-01-16 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
WO2018129907A1 (zh) * 2017-01-11 2018-07-19 中芯长电半导体（江阴）有限公司 一种集成供电系统的封装件及封装方法
US11430740B2 (en) * 2017-03-29 2022-08-30 Intel Corporation Microelectronic device with embedded die substrate on interposer
US10475718B2 (en) * 2017-05-18 2019-11-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package comprising a dielectric layer with built-in inductor
US10217720B2 (en) * 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10283474B2 (en) * 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10373893B2 (en) 2017-06-30 2019-08-06 Intel Corporation Embedded bridge with through-silicon vias
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10535643B2 (en) 2017-08-04 2020-01-14 Samsung Electronics Co., Ltd. Connection system of semiconductor packages using a printed circuit board
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10515888B2 (en) 2017-09-18 2019-12-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
US10403600B2 (en) 2017-10-13 2019-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. Modular voltage regulators
US10763239B2 (en) * 2017-10-27 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same
DE102018124695A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrieren von Passivvorrichtungen in Package-Strukturen
US10867954B2 (en) * 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10504873B1 (en) 2018-06-25 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. 3DIC structure with protective structure and method of fabricating the same and package
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11450560B2 (en) * 2018-09-24 2022-09-20 Intel Corporation Microelectronic assemblies having magnetic core inductors
US11417593B2 (en) 2018-09-24 2022-08-16 Intel Corporation Dies with integrated voltage regulators
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11769735B2 (en) * 2019-02-12 2023-09-26 Intel Corporation Chiplet first architecture for die tiling applications
US11088100B2 (en) * 2019-02-21 2021-08-10 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
US11139270B2 (en) 2019-03-18 2021-10-05 Kepler Computing Inc. Artificial intelligence processor with three-dimensional stacked memory
US11836102B1 (en) 2019-03-20 2023-12-05 Kepler Computing Inc. Low latency and high bandwidth artificial intelligence processor
US11088068B2 (en) * 2019-04-29 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of manufacturing the same
US10840190B1 (en) * 2019-05-16 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US12079475B1 (en) 2019-05-31 2024-09-03 Kepler Computing Inc. Ferroelectric memory chiplet in a multi-dimensional packaging
US12086410B1 (en) 2019-05-31 2024-09-10 Kepler Computing Inc. Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer
US11844223B1 (en) 2019-05-31 2023-12-12 Kepler Computing Inc. Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
US11152343B1 (en) 2019-05-31 2021-10-19 Kepler Computing, Inc. 3D integrated ultra high-bandwidth multi-stacked memory
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
KR20210007457A (ko) 2019-07-11 2021-01-20 삼성전자주식회사 반도체 패키지
KR102661671B1 (ko) * 2019-07-25 2024-04-29 삼성전자주식회사 적층된 반도체 칩들을 포함하는 반도체 패키지
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11309243B2 (en) * 2019-08-28 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package having different metal densities in different regions and manufacturing method thereof
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US12021156B2 (en) * 2019-09-30 2024-06-25 Texas Instruments Incorporated Windowed wafer assemblies having interposers
KR20210079005A (ko) 2019-12-19 2021-06-29 삼성전자주식회사 반도체 패키지 및 그 제조방법
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
US11715754B2 (en) * 2020-06-09 2023-08-01 Mediatek Inc. Semiconductor package with TSV inductor
IL275736A (en) * 2020-06-29 2022-01-01 Elta Systems Ltd You will include slice phase transducers, techniques and applications
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11587894B2 (en) * 2020-07-09 2023-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package and method of fabricating the same
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
KR20220034596A (ko) * 2020-09-11 2022-03-18 삼성전자주식회사 반도체 패키지
US11355379B1 (en) * 2020-11-24 2022-06-07 International Business Machines Corporation Oxide-bonded wafer pair separation using laser debonding
EP4024222A1 (en) 2021-01-04 2022-07-06 Imec VZW An integrated circuit with 3d partitioning
US11791233B1 (en) 2021-08-06 2023-10-17 Kepler Computing Inc. Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging
US11942447B2 (en) * 2021-08-27 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Storage layers for wafer bonding
US11967559B2 (en) 2021-11-24 2024-04-23 Advanced Semiconductor Engineering, Inc. Electronic package
US11881446B2 (en) 2021-12-23 2024-01-23 Nanya Technology Corporation Semiconductor device with composite middle interconnectors
US20230253302A1 (en) * 2022-02-10 2023-08-10 Advanced Semiconductor Engineering, Inc. Electronic package
US20230268293A1 (en) * 2022-02-18 2023-08-24 Advanced Semiconductor Engineering, Inc. Electronic device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120112352A1 (en) * 2010-11-10 2012-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit system with distributed power supply

Family Cites Families (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070013080A1 (en) 2005-06-29 2007-01-18 Intel Corporation Voltage regulators and systems containing same
JP4509972B2 (ja) 2005-09-01 2010-07-21 日本特殊陶業株式会社 配線基板、埋め込み用セラミックチップ
US7701057B1 (en) 2007-04-25 2010-04-20 Xilinx, Inc. Semiconductor device having structures for reducing substrate noise coupled from through die vias
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US7838424B2 (en) 2007-07-03 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
US20090008929A1 (en) * 2007-07-05 2009-01-08 David Vernon Person Pipe coupling spacer insert
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US7863742B2 (en) 2007-11-01 2011-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Back end integrated WLCSP structure without aluminum pads
US7750459B2 (en) * 2008-02-01 2010-07-06 International Business Machines Corporation Integrated module for data processing system
US8039303B2 (en) 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
US7808258B2 (en) 2008-06-26 2010-10-05 Freescale Semiconductor, Inc. Test interposer having active circuit component and method therefor
US8193799B2 (en) * 2008-09-23 2012-06-05 Globalfoundries Inc. Interposer including voltage regulator and method therefor
US8067308B2 (en) 2009-06-08 2011-11-29 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support
TWI401753B (zh) 2009-12-31 2013-07-11 Advanced Semiconductor Eng 可堆疊式封裝結構之製造方法
US8822281B2 (en) 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US8618654B2 (en) 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
WO2011125277A1 (ja) 2010-04-07 2011-10-13 株式会社島津製作所 放射線検出器およびそれを製造する方法
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8217502B2 (en) 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US9048112B2 (en) * 2010-06-29 2015-06-02 Qualcomm Incorporated Integrated voltage regulator with embedded passive device(s) for a stacked IC
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8415781B2 (en) 2010-08-09 2013-04-09 Ibiden Co., Ltd. Electronic component and method for manufacturing the same
KR20120031697A (ko) 2010-09-27 2012-04-04 삼성전자주식회사 패키지 적층 구조 및 그 제조 방법
US8993377B2 (en) 2010-09-29 2015-03-31 Stats Chippac, Ltd. Semiconductor device and method of bonding different size semiconductor die at the wafer level
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
TWI418269B (zh) 2010-12-14 2013-12-01 Unimicron Technology Corp 嵌埋穿孔中介層之封裝基板及其製法
JP5412462B2 (ja) * 2011-04-19 2014-02-12 日本パーカライジング株式会社 金属材料用耐食合金コーティング膜及びその形成方法
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US8754514B2 (en) 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
CN102394227B (zh) 2011-11-30 2013-07-10 上海华力微电子有限公司 可降低方块电阻的铜互连结构的制造方法
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9263839B2 (en) 2012-12-28 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved fine pitch joint
US8987058B2 (en) 2013-03-12 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for wafer separation
US9257333B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
KR20130124858A (ko) 2012-05-07 2013-11-15 삼성전자주식회사 반도체 패키지
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9196532B2 (en) 2012-06-21 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods for forming the same
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8865585B2 (en) 2012-07-11 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming post passivation interconnects
US8987884B2 (en) 2012-08-08 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package assembly and methods for forming the same
US9275924B2 (en) 2012-08-14 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having a recess filled with a molding compound
US8754508B2 (en) 2012-08-29 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Structure to increase resistance to electromigration
US8952530B2 (en) 2012-09-14 2015-02-10 Taiwan Semiconductor Manufacturing Company, Ltd. Post passivation interconnect structures and methods for forming the same
US8772151B2 (en) 2012-09-27 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation scheme
US9921640B2 (en) 2012-09-28 2018-03-20 Intel Corporation Integrated voltage regulators with magnetically enhanced inductors
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8884400B2 (en) 2012-12-27 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor in Post-Passivation structures and methods of forming the same
US8846548B2 (en) 2013-01-09 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods for forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9773732B2 (en) 2013-03-06 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for packaging pad structure
US9196559B2 (en) 2013-03-08 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Directly sawing wafers covered with liquid molding compound
US8933551B2 (en) 2013-03-08 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3D-packages and methods for forming the same
US8987922B2 (en) 2013-03-11 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for wafer level packaging
US9275925B2 (en) 2013-03-12 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved interconnect structure
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9263376B2 (en) * 2013-04-15 2016-02-16 Intel Deutschland Gmbh Chip interposer, semiconductor device, and method for manufacturing a semiconductor device
JP5889855B2 (ja) * 2013-10-11 2016-03-22 シャープ株式会社 画像形成装置
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9735134B2 (en) 2014-03-12 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with through-vias having tapered ends
US9543170B2 (en) 2014-08-22 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US10236209B2 (en) * 2014-12-24 2019-03-19 Intel Corporation Passive components in vias in a stacked integrated circuit package
US9633974B2 (en) 2015-03-04 2017-04-25 Apple Inc. System in package fan out stacking architecture and process flow
US9679801B2 (en) * 2015-06-03 2017-06-13 Apple Inc. Dual molded stack TSV package
US9627365B1 (en) * 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US10319683B2 (en) * 2017-02-08 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stacked package-on-package structures
US11282761B2 (en) * 2018-11-29 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of manufacturing the same
US10970439B2 (en) * 2018-11-29 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design
US11195816B2 (en) * 2019-07-23 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages comprising a plurality of redistribution structures and methods of forming the same
US11404316B2 (en) * 2019-12-27 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. System, device and methods of manufacture
US11482484B2 (en) * 2020-02-27 2022-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Symmetrical substrate for semiconductor packaging

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120112352A1 (en) * 2010-11-10 2012-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit system with distributed power supply

Also Published As

Publication number Publication date
US11244924B2 (en) 2022-02-08
US10163851B2 (en) 2018-12-25
US20190123019A1 (en) 2019-04-25
DE102016102108A1 (de) 2017-06-01
CN107026153A (zh) 2017-08-08
US10748870B2 (en) 2020-08-18
US20170221858A1 (en) 2017-08-03
KR20170063324A (ko) 2017-06-08
US9627365B1 (en) 2017-04-18
CN107026153B (zh) 2019-08-02
DE102016102108B4 (de) 2022-06-09
TW201733068A (zh) 2017-09-16
KR101917418B1 (ko) 2018-11-09
US20200381392A1 (en) 2020-12-03

Similar Documents

Publication Publication Date Title
TWI627722B (zh) 三層式基板上覆晶圓上覆晶片結構
US11063016B2 (en) Integrated fan-out package including voltage regulators and methods forming same
US12119338B2 (en) Semiconductor device packages, packaging methods, and packaged semiconductor devices
US11728217B2 (en) Wafer level package structure and method of forming same
US11942433B2 (en) Integrated circuit package and method
US11127644B2 (en) Planarization of semiconductor packages and structures resulting therefrom
US9997464B2 (en) Dummy features in redistribution layers (RDLS) and methods of forming same
US11217546B2 (en) Embedded voltage regulator structure and method forming same
US20180226349A1 (en) Multi-Stacked Package-on-Package Structures
US10177032B2 (en) Devices, packaging devices, and methods of packaging semiconductor devices
TW201810555A (zh) 半導體封裝及其製造方法
US9704739B2 (en) Semiconductor device packages, packaging methods, and packaged semiconductor devices
US20210118858A1 (en) Integrated Circuit Package and Method
US20240258286A1 (en) Integrated circuit package and method
US11063023B2 (en) Semiconductor package
TW202022954A (zh) 半導體結構及其形成方法