TWI619252B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TWI619252B
TWI619252B TW102126604A TW102126604A TWI619252B TW I619252 B TWI619252 B TW I619252B TW 102126604 A TW102126604 A TW 102126604A TW 102126604 A TW102126604 A TW 102126604A TW I619252 B TWI619252 B TW I619252B
Authority
TW
Taiwan
Prior art keywords
semiconductor
region
substrate
crystal orientation
active region
Prior art date
Application number
TW102126604A
Other languages
English (en)
Other versions
TW201409710A (zh
Inventor
喬滋爾斯 凡里恩提斯
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201409710A publication Critical patent/TW201409710A/zh
Application granted granted Critical
Publication of TWI619252B publication Critical patent/TWI619252B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一種半導體裝置，包括：一基底，具有一第一晶向；一主動區域，形成於基底上，其中主動區域之一頂部部份具有一第二晶向；以及主動區域之該頂部部份的兩側被一閘結構包覆。半導體裝置更包括：一溝槽，形成於基底之中且被多個隔離區域圍繞，其中主動區域之頂部部份高於隔離區域之頂表面。

Description

半導體裝置及其製造方法
本發明係有關於一種半導體裝置，特別係有關於一種多重閘極的半導體裝置及其製造方法。
隨著技術的發展，半導體處理節點(semiconductor process nodes)已經過微縮化(scaled down)以達到高密度積體電路。因此，積體電路的形成要素藉由縮小半導體處理節點(例如，縮小半導體處裡節點至接近次(sub)20nm節點)而改善。隨著半導體裝置的微縮，需要新的技術以從一個世代至下個世代維持電子元件的效能。舉例來說，藉由高載子遷移率(carrier mobility)的材料(例如，III-V金屬、及/或鍺等)以形成高密度與高速積體電路是令人滿意的。
鍺與矽在元素週期表中屬於IV族。相較於矽，鍺具有較高的載子與電洞遷移率(hole mobility)。鍺的較高載子與電洞遷移率可使裝置的電性性質更好。舉例來說，矽的晶格電子遷移率(lattice electron mobility)為1417cm2/V-sec。反之，鍺的晶格電子遷移率為3900cm2/V-sec。鍺的電子遷移率為矽的電子遷移率約2.75倍。鍺如此高的電子遷移率提高了驅動電流(drive current)且縮短了閘延遲(gate delay)。
鍺基(based)電晶體的另一個有利的特徵為鍺具有 較小的能隙(band gap)。具體來說，相較於矽的能隙約1.2eV，鍺的能隙為約0.6eV。如此小的能隙有助於降低鍺基電晶體的閾值電壓(threshold voltage)。
相較於矽，鍺具有多種優點。然而，因為鍺晶圓價格不斐，故矽晶圓在半導體工藝裡佔主要地位。一種廣為接受的製造鍺基電晶體方法為藉由磊晶成長(epitaxial growth)製程在矽基底上生長鍺主動區域(active region)。
在矽基底上生長鍺層通常稱為鍺-矽異磊晶成長(germanium-silicon hetero-epitaxial growth)。鍺的晶格常數為約4.2%大於矽的晶格常數。當鍺層成長於矽基底上，鍺層受到壓縮應力以符合矽基底的晶格間隙。當鍺層成長超出臨界厚度後，鍺層可藉由形成各種穿透錯位(threading dislocation)而從應力中被釋放。此種穿透錯位係瑕疵，會降低鍺基電晶體的電性性質。
本發明提供一種半導體裝置，包括：一基底，具有一第一晶向；一主動區域，形成於基底上，其中：主動區域之一頂部部份具有一第二晶向；以及主動區域之頂部部份的兩側被一閘結構包覆；以及一溝槽，形成於基底之中且被多個隔離區域圍繞，其中：主動區域之頂部部份高於隔離區域之頂表面。
本發明又提供一種半導體裝置，包括：一基底，具有一<001>晶向，其中基底係由一第一半導體材料所形成；多個隔離區域，形成於基底之上，其中兩個相鄰的隔離區域形 成一溝槽於基底中；一通道區域，形成於基底之上且連接一第一極/源區域與一第二極/源區域；其中：通道區域係由一第二半導體材料所形成；通道區域之一側剖面係三角形；以及通道區域具有一<111>晶向；以及一閘極，包覆著通道區域的兩側。
本發明亦提供一種半導體裝置的製造方法，包括：提供具有一第一晶向的一基底，其中基底係由一第一半導體材料所形成；蝕刻去除部份的基底以形成一溝槽於相鄰的兩個隔離區域之間；透過一磊晶成長製程成長一半導體區域於溝槽之中與基底之上，其中半導體區域的一頂部部份之剖面係三角形，且頂部部份具有一第二晶向；以及形成一閘結構於半導體區域的至少兩側上。
100、200‧‧‧半導體裝置
202‧‧‧基底
102、204‧‧‧隔離區域
104、206‧‧‧主動區域
<111>‧‧‧晶向
208‧‧‧閘極
210‧‧‧閘介電層
402、1102、1702‧‧‧開口
502、602‧‧‧半導體區域
504、604‧‧‧底部區域
1002、1802、1902‧‧‧第一半導體區域
1202、1302、2002‧‧‧第二半導體區域
1402、2102‧‧‧第三半導體區域
第1圖根據一實施例繪示出半導體裝置的主動區域之透視圖；第2圖係根據一實施例繪示出多重閘極電晶體之剖面示意圖；第3圖根據一實施例繪示出具有第一晶向基底的半導體裝置；第4圖係根據一實施例繪示出在第3圖中的基底內形成開口後的半導體裝置之剖面示意圖；第5圖根據一實施例繪示出在第4圖中的開口與基底上成長半導體區域後的半導體裝置之剖面示意圖；第6圖根據一實施例繪示出在第5圖中的隔離區域之頂表 面上進行蝕刻製程後的半導體裝置之示意圖；第7圖根據另一實施例繪示出在第4圖中的開口與基底上成長半導體區域後的半導體裝置之示意圖；第8~15圖係根據另一實施例繪示出第1圖中的主動區域之中間製造步驟的示意圖；第16~21圖根據又一實施例繪示出第1圖中的主動區域之中間製造步驟的示意圖。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
以下將敘述有關特定背景的實施例，即鍺基多重閘極電晶體(germanium based multiple gate transistor)。然而，本發明之實施例亦適用於各種電晶體，例如，由IV族元素、III-V族化合物、與II-VI族化合物所形成的電晶體。不同實施例將對應到附圖在以下作詳述。
第1圖根據一實施例繪示出半導體裝置的主動區域之透視圖。半導體裝置100包括隔離區域102及主動區域104。主動區域104可分成兩個部份。主動區域的底部部份被隔離區域102圍繞(surround)。主動區域104的頂部部份位於隔離區域102之頂表面上方。具體來說，主動區域104的頂部部份具有<111>晶向(crystal orientation)。主動區域104可由半導體材料形成，半導體材料可包括IV族元素、III-V族化合物、 或II-VI族化合物。
應注意的是，雖然第1圖所繪示之主動區域104可由單一半導體材料所形成，然而，主動區域104可由多個半導體層堆疊形成，且堆疊的各個半導體層可由不同半導體材料形成，例如，IV族元素、III-V族化合物、或II-VI族化合物。詳細的主動區域104之製造流程將會配合第3~21圖在以下詳述。
第2圖係根據一實施例繪示出多重閘極電晶體之剖面示意圖。多重閘極電晶體200包括主動區域206，其相似於第1圖之主動區域104。主動區域206係從基底202成長而成。主動區域206之頂部部份從多重閘極電晶體200之隔離區域204的頂表面伸出。主動區域206的頂部部份的側剖面係三角形。此外，多重閘極電晶體200之閘極208包覆著主動區域206之頂部部份的兩面。因為閘極208包覆著主動區域206之頂部部份的兩面，多重閘極電晶體200亦稱為雙閘極(double gate)電晶體。
如第2圖所示，可在閘極208與主動區域206的頂部部份之間形成閘介電層210。主動區域206的頂部部份可作為多重閘極電晶體200的通道(channel)區域。多重閘極電晶體200可進一步包括汲/源區域與間隔物(spacer)(都未顯示)。為了簡單起見，汲/源區域與間隔物未包含在第2圖所示的剖面示意圖。
根據一實施例，基底202可為結晶(crystalline)基底。基底202可由矽形成，然而，基底202亦可由其他III族 元、IV族、及/或V族元素(例如，矽、鍺、鎵、砷、及前述之組合)而形成。根據一實施例，基底202可由具有第一晶向的第一半導體材料形成。根據實施例，第一半導體材料是矽，而第一晶向為<001>晶向。
主動區域206形成於基底202上方的溝槽(trench)中。主動區域206的結構已於對應到第1圖的上文詳述，故不在此重複敘述。應注意的是，主動區域206可由第二半導體材料所形成。根據一實施例，第二半導體材料為鍺。此外，主動區域206之頂部部份具有第二晶向。根據一實施例，第二晶向為<111>晶向。第2圖中所示的半導體結構的一個有利的特徵係在於多重閘極電晶體200在閘極下的主動區域之側壁可具有<111>晶向。<111>晶向有助於改善多重閘極電晶體200的電性特性(characteristic)。
多重閘極電晶體200可包括隔離區域204。如第2圖所示，隔離區域204包覆著主動區域206之底部部份。可藉由淺溝隔離(shallow trench isolation,STI)結構形成隔離區域204。可使用適合的技術製造STI結構(即隔離結構204)，其包括光微影(photolithography)與蝕刻製程。具體而言，光微影與蝕刻製程可包括在基底202上沉積常用的遮罩(mask)材料(例如，光阻(photoresist))、曝光遮罩材料以形成圖案(pattern)、及根據圖案以蝕刻基底202。以此方式，可形成多個開口。接著，在開口中填入介電材料以形成STI結構(即隔離結構204)。根據一實施例，隔離區域可以介電材料填充，例如，氧化物材料、或高密度電漿(high-density plasma,HDP)氧化物等的介電 材料。之後，進行化學機械研磨(chemical mechanical polishing,CMP)以移除介電材料多餘的部份，剩下的部份為隔離區域204。
如第2圖所示，隔離區域204可為多個部份的連續區域，根據一實施例，隔離區域204可形成隔離環(isolation ring)。除此之外，隔離區域204可為兩個分開的隔離區域，以其側壁互相面對。
如第2圖所示，在主動區域206之頂部部份與閘極208之間可形成閘介電層210。閘介電層210可由氧化物材料形成，並且可由合適的製程形成，例如，乾或濕式熱氧化(thermal oxidation)、濺鍍(sputtering)、或藉由使用四乙氧基矽烷(tetra-ethyl-ortho-silicate,TEOS)與氧氣為前驅物的化學氣相沉積(chemical vapor deposition,CVD)技術。此外，閘介電層210可為高介電常數(high-k)材料，例如，氧化矽、氮氧化矽、氮化矽、氧化物、含氮氧化物、氧化鋁、氧化鑭、氧化鉿、氧化鋅、氮氧化鉿、或前述之組合等。高介電材料可藉由合適的製程沉積，例如原子層沉積(atomic layer deposition,ALD)。
閘極208可包括導電材料，導電材料包括多晶矽、多晶鍺化矽(poly-crystalline silicon-germanium,poly-SiGe)、金屬材料、金屬矽化物材料、金屬氮化物材料、或金屬氧化物材料等。舉例來說，金屬材料可包括鉭、鈦、鉬、鎢、鉑、鋁、鉿、釕、或前述之組合等。金屬矽化物材料包括矽化鈦、矽化鈷、矽化鎳、矽化鉭、或前述之組合等。金屬氮化物材料包括氮化鈦、氮化鉭、氮化鉭、或前述之組合等。金屬氧化物材料 包括氧化釕、氧化銦錫、或前述之組合等。
應被注意的是，可使用其他製程以形成閘極208。其他製程包括，但不限於，化學氣相沉積(chemical vapor deposition,CVD)、物理氣相沉積(physical vapor deposition,PVD)、電漿增強CVD(plasma enhanced CVD,PECVD)、常壓CVD(atmospheric pressure CVD,APCVD)、高密度電漿CVD(high density plasma CVD,HD CVD)、低壓CVD(low-pressure CVD,LPCVD)、原子層CVD(atmoic layer CVD,ALCVD)等。
第3~6圖係根據一實施例繪示出第1圖中的主動區域之中間製造步驟的示意圖。第3圖根據一實施例繪示出具有第一晶向基底的半導體裝置。半導體裝置200包括基底202與形成於基底202中的隔離區域204。形成隔離區域204的製程相似於第2圖所示的隔離區域之形成製程，故在此不再敘述以防重複。基底202可由矽形成。根據一實施例，基底202可具有<001>晶向。第4圖係根據一實施例繪示出在第3圖中的基底內形成開口後的半導體裝置之剖面示意圖。可執行適合的矽移除製程(例如，蝕刻製程)以移除基底202之頂部部份。如此一來，在隔離區域204之間形成開口402。應被注意的是，矽移除製程被良好控制使剩餘的矽基底202之頂表面高於隔離區域204之底表面。
第5圖根據一實施例繪示出在第4圖中的開口與基底上成長半導體區域後的半導體裝置之剖面示意圖。具有不同的半導體材料的半導體區域502在開口中從基底開始成長。 根據實施例，半導體區域502包括鍺，其具有不同於基底202的晶格常數，基底202可由矽所形成。半導體區域502可藉由選擇性磊晶成長(selective epitaxial growth,SEG)製程而形成。
根據另一實施例，半導體區域502可包括鍺化矽，其可以Si1-xGex表示，其中x為鍺化矽中的鍺之原子百分比，且x可大於0、等於或小於1。當x等於1時，半導體區域502可由純鍺所形成。根據又一實施例，半導體區域502可包括化合物半導體材料，其包括III族與V族元素、或包括II族與VI族元素的化合物材料。控制形成半導體區域502的製程條件使半導體區域502之頂部部份具有<111>晶向。舉例來說，可藉由提高SEG製程的成長溫度與降低SEG製程的壓力而達成。根據一實施例，成長溫度為約500~650℃。SEG製程的壓力可進可能地壓低以形成具有<111>晶向的頂部部份。SEG製程的壓力可小於0.13torrs。
鍺的晶格常數大於矽的晶格常數。鍺與矽可有4.2%的晶格失配(mismatch)。如此一來，在SEG製程期間可產生多個穿透錯位。然而，穿透錯位可被限制(trapped)於溝槽中。具體而言，穿透錯位被限制於底部區域504。當半導體區域502逐漸的長高，越來越多的穿透錯位被溝槽的側壁阻擋。如此一來，頂部部份(即半導體區域502的三角形部份)沒有穿透位錯。此外，頂部部份可具有<111>晶向。
第6圖根據一實施例繪示出在第5圖中的隔離區域之頂表面上進行蝕刻製程後的半導體裝置之示意圖。為了形成多重閘極電晶體，隔離區域的頂部部份被蝕刻去除。如第6 圖所示，控制蝕刻製程以暴露出主動區域的三角形頂部部份。如對應到第2圖的上文所述，半導體區域502的頂部部份可作為多重閘極電晶體的通道區域。
第7圖根據另一實施例繪示出在第4圖中的開口與基底上成長半導體區域後的半導體裝置之示意圖。第7圖的成長製程相似於第5圖的成長製程，除了半導體區域602過度成長。如此一來，半導體區域602的三角形頂部部份形成於隔離區域204的頂表面之上。因此，不需要在隔離區域204之頂表面上施加蝕刻製程。如第5圖所示的頂部部份，半導體區域602的頂部部份可具有<111>晶向。
第8~15圖係根據另一實施例繪示出第1圖中的主動區域之中間製造步驟的示意圖。第8~10圖所示的製造步驟分別相似於第3圖、第4圖與第6圖所示的步驟，故在此不再敘述。
第11圖根據一實施例繪示出在第10圖中的主動區域之頂部部份上進行半導體移除製程後的半導體裝置之示意圖。實施化學機械研磨製程移除半導體區域1002之頂部部份以使半導體區域1002之頂表面與隔離區域204之頂表面齊高。可執行蝕刻製程以移除半導體區域1002之頂部部份。如此一來，在隔離區域204之間形成開口1102。應被注意的是，移除製程被良好控制使剩餘的半導體區域1002高於含有穿透錯位的區域(被虛線方框包圍的半導體區域)。
第12圖與第13圖繪示出在第一半導體區域1102上形成由第二半導體材料所組成的第二半導體區域。形成第二 半導體區域的成長製程之溫度與壓力相似於第一半導體區域的成長製程，已於對應到第5圖的上文中敘述。
第14圖根據一實施例繪示出在第二半導體區域之上形成第三半導體區域。第三半導體材料成長於第二半導體區域之上。第三半導體區域係形成於第二半導體區域之上的薄膜。應被注意的是，第一半導體區域、第二半導體區域、與第三半導體區域可由不同半導體材料所形成，例如，IV族元素、III-V族化合物、II-VI族化合物等。
第15圖繪示出隔離區域的頂部部份被蝕刻去除。控制蝕刻製程以暴露出半導體區域的三角形頂部部份。具體來說，如第15圖所示，第三半導體區域(薄膜)被暴露。
第16~21圖根據又一實施例繪示出第1圖中的主動區域之中間製造步驟的示意圖。第16~21圖所示的製造步驟相似於第8~15圖所示的步驟，除了第二半導體區域過度成長。如此一來，三角形頂部部份形成於隔離區域的頂表面之上。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。
再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組 成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。

Claims (10)

  1. 一種半導體裝置，包括：一基底，具有一第一晶向；一主動區域，形成於該基底上，其中：該主動區域之一頂部部份具有一第二晶向；該主動區域之該頂部部份的兩側被一閘結構包覆；以及一溝槽，形成於該基底之中且被多個隔離區域圍繞，其中：該主動區域之一底部部份係形成於該溝槽中，該底部部份係由不同於該基底之材料所形成使得該底部部份及該基底之間具有一界面，而該主動區域之該頂部部份高於該些隔離區域之頂表面。
  2. 如申請專利範圍第1項所述之半導體裝置，其中：該基底具有<001>晶向；以及該主動區域之該頂部部份具有<111>晶向。
  3. 如申請專利範圍第1項所述之半導體裝置，其中：該基底係由矽所形成；以及該主動區域係由鍺所形成。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該該主動區域包括：一第一部份，由一第一半導體材料所形成；一第二部份，由一第二半導體材料所形成，其中該第二部份形成於該第一部份之上；以及一第三部份，由一第三半導體材料所形成，其中該第三部份形成於該第二部份之上，其中該第一半導體材料、該第 二半導體材料、該第三半導體材料包括IV族、III-V族、II-VI族半導體材料、或前述之組合。
  5. 如申請專利範圍第1項所述之半導體裝置，其中該主動區域的該頂部部份之剖面係三角形。
  6. 一種半導體裝置的製造方法，包括：提供具有一第一晶向的一基底，其中該基底係由一第一半導體材料所形成；蝕刻去除部份的該基底以形成一溝槽於相鄰的兩個隔離區域之間；透過一磊晶成長製程成長一半導體區域於該溝槽之中與該基底之上，其中該半導體區域的一底部部份係由不同於該基底之材料所形成使得該底部部份及該基底之間具有一界面，而該半導體區域的一頂部部份之剖面係三角形，且該頂部部份具有一第二晶向；以及形成一閘結構於該半導體區域的至少兩側上。
  7. 如申請專利範圍第6項所述之半導體裝置的製造方法，更包括：使該半導體區域過度成長，而使該半導體區域之該頂部部份高於該隔離區域之頂表面。
  8. 如申請專利範圍第6項所述之半導體裝置的製造方法，更包括：蝕刻去除該隔離區域的頂部部份使該半導體區域的該頂部部份高於該隔離區域的頂表面。
  9. 如申請專利範圍第6項所述之半導體裝置的製造方法，更 包括：以一第二半導體材料成長一第一半導體層於該基底之上；以一第三半導體材料成長一第二半導體層於該第一半導體層之上；以及以一第四半導體材料成長一第三半導體層於該第二半導體層之上。
  10. 如申請專利範圍第6項所述之半導體裝置的製造方法，其中：該半導體區域之晶格常數大於該基底之晶格常數；且其中：該第一晶向為<001>晶向；以及該第二晶向為<111>晶向。
TW102126604A 2012-08-24 2013-07-25 半導體裝置及其製造方法 TWI619252B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/594,579 2012-08-24
US13/594,579 US20140054646A1 (en) 2012-08-24 2012-08-24 Apparatus and Method for Multiple Gate Transistors

Publications (2)

Publication Number Publication Date
TW201409710A TW201409710A (zh) 2014-03-01
TWI619252B true TWI619252B (zh) 2018-03-21

Family

ID=50069528

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102126604A TWI619252B (zh) 2012-08-24 2013-07-25 半導體裝置及其製造方法

Country Status (4)

Country Link
US (2) US20140054646A1 (zh)
CN (1) CN103633115B (zh)
DE (1) DE102012111822B4 (zh)
TW (1) TWI619252B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9953979B2 (en) 2014-11-24 2018-04-24 Qualcomm Incorporated Contact wrap around structure
CN107924944B (zh) 2015-09-11 2021-03-30 英特尔公司 磷化铝铟子鳍状物锗沟道晶体管
US9825036B2 (en) * 2016-02-23 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for semiconductor device
WO2017218014A1 (en) 2016-06-17 2017-12-21 Intel Corporation Field effect transistors with gate electrode self-aligned to semiconductor fin
CN107785272A (zh) * 2016-08-31 2018-03-09 中芯国际集成电路制造(上海)有限公司 一种量子阱FinFET器件及其制备方法、电子装置
US9837497B1 (en) 2016-10-18 2017-12-05 United Microelectronics Corp. Channel structure and manufacturing method thereof
US11227799B2 (en) 2018-04-05 2022-01-18 Intel Corporation Wrap-around contact structures for semiconductor fins
EP3671856B1 (en) 2018-12-21 2023-01-25 IMEC vzw A method for forming a group iii-v heterojunction bipolar transistor on a group iv substrate and corresponding heterojunction bipolar transistor device
KR20210043842A (ko) 2019-10-14 2021-04-22 삼성전자주식회사 반도체 장치

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200807632A (en) * 2006-06-06 2008-02-01 Ibm CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100674914B1 (ko) * 2004-09-25 2007-01-26 삼성전자주식회사 변형된 채널층을 갖는 모스 트랜지스터 및 그 제조방법
US20070267722A1 (en) * 2006-05-17 2007-11-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
JP2007005568A (ja) * 2005-06-23 2007-01-11 Toshiba Corp 半導体装置
WO2007112066A2 (en) * 2006-03-24 2007-10-04 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication
JP4960007B2 (ja) * 2006-04-26 2012-06-27 株式会社東芝 半導体装置及び半導体装置の製造方法
WO2008039534A2 (en) * 2006-09-27 2008-04-03 Amberwave Systems Corporation Quantum tunneling devices and circuits with lattice- mismatched semiconductor structures
US8367528B2 (en) * 2009-11-17 2013-02-05 Asm America, Inc. Cyclical epitaxial deposition and etch
US9117905B2 (en) * 2009-12-22 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method for incorporating impurity element in EPI silicon process
US8211772B2 (en) * 2009-12-23 2012-07-03 Intel Corporation Two-dimensional condensation for uniaxially strained semiconductor fins
US8119494B1 (en) 2010-07-29 2012-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Defect-free hetero-epitaxy of lattice mismatched semiconductors
US9761666B2 (en) * 2011-06-16 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel field effect transistor
US8841701B2 (en) * 2011-08-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having a channel defined in a diamond-like shape semiconductor structure
US8624326B2 (en) * 2011-10-20 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8481341B2 (en) * 2011-11-05 2013-07-09 Tokyo Electron Limited Epitaxial film growth in retrograde wells for semiconductor devices
US8680576B2 (en) * 2012-05-16 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device and method of forming the same
US8673718B2 (en) * 2012-07-09 2014-03-18 Globalfoundries Inc. Methods of forming FinFET devices with alternative channel materials

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200807632A (en) * 2006-06-06 2008-02-01 Ibm CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy

Also Published As

Publication number Publication date
DE102012111822B4 (de) 2015-07-02
CN103633115A (zh) 2014-03-12
DE102012111822A1 (de) 2014-02-27
CN103633115B (zh) 2017-04-12
TW201409710A (zh) 2014-03-01
US9954077B2 (en) 2018-04-24
US20150372116A1 (en) 2015-12-24
US20140054646A1 (en) 2014-02-27

Similar Documents

Publication Publication Date Title
TWI619252B (zh) 半導體裝置及其製造方法
US11049953B2 (en) Nanosheet transistor
TWI523149B (zh) 半導體製造製程及形成半導體器件之方法
US9812530B2 (en) High germanium content silicon germanium fins
TWI411100B (zh) 用於增進通道載子移動性之具有高應力襯料之基於Ｓｉ-Ｇｅ的半導體裝置
US9620506B2 (en) Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
US11881505B2 (en) Tri-layer STI liner for nanosheet leakage control
US11189532B2 (en) Dual width finned semiconductor structure
US10332983B1 (en) Vertical field-effect transistors including uniform gate lengths
CN104051526B (zh) 紧邻半导体鳍的沟渠及其形成方法
US9431425B1 (en) Directly forming SiGe fins on oxide
TW202008454A (zh) 半導體裝置的製造方法
US10319645B2 (en) Method for forming a semiconductor structure containing high mobility semiconductor channel materials
JP2009182264A (ja) 半導体装置およびその製造方法
US9887084B2 (en) Semiconductor devices and methods of manufacture thereof
US20170179127A1 (en) Semiconductor structure having silicon germanium fins and method of fabricating same
US20120241866A1 (en) Transistor structure and manufacturing method which has channel epitaxial equipped with lateral epitaxial structure
JP2007506290A (ja) 絶縁構造部上の半導体チャンネル
JP2009064875A (ja) 半導体装置
CN107369648B (zh) 一种双栅氧化层制造方法
CN108172546B (zh) 一种cmos纳米线及其制造方法
CN109003902B (zh) 一种半导体结构及其制备方法
US20230420530A1 (en) Forming a forksheet nanodevice
TW202240701A (zh) 半導體裝置的形成方法
CN114334831A (zh) Nmos结构、制造方法及半导体器件