TWI610352B - 半導體結構與其製造方法 - Google Patents
半導體結構與其製造方法 Download PDFInfo
- Publication number
- TWI610352B TWI610352B TW105139534A TW105139534A TWI610352B TW I610352 B TWI610352 B TW I610352B TW 105139534 A TW105139534 A TW 105139534A TW 105139534 A TW105139534 A TW 105139534A TW I610352 B TWI610352 B TW I610352B
- Authority
- TW
- Taiwan
- Prior art keywords
- insulating structure
- semiconductor fin
- active semiconductor
- substrate
- top surface
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 192
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 239000010410 layer Substances 0.000 claims description 132
- 238000000034 method Methods 0.000 claims description 73
- 238000009413 insulation Methods 0.000 claims description 64
- 239000002019 doping agent Substances 0.000 claims description 27
- 239000011241 protective layer Substances 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052787 antimony Inorganic materials 0.000 claims description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 description 53
- 230000005669 field effect Effects 0.000 description 18
- 239000000463 material Substances 0.000 description 16
- 238000005530 etching Methods 0.000 description 14
- 238000005468 ion implantation Methods 0.000 description 14
- 238000001459 lithography Methods 0.000 description 14
- 230000000873 masking effect Effects 0.000 description 13
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 9
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 8
- 238000001039 wet etching Methods 0.000 description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000000137 annealing Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- ARXJGSRGQADJSQ-UHFFFAOYSA-N 1-methoxypropan-2-ol Chemical compound COCC(C)O ARXJGSRGQADJSQ-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000011538 cleaning material Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- LLHKCFNBLRBOGN-UHFFFAOYSA-N propylene glycol methyl ether acetate Chemical compound COCC(C)OC(C)=O LLHKCFNBLRBOGN-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- LXPCOISGJFXEJE-UHFFFAOYSA-N oxifentorex Chemical compound C=1C=CC=CC=1C[N+](C)([O-])C(C)CC1=CC=CC=C1 LXPCOISGJFXEJE-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- HPXRVTGHNJAIIH-UHFFFAOYSA-N cyclohexanol Chemical compound OC1CCCCC1 HPXRVTGHNJAIIH-UHFFFAOYSA-N 0.000 description 2
- XCIXKGXIYUWCLL-UHFFFAOYSA-N cyclopentanol Chemical compound OC1CCCC1 XCIXKGXIYUWCLL-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 150000002978 peroxides Chemical class 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000004094 surface-active agent Substances 0.000 description 2
- RWRDLPDLKQPQOW-UHFFFAOYSA-N tetrahydropyrrole Substances C1CCNC1 RWRDLPDLKQPQOW-UHFFFAOYSA-N 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 108091081062 Repeated sequence (DNA) Proteins 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000002052 molecular layer Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
一種半導體結構包含基板、至少一主動半導體鰭片、至少一絕緣結構、閘極電極,以及閘極介電質。至少一主動半導體鰭片配置於基板上。至少一絕緣結構配置於基板上且相鄰於主動半導體鰭片,其中絕緣結構之頂表為非凹面的且低於主動半導體鰭片之另一頂表面。閘極電極配置於主動半導體鰭片上方。閘極介電質,配置於閘極電極與主動半導體鰭片之間。
Description
本揭露是關於一種半導體結構與其製造方法。
半導體積體電路(integrated circuit;IC)行業已經歷指數式增長。積體電路材料及設計之技術性進步已產生數代積體電路,其中每一代皆具有比前一代更小且更複雜之電路。在積體電路進化過程中,功能密度(亦即,每晶片面積中互連裝置之數目)已增大而幾何形狀尺寸(亦即,可使用製造製程建立之最小部件(或線))已減小。此按比例縮小過程使得能夠增加生產效率且降低相關聯之成本。
此按比例縮小亦已增加處理及製造積體電路之複雜性且提供積體電路處理及製造之類似發展。舉例而言,已引入三維電晶體(諸如,鰭式場效應電晶體(FinFET))以替代平面電晶體。鰭式電晶體具有與頂表面及相反側壁相關聯之通道(稱為鰭式通道)。鰭式通道具有由頂表面及相反側壁界定之總通道寬度。
本揭露之實施例為一種半導體結構,包含基板、至少一主動半導體鰭片、至少一絕緣結構、閘極電極,以及閘極介電質。至少一主動半導體鰭片配置於基板上。至少一絕緣結構配置於基板上且相鄰於主動半導體鰭片,其中絕緣結構之頂表為非凹面的且低於主動半導體鰭片之另一頂表面。閘極電極配置於主動半導體鰭片上方。閘極介電質,配置於閘極電極與主動半導體鰭片之間。
本揭露之另一實施例為一種半導體結構,包含基板、第一絕緣結構及第二絕緣結構、至少一第一主動半導體鰭片及至少一第二主動半導體鰭片。第一絕緣結構及第二絕緣結構配置於基板上,其中第一絕緣結構及第二絕緣結構包含不同之複數個摻雜劑。至少一第一主動半導體鰭片配置於基板上且具有突出部分,突出部分自第一絕緣結構突出。至少一第二主動半導體鰭片配置於基板上且具有另一突出部分,突出部分自第二絕緣結構突出,其中第一主動半導體鰭片之突出部分及第二主動半導體鰭片之突出部分具有不同高度。
本揭露之又一實施例為一種用於製造一半導體結構之方法,包含在基板上形成至少一第一主動半導體鰭片及至少一第二主動半導體鰭片,其中基板具有第一區及第二區,第一主動半導體鰭片形成於基板之第一區上,且第二主動半導體鰭片形成於基板之第二區上。在基板之第一區及第二區上形成介電層。使用複數個第一摻雜劑在基板之第一區上摻雜介電層之一部分以形成第一絕緣結構。使用複數個第
二摻雜劑在基板之第二區上摻雜介電層之另一部分以形成第二絕緣結構,其中第二摻雜劑不同於第一摻雜劑。在第一絕緣結構及第二絕緣結構上形成至少一犧牲層,其中至少一犧牲層包含第一絕緣結構之一部分及第二絕緣結構之另一部分。移除至少一犧牲層。
102‧‧‧第一區
104‧‧‧第二區
110‧‧‧基板
112‧‧‧第一主動半導體鰭片
112p‧‧‧突出部分
113‧‧‧頂表面
114‧‧‧第二主動半導體鰭片
114p‧‧‧突出部分
115‧‧‧頂表面
116‧‧‧虛設半導體鰭片
120'‧‧‧介電層
122‧‧‧襯墊層
124‧‧‧遮罩層
125‧‧‧頂表面
130‧‧‧保護層
140‧‧‧圖案化遮罩層
142‧‧‧開口
145‧‧‧圖案化遮罩層
147‧‧‧開口
150‧‧‧第一絕緣結構
151‧‧‧邊緣部分
152‧‧‧頂表面
152a‧‧‧頂表面
152b‧‧‧頂表面
152c‧‧‧頂表面
152d‧‧‧頂表面
152e‧‧‧頂表面
153d‧‧‧底部表面
154‧‧‧凹部
154d‧‧‧凹部
155‧‧‧第二絕緣結構
156‧‧‧邊緣部分
157‧‧‧頂表面
157a‧‧‧頂表面
157b‧‧‧頂表面
157c‧‧‧頂表面
157d‧‧‧頂表面
157e‧‧‧頂表面
158d‧‧‧底部表面
159d‧‧‧凹部
159‧‧‧凹部
160‧‧‧犧牲層
170‧‧‧閘極介電質
175‧‧‧閘極介電質
180‧‧‧閘極電極
185‧‧‧閘極電極
210‧‧‧離子植入製程
215‧‧‧離子植入製程
B‧‧‧區域
C‧‧‧區域
F1‧‧‧N型鰭片場效電晶體
F2‧‧‧P型鰭片場效電晶體
H1‧‧‧高度
H2‧‧‧高度
H3‧‧‧高度
H4‧‧‧高度
H5‧‧‧高度
T1‧‧‧厚度
T2‧‧‧厚度
當結合所附圖閱讀時依據以下詳細描述最佳地理解本揭露之態樣。應注意,根據行業中之標準規程,各種特徵並非按比例繪製。事實上,為論述清晰起見,可任意增加或減小各種特徵之尺寸。
第1A圖至第1L圖係根據本揭露之一些實施例之用於製造半導體結構之方法在各階段之橫截面圖。
第2A圖係根據本揭露之一些實施例之半導體結構之橫截面圖。
第2B圖係第2A圖之區域B之放大圖。
第2C圖係第2A圖之區域C之放大圖。
第3A圖係根據本揭露之一些實施例之半導體結構之橫截面圖。
第3B圖係第3A圖之區域B之放大圖。
第3C圖係第3A圖之區域C之放大圖。
以下揭示內容提供用於實施所提供標的之不同特徵之諸多不同實施例或實例。下文描述部件件及排列之特定實例以簡化本揭露。當然,此等僅係示例性且並非意欲為限制性。舉例而言,隨後之描述中之在第二特徵上方或在第二特徵上形成第一特徵可包含其中第一特徵及第二特徵直接接觸形成之實施例且亦可包含其中可在第一特徵與第二特徵之間形成額外特徵以使得第一特徵及第二特徵可不直接接觸之實施例。另外,本揭露可在各種實例中重複元件符號及/或字母。此重複係出於簡單及清晰之目的且其本身並非指示所論述之各種實施例及/或配置之間的關係。
進一步而言,為了便於描述,本文可使用諸如「下面」、「下方」、「下部」、「上方」、「上部」及類似者等空間相對性術語來描述如圖所示之一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了圖中所描繪之定向外,空間相對性術語意欲囊括使用或操作中之裝置之不同定向。設備可經其他方式定向(旋轉90度或處於其他定向)且因此可同樣解讀本文所使用之空間相對性描述詞。
可依據本揭露之一或多個實施例改良之裝置之實例係半導體結構。舉例而言,此類裝置係鰭式場效應電晶體(fin field effect transistor;FinFET)裝置。鰭式場效應電晶體裝置例如可係互補型金屬氧化物半導體(complementary metal oxide Semiconductor;CMOS)
裝置,此裝置包括至少一個P型金屬氧化物半導體(PMOS)鰭式場效應電晶體裝置及至少一個N型金屬氧化物半導體(NMOS)鰭式場效應電晶體裝置。以下揭示內容將繼續藉助鰭式場效應電晶體實例來說明本申請案之各種實施例。然而,應理解,本申請案應不限於特定類型之裝置。
第1A圖至第1L圖係根據本揭露之一些實施例之用於製造半導體結構之方法在各階段處之橫截面圖。參看第1A圖。提供了基板110。基板110具有至少一個第一區102及至少一個第二區104。舉例而言,在第1A圖中,基板110具有一個第一區102及毗鄰於第一區102之一個第二區104。在一些實施例中,第一區102及第二區104係選自基本上由以下各項構成之群組的不同區:邏輯核心區、記憶體區(諸如嵌入式靜態隨機存取記憶體(SRAM)區)、類比區、輸入/輸出(亦稱為周邊)區、虛設區(用於形成虛設圖案)及類似者。在一些實施例中,第一區102為N型鰭式場效應電晶體區,而第二區104為P型鰭式場效應電晶體區,反之亦然。在替代性實施例中,第一區102為邏輯核心區,而第二區104為輸入輸出(IO)區,反之亦然。
在一些實施例中,基板110包含矽。或者,基板110可包含鍺、矽鍺、砷化鎵或其他適當半導體材料。另外替代地,基板110可包含磊晶層。舉例而言,基板110可具有上覆於塊體半導體之磊晶層。此外,基板110可經應變以增強效能。舉例而言,磊晶層可包含不同於塊體半導體之半導體材料的半導體材料,諸如上覆於塊體矽之矽鍺層
或上覆於塊體矽鍺之矽層。可藉由選擇性磊晶成長(selective epitaxial growth;SEG)形成此類應變基板。此外,基板110可包括絕緣體上半導體(semiconductor on insulator;SOI)結構。另外替代地,基板110可包含內埋式介電層,諸如內埋式氧化物(buried-oxide;BOX)層,諸如藉由氧植入式分離(separation by implanted oxygen;SIMOX)技術、晶圓接合、選擇性磊晶成長或其他適當方法形成之層。
在基板110上形成複數個半導體鰭片。更詳細地,半導體鰭片包括至少一個第一主動半導體鰭片112及至少一個第二主動半導體鰭片114。舉例而言,在第1A圖中,存在四個第一主動半導體鰭片112及四個第二主動半導體鰭片114。第一主動半導體鰭片112形成於基板110之第一區102上,且第二主動半導體鰭片114形成於基板110之第二區104上。在一些實施例中,第一主動半導體鰭片112及第二主動半導體鰭片114包含矽。應注意,第1A圖中之第一主動半導體鰭片112及第二主動半導體鰭片114之數目係說明性的且不應限制本揭露之所請求保護的範疇。本領域之一般技藝人士可根據實際情況選擇第一主動半導體鰭片112及第二主動半導體鰭片114的適合數目。
可例如藉由使用光微影術圖案化且蝕刻基板110來形成第一主動半導體鰭片112及第二主動半導體鰭片114。在一些實施例中,襯墊層122、遮罩層124及光阻劑材料層(未圖示)按順序地沉積於基板110上方。光阻劑材
料層根據所需圖案(在此情形中為第一主動半導體鰭片112及第二主動半導體鰭片114)經照射(曝光)且經顯影以移除光阻劑材料、遮罩層124及襯墊層122之部分。剩餘之光阻劑材料、遮罩層124及襯墊層122保護下層材料免於後續製程步驟,諸如蝕刻。應注意,亦可在蝕刻製程中使用其他遮罩,諸如氧化物或氮化矽遮罩。在一些實施例中,襯墊層122可為氧化矽層,且遮罩層124可為氮化矽層。
在一些實施例中,在基板110上形成至少一個虛設半導體鰭片116。舉例而言,在第1A圖中,存在十個虛設半導體鰭片116。虛設半導體鰭片116可安置於基板110之第一區102及/或第二區104中,且可安置於第一主動半導體鰭片112與第二主動半導體鰭片114之間。虛設半導體鰭片116在半導體結構中不具有功能性但使裝置製程更統一、更可再現且更可製造。第一主動半導體鰭片112及第二主動半導體鰭片114在半導體結構中具有功能性。
虛設半導體鰭片116可與第一主動半導體鰭片112及第二主動半導體鰭片114一起形成。更詳細地,在基板110上預先形成具有實質上相等間隔及實質上相同高度之複數個半導體鰭片。執行額外微影術及蝕刻操作以移除(或切割)鰭片中之一些鰭片(稱為虛設半導體鰭片116)。微影術及蝕刻操作可執行一次或多次。未切割之半導體鰭片稱為第一主動半導體鰭片112及第二主動半導體鰭片114。亦即,第一主動半導體鰭片112之高度H1及第二主動半導體鰭片114之高度H2大於虛設半導體鰭片116之高度
H3。此操作可防止不同鰭片線輪廓(包含臨界尺寸及側壁輪廓角度兩者)。然而,在一些其他實施例中,可省略虛設半導體鰭片116。在一些實施例中,第一主動半導體鰭片112及第二主動半導體鰭片114相對於基板110具有實質上相同的高度,亦即,高度H1實質上等於高度H2,且高度H1及/或高度H2係約100nm至約160nm,且所請求保護的範疇在此方面不受限制。
參看第1B圖。介電材料120安置於基板110上且覆蓋第一主動半導體鰭片112、第二主動半導體鰭片114及虛設半導體鰭片116。在一些實施例中,介電材料120包含氧化物及/或其他介電材料。視情況,可預先形成襯裡氧化物(未圖示)。在一些實施例中,襯裡氧化物可係熱氧化物。在一些其他實施例中,可使用原位蒸汽產生(in-situ steam generation;ISSG)來形成襯裡氧化物。在又一些其他實施例中,可使用選擇性區域化學氣相沉積(selective area CVD;SACVD)或其他常用之化學氣相沉積方法來形成襯裡氧化物。襯裡氧化物之形成減小了電場且由此改良所得半導體結構之效能。
參看第1C圖。執行化學機械拋光(chemical mechanical polishing;CMP)以使介電材料120之頂表面與遮罩層124之頂表面齊平,從而形成介電層120’。換言之,介電層120’覆蓋虛設半導體鰭片116。遮罩層124可用作CMP停止層。
保護層130形成於介電材料120’上且覆蓋第
一主動半導體鰭片112及第二主動半導體鰭片114。保護層130允許穿過其植入同時防止損壞下層基板(亦即,第一主動半導體鰭片112、第二主動半導體鰭片114及介電材料120’)。適合保護層130之實例可係氧化物層或包含藉由化學氣相沉積製程(例如,MOCVD)沉積之二氧化矽(SiO2)或氮化矽(SiN)層,或藉由原子層沉積之氧化鋁(Al2O3)層或奈米層壓層(包含諸如二氧化鉿(HfO2)及/或氧化鋁鉿(HfAlO)之材料)。
參看第1D圖。圖案化遮罩層140形成於保護層130及基板110之第二區104上。圖案化遮罩層140可係抗蝕劑層,其亦稱為光阻劑層、光敏感層、成像層、圖案化層或輻射敏感層。圖案化遮罩層140包含正型抗蝕劑材料、負型抗蝕劑材料、其他類型材料,或其組合。圖案化遮罩層140藉由微影術製程形成於保護層130上。微影術製程包括抗蝕劑塗佈(舉例而言,旋塗式塗佈)、軟烘烤、遮罩對準、曝露、曝露后烘烤、使抗蝕劑顯影、沖洗、乾燥(舉例而言,硬烘烤)、其他適合製程,或其組合。或者,藉由諸如無遮罩微影術、電子束刻寫或離子束刻寫等其他方法實施或替代微影術製程。在又一替代案中,在微影術製程中執行奈米壓印技術以圖案化遮罩層。在一些實施例中,於微影術製程中執行蝕刻製程,諸如乾式蝕刻、濕式蝕刻、其他蝕刻方法,或其組合。可在形成圖案化遮罩層140之前對保護層130執行沖洗製程(諸如,經去離子水沖洗)。
圖案化遮罩層140包括開口142,此開口曝露
位於基板110之第一區102上之保護層130之一部分。在第1D圖中,使用圖案化遮罩層140作為遮罩對介電層120’執行離子植入製程(或摻雜製程)210。在第1D圖中,離子植入製程210在介電層120’中形成至少一個第一絕緣結構150。離子植入製程210植入P型摻雜劑(諸如,硼(B)、銦(In)、鋁(Al)、鎵(Ga)、IIIA族元素,或其組合)。在一些實施例中,第一絕緣結構150為半導體結構(諸如,電晶體)之半導體鰭片之間的電絕緣。離子植入製程210以適合能量及劑量執行以達成半導體結構之所欲的特性。在一些實施例中,離子植入製程210之植入劑量係約8×1012個離子/平方公分(cm2)至約2×1014個離子/平方公分(cm2),且離子植入製程210之能量係約20keV至約120keV,且所請求保護的範疇在此方面不受限制。
參看第1E圖。圖案化遮罩層140(參見第1D圖)被移除。在一些實施例中,藉由執行濕式蝕刻製程來移除圖案化遮罩層140。在一些實施例中,用於濕式蝕刻製程之濕式蝕刻溶液包括硫酸(H2SO4)及過氧化物(H2O2)。或者,藉由選自以下各項之化學溶液來移除圖案化遮罩層140:O3水、硫酸(H2SO4)與臭氧(O3)、H2SO4與H2O2、N-甲基-2-吡咯啶(NMP)、環己醇、環戊醇、丙二醇单甲醚(PGME)及丙二醇单甲醚乙酸酯(PGMEA)。在一些其他實施例中,藉由選自基於氧化劑之溶液的化學溶液來移除圖案化遮罩層140。在一些實施例中,在移除圖案化遮罩層140之後執行清洗製程以清洗有機殘留物或其他殘留物。清
洗材料能夠移除有機殘留物。清洗材料可包含溶劑、表面活性劑或聚合物成分。
另一圖案化遮罩層145形成於保護層130及基板110之第一區102上。圖案化遮罩層145可為抗蝕劑層,其亦稱為光阻劑層、光敏感層、成像層、圖案化層或輻射敏感層。圖案化遮罩層145包含正型抗蝕劑材料、負型抗蝕劑材料、其他類型材料,或其組合。圖案化遮罩層145藉由微影術製程形成於保護層130上。微影術製程包括抗蝕劑塗佈(舉例而言,旋塗式塗佈)、軟烘烤、遮罩對準、曝露、曝露后烘烤、使抗蝕劑顯影、沖洗、乾燥(舉例而言,硬烘烤)、其他適合製程,或其組合。或者,藉由諸如無遮罩微影術、電子束刻寫或離子束刻寫等其他方法實施或替代微影術製程。在又一替代案中,於微影術製程中執行奈米壓印技術以圖案化遮罩層。在一些實施例中,於微影術製程中執行蝕刻製程,諸如乾式蝕刻、濕式蝕刻、其他蝕刻方法,或其組合。可在形成圖案化遮罩層145之前對保護層130執行沖洗製程(諸如,經去離子化水沖洗)。
圖案化遮罩層145包括開口147,此開口曝露位於基板110之第二區104上之保護層130之一部分。在第1E圖中,使用圖案化遮罩層145作為遮罩對介電層120’執行另一離子植入製程(或摻雜製程)215。在第1E圖中,離子植入製程215在介電層120’中形成至少一個第二絕緣結構155。離子植入製程215植入N型摻雜劑(諸如,氮(N)、磷(P)、砷(As)、銻(Sb)、VA族元素,或其組合)。在一些
實施例中,第二絕緣結構155係半導體結構(諸如,電晶體)之半導體鰭片之間的電絕緣。離子植入製程215以適合能量及劑量執行以達成半導體結構之所期望特性。在一些實施例中,離子植入製程215之植入劑量係約8×1012個離子/平方公分(cm2)至約3×1014個離子/平方公分(cm2),且離子植入製程215之能量係約20keV至約250keV,且所請求保護的範疇在此方面不受限制。
參看第1F圖。圖案化遮罩層145(參見第1E圖)及保護層130(參見第1E圖)被移除。在一些實施例中,藉由執行濕式蝕刻製程來移除圖案化遮罩層145。在一些實施例中,用於濕式蝕刻製程之濕式蝕刻溶液包括硫酸(H2SO4)及過氧化物(H2O2)。或者,藉由選自以下各項之化學溶液來移除圖案化遮罩層145:O3水、硫酸(H2SO4)與臭氧(O3)、H2SO4與H2O2、N-甲基-2-吡咯啶(NMP)、環己醇、環戊醇、丙二醇单甲醚(PGME)及丙二醇单甲醚乙酸酯(PGMEA)。在一些其他實施例中,藉由選自基於氧化劑之溶液的化學溶液來移除圖案化遮罩層145。在一些實施例中,在移除圖案化遮罩層145之後執行清洗製程以清洗有機殘留物或其他殘留物。清洗材料能夠移除有機殘留物。清洗材料可包含溶劑、表面活性劑或聚合物成分。
在一些實施例中,可在移除圖案化遮罩層145之後執行退火(下文稱為擴散退火)製程。退火製程將強迫摻雜劑在第一絕緣結構150及第二絕緣結構155中擴散。擴散退火可包括快速熱退火(RTA)及/或固相磊晶再生長退
火。由於擴散退火,第一絕緣結構140及第二絕緣結構145具有較均勻的摻雜劑分佈。
參看第1G圖。第一絕緣結構150及第二絕緣結構155經開槽以曝露遮罩層124之部分。在一些實施例中,開槽第一絕緣結構150及第二絕緣結構155包含濕式浸漬於(例如)稀氫氟(HF)酸溶液中,此稀氫氟(HF)酸溶液可具有低於約1%之HF濃度。在替代性實施例中,蝕刻係乾式蝕刻,其中使用包含氨(NH3)及氫氟酸之製程氣體。在第1G圖中,第一絕緣結構150及第二絕緣結構155經開槽,以使得遮罩層124自第一絕緣結構150及第二絕緣結構155突出而第一主動半導體鰭片112及第二主動半導體鰭片114嵌入其中。亦即,第一絕緣結構150之頂表面152低於遮罩層124之頂表面125且高於第一主動半導體鰭片112之頂表面113。另外,第二絕緣結構155之頂表面157低於遮罩層124之頂表面125且高於第二主動半導體鰭片114之頂表面115。
參看第1H圖。遮罩層124及襯墊層122(參見第1G圖)被移除或經蝕刻。在一些實施例中,使用熱磷酸(H3PO4)藉由濕式製程移除遮罩層124,且使用稀釋氫氟酸移除襯墊層122。可藉此曝露第一主動半導體鰭片112之頂表面113及第二主動半導體鰭片114之頂表面115。
參看第1I圖。在第一絕緣結構150及第二絕緣結構155上形成至少一個犧牲層160。在一些實施例中,將氟化氫(HF)及氨氣(NH3)作為蝕刻劑引入至第一絕緣結構
150及第二絕緣結構155。氟化氫(HF)及氨氣(NH3)可相互反應,並且與存在於第一絕緣結構150及第二絕緣結構155中之氧化物反應以在第一絕緣結構150及第二絕緣結構155上產生六氟矽酸銨(NH4)2SiF6,藉此形成犧牲層160。亦即,犧牲層160由六氟矽酸銨構成。由於犧牲層160形成於第一絕緣結構150及第二絕緣結構155上,因此犧牲層160將充當將防止氟化氫及氨氣進一步擴散至犧牲層160中之擴散阻障層。換言之,犧牲層160之形成將防止進一步在第一絕緣結構150和第二絕緣結構155內之更深深度處形成六氟矽酸銨。可根據製程條件調整犧牲層160所欲形成之深度。另外,犧牲層160實質上均勻地形成。如本文所用之術語「實質上」可適於修飾可准許變化而不導致與其相關之基本功能之改變的任何數量表示。
參看第1J圖。當反應自中止(self-terminated)時,即可加熱犧牲層160、第一絕緣結構150及第二絕緣結構155(連同基板110)以便移除犧牲層160,藉此減小第一絕緣結構150及第二絕緣結構155之厚度且曝露第一絕緣結構150及第二絕緣結構155之剩餘部分以供進一步處理。加熱可致使犧牲層160熱分解成氮氣(N2)、水(H2O)、四氟化矽(SiF4)及氨(NH3),上述成分可為蒸氣且可自第一絕緣結構150及第二絕緣結構155移除。在一些實施例中,藉由升高加熱溫度可增大移除(或蝕刻)速率。
在第1J圖中,由於第一絕緣結構150及第二絕
緣結構155具有不同摻雜劑,因此第一絕緣結構150及第二絕緣結構155蝕刻速率係不同的。舉例而言,在第1J圖中,第一絕緣結構150之頂表面152低於第二絕緣結構155之頂表面157。換言之,第一絕緣結構150之頂表面152及第二絕緣結構155之頂表面157並非共平面。因此,具有不同厚度T1及T2之第一絕緣結構150及第二絕緣結構155可在同一製程中形成。
此外,由於犧牲層160實質上均勻地形成,因此犧牲層160實質上亦均勻地移除。因此,在第1J圖中,第一絕緣結構150之頂表面152之中間部分係實質上平坦。此外,在第一絕緣結構150之邊緣處形成至少一個凹部154。在第1J圖中,頂表面152為凸面。此外,第一絕緣結構155之頂表面157之中間部分係實質上平坦。在第二絕緣結構155之邊緣處形成至少一個凹部159。在第1J圖中,頂表面157為凸面。
參看第1K圖。在犧牲層160(參見第1I圖)經移除之後,第一絕緣結構150及第二絕緣結構155再次曝露且可進一步處理。在一些實施例中,可重複地執行另一移除循環(諸如,類似於第1I圖及第1J圖中所描述之形成及移除製程之移除循環)以更進一步可控制地減小第一絕緣結構150及第二絕緣結構155之厚度T1及T2,諸如將第一絕緣結構150及第二絕緣結構155減小額外幾奈米。然而,如本領域之一般技藝人士將認識到,如上文所述的移除循環之類型、移除循環之重複次數、用於移除循環之製程參數以
及第一絕緣結構150及第二絕緣結構155之厚度意欲僅為說明性,此係因可替代地利用任何重複次數以及第一絕緣結構150及第二絕緣結構155之任何所期望厚度。
在第1K圖中,執行兩次移除循環(亦即,第1I圖及第1J圖之形成及移除製程為一次移除循環的)。第一絕緣結構150及第二絕緣結構155進一步經開槽,以使得第一主動半導體鰭片112自第一絕緣結構150突出且在本文中稱為突出部分112p,且第二主動半導體鰭片114自第二絕緣結構155突出且在本文中稱為突出部分114p。在一些實施例中,突出部分112p及114p可係鰭式場效應電晶體之源極/汲極特徵。在一些實施例中,第一主動半導體鰭片112中之一者之突出部分112p之高度H4可係約8nm,且第二主動半導體鰭片114中之一者之突出部分114p之高度H5可小於約8nm。藉由增加移除循環之次數,可增大高度H4及H5。並同時減小第一絕緣結構150及第二絕緣結構155之厚度T1及T2。在第1K圖中,高度H4大於高度H5,且厚度T1小於厚度T2。
根據上述實施例,執行複數個移除循環以開槽第一絕緣結構及第二絕緣結構。移除循環包含在第一絕緣結構及第二絕緣結構上形成犧牲層且移除犧牲層。在第一絕緣結構及第二絕緣結構經開槽之後,第一半導體鰭片及第二半導體鰭片可自第一絕緣結構及第二絕緣結構突出。因此,可藉由判定移除循環之次數來調整半導體鰭片之突出部分之高度(以及絕緣結構之厚度)。舉例而言,由於第
一絕緣結構及第二絕緣結構之蝕刻速率不同,因此N型鰭式場效應電晶體之半導體鰭片之突出部分之高度可不同於P型鰭式場效應電晶體之半導體鰭片之突出部分之高度。替代地,可藉由執行不同次數之移除循環調整突出部分之高度。
應注意,儘管在第1I圖至第1K圖中第一絕緣結構150及第二絕緣結構155在同一製造製程中經開槽(或經蝕刻),但在一些其他實施例中可單獨地開槽(或蝕刻)第一絕緣結構150及第二絕緣結構155。
參看第1L圖。閘極介電質170及175經形成以分別覆蓋第一主動半導體鰭片112之第一突出部分112p及第二主動半導體鰭片114及第二突出部分114p。閘極介電質170及175可藉由熱氧化形成且因此可包含熱氧化矽。接著,分別在閘極介電質170及175上形成閘極電極180及185。在一些實施例中,閘極電極180覆蓋第一主動半導體鰭片112中之一者以上以形成N型鰭式場效電晶體F1,且閘極電極185覆蓋第二主動半導體鰭片114中之一者以上以形成P型鰭式場效電晶體F2。在替代性實施例中,可使用第一主動半導體鰭片112及/或第二主動半導體鰭片114中之至少一者來形成一個鰭式場效應電晶體。
第2A圖係根據本揭露之一些實施例之半導體結構之橫截面圖,第2B圖係第2A圖之區域B之放大圖且第2C圖係第2A圖之區域C之放大圖。第2A圖及第1K圖之半導體結構之間的區別與移除循環之數目有關。在第2A圖
中,執行三次移除循環。第2A圖至第2C圖中之虛線表示在執行第三移除循環之前的第一絕緣結構150及第二絕緣結構155之頂表面。更詳細地,以第一絕緣結構150為例(參見第2B圖),第一絕緣結構150在執行第一移除循環之前具有頂表面152a,第一絕緣結構150在執行第一移除循環之後具有頂表面152b且第一絕緣結構150在執行第二移除循環之後具有頂表面152c。此外,第一絕緣結構150在執行第三移除循環之後具有頂表面152d。當增加移除循環之次數時,第一主動半導體鰭片112之突出部分112p之高度H4增大,且第一絕緣結構150之厚度T1(參見第2A圖)減小。
在一些實施例中,頂表面152a與152b之間的高度差係約10nm,頂表面152b與152c之間的高度差係約8nm,頂表面152c與152d之間的高度差係約5nm,且本揭露所請求保護的範疇在此方面不受限制。此外,頂表面152b、152c、152d係凸面的。在第一絕緣結構150之邊緣部分151處形成兩個凹部154d。此外,凹部154d中之至少一者具有自第一絕緣結構150之頂表面152d向下延伸至第一主動半導體鰭片112之至少一個底部表面153d。
類似地,在第2C圖中,第二絕緣結構155在執行第二移除循環之前具有頂表面157a,第二絕緣結構155在執行第二移除循環之後具有頂表面157b且第二絕緣結構155在執行第二移除循環之後具有頂表面157c。此外,第二絕緣結構155在執行第三移除循環之後具有頂表面157d。當增加移除循環之次數時,第二主動半導體鰭片114
之突出部分114p之高度H5增大且第二絕緣結構155之厚度T2(參見第2A圖)減小。此外,頂表面157b、157c、157d係凸面的。在第二絕緣結構155之邊緣部分156處形成兩個凹部159d。此外,凹部159d中之至少一者具有自第二絕緣結構155之頂表面157d向下延伸至第二主動半導體鰭片114之至少一個底部表面158d。第2A圖之半導體結構之其他相關結構及製造細節類似於第1K圖之半導體結構,且因此,下文將不重複此方面之描述。
第3A圖係根據本揭露之一些實施例之半導體結構之橫截面圖,第3B圖係第3A圖之區域B之放大圖且第3C圖係第3A圖之區域C之放大圖。第3A圖與第1K圖之半導體結構之間的區別與移除循環之次數有關。在第3A圖中,執行四次移除循環。第3A圖至第3C圖中之虛線表示在執行第四移除循環之前的第一絕緣結構150及第二絕緣結構155之頂表面。更詳細地,以第一絕緣結構150為例(參見第3B圖),第一絕緣結構150在執行第一移除循環之前具有頂表面152a,第一絕緣結構150在執行第一移除循環之後具有頂表面152b,第一絕緣結構150在執行第二移除循環之後具有頂表面152c,且第一絕緣結構150在執行第二移除循環之後具有頂表面152d。此外,第一絕緣結構150在執行第四移除循環之後具有頂表面152e。當增加移除循環之次數時,第一主動半導體鰭片112之突出部分112p之高度H4增大且第一絕緣結構150之厚度T1(參見第3A圖)減小。
在一些實施例中,頂表面152a與152b之間的高度差係約10nm,頂表面152b與152c之間的高度差係約8nm,頂表面152c與152d之間的高度差係約5nm,頂表面152d與152e之間的高度差係約4nm,且本揭露所請求保護的範疇在此方面不受限制。此外,頂表面152b、152c、152d係凸面的且頂表面152e係實質上平坦。
類似地,在第3C圖中,第二絕緣結構155在執行第二移除循環之前具有頂表面157a,第二絕緣結構155在執行第二移除循環之後具有頂表面157b,第二絕緣結構155在執行第二移除循環之後具有頂表面157c,且第二絕緣結構155在執行第三移除循環之後具有頂表面157d。此外,第二絕緣結構155在執行第四移除循環之後具有頂表面157e。當增加移除循環之次數時,第二主動半導體鰭片114之突出部分114p之高度H5增大且第二絕緣結構155之厚度T2(參見第3A圖)減小。此外,頂表面157b、157c、157d為凸面的且頂表面157e係實質上平坦。第3A圖之半導體結構之其他相關結構及製造細節類似於第1K圖之半導體結構,且因此,下文將不重複此方面之描述。
根據上述實施例,當增加移除循環之次數時頂表面輪廓可被改變。因此,亦可藉由判定移除循環之次數來調整第一絕緣結構及第二絕緣結構之頂表面輪廓(例如,凸面或實質上平坦)。由於第一絕緣結構及第二絕緣結構之頂表面係非凹面的,因此可進一步曝露第一主動半導體鰭片及第二主動半導體鰭片之側壁且可改良半導體裝置
之寄生電容。另外,可藉由調整半導體鰭片之突出部分之高度、絕緣結構之厚度及/或絕緣結構之頂表面輪廓來調節半導體結構之效能(例如,接通/關斷電流)。
此外,由於第一絕緣結構及第二絕緣結構包含不同摻雜劑,因此第一絕緣結構及第二絕緣結構之蝕刻速率係不同的。第一主動半導體鰭片之第一突出部分之高度不同於第二主動半導體鰭片之第二突出部分之高度。亦即,藉助至少一個蝕刻製程,可形成具有不同高度之主動半導體鰭片。藉由差異化不同裝置區中之鰭片高度,增大接面窗,此意指不同裝置區中之鰭式場效應電晶體之鰭片高度不再連結在一起。鑒於不同裝置區中之鰭式場效應電晶體具有不同鰭片高度,更易於調整不同裝置區中之裝置效能。
本揭露之實施例為一種半導體結構,包含基板、至少一主動半導體鰭片、至少一絕緣結構、閘極電極,以及閘極介電質。至少一主動半導體鰭片配置於基板上。至少一絕緣結構配置於基板上且相鄰於主動半導體鰭片,其中絕緣結構之頂表為非凹面的且低於主動半導體鰭片之另一頂表面。閘極電極配置於主動半導體鰭片上方。閘極介電質,配置於閘極電極與主動半導體鰭片之間。
本揭露之另一實施例為一種半導體結構,包含基板、第一絕緣結構及第二絕緣結構、至少一第一主動半導體鰭片及至少一第二主動半導體鰭片。第一絕緣結構及第二絕緣結構配置於基板上,其中第一絕緣結構及第二絕
緣結構包含不同之複數個摻雜劑。至少一第一主動半導體鰭片配置於基板上且具有突出部分,突出部分自第一絕緣結構突出。至少一第二主動半導體鰭片配置於基板上且具有另一突出部分,突出部分自第二絕緣結構突出,其中第一主動半導體鰭片之突出部分及第二主動半導體鰭片之突出部分具有不同高度。
本揭露之又一實施例為一種用於製造一半導體結構之方法,包含在基板上形成至少一第一主動半導體鰭片及至少一第二主動半導體鰭片,其中基板具有第一區及第二區,第一主動半導體鰭片形成於基板之第一區上,且第二主動半導體鰭片形成於基板之第二區上。在基板之第一區及第二區上形成介電層。使用複數個第一摻雜劑在基板之第一區上摻雜介電層之一部分以形成第一絕緣結構。使用複數個第二摻雜劑在基板之第二區上摻雜介電層之另一部分以形成第二絕緣結構,其中第二摻雜劑不同於第一摻雜劑。在第一絕緣結構及第二絕緣結構上形成至少一犧牲層,其中至少一犧牲層包含第一絕緣結構之一部分及第二絕緣結構之另一部分。移除至少一犧牲層。
上文概述數個實施例之特徵以使得熟習此項技術者可較佳地理解本揭露之態樣。熟習此項技術者應瞭解,其可容易地使用本揭露作為基礎來設計或修改用於實行本文所引入之實施例之相同目的及/或達成相同優點之其他製程及結構。熟習此項技術者亦應認識到,此等等效構造並不背離本揭露之精神及範疇,且其可在不背離本揭
露之精神及範疇之情況下做出各種改變、替代及變更。
102‧‧‧第一區
104‧‧‧第二區
110‧‧‧基板
112‧‧‧第一主動半導體鰭片
112p‧‧‧突出部分
114‧‧‧第二主動半導體鰭片
114p‧‧‧突出部分
150‧‧‧第一絕緣結構
152‧‧‧頂表面
155‧‧‧第二絕緣結構
157‧‧‧頂表面
T1‧‧‧厚度
T2‧‧‧厚度
H4‧‧‧高度
H5‧‧‧高度
Claims (10)
- 一種半導體結構,包含:一基板;至少一主動半導體鰭片,配置於該基板上;至少一絕緣結構,配置於該基板上且相鄰於該至少一主動半導體鰭片,其中該絕緣結構之一頂表為非凹面的且低於該至少一主動半導體鰭片之另一頂表面,且該絕緣結構具有至少一凹部,該凹部配置於與該主動半導體鰭片相鄰之該絕緣結構之至少一邊緣部分中,其中該凹部具有自該絕緣結構之該頂表面向下延伸至該主動半導體鰭片之至少一底部表面;一閘極電極,配置於該至少一主動半導體鰭片上方;以及一閘極介電質,配置於該至少一閘極電極與該主動半導體鰭片之間。
- 如請求項1所述之半導體結構,其中該絕緣結構之該頂表面為凸面。
- 如請求項1所述之半導體結構,其中該絕緣結構包含複數個摻雜劑。
- 一種半導體結構,包含:一基板; 一第一絕緣結構及一第二絕緣結構,配置於該基板上,其中該第一絕緣結構及該第二絕緣結構包含不同之複數個摻雜劑;至少一第一主動半導體鰭片,配置於該基板上且具有一突出部分,該突出部分自該第一絕緣結構突出;以及至少一第二主動半導體鰭片,配置於該基板上且具有另一突出部分,該突出部分自該第二絕緣結構突出,其中該第一主動半導體鰭片之該突出部分及該第二主動半導體鰭片之該突出部分具有不同高度。
- 如請求項4所述之半導體結構,其中該第一主動半導體鰭片及該第二主動半導體鰭片具有實質上與該基板相同之高度。
- 如請求項4所述之半導體結構,其中該第一絕緣結構具有一第一厚度,且該第二絕緣結構具有不同於該第一厚度之一第二厚度。
- 如請求項4-6任一項所述之半導體結構,其中該第一絕緣結構之該些摻雜劑為N型,而該第二絕緣結構之該些摻雜劑為P型;或者其中該第一絕緣結構之一頂表面與該第二絕緣結構之另一頂表面為非共面。
- 一種用於製造一半導體結構之方法,包含: 在一基板上形成至少一第一主動半導體鰭片及至少一第二主動半導體鰭片,其中該基板具有一第一區及一第二區,該第一主動半導體鰭片形成於該基板之該第一區上,且該第二主動半導體鰭片形成於該基板之該第二區上;在該基板之該第一區及該第二區上形成一介電層;使用複數個第一摻雜劑在該基板之該第一區上摻雜該介電層之一部分以形成一第一絕緣結構;使用複數個第二摻雜劑在該基板之該第二區上摻雜該介電層之另一部分以形成一第二絕緣結構,其中該些第二摻雜劑不同於該些第一摻雜劑;在該第一絕緣結構及該第二絕緣結構上形成至少一犧牲層,其中該至少一犧牲層包含該第一絕緣結構之一部分及該第二絕緣結構之另一部分;以及移除該至少一犧牲層。
- 如請求項8所述之方法,其中該形成該至少一犧牲層之步驟包含:提供至少一蝕刻劑以與該第一絕緣結構之該部分及該第二絕緣結構之該部分反應;或者其中該移除該至少一犧牲層之步驟包含:加熱該至少一犧牲層以移除該至少一犧牲層;或者此方法更包含:將形成該至少一犧牲層之步驟及移除該至少一犧牲層之步驟重複至少一次;或者 此方法更包含:將形成該至少一犧牲層之步驟及移除該至少一犧牲層之步驟重複至少一次來調整該第一絕緣結構之一厚度;或者此方法更包含:將形成該至少一犧牲層之步驟之步驟及移除該至少一犧牲層之步驟重複至少一次來調整該第一絕緣結構之一表面輪廓;或者此方法更包含:在該介電層上形成一保護層。
- 如請求項8或9任一項所述之方法,其中該第一絕緣結構之該些第一摻雜劑包括硼(B)、銦(In)、鋁(Al)、鎵(Ga)、IIIA族元素,或上述之組合;或者其中該第二絕緣結構之該些第二摻雜劑包括氮(N)、磷(P)、砷(As)、銻(Sb)、VA族元素,或上述之組合。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/984,555 US9786505B2 (en) | 2015-12-30 | 2015-12-30 | FinFET device using dummy fins for smooth profiling |
US14/984,555 | 2015-12-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201724217A TW201724217A (zh) | 2017-07-01 |
TWI610352B true TWI610352B (zh) | 2018-01-01 |
Family
ID=59235878
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105139534A TWI610352B (zh) | 2015-12-30 | 2016-11-30 | 半導體結構與其製造方法 |
Country Status (3)
Country | Link |
---|---|
US (3) | US9786505B2 (zh) |
CN (1) | CN106952910B (zh) |
TW (1) | TWI610352B (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9825128B2 (en) | 2015-10-20 | 2017-11-21 | Maxpower Semiconductor, Inc. | Vertical power transistor with thin bottom emitter layer and dopants implanted in trenches in shield area and termination rings |
TWI678732B (zh) | 2016-03-22 | 2019-12-01 | 聯華電子股份有限公司 | 一種形成半導體鰭狀結構的方法 |
US9905663B2 (en) * | 2016-06-24 | 2018-02-27 | International Business Machines Corporation | Fabrication of a vertical fin field effect transistor with a reduced contact resistance |
US10514711B2 (en) * | 2016-10-09 | 2019-12-24 | Airspace Systems, Inc. | Flight control using computer vision |
US10014297B1 (en) * | 2017-05-08 | 2018-07-03 | Globalfoundries Inc. | Methods of forming integrated circuit structure using extreme ultraviolet photolithography technique and related integrated circuit structure |
CN110998858A (zh) * | 2017-08-16 | 2020-04-10 | 东京毅力科创株式会社 | 用于将单扩散隔断并入fet器件的纳米沟道结构中的方法和器件 |
US10269803B2 (en) * | 2017-08-31 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid scheme for improved performance for P-type and N-type FinFETs |
US10361125B2 (en) | 2017-12-19 | 2019-07-23 | International Business Machines Corporation | Methods and structures for forming uniform fins when using hardmask patterns |
CN110854195B (zh) * | 2018-08-21 | 2023-09-12 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
KR102582074B1 (ko) * | 2018-12-28 | 2023-09-21 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
CN112103182B (zh) * | 2019-06-18 | 2024-05-17 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201401513A (zh) * | 2012-05-21 | 2014-01-01 | Globalfoundries Us Inc | 形成具有替代通道材料之鰭式場效電晶體設備的方法 |
TW201507158A (zh) * | 2013-03-30 | 2015-02-16 | Intel Corp | 鰭爲基的電晶體架構上的平坦裝置 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6188106B1 (en) * | 1998-09-03 | 2001-02-13 | Advanced Micro Devices, Inc. | MOSFET having a highly doped channel liner and a dopant seal to provide enhanced device properties |
US6770516B2 (en) * | 2002-09-05 | 2004-08-03 | Taiwan Semiconductor Manufacturing Company | Method of forming an N channel and P channel FINFET device on the same semiconductor substrate |
KR100526889B1 (ko) * | 2004-02-10 | 2005-11-09 | 삼성전자주식회사 | 핀 트랜지스터 구조 |
KR100614800B1 (ko) * | 2004-12-10 | 2006-08-22 | 삼성전자주식회사 | 복수개의 돌출된 채널을 갖는 트랜지스터의 제조 방법 |
US8263462B2 (en) * | 2008-12-31 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dielectric punch-through stoppers for forming FinFETs having dual fin heights |
JP4968861B2 (ja) * | 2009-03-19 | 2012-07-04 | 東京エレクトロン株式会社 | 基板のエッチング方法及びシステム |
US9953885B2 (en) | 2009-10-27 | 2018-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI shape near fin bottom of Si fin in bulk FinFET |
US9087725B2 (en) * | 2009-12-03 | 2015-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with different fin height and EPI height setting |
CN102157554A (zh) * | 2010-02-12 | 2011-08-17 | 中国科学院微电子研究所 | 鳍式晶体管结构及其制作方法 |
JP5713837B2 (ja) * | 2011-08-10 | 2015-05-07 | 株式会社東芝 | 半導体装置の製造方法 |
US9023715B2 (en) * | 2012-04-24 | 2015-05-05 | Globalfoundries Inc. | Methods of forming bulk FinFET devices so as to reduce punch through leakage currents |
US8603893B1 (en) * | 2012-05-17 | 2013-12-10 | GlobalFoundries, Inc. | Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates |
US8697515B2 (en) | 2012-06-06 | 2014-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a FinFET device |
US9583398B2 (en) * | 2012-06-29 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having FinFETS with different fin profiles |
US9318367B2 (en) * | 2013-02-27 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET structure with different fin heights and method for forming the same |
US8999792B2 (en) * | 2013-03-15 | 2015-04-07 | Qualcomm Incorporated | Fin-type semiconductor device |
CN104253046B (zh) * | 2013-06-26 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管及其形成方法 |
US9520502B2 (en) * | 2013-10-15 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs having epitaxial capping layer on fin and methods for forming the same |
US9356046B2 (en) * | 2013-11-22 | 2016-05-31 | Globalfoundries Inc. | Structure and method for forming CMOS with NFET and PFET having different channel materials |
US9184087B2 (en) * | 2013-12-27 | 2015-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanisms for forming FinFETs with different fin heights |
CN104782503A (zh) | 2014-01-21 | 2015-07-22 | 浙江布莱蒙农业科技股份有限公司 | 一种猪舍换气供暖系统 |
CN105374871B (zh) * | 2014-08-22 | 2020-05-19 | 联华电子股份有限公司 | 鳍状结构及其形成方法 |
US9401372B1 (en) * | 2015-02-10 | 2016-07-26 | International Business Machines Corporation | Dual isolation on SSOI wafer |
US10050147B2 (en) * | 2015-07-24 | 2018-08-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9559192B1 (en) * | 2015-11-18 | 2017-01-31 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
-
2015
- 2015-12-30 US US14/984,555 patent/US9786505B2/en active Active
-
2016
- 2016-11-30 TW TW105139534A patent/TWI610352B/zh active
- 2016-12-16 CN CN201611170509.6A patent/CN106952910B/zh active Active
-
2017
- 2017-09-26 US US15/715,762 patent/US10460942B2/en active Active
-
2019
- 2019-10-28 US US16/666,218 patent/US11145510B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201401513A (zh) * | 2012-05-21 | 2014-01-01 | Globalfoundries Us Inc | 形成具有替代通道材料之鰭式場效電晶體設備的方法 |
TW201507158A (zh) * | 2013-03-30 | 2015-02-16 | Intel Corp | 鰭爲基的電晶體架構上的平坦裝置 |
Also Published As
Publication number | Publication date |
---|---|
US10460942B2 (en) | 2019-10-29 |
CN106952910A (zh) | 2017-07-14 |
US20180019128A1 (en) | 2018-01-18 |
CN106952910B (zh) | 2020-12-18 |
US20200066530A1 (en) | 2020-02-27 |
US11145510B2 (en) | 2021-10-12 |
US9786505B2 (en) | 2017-10-10 |
US20170194149A1 (en) | 2017-07-06 |
TW201724217A (zh) | 2017-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI610352B (zh) | 半導體結構與其製造方法 | |
US10998235B2 (en) | FinFET with sloped surface at interface between isolation structures and manufacturing method thereof | |
US10825689B2 (en) | Method of fabricating semiconductor fins by enhancing oxidation of sacrificial mandrels sidewalls through angled ion beam exposure | |
US9425053B2 (en) | Block mask litho on high aspect ratio topography with minimal semiconductor material damage | |
KR102222909B1 (ko) | 반도체 소자의 제조방법 | |
KR102222818B1 (ko) | 반도체 장치의 제조 방법 | |
CN111244175B (zh) | 电路器件及其形成方法 | |
US9613811B2 (en) | Methods of manufacturing semiconductor devices | |
CN109037154B (zh) | 一种半导体器件的制造方法 | |
US11798939B2 (en) | Fin field effect transistor (FinFET) device with protection layer | |
US20160276164A1 (en) | Method for Forming Patterns with Sharp Jogs | |
CN109887845B (zh) | 半导体器件及其形成方法 | |
JP2004356576A (ja) | 半導体装置およびその製造方法 | |
CN107731751B (zh) | 半导体结构及其形成方法 | |
CN107591330B (zh) | 半导体结构的形成方法 | |
CN107731685B (zh) | 半导体结构的形成方法 |