TWI607570B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI607570B
TWI607570B TW105125571A TW105125571A TWI607570B TW I607570 B TWI607570 B TW I607570B TW 105125571 A TW105125571 A TW 105125571A TW 105125571 A TW105125571 A TW 105125571A TW I607570 B TWI607570 B TW I607570B
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Taiwan
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source
gate
drain
forming
semiconductor device
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TW105125571A
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TW201727907A (zh
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賴瑞堯
世海 楊
陳盈燕
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台灣積體電路製造股份有限公司
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    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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Description

半導體裝置及其製造方法
本揭示係有關於半導體技術，且特別是有關於具有局部內連線(local interconnect)連接源極/汲極區的半導體裝置結構及其製造方法。
隨著具有複雜佈局結構之半導體裝置的尺寸縮減，已發展出連接源極/汲極區至另一源極/汲極區的局部內連線。局部內連線係設置於第一金屬配線層(first metal wiring layer)之下的導電層且連接具有相對短距離的元件。在設計標準單元(standard cell)時，局部內連線加強設計靈活性和最小化標準單元的尺寸。為了有更大的設計靈活性和更高的可靠度，需要提供局部內連線之結構和製造過程。
根據本揭示之一方面，半導體裝置包含第一電晶體具有第一閘極、第一源極和第一汲極，第二電晶體具有第二閘極、第二源極和第二汲極，隔離區分隔開第一電晶體與第二電晶體，以及局部內連線連接第一源極和第一汲極中的至少一個到至少第二源極和第二汲極，局部內連線接觸第一源極和第一汲極中的至少一個之表面、第二源極和第二汲極中的至少一個之表面和一部分隔離區之表面。
根據本揭示之另一方面，半導體裝置包含複數個源極/汲極區以第一方向延伸，隔離區分隔開這些源極/汲極區，第一閘極圖案以第一方向延伸，第二閘極圖案以第一方向延伸，第三閘極圖案以第一方向延伸且與第二閘極圖案對齊於第一方向，以及局部內連線。第二閘極圖案之一端面對第三閘極圖案之一端，且有間隔於上述兩者之間。局部內連線接觸該些源極/汲極區之至少一個的表面和隔離區之表面中的至少一個。局部內連線以交叉於第一方向的第二方向延伸且穿過間隔。
根據本揭示之另一方面，在半導體裝置的製造方法中，形成隔離區於基底中。形成第一電晶體結構和第二電晶體結構於基底之上。第一電晶體結構包含第一閘極、第一蓋絕緣層設置於第一閘極之上、第一側壁間隔物設置於第一閘極之側面和第一蓋絕緣層之側面上、第一源極和第一汲極。第二電晶體結構包含第二閘極、第二蓋絕緣層設置於第二閘極之上、第二側壁間隔物設置於第二閘極之側面和第二蓋絕緣層之側面上、第二源極和第二汲極。形成第一絕緣層於第一電晶體結構和第二電晶體結構之間。形成開口於第一絕緣層內，使第一源極和第一汲極中的至少一個之表面、至少第二源極和第二汲極之表面和一部分隔離區之表面露出。以導電材料填充開口，形成局部內連線。
10N、10P‧‧‧鰭結構
15‧‧‧隔離絕緣區
20‧‧‧虛設層
25‧‧‧圖案化虛設閘極電極
30‧‧‧硬遮罩圖案
40‧‧‧毯覆層
45‧‧‧側壁間隔物
50N、50P‧‧‧源極/汲極區
60‧‧‧絕緣層
65‧‧‧開口
70‧‧‧金屬閘極電極
80‧‧‧蓋絕緣層
90‧‧‧局部內連線
95‧‧‧局部金屬層
TR1、TR2、TR3、TR4、TR5、TR6‧‧‧鰭式場效電晶體
ILD1‧‧‧第一層間介電層
ILD2‧‧‧第二層間介電層
V1‧‧‧第一導通孔塞
V2‧‧‧第二導通孔塞
M1‧‧‧第一金屬線
M2‧‧‧第二金屬線
X1-X1、X2-X2、Y1-Y1‧‧‧線段
根據以下的詳細說明並配合所附圖式做完整揭示。應注意的是，根據本產業的一般作業，圖示中的各種特徵 部件並未必按照比例繪製。事實上，可能任意的放大或縮小各種特徵部件的尺寸，以做清楚的說明。
第1A-3A、1B-3B、4A-10A、4B-10B、4C-10C、11A-11D、12圖顯示依據本揭示的一些實施例，說明半導體裝置的連續製造過程之例示性圖示；第13A-13C圖顯示依據本揭示的各方面的半導體裝置之例示性佈局結構。
要瞭解的是本說明書以下的揭示內容提供許多不同的實施例或範例，以實施本揭示的不同特徵部件。而本說明書以下的揭示內容是敘述各個構件及其排列方式的特定範例，以求簡化本揭示的說明。當然，這些特定的範例並非用以限定本揭示。例如，元件之尺寸並未侷限於揭露的範圍或數值，而取決於裝置的製程條件及/或需求性質，此外，若是本說明書以下的揭示內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。為了簡化與清晰的目的，不同的特徵部件可能以不同的尺度大小任意描繪。
再者，為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類 似的用語。除了圖式所繪示的方位之外，空間相關用語涵蓋使用或操作中的裝置的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。此外，用語”由...製成”可表示”包括”或”由..組成”。
第1A和1B-12圖顯示依據本揭示的一些實施例說明半導體裝置的連續製造過程之例示性圖示。為簡化，在這些圖中，一些層/特徵部件被省略，以求簡化。可理解的是，於這些圖中描述的各階段之前、之中及之後，可提供一些附加操作，且以下描述的一些操作可依據方法的附加實施例被代替或消除，操作/過程的順序為可互換的。
第1A和1B圖顯示依據本揭示的一些實施例之半導體裝置的連續製造過程的其中一個階段。第1A圖顯示平面(俯視)圖，而第1B圖顯示沿第1A圖之線段X1-X1的剖面示意圖。
如第1A和1B圖所示，作為主動區的鰭結構10N和10P形成於基底(未繪示)之上，且藉由隔離絕緣區15例如淺溝槽隔離(shallow trench isolation)分隔開。在這個實施例中，鰭結構10N作為n型鰭式場效電晶體(Fin FETs)，而鰭結構10P作為p型鰭式場效電晶體。在其他一些實施例中，鰭結構10N和10P兩者為同樣導電類型的鰭式場效電晶體。
基底是例如具有雜質濃度範圍從大約1×1015cm-3到大約1×1018cm-3的p型矽基底。在其他一些實施例中，基底是具有雜質濃度範圍從大約1×1015cm-3到大約1×1018cm-3的n型矽基底。可替換的是，基底可包括其他元素半導體，例如鍺；化 合物半導體包含IV-IV族的化合物半導體，例如碳化矽(SiC)和矽鍺(SiGe)，III-V族的化合物半導體，例如砷化鎵(GaAs)、磷化鎵(GaP)、氮化鎵(GaN)、磷化銦(InP)、砷化銦(InAs)、銻化銦(InSb)、磷砷化鎵(GaAsP)、氮化鋁鎵(AlGaN)、砷化銦鋁(AlInAs)、鋁鎵砷(AlGaAs)、砷化鎵銦(GaInAs)、磷化鎵銦(GaInP)及/或砷磷化鎵銦(GaInAsP)或前述的組合。在一實施例中，基底是絕緣體覆矽(silicon-on insulator,SOI)基底之矽層。
鰭結構藉由例如溝槽蝕刻(trench-etching)基底形成。
隔離絕緣區15包含一或多層之絕緣材料例如氧化矽、氮氧化矽或氮化矽，且藉由低壓化學氣相沉積(low pressure chemical vapor deposition，LPCVD)、電漿輔助化學氣相沈積(plasma-CVD)或流動式化學氣相沉積(flowable CVD)形成。隔離絕緣層可由一或多層之旋塗式玻璃(spin-on-glass，SOG)、氧化矽(SiO)、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)及/或掺氟矽酸鹽玻璃(fluorine-doped silicate glass，FSG)形成。
形成隔離絕緣區於鰭結構之上後，實施平坦化操作以移除部分之隔離絕緣區。平坦化操作可包含化學機械研磨(chemical mechanical polishing，CMP)及/或回蝕刻製程(etch-back process)。然後更進一步移除(凹入)隔離絕緣區使露出鰭結構的上方區域。
虛設閘極電極的虛設層20和虛設絕緣層(未繪示)形成於鰭結構10N、10P和隔離絕緣區15之上。在第1A圖，省略虛設層20(透明的)。虛設層20例如為多晶矽層由化學氣相沉 積(chemical vapor deposition，CVD)形成，硬遮罩圖案30接著形成於虛設層20之上。在一實施例中，虛設層20的厚度範圍從大約100奈米至大約35奈米，而硬遮罩圖案30的厚度範圍從大約50奈米至大約200奈米。
硬遮罩圖案30包含一或多層之介電材料，一或多層介電材料的毯覆層(blanket layer)形成於虛設層20之上，且實施圖案化操作包含微影製程和乾蝕刻(dry etching)以得到硬遮罩圖案30。在一實施例中，硬遮罩圖案30包含氧化矽層和設置於氧化矽層之上的氮化矽層。在其他一些實施例中，氧化矽層設置於氮化矽層之上。
如第2A和2B圖所示，接著分割一些硬遮罩圖案30成複數個部分，且各自對應至一個虛設閘極圖案。第2A圖顯示平面(俯視)圖，而第2B圖顯示沿第2A圖之X1-X1線段的剖面示意圖。第2A圖中，省略虛設層20(透明的)。
如第3A和3B圖所示，藉由使用分割的硬遮罩圖案30，圖案化虛設層20成虛設閘極電極25。第3A圖顯示平面(俯視)圖，而第3B圖顯示沿第3A圖之X1-X1線段的剖面示意圖。在其他一些實施例中，圖案化虛設層然後分割圖案化的虛設層成複數個部分，然而在這樣的情況，分割圖案化的虛設層可能需要針對高深寛比圖案(high aspect ratio pattern)的蝕刻。
如第4A-4C圖所示，作為側壁間隔物的毯覆層40形成於圖案化的虛設閘極電極25和硬遮罩圖案30之上。第4A圖顯示平面(俯視)圖，第4B圖顯示沿第4A圖之X1-X1線段的剖面示意圖，而第4C圖顯示沿第4A圖之X2-X2線段的剖面示意圖。
毯覆層40包含一或多層之絕緣材料例如二氧化矽(SiO2)、氮化矽(SiN)、氮碳化矽(SiCN)、氮氧化矽(SiON)和氮碳氧化矽(SiOCN)，藉由低壓化學氣相沉積(LPCVD)、電漿輔助化學氣相沈積或原子層沉積(Atomic Layer Deposition，ALD)形成。如第4B和4C圖所示，毯覆層40為順應地(conformally)形成於圖案化的虛設閘極電極25和硬遮罩圖案30、鰭結構和隔離絕緣區15之上。在一實施例中，使用以氮化物為主的絕緣材料作為毯覆層40，且具有厚度範圍從大約5奈米至大約10奈米。
如第5A-5C圖所示，接著實施異向性蝕刻(anisotropic etching)以形成側壁間隔物45於圖案化虛設閘極電極25和硬遮罩圖案30的兩面側壁上。第5A圖顯示平面(俯視)圖，第5B圖顯示沿第5A圖之X1-X1線段的剖面示意圖，而第5C圖顯示沿第5A圖之X2-X2線段的剖面示意圖。
如第6A-6C圖所示，形成側壁間隔物後，形成源極/汲極區50N、50P。第6A圖顯示平面(俯視)圖，第6B圖顯示沿第6A圖之X1-X1線段的剖面示意圖，而第6C圖顯示沿第6A圖之X2-X2線段的剖面示意圖。在本揭示中，源極和汲極可互換使用。
未被虛設閘極電極所覆蓋的鰭結構凹入隔離絕緣區之上方表面的下方，接著源極/汲極區50N、50P藉由使用磊晶成長法形成於凹入的鰭結構之上。這些源極/汲極區可包含應變材料以施加應力於複數個通道區，當鰭結構是矽時，用於n型鰭式場效電晶體之應變材料的例子為碳化矽(SiC)、磷化矽(SiP)或磷碳化矽(SiCP)，且用於p型鰭式場效電晶體為矽鍺 (SiGe)。在其他一些實施例中，這些源極/汲極區藉由離子佈植(ion implantation)形成。矽化物(silicide)層由例如鈦(Ti)、鎳(Ni)、鉭(Ta)、鈷(Co)或鎢(W)形成，可形成於複數個源極/汲極區中。
源極/汲極結構形成後，絕緣層60形成於虛設閘極結構之上，絕緣層60包含一或多層之絕緣材料。在這個實施例中，使用氧化矽或以氧化矽為主的絕緣材料。接著如第7A-7C圖所示，實施平坦化操作例如CMP，以移除絕緣層60的上方部分和於虛設閘極電極25之上的硬遮罩圖案30。第7A圖顯示金屬閘極圖案形成前的平面(俯視)圖，第7B圖顯示沿第7A圖之X1-X1線段的剖面示意圖，而第7C圖顯示沿第7A圖之X2-X2線段的剖面示意圖。在第7A圖中，省略絕緣層60。
在平坦化操作後，移除虛設閘極結構(虛設閘極電極和虛設絕緣層)以製作閘極空隙，接著如第8A-8C圖所示，形成金屬閘極結構包含金屬閘極電極70和閘極介電層(未繪示)例如高介電常數(high-k)介電層於閘極空隙中。第8A圖顯示金屬閘極圖案形成後的平面(俯視)圖，第8B圖顯示沿第8A圖之X1-X1線段的剖面示意圖，而第8C圖顯示沿第8A圖之X2-X2線段的剖面示意圖。在第8A圖中，省略絕緣層60。
金屬閘極電極70包含一或多層之金屬材料例如鋁(Al)、銅(Cu)、鎢(W)、鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、鈦鋁(TiAl)、碳化鈦鋁(TiAlC)、氮化鈦鋁(TiAlN)、氮化鉭(TaN)、矽化鎳(NiSi)、矽化鈷(CoSi)和其他導電材料。金屬閘極電極70可藉由CVD、物理氣相沈積法(Physical Vapor Deposition，PVD)、 ALD或電鍍(electroplating)製成。閘極介電層(未繪示)包含一或多層之金屬氧化物例如高介電常數金屬氧化物，用在高介電常數介電質的金屬氧化物的例子包含鋰(Li)、鈹(Be)、鎂(Mg)、鈣(Ca)、鍶(Sr)、鈧(Sc)、釔(Y)、鋯(Zr)、鉿(Hf)、鋁(Al)、鑭(La)、鈰(Ce)、鐠(Pr)、釹(Nd)、釤(Sm)、銪(Eu)、釓(Gd)、鋱(Tb)、鏑(Dy)、鈥(Ho)、鉺(Er)、銩(Tm)、鐿(Yb)、鎦(Lu)及/或上述的混合物之氧化物。閘極介電層可藉由CVD、PVD或ALD製成。在一些實施例中，插入一或多個功函數調整層(未繪示)於閘極介電層與金屬閘極電極70之間，功函數調整層由導電材料形成例如單層的氮化鈦(TiN)、氮化鉭(TaN)、碳化鉭鋁(TaAlC)、碳化鈦(TiC)、碳化鉭(TaC)、鈷(Co)、鋁(Al)、鈦鋁(TiAl)、鉿鈦(HfTi)、矽化鈦(TiSi)、矽化鉭(TaSi)或碳化鈦鋁(TiAlC)或多層之這些材料中的兩或多個。在n型鰭式場效電晶體中，使用氮化鉭(TaN)、碳化鉭鋁(TaAlC)、氮化鈦(TiN)、碳化鈦(TiC)、鈷(Co)、鈦鋁(TiAl)、鉿鈦(HfTi)、矽化鈦(TiSi)和矽化鉭(TaSi)中的一或多個作為功函數調整層，而在p型鰭式場效電晶體中，使用碳化鈦鋁(TiAlC)、鋁(Al)、鈦鋁(TiAl)、氮化鉭(TaN)、碳化鉭鋁(TaAlC)、氮化鈦(TiN)、碳化鈦(TiC)和鈷(Co)中的一或多個作為功函數調整層。
如第9A-9C圖所示，接著將金屬閘極電極70凹入且形成蓋絕緣層80。第9A圖顯示金屬閘極圖案形成後的平面(俯視)圖，第9B圖顯示沿第9A圖之X1-X1線段的剖面示意圖，而第9C圖顯示沿第9A圖之X2-X2線段的剖面示意圖。在第9A圖中，省略絕緣層60。蓋絕緣層80包含一或多層之絕緣材料例如 二氧化矽(SiO2)、氮化矽(SiN)、氮氧化矽(SiON)、氮碳化矽(SiCN)或氮碳氧化矽(SiOCN)。在這個實施例中，使用氮化矽或以氮化矽為主的材料作為蓋絕緣層80，蓋絕緣層80藉由以CVD沉積絕緣材料之毯覆層和實施平坦化操作(例如CMP)形成。
如第10A-10C圖所示，形成蓋絕緣層80之後，形成開口65於絕緣層60中。第10A圖顯示金屬閘極圖案形成後的平面(俯視)圖，第10B圖顯示沿第10A圖之X1-X1線段的剖面示意圖，而第10C圖顯示沿第10A圖之X2-X2線段的剖面示意圖。在第10A圖中，省略絕緣層60，且開口65的周長以虛線表示。
藉由圖案化絕緣層60，使至少一部分之源極/汲極區50P、50N的表面和一部分隔離區的表面露出於開口65中。
在這個實施例中，側壁間隔物45和蓋絕緣層80由以氮化矽為主的材料(例如氮化矽(SiN))形成，而絕緣層60由以氧化矽為主的材料(例如二氧化矽(SiO2))形成，因此，在絕緣層60之氧化物蝕刻時，源極/汲極區50P、50N以自對齊的方式露出，而未損害金屬閘極電極70。在絕緣層60之氧化物蝕刻時，隔離絕緣區15的上方表面可能被蝕刻。
如第11A-11D圖所示，填充導電材料於開口65中以形成局部內連線90。第11A圖顯示金屬閘極圖案形成後的平面(俯視)圖，第11B圖顯示沿第11A圖之X1-X1線段的剖面示意圖，而第11C圖顯示沿第11A圖之X2-X2線段的剖面示意圖，且第11D圖顯示沿第11A圖之Y1-Y1線段的剖面示意圖。在第11A圖中，省略絕緣層60。
一或多層之金屬材料例如鎢、鈦、鈷和鎳或上述的矽化物或其他合適的材料形成於第10A-10C圖之結構之上，且實施平坦化操作例如CMP，以得到第11A-11D圖之結構。填充金屬材料於開口65，藉此形成局部內連線90連接源極/汲極區50P和源極/汲極區50N。
如第11B-11D圖所示，局部內連線90接觸源極/汲極區50N和50P之上方表面和一部分隔離區15之上方表面。局部內連線90接觸側壁間隔物45和蓋絕緣層80之上方表面，側壁間隔物45的上方表面(頂部分)和局部內連線90的上方表面為彼此大抵上齊平，亦即在相同平面上。在這個揭示中，當特徵部件之高度差異小於最高的特徵部件之10%時，即被認為這些特徵部件為彼此大抵上齊平。在一實施例中，局部內連線90自源極/汲極區之表面的高度範圍從大約60奈米至大約180奈米。
第11A圖顯示六個鰭式場效電晶體TR1、TR2、TR3、TR4、TR5和TR6，局部內連線90連接TR1、TR2、TR3和TR4的源極/汲極區。再者，與局部內連線90同一時間製成的局部金屬層95形成於鰭式場效電晶體TR3和TR5之間的共用源極/汲極區上，這樣的局部金屬層95可降低源極/汲極區的接觸電阻。
第12圖顯示依據本揭示的一實施例之半導體裝置的例示性剖面示意圖。
形成局部內連線90後，第一層間介電層(first interlayer dielectric，ILD)ILD1形成於第11A-11D圖之結構之上。接著實施圖案化操作以形成導通孔洞(via hole)，且以一或 多個導電材料填充導通孔洞以形成第一導通孔塞(via plug)V1。第一金屬線M1亦形成於第一導通孔塞V1之上。第一金屬線M1和第一導通孔塞V1可由雙鑲崁(dual damascene)法形成，一些第一導通孔塞V1連接至局部內連線90。再者，第二層間介電層ILD2形成於第一金屬線M1之上，接著實施圖案化製程以形成導通孔洞，且以一或多個導電材料填充導通孔洞以形成第二導通孔塞V2。第二金屬線M2亦形成於第二導通孔塞V2之上。第二金屬線M2和第二導通孔塞V2可由雙鑲崁(dual damascene)法形成。第一和第二層間介電層包含一或多層之絕緣材料例如基於氧化矽的材料例如二氧化矽(SiO2)和氮氧化矽(SiON)。
第13A-13C圖顯示依據本揭示的各方面之半導體裝置的例示性佈局結構。在標準元件(standard cell)中，可能設置各式不同的局部內連線之排列方式。在一實施例中，於平面圖中，局部內連線90或局部金屬層95沿平行於金屬閘極電極70線性地延伸。在其他一些實施例中，在平面圖中局部內連線具有曲柄把手形狀(crank handle shape)。
第11A、13B和13C圖中，複數個閘極圖案端互相面對且具有間隔於上述閘極圖案之間，且局部內連線穿過間隔。間隔可位於源極/汲極區之上或可位於隔離區之上。
本揭示所敘述的各種實施例或例子對現有技術上提供了一些優點。例如在本揭示中，由於局部內連線(和局部金屬層)以自對齊的方式形成，可避免因製程偏差(process variation)(例如在微影製程操作中的對準誤差)引起的短路。此 外，可提高在設計標準單元中設計的靈活性。
可以理解的是，並不是所有的優點都已於此描述中討論，不需要有特定的優點對應所有的實施例和例子，且其他一些實施例或例子可提供不同的優點。
根據本揭示之一方面，半導體裝置包括第一電晶體具有第一閘極、第一源極和第一汲極，第二電晶體具有第二閘極、第二源極和第二汲極，隔離區分隔開第一電晶體與第二電晶體，以及局部內連線連接第一源極和第一汲極中的至少一個到至少第二源極和第二汲極，局部內連線接觸第一源極和第一汲極中的至少一個之表面、第二源極和第二汲極中的至少一個之表面和一部分隔離區之表面。
根據本揭示之另一方面，半導體裝置包含複數個源極/汲極區以第一方向延伸，隔離區分隔開這些源極/汲極區，第一閘極圖案以第一方向延伸，第二閘極圖案以第一方向延伸，第三閘極圖案以第一方向延伸且與第二閘極圖案對齊於第一方向，以及局部內連線。第二閘極圖案之一端面對第三閘極圖案之一端，且有間隔於上述兩者之間。局部內連線接觸該些源極/汲極區之至少一個的表面和隔離區之表面中的至少一個。局部內連線以交叉於第一方向的第二方向延伸且穿過間隔。
根據本揭示之另一方面，在半導體裝置的製造方法中，形成隔離區於基底中。形成第一電晶體結構和第二電晶體結構於基底之上。第一電晶體結構包含第一閘極、第一蓋絕緣層設置於第一閘極之上、第一側壁間隔物設置於第一閘極之 側面和第一蓋絕緣層之側面上、第一源極和第一汲極。第二電晶體結構包含第二閘極、第二蓋絕緣層設置於第二閘極之上、第二側壁間隔物設置於第二閘極之側面和第二蓋絕緣層之側面上、第二源極和第二汲極。形成第一絕緣層於第一電晶體結構和第二電晶體結構之間。形成開口於第一絕緣層內，使第一源極和第一汲極中的至少一個之表面、至少第二源極和第二汲極之表面和一部分隔離區之表面露出。以導電材料填充開口，形成局部內連線。
以上概略說明了本揭示數個實施例的特徵部件，使所屬技術領域中具有通常知識者對於本揭示的概念可更為容易理解。所屬技術領域中具有通常知識者應瞭解到本說明書可作為其他結構或製程的變更或設計基礎，以實現相同於本揭示實施例的目的及/或獲得相同的優點。所屬技術領域中具有通常知識者也可理解與上述等同的結構或製程並未脫離本揭示之精神及保護範圍內，且可在不脫離本揭示之精神及範圍內，當可作更動、替代與潤飾。
15‧‧‧隔離絕緣區
45‧‧‧側壁間隔物
50N、50P‧‧‧源極/汲極區
80‧‧‧蓋絕緣層
90‧‧‧局部內連線
95‧‧‧局部金屬層
TR1、TR2、TR3、TR4、TR5、TR6‧‧‧鰭式場效電晶體
X1-X1、X2-X2、Y1-Y1‧‧‧對稱軸

Claims (11)

  1. 一種半導體裝置，包括：一第一電晶體，具有一第一閘極、一第一源極和一第一汲極；一第二電晶體，具有一第二閘極、一第二源極和一第二汲極；一隔離區，由一絕緣材料形成且分隔開該第一電晶體與該第二電晶體；以及一局部內連線，連接該第一源極和該第一汲極中的至少一個到至少該第二源極和該第二汲極；其中，該局部內連線接觸該第一源極和該第一汲極中的該至少一個之一表面、該至少該第二源極和該第二汲極之一表面和一部分該隔離區之一表面。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一閘極具有複數個第一側壁間隔物層，且該局部內連線接觸該些第一側壁間隔物層的其中一個。
  3. 如申請專利範圍第2項所述之半導體裝置，其中該局部內連線之一最上部分位於與該些第一側壁間隔物層之一最上部分相同水平，且其中該第一閘極具有一蓋絕緣層，且該局部內連線之該最上部分位於與該蓋絕緣層之一最上部分相同水平。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該局部內連線線性地延伸，且在一平面圖中與至少一個該第一閘極和該第二閘極中的至少一個平行。
  5. 如申請專利範圍第1項所述之半導體裝置，其中該局部內連線具有互相連接的一第一部分與一第二部分，且在一平面圖中該第一部分與該第二部分垂直。
  6. 一種半導體裝置，包括：複數個源極/汲極區，以一第一方向延伸；一隔離區，分隔開該些源極/汲極區；一第一閘極圖案，以該第一方向延伸；一第二閘極圖案，以該第一方向延伸；一第三閘極圖案，以該第一方向延伸，且與該第二閘極圖案對齊於該第一方向；以及一局部內連線；其中，該第二閘極圖案之一端面對該第三閘極圖案之一端，且有一間隔於上述兩者之間；該局部內連線接觸該些源極/汲極區之至少一個的一表面和該隔離區之一表面中的至少一個；且該局部內連線以交叉於該第一方向的一第二方向延伸，且穿過該間隔。
  7. 如申請專利範圍第6項所述之半導體裝置，其中該間隔位於該些源極/汲極區的該至少一個之上或該隔離區之上。
  8. 如申請專利範圍第7項所述之半導體裝置，其中：該些源極/汲極區包含一第一源極/汲極區和一第二源極/汲極區；該第一閘極圖案設置於該第一源極/汲極區和該第二源極/汲極區之上； 該第二閘極圖案設置於該第一源極/汲極區之上；該第三閘極圖案設置於該第二源極/汲極區之上；且該局部內連線接觸該第一源極/汲極區之一表面和該第二源極/汲極區之一表面。
  9. 一種半導體裝置的製造方法，包括：形成一隔離區於一基底中；形成一第一電晶體結構和一第二電晶體結構於該基底之上，該第一電晶體結構包含一第一閘極、一第一蓋絕緣層設置於該第一閘極之上、一第一側壁間隔物設置於該第一閘極之側面和該第一蓋絕緣層之側面上、一第一源極和一第一汲極，該第二電晶體結構包含一第二閘極、一第二蓋絕緣層設置於該第二閘極之上、一第二側壁間隔物設置於該第二閘極之側面和該第二蓋絕緣層之側面上、一第二源極和一第二汲極；形成一第一絕緣層於該第一電晶體結構和該第二電晶體結構之間；形成一開口於該第一絕緣層內，使該第一源極和該第一汲極中的至少一個之一表面、至少該第二源極和該第二汲極之一表面和一部分隔離區之一表面露出；以及以一導電材料填充該開口，形成一局部內連線。
  10. 如申請專利範圍第9項所述之半導體裝置的製造方法，其中形成該第一電晶體結構包含：形成一主動區；形成一虛設閘極圖案於該主動區和該隔離區之上； 形成該第一側壁間隔物；形成該第一源極和該第二源極於該主動區之上；移除該虛設閘極圖案，藉此形成一閘極空隙；形成一金屬材料於該閘極空隙中；以及形成該第一蓋絕緣層於該金屬材料之上。
  11. 如申請專利範圍第10項所述之半導體裝置的製造方法，其中形成該虛設閘極圖案包含：形成一虛設層於該主動區和該隔離區之上；形成一硬遮罩圖案於該虛設層之上；分割該硬遮罩圖案；以及使用該分割的硬遮罩圖案為一蝕刻遮罩圖案化該虛設層，且其中以一導電材料填充該開口包含一平坦化操作，使該局部內連線之一最上部分位於與該第一蓋絕緣層之一最上部分相同水平。
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