TWI581326B - 積體電路中的蝕刻停止層 - Google Patents
積體電路中的蝕刻停止層 Download PDFInfo
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Description
本揭露係關於積體電路中的蝕刻停止層。
在積體電路技藝中,已知通常用於形成互連結構且包含金屬線與通路的方法係「鑲嵌(damascene)」。一般而言,此方法涉及使用光微影蝕刻遮罩與蝕刻技術在介電層形成開口。在形成之後,以銅或銅合金填充開口。而後,經由化學機械拋光(CMP)製程,移除介電層表面上過多的銅。剩餘的銅或銅合金形成金屬通路以及/或金屬線。
鑲嵌製程包含雙鑲嵌製程與單鑲嵌製程。在雙鑲嵌製程中,先形成溝槽與通路開口。通路開口對準傳導特徵,例如在下層中的金屬線。而後,以相同的金屬填充製程填充溝槽與通路開口,以分別形成金屬線與通路。在單鑲嵌製程中,形成金屬線或通路,而非形成二者。
為了在介電層中形成通路開口,進行蝕刻製程以暴露下方的金屬線。可使用蝕刻停止層,以防止過多的過度蝕刻,過多的過度蝕刻會破壞下方的金屬層。蝕刻製程先停在蝕刻停止層上,而後使用不同的氣體/化合物蝕刻穿過蝕刻停止層,因而暴露下方的金屬線。通常使用的蝕刻停止材料包含氮化矽、碳化矽、碳氮化矽、或類似物。
本揭露的一些實施例係提供一種積體電路結構,其包括第一介電層;以及蝕刻停止層,其包括第一子層,其包括在該第一介電層上方的金屬氮化物;以及第二子層,其係位在該第一子層的上方或下方,其中該第二子層包括第一金屬化合物,其包括選自於碳與氧的元素,並且係與該第一子層接觸。
本揭露的一些實施例係提供一種積體電路結構,其包括第一低介電常數介電層;蝕刻停止層,其包括第一子層,其包括金屬碳化物;第二子層,其係位在該第一子層上方,其中該第二子層包括金屬氮化物;以及第三子層,其係位在該第二子層上,其中該第三子層包括金屬化合物,其包括選自於碳與氧的元素;第二低介電常數介電層,其係位在該蝕刻停止層上方;以及通路,其包括在該第二低介電常數介電層中的一部分,其中該通路穿過該蝕刻停止層。
本揭露的一些實施例係提供一種方法,其包括在第一介電層上方,形成蝕刻停止層,其中形成該蝕刻停止層包括在該第一介電層上方,形成金屬氮化物層;以及使用含氧氣體或是含碳氣體,在該金屬氮化物層上,進行處理,其中該金屬氮化物層的頂表面層係被轉換為該蝕刻停止層的第二子層,以及該金屬氮化物層的底層係維持未處理而作為該蝕刻停止層的第一子層;在該蝕刻停止層上方,形成第二介電層;蝕刻該第二介電層,其中該蝕刻停止在該蝕刻停止層上;以及蝕刻穿過該蝕刻停止層。
100‧‧‧晶圓
20‧‧‧半導體基板
22‧‧‧積體電路裝置
24‧‧‧層間介電(ILD)
26‧‧‧蝕刻停止層
28‧‧‧接點插塞
30‧‧‧IMD層
32‧‧‧傳導金屬線
34‧‧‧擴散阻障層
36‧‧‧含銅材料
38‧‧‧金屬覆蓋層
40、40a、40b、40c‧‧‧蝕刻停止層
42‧‧‧IMD層
44‧‧‧通路開口
46‧‧‧溝槽
48‧‧‧傳導通路
50‧‧‧傳導線
52‧‧‧襯墊
54‧‧‧金屬覆蓋層
56‧‧‧蝕刻停止層
由以下詳細說明與附隨圖式得以最佳了解本揭露之各方面。注意,根據產業之標準實施方式,各種特徵並非依比例繪示。實際上,為了清楚討論,可任意增大或縮小各種特徵的尺寸。
圖1至12係根據一些實施例說明形成互連結構之中間
階段的剖面圖。
圖13係根據一些實施例說明互連結構的剖面圖,其中金屬碳化物層與上方金屬氮化物層組合形成蝕刻停止層。
圖14係根據一些實施例說明互連結構的剖面圖,其中金屬氮化物層與上方的金屬碳化物層或是金屬氧化物層組合形成蝕刻停止層。
圖15係根據一些實施例說明形成互連結構的製程流程。
以下揭示內容提供許多不同的實施例或範例,用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下,以簡化本申請案之揭示內容。當然,這些僅為範例,並非用於限制本申請案。例如,以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施例,亦可包含在該第一與第二特徵之間形成其他特徵的實施例,因而該第一與第二特徵並非直接接觸。此外,本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的,而非支配不同實施例與/或所討論架構之間的關係。
再者,本申請案可使用空間對應語詞,例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明,以描述圖式中一元件或特徵與另一元件或特徵的關係。空間對應語詞係用以包括除了圖式中描述的位向之外,裝置於使用或操作中之不同位向。裝置或可被定位(旋轉90度或是其他位向),並且可相應解釋本申請案使用的空間對應描述。
不同的例示實施例提供積體電路的互連結構及其形成方法。說明形成互連結構的中間階段。討論實施例的變化。在不同的
圖式與說明實施例中,相同的元件符號係用以代表相同的元件。
圖1至12係根據一些實施例說明形成互連結構之中間
階段的剖面圖。圖1至12所示之步驟亦說明於圖15所示之製程流程200中。在後續的討論中,圖1至12所示製程步驟之討論亦可參閱圖15的製程步驟。
圖1說明晶圓100,其包含半導體基板20以及在半導體
基板20的頂部表面上所形成的特徵。根據本揭露的一些實施例,半導體基板20係由結晶半導體材料所形成,例如矽、鍺、矽鍺、III-V族化合物半導體,例如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP以及/或類似物。半導體基板20可為大塊矽基板或是絕緣體上矽(SOI)基板。
根據本揭露的一些實施例,晶圓100係用以形成裝置
晶粒。在這些實施例中,在半導體基板20的頂部表面形成積體電路裝置22。例如,積體電路裝置22可包含互補金屬氧化物半導體(CMOS)電晶體、電阻器、電容器、二極體、以及類似物。本文未說明積體電路22的詳細內容。在其他實施例中,晶圓100係用於形成插入物。在這些實施例中,基板20的表面未形成主動裝置,例如電晶體與二極體。在晶圓100中,可形成(或未形成)被動裝置,例如電容器、電阻器、電感、或類似物。在晶圓100為插入物晶圓的實施例中,基板20亦可為介電質基板。再者,可形成貫穿通路(未繪示)貫穿基板20,以互連基板20之對側上的組件。
層間介電(ILD)24形成在半導體基板20上方,並且填
充積體電路裝置22中電晶體(未繪示)的閘極堆疊之間的空間。在一些實施例中,ILD 24包括磷矽酸鹽玻璃(PSG)、硼矽酸鹽(BSG)、硼摻雜的磷矽酸鹽玻璃(BPSG)、氟摻雜的矽酸鹽玻璃(FSG)、四乙基矽氧烷(TEOS)、或類似物。可使用旋塗、可流動化學氣相沉積(FCVD)、或
類似方法形成ILD 24。根據本揭露的其他實施例,使用沉積方法,例如電漿促進化學氣相沉積(PECVD)、低壓化學氣相沉積(LPCVD)、類似方法,形成ILD 24。
在ILD 24中形成接點插塞28,並且用於電連接至積體
電路裝置22。例如,接點插塞28可包含閘極接點插塞,其連接至積體電路裝置22中之電晶體的閘極電極,以及源極/汲極接點插塞,其電連接至電晶體的源極/汲極區。根據本揭露的一些實施例,接點插塞28的形成材料係選擇自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金、以及/或其多層。接點插塞28的形成可包含蝕刻ILD 24以形成接點開口,將傳導材料填充至接點開口中直到接點開口全部填充傳導材料,以及進行平坦化(例如化學機械拋光(CMP)),使得接點插塞28的頂部表面與ILD 24的頂部表面齊平。
參閱圖2,若需要,可在ILD 24與積體電路裝置22上
方,形成蝕刻停止層26。蝕刻停止層26可包括金屬氮化物、金屬碳化物、金屬氧化物、以及/或類似物,其中金屬可包含鋁(Al)、錳(Mn)、銅(Cu)、或其多層。蝕刻停止層26亦可具有類似於後續所形成的蝕刻停止層40(例如圖6、13與14所示)之結構。根據其他實施例,蝕刻停止層26包含碳化矽、氮化矽、氮氧化矽、碳氮化矽、或類似物。形成蝕刻停止層26的材料對於上方介電層30具有高蝕刻選擇性,因而蝕刻停止層26可用於停止介電層30的蝕刻。
圖2進一步說明介電層30,其亦稱為金屬間介電
(IMD)層30。根據本揭露的一些實施例,IMD層30係由低介電常數介電材料形成,其介電常數(k值)低於約3.0、約2.5、或甚至更低。IMD層30可包括Black Diamond(Applied Materials的註冊商標)、含碳的低介電常數之介電材料、Hydrogen SilsesQuioxane(HSQ)、MethylSilsesQuioxane(MSQ)、或類似物。
在IMD層30中形成傳導金屬線32。個別步驟亦如圖15
之製程流程200的步驟202所示。根據一些實施例,金屬線32包含擴散阻障層34以及在擴散阻障層34上方的含銅材料36。擴散阻障層34可包含鈦、氮化鈦、鉭、氮化鉭、或類似物,並且具有防止含銅材料36中的銅擴散至IMD層30的功能。在下文中,傳導線32係指金屬線32。圖2說明金屬線係在底部金屬層中,其係位於接點插塞28正上方的金屬層。所述之金屬線32亦代表位於底部金屬層上方之任何金屬層中的金屬線。
根據本揭露的一些實施例,如圖3所示,在金屬線32
上方,形成金屬覆蓋層38。個別步驟亦如圖15之製程流程200的步驟204所示。根據本揭露的一些實施例,金屬覆蓋層38包含鈷(Co)、鎢(W)、鉭(Ta)、鎳(Ni)、鉬(Mo)、錳(Mn)、鈦(Ti)、鐵(Fe)、CoWP、CoB、或其組合。可選擇性使用無電鍍形成金屬覆蓋層38,晶圓100係浸入鍍溶液中。在其他實施例中,例如,使用物理氣相沉積(PVD)、接著光微影蝕刻製程以蝕刻所不要的部分,在金屬線32與IMD層30上形成金屬覆蓋層38毯狀物。
接著,如圖4至6所示,形成蝕刻停止層40。根據本揭
露的一些實施例,蝕刻停止層40包含由金屬化合物所形成之二或多個子層,在下文中,各子層亦指蝕刻停止層。
參閱圖4,形成蝕刻停止層40a(其係圖6所示之蝕刻停止層40的子層)。個別步驟亦如圖15之製程流程200的步驟206所示。根據本揭露的一些實施例,蝕刻停止層40a包含金屬碳化物。蝕刻停止層40a中的金屬可包含Al、Cu、Mn、或其組合。據此,蝕刻停止層40a可包含碳化鋁、碳化銅、碳化錳、或其組合。在一些例示實施例中,蝕刻停止層40a無氮、或是實質無氮(例如,原子百分比小於約百分之一)。在其他實施例中,蝕刻停止層40a進一步包括氮,因而可包
含金屬碳氮化合物。金屬碳氮化合物中的氮可為低,例如原子百分比低於約百分之十或示低於約百分之五。再者,蝕刻停止層40a係無氧。
蝕刻停止層40a的形成方法包含但不限於CVD以及原
子層沉積(ALD)。蝕刻停止層40a的厚度T1係小於約20Å,並且可為約5Å至20Å之間。蝕刻停止層40a的底表面係與IMD層30以及金屬覆蓋層38的頂表面接觸。蝕刻停止層40a對於IMD層30以及金屬覆蓋層38具有良好的黏附性。
接著,如圖5所示,形成蝕刻停止層40b(其亦為圖6所
示之蝕刻停止層40的子層)。個別步驟亦如圖15之製程流程200的步驟208所示。根據本揭露的一些實施例,蝕刻停止層40b包含金屬氮化物。蝕刻停止層40b中的金屬可包含Al、Cu、Mn、或其組合。據此,蝕刻停止層40b可包含氮化鋁、氮化銅、氮化錳、或其組合。蝕刻停止層40b中的金屬可與蝕刻停止層40a中的金屬相同。蝕刻停止層40a與40b中具有相同金屬可有利地改良蝕刻停止層40a與40b之間的黏附性、使得形成製程更容易、並且減少蝕刻停止層40a與40b之間所不欲知交互作用。根據其他實施例,蝕刻停止層40b中的金屬係不同於蝕刻停止層40a中的金屬。根據一些例示實施例,蝕刻停止層40b中金屬與氮的原子百分比可為約百分之二十至約百分之八十之間。例如,根據一些例示實施例,蝕刻停止層40b可包含Al2N3。
當沉積時,蝕刻停止層可無碳與氧,或實質無氮與氧,例如(若有)碳與氧各自的原子百分比係低於約百分之一。
形成蝕刻停止層40b的形成方法包含但不限於CVD與ALD。蝕刻停止層40b的厚度T2係小於約70Å,並且可為約5Å至約70Å之間。蝕刻停止層40b的底表面可與蝕刻停止層40a接觸。
接著,如圖6所示,形成蝕刻停止層40c。個別步驟亦
如圖15之製程流程200的步驟210所示。根據本揭露的一些實施例,在蝕刻停止層40b上進行處理,形成蝕刻停止層40c,因而蝕刻停止層40b的頂部表面層被轉換為蝕刻停止層40c。另一方面,蝕刻停止層40b的底部並未轉換,因而保留為金屬氮化物層。可使用含碳製程氣體進行處理,例如使用CHx(x為例如1、2、4或4的整數)、CO2或類似物。例如,在處理期間,可加熱晶圓100至溫度為約200℃至約400℃。處理期間可為約5秒至約30秒。可用電漿進行處理。或者,可不用電漿進行處理。
在含碳製程氣體中處理蝕刻停止層40b使得蝕刻停止
層40c包括金屬碳氮化合物。取決於蝕刻停止層40b中的金屬,金屬碳氮化合物可為碳氮化鋁、碳氮化銅、碳氮化錳、或其組合。在這些實施例中,蝕刻停止層40c中的金屬係與蝕刻停止層40b中的金屬相同形式。同樣地,蝕刻停止層40a中金屬原子百分比與氮原子百分比之比例係等於40b中金屬原子百分比與氮原子百分比之比例。根據一些實施例,蝕刻停止層40c的厚度T3可小於約20Å,並且可為約5Å至約20Å。再者,由於蝕刻停止層40b的頂層係轉換為蝕刻停止層40c,因而蝕刻停止層40b的厚度係由T2(圖5)減少至T4。T4的厚度範圍可為約5Å至約50Å。再者,實驗結果顯示當金屬氮化物層40b的厚度約10Å或較小時(約5Å),其仍能可靠地作為蝕刻停止層,停止上方低介電常數介電層的蝕刻。據此,厚度T4可為約5Å至約20Å(並且可小於約10Å),因而其可進行停止蝕刻的功能,同時其厚度仍夠小,而不在所得互連結構中造成顯著的寄生電容。
根據本揭露的其他實施例,經由沉積形成蝕刻停止層
40c,例如使用CVD或ALD。據此,蝕刻停止層40c可包括金屬碳化物,並且可無氮、或實質無氮(例如氮原子百分比係小於約百分之一)。或者,蝕刻停止層40c可沉積為金屬碳氮化物。在這些實施例
中,蝕刻停止層40c中的金屬可與蝕刻停止層40b中的金屬相同或不同,以及厚度T4可小於約50Å、小於約10Å或在約5Å至約20Å之間。
根據本揭露的其他實施例,使用含氧製程氣體,例如
O2,在蝕刻停止層40b上進行處理,形成蝕刻停止層40c。在處理過程中,例如,可加熱晶圓100至溫度約200℃至約400℃的範圍之間。處理期間可為約5秒至約60秒之間。可用電漿進行處理。或是,不用電漿進行處理。
在含氧製程氣體中處理蝕刻停止層40b,使得所得到
的蝕刻停止層40c包括金屬氧氮化物。取決於蝕刻停止層40b中的金屬,金屬氧氮化物可為氧氮化鋁、氧氮化銅、氧氮化錳、或其組合。
在這些實施例中,蝕刻停止層40c中的金屬係與蝕刻停止層40b中的金屬相同。注意,由於金屬氧氮化物中的氧可降低金屬覆蓋層38防止電遷移的能力,因而金屬氧氮化物並非用於形成蝕刻停止層40a。在使用含氧製程氣體處理的過程中,蝕刻停止層40b的底層並未被轉換為金屬氧氮化物,並且保持為金屬氮化物層。在這些實施例中,厚度T1、T3與T4可與蝕刻停止層40c包括碳而非氧的實施例之厚度相似。
在本揭露內容中,蝕刻停止層40a、40b與40c的組合
係指蝕刻停止層40。蝕刻停止層40b(在形成蝕刻停止層40c之後)可無碳與氧,或是實質無碳與氧。例如,(若有)碳與氧各自的原子百分比係低於約百分之一。此外,蝕刻停止層40b的組成係不同於蝕刻停止層40a與40c之各自的組成,其中蝕刻停止層40b包含的元素係不同於蝕刻停止層40a與40c的元素,以及/或蝕刻停止層40b的原子百分比係不同於蝕刻停止層40a與40c中對應元素的原子百分比。
參閱圖7,在蝕刻停止層40上方,形成IMD層42。個
別步驟亦如圖15之製程流程200的步驟212所示。根據一些實施例,形
成IMD層的材料係選自於與形成IMD層30的候選材料相同。例如,IMD層42可由含碳的介電材料、Black Diamond、MSQ或類似物所形成。IMD層42亦可具有低介電常數值,其可低於約3.0、2.5或2.0。根據本揭露的一些實施例,IMD層42的行程包含沉積含有成孔劑(porogen)的介電材料,而後進行硬化製程以驅趕成孔劑,因而剩餘的IMD層42為多孔的。
參閱圖8,在IMD層42中,形成溝槽46與通路開口
44。個別步驟亦如圖15之製程流程200的步驟214所示。根據本揭露的一些實施例,形成製程包含進行光微影蝕刻製程,蝕刻IMD層42,以形成初始通路開口,其中初始通路開口從IMD層42的頂表面延伸至IMD層42的頂表面與底表面之間的中間階層。接著,形成且圖案化硬遮罩(未繪示),以定義溝槽46的圖案。而後,進行非等向性蝕刻以蝕刻IMD層42,以形成溝槽46。在形成溝槽46的同時,通路開口向下延伸至蝕刻停止層40,形成通路開口44,如圖8所示。可使用時間模式,進行形成溝槽46的蝕刻步驟,並且在蝕刻已經進行一段預設時間之後停止。然而,亦考量其他的蝕刻與停止點偵測技術。在其他實施例中,以個別的微影蝕刻製程形成通路開口44與溝槽46。例如,在第一光微影蝕刻製程中,形成通路開口44向下延伸至蝕刻停止層40。在第二光微影蝕刻製程中,形成溝槽46延伸至IMD層42的中間階層。而後,蝕刻蝕刻停止層40以暴露下方的金屬覆蓋層38。
根據本揭露的一些實施例,使用包含氟與碳的製程氣
體,進行IMD層42的蝕刻,其中氟係用於蝕刻,而碳形成聚合物保護所得之通路開口44與溝槽46的側壁。藉由適當的氟與碳比例,通路開口44與溝槽46可具有所欲之輪廓。例如,用於蝕刻的製程氣體具有例如C4F8與/或CF4之含氟與碳之氣體,以及例如N2之載體氣體。在其他實施例中,用於蝕刻的製程氣體包含CH2F2,以及例如N2之載體氣
體。
蝕刻的進行係使用蝕刻停止層40用以停止蝕刻。根據一些實施例,通路開口44穿過蝕刻停止層40c並且停止在蝕刻停止層40b上。蝕刻停止層40中的金屬氮化物係用於停止IMD層42的蝕刻。據此,雖然蝕刻停止層40b非常薄,有時厚度為數埃至數十埃,其仍有效地停止蝕刻。
圖9係說明蝕刻停止層40b與40a。在蝕刻IMD層42之後,將製程氣體改變為用於蝕刻穿過蝕刻停止層40b與蝕刻停止層40a的製程氣體,因而金屬覆蓋層38係暴露至所得到的通路開口44。
圖10係說明在通路開口44中形成傳導通路48(圖9)與在溝槽46中形成傳導線50。個別步驟亦如圖15之製程流程200的步驟216所示。通路48與傳導線50可包含襯墊52,例如擴散阻障層、黏著層或類似物。襯墊52可包含鈦、氮化鈦、鉭、氮化鉭、或其他。在襯墊52上方之傳導線50的內部材料係傳導材料,例如銅、銅合金、鎳、金、鎢、鋁、或類似物。在一些實施例中,通路48與傳導線50的形成包含進行毯沉積以形成襯墊52,沉積銅或銅合金的薄晶種層,以及經由電鍍、無電鍍、沉積或類似方法,填充剩餘的通路開口44與溝槽46。進行CMP,使得傳導線50與/或襯墊52的表面齊平,並且從IMD層42的表面移除過多材料。
圖11係說明在傳導線50上方形成金屬覆蓋層54。形成金屬覆蓋層54的材料可與形成金屬覆蓋層38的候選材料相同。再者,可使用與形成金屬覆蓋層38的相同方法,形成金屬覆蓋層54。
在後續步驟中,如圖12所示,在金屬覆蓋層54與IMD層42上方,形成蝕刻停止層56。蝕刻停止層56的結構、材料與形成方法係類似於蝕刻停止層40之結構、材料與形成方法,因而不再重複說明。而後,可繼續製程,形成更多的特徵,例如IMD層、金屬線、通
路、以及類似物、或圖12中的結構。
圖13與14係根據其他實施例說明包含互連結構的晶圓
100。除非特別說明,否則這些實施例中的組件之材料與形成方法係本質上與類似組件相同,其在圖1至12所示的實施例中具有相同的元件符號。因此,圖13與14所示之組件的形成製程與材料之相關細節係如圖1至12所示之實施例的討論中所述。
圖13所示的結構係類似於圖11所示之結構,除了蝕刻
停止層40c(圖12)並未形成在這些實施例中。形成蝕刻停止層40a與40b。蝕刻停止層40a係與下方的金屬覆蓋層38以及IMD層30接觸。蝕刻停止層40b係與上方的IMD層42以及通路48接觸。
圖14所示之結構亦類似於圖11所示之結構,除了蝕刻
停止層40a(圖12)並未形成在這些實施例中。形成蝕刻停止層40b與40c。蝕刻停止層40b係與下方的金屬覆蓋層38以及IMD層30接觸。蝕刻停止層40c係與上方的IMD層42以及通路48接觸。
本揭露的實施例具有一些有利的特徵。一些金屬氮化
物可為良好的蝕刻停止層,其可有效停止上方IMD層的蝕刻。據此,當作為蝕刻停止層時,這些金屬氮化物可形成非常薄,而不會犧牲其停止蝕刻的能力。由於金屬氮化物形成的蝕刻停止層非常薄,因而可顯著降低蝕刻停止層所造成的寄生電容。這對於使用16nm技術或以下之小規模積體電路而言是有利的,其中蝕刻停止層所造成的寄生電容是不可忽略的。然而,金屬氮化物對於低介電常數介電材料可能具有不良的黏附性,因而可造成問題,例如當作為蝕刻停止層時會發生脫層。由於金屬碳氮化物、金屬氮化物、或金屬氧氮化物對於金屬氮化物與低介電常數介電層具有良好的黏附性,因而藉由在金屬氮化物層上方與/或下方形成金屬碳氮化合物、金屬氮化物、或金屬氧氮化物,解決黏附性問題。多層蝕刻停止層的整體厚度仍小,因而所造成
的寄生電容仍小。相較之下,為了有效停止蝕刻,由氮化矽、碳化矽、碳氮化矽以及類似物所形成之習知的蝕刻停止層典型厚度係大於100Å。因此,相對應的寄生電容很高。
根據本揭露的一些實施例,積體電路結構包含介電層
與蝕刻停止層。蝕刻停止層包含第一子層,其包含在第一介電層上方金屬氮化物的,以及在第一子層上方或下方的第二子層。第二子層係包含金屬化合物,其包括選自於碳與氧的元素,並且接觸第一子層。
根據本揭露的其他實施例,積體電路結構包含第一低
介電常數介電層與蝕刻停止層。蝕刻停止層包含第一子層,其包括金屬碳化物,位在第一子層上方的第二子層,其中第二子層包括金屬氮化物,以及位在第二子層上方的第三子層,其中第三子層包括金屬化合物,其包括選自於碳與氧的元素。第二低介電常數介電層係位於蝕刻停止層上方。通路包含位於第二低介電常數介電層中的一部分,其中通路穿過蝕刻停止層。
根據本揭露的其他實施例,方法包含在第一介電層上
方形成蝕刻停止層,其包含在第一介電層上方形成金屬氮化物層,以及使用含氧氣體或含碳氣體在金屬氮化物層上進行處理。金屬氮化物層的頂部表面係轉換為蝕刻停止層的第二子層,以及金屬氮化物層的底層保持為未處理,以作為蝕刻停止層的第一子層。方法進一步包含在蝕刻停止層上方形成第二介電層,並且蝕刻第二介電層,其中蝕刻停止於蝕刻停止層上,以及蝕刻穿過蝕刻停止層。
前述內容概述一些實施方式的特徵,因而熟知此技藝
之人士可更加理解本揭露之各方面。熟知此技藝之人士應理解可輕易使用本揭露作為基礎,用於設計或修飾其他製程與結構而實現與本申請案所述之實施方式具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本揭露的精神與範圍,以及熟知
此技藝之人士可進行各種變化、取代與替換,而不脫離本揭露之精神與範圍。
100‧‧‧晶圓
20‧‧‧半導體基板
22‧‧‧積體電路裝置
24‧‧‧層間介電(ILD)
26‧‧‧蝕刻停止層
28‧‧‧接點插塞
30‧‧‧IMD層
32‧‧‧傳導金屬線
34‧‧‧擴散阻障層
36‧‧‧含銅材料
38‧‧‧金屬覆蓋層
40、40a、40b‧‧‧蝕刻停止層
42‧‧‧IMD層
48‧‧‧傳導通路
50‧‧‧傳導線
52‧‧‧襯墊
54‧‧‧金屬覆蓋層
56‧‧‧蝕刻停止層
Claims (10)
- 一種積體電路結構,其包括:第一介電層;以及蝕刻停止層,其包括:第一子層,其包括在該第一介電層上方的金屬氮化物;以及第二子層,其係位在該第一子層的上方或下方,其中該第二子層包括第一金屬化合物,其包括選自於碳與氧的元素,並且係與該第一子層接觸。
- 如請求項1所述之積體電路結構,其中該第二子層係在該第一子層下方,以及該第二子層係包括碳且實質無氧。
- 如請求項1所述之積體電路結構,其中該第二子層係在該第一子層上方,包括碳或氧。
- 如請求項3所述之積體電路結構,進一步包括位在該第一子層下方的第三子層,其中該第三子層包括金屬碳化物。
- 如請求項1所述之積體電路結構,進一步包括:第一傳導線,其係位在該第一介電層中;金屬覆蓋層,其係位在該第一傳導線上方,該蝕刻停止層係位在該金屬覆蓋層與該第一介電層上方並且接觸該金屬覆蓋層與該第一介電層;第二介電層,其係位在該蝕刻停止層上方;以及通路,其包括在該第二介電層中的一部分,其中該通路進一步穿過該蝕刻停止層以電耦合至該金屬覆蓋層。
- 一種積體電路結構,其包括:第一低介電常數介電層; 蝕刻停止層,其包括:第一子層,其包括金屬碳化物;第二子層,其係位在該第一子層上方,其中該第二子層包括金屬氮化物;以及第三子層,其係位在該第二子層上,其中該第三子層包括金屬化合物,其包括選自於碳與氧的元素;第二低介電常數介電層,其係位在該蝕刻停止層上方;以及通路,其包括在該第二低介電常數介電層中的一部分,其中該通路穿過該蝕刻停止層。
- 如請求項6所述之積體電路結構,其中該第三子層包括金屬碳化物。
- 一種積體電路結構的製造方法,其包括:在第一介電層上方,形成蝕刻停止層,其中形成該蝕刻停止層包括:在該第一介電層上方,形成金屬氮化物層;以及使用含氧氣體或是含碳氣體,在該金屬氮化物層上,進行處理,其中該金屬氮化物層的頂表面層係被轉換為該蝕刻停止層的第二子層,以及該金屬氮化物層的底層係維持未處理而作為該蝕刻停止層的第一子層;在該蝕刻停止層上方,形成第二介電層;蝕刻該第二介電層,其中該蝕刻停止在該蝕刻停止層上;以及蝕刻穿過該蝕刻停止層。
- 如請求項8所述之方法,其中形成該蝕刻停止層進一步包括:在形成該金屬氮化物層之前,在該第一介電層上方形成該蝕刻停止層之第三子層且與該第一介電層接觸,該金屬氮化物層係在該第三子層上方並且接觸該第三子層,其中該第三子層包括金屬 碳化物。
- 如請求項9所述之方法,其中該第三子層與該金屬氮化物層係包括相同的金屬。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11018052B2 (en) | 2019-06-27 | 2021-05-25 | Yangtze Memory Technologies Co., Ltd. | Interconnect structure and method of forming the same |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9437484B2 (en) | 2014-10-17 | 2016-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch stop layer in integrated circuits |
US9627215B1 (en) * | 2015-09-25 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for interconnection |
US9659864B2 (en) * | 2015-10-20 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer |
US9837306B2 (en) | 2015-12-21 | 2017-12-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure and manufacturing method thereof |
CN105702586B (zh) * | 2016-04-28 | 2019-06-07 | 京东方科技集团股份有限公司 | 一种薄膜晶体管、阵列基板、其制作方法及显示装置 |
US10685873B2 (en) | 2016-06-29 | 2020-06-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch stop layer for semiconductor devices |
US10358719B2 (en) * | 2016-11-23 | 2019-07-23 | Applied Materials, Inc. | Selective deposition of aluminum oxide on metal surfaces |
US10276505B2 (en) | 2017-03-08 | 2019-04-30 | Samsung Electronics Co., Ltd. | Integrated circuit device and method of manufacturing the same |
KR102248788B1 (ko) * | 2017-03-08 | 2021-05-06 | 삼성전자 주식회사 | 집적회로 소자 및 그 제조 방법 |
KR102217242B1 (ko) * | 2017-03-08 | 2021-02-18 | 삼성전자주식회사 | 집적회로 소자 및 그 제조 방법 |
CN108573949B (zh) * | 2017-03-08 | 2022-04-05 | 三星电子株式会社 | 集成电路器件及其制造方法 |
US10707165B2 (en) * | 2017-04-20 | 2020-07-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having an extra low-k dielectric layer and method of forming the same |
US10707123B2 (en) | 2017-04-28 | 2020-07-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch profile control of interconnect structures |
KR102356754B1 (ko) | 2017-08-02 | 2022-01-27 | 삼성전자주식회사 | 반도체 장치 |
US10714421B2 (en) * | 2017-08-29 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device with self-aligned conductive features |
CN109545735B (zh) * | 2017-09-22 | 2022-01-28 | 蓝枪半导体有限责任公司 | 金属内连线结构及其制作方法 |
US10727178B2 (en) | 2017-11-14 | 2020-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via structure and methods thereof |
KR102451171B1 (ko) | 2018-01-25 | 2022-10-06 | 삼성전자주식회사 | 반도체 소자 |
US10468297B1 (en) * | 2018-04-27 | 2019-11-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal-based etch-stop layer |
US11315828B2 (en) * | 2018-08-15 | 2022-04-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal oxide composite as etch stop layer |
KR102580659B1 (ko) * | 2018-10-01 | 2023-09-20 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US11322397B2 (en) * | 2018-10-30 | 2022-05-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor devices including formation of adhesion enhancement layer |
US10930551B2 (en) * | 2019-06-28 | 2021-02-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for fabricating a low-resistance interconnect |
KR20210003328A (ko) | 2019-07-01 | 2021-01-12 | 삼성전자주식회사 | 반도체 소자 |
US11335592B2 (en) * | 2019-09-17 | 2022-05-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact resistance between via and conductive line |
US11227792B2 (en) * | 2019-09-19 | 2022-01-18 | International Business Machines Corporation | Interconnect structures including self aligned vias |
US11282742B2 (en) * | 2019-10-17 | 2022-03-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with multi-layer etch stop structure and method for forming the same |
US11854878B2 (en) * | 2019-12-27 | 2023-12-26 | Taiwan Semiconductor Manufacturing Ltd. | Bi-layer alloy liner for interconnect metallization and methods of forming the same |
US11532548B2 (en) * | 2020-02-19 | 2022-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nitrogen plasma treatment for improving interface between etch stop layer and copper interconnect |
DE102020128037A1 (de) * | 2020-02-19 | 2021-08-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Stickstoffplasmabehandlung zur verbesserung der grenzfläche zwischen einer ätzstoppschicht und einem kupfer-interconnect |
US11615983B2 (en) * | 2020-04-22 | 2023-03-28 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor structure and method for forming the same |
KR20210137276A (ko) * | 2020-05-07 | 2021-11-17 | 삼성전자주식회사 | 반도체 소자 |
CN114068612A (zh) * | 2020-08-05 | 2022-02-18 | 联华电子股份有限公司 | 磁阻式随机存取存储器结构及其制作方法 |
US11749732B2 (en) * | 2020-09-29 | 2023-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch profile control of via opening |
US11942371B2 (en) * | 2020-09-29 | 2024-03-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch profile control of via opening |
CN114512597A (zh) * | 2020-11-16 | 2022-05-17 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
US11854963B2 (en) * | 2021-03-03 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor interconnection structure and methods of forming the same |
KR20220132139A (ko) * | 2021-03-23 | 2022-09-30 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
US11776895B2 (en) * | 2021-05-06 | 2023-10-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method for manufacturing the same |
CN115621191A (zh) * | 2021-07-12 | 2023-01-17 | 长鑫存储技术有限公司 | 一种半导体结构的形成方法 |
US12063790B2 (en) | 2021-08-30 | 2024-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for MRAM devices |
US20230215806A1 (en) * | 2021-12-31 | 2023-07-06 | International Business Machines Corporation | Reducing copper line resistance |
JP2023135467A (ja) * | 2022-03-15 | 2023-09-28 | キオクシア株式会社 | テンプレートおよび半導体装置の製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200737285A (en) * | 2006-03-21 | 2007-10-01 | Taiwan Semiconductor Mfg Co Ltd | Method for forming a 3D interconnect and resulting structure |
TW201250044A (en) * | 2011-03-23 | 2012-12-16 | Hitachi Int Electric Inc | Method of manufacturing semiconductor device, substrate processing method and substrate processing apparatus |
TW201403710A (zh) * | 2012-03-09 | 2014-01-16 | Hitachi Int Electric Inc | 製造半導體裝置之方法、處理基板之方法、基板處理設備及非暫時性電腦可讀取記錄媒體 |
TW201436037A (zh) * | 2013-03-11 | 2014-09-16 | Taiwan Semiconductor Mfg | 半導體元件及其製造方法 |
Family Cites Families (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1055788C (zh) * | 1997-03-14 | 2000-08-23 | 联华电子股份有限公司 | 在半导体器件内制作内连线的方法 |
US6140226A (en) * | 1998-01-16 | 2000-10-31 | International Business Machines Corporation | Dual damascene processing for semiconductor chip interconnects |
US6054379A (en) * | 1998-02-11 | 2000-04-25 | Applied Materials, Inc. | Method of depositing a low k dielectric with organo silane |
US6235603B1 (en) * | 1999-07-12 | 2001-05-22 | Motorola Inc. | Method for forming a semiconductor device using an etch stop layer |
US6335283B1 (en) * | 2000-01-05 | 2002-01-01 | Advanced Micro Devices, Inc. | Method of reducing in-line copper diffusion |
JP4377040B2 (ja) * | 2000-07-24 | 2009-12-02 | Necエレクトロニクス株式会社 | 半導体の製造方法 |
US6734116B2 (en) * | 2002-01-11 | 2004-05-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Damascene method employing multi-layer etch stop layer |
US6828245B2 (en) * | 2002-03-02 | 2004-12-07 | Taiwan Semiconductor Manufacturing Co. Ltd | Method of improving an etching profile in dual damascene etching |
US6730445B2 (en) | 2002-04-12 | 2004-05-04 | International Business Machines Corporation | Attenuated embedded phase shift photomask blanks |
US7132369B2 (en) * | 2002-12-31 | 2006-11-07 | Applied Materials, Inc. | Method of forming a low-K dual damascene interconnect structure |
JP4086673B2 (ja) | 2003-02-04 | 2008-05-14 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP4454242B2 (ja) | 2003-03-25 | 2010-04-21 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
US6902440B2 (en) * | 2003-10-21 | 2005-06-07 | Freescale Semiconductor, Inc. | Method of forming a low K dielectric in a semiconductor manufacturing process |
US7352053B2 (en) * | 2003-10-29 | 2008-04-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Insulating layer having decreased dielectric constant and increased hardness |
US7115993B2 (en) * | 2004-01-30 | 2006-10-03 | Tokyo Electron Limited | Structure comprising amorphous carbon film and method of forming thereof |
US7253501B2 (en) | 2004-08-03 | 2007-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance metallization cap layer |
US20060051681A1 (en) * | 2004-09-08 | 2006-03-09 | Phototronics, Inc. 15 Secor Road P.O. Box 5226 Brookfield, Conecticut | Method of repairing a photomask having an internal etch stop layer |
US7217648B2 (en) | 2004-12-22 | 2007-05-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post-ESL porogen burn-out for copper ELK integration |
US20070126120A1 (en) * | 2005-12-06 | 2007-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device |
US7465676B2 (en) * | 2006-04-24 | 2008-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming dielectric film to improve adhesion of low-k film |
US8178436B2 (en) * | 2006-12-21 | 2012-05-15 | Intel Corporation | Adhesion and electromigration performance at an interface between a dielectric and metal |
DE102007004867B4 (de) | 2007-01-31 | 2009-07-30 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Erhöhen der Zuverlässigkeit von kupferbasierten Metallisierungsstrukturen in einem Mikrostrukturbauelement durch Anwenden von Aluminiumnitrid |
US9385034B2 (en) | 2007-04-11 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Carbonization of metal caps |
US7667271B2 (en) | 2007-04-27 | 2010-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field-effect transistors |
KR20090011190A (ko) | 2007-07-25 | 2009-02-02 | 박석철 | 전기유압 모터 발전기 |
CN101447472B (zh) * | 2007-11-27 | 2012-03-07 | 中芯国际集成电路制造(上海)有限公司 | 刻蚀停止层、双镶嵌结构及其形成方法 |
US7910453B2 (en) | 2008-07-14 | 2011-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Storage nitride encapsulation for non-planar sonos NAND flash charge retention |
US20100252930A1 (en) * | 2009-04-01 | 2010-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Improving Performance of Etch Stop Layer |
US20110081500A1 (en) * | 2009-10-06 | 2011-04-07 | Tokyo Electron Limited | Method of providing stable and adhesive interface between fluorine-based low-k material and metal barrier layer |
KR20110090583A (ko) * | 2010-02-04 | 2011-08-10 | 삼성전자주식회사 | 상변화 메모리 장치 및 그 형성 방법 |
US8310013B2 (en) | 2010-02-11 | 2012-11-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a FinFET device |
US8232148B2 (en) | 2010-03-04 | 2012-07-31 | International Business Machines Corporation | Structure and method to make replacement metal gate and contact metal |
US8399931B2 (en) | 2010-06-30 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout for multiple-fin SRAM cell |
US8729627B2 (en) | 2010-05-14 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel integrated circuit devices |
US8816444B2 (en) | 2011-04-29 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and methods for converting planar design to FinFET design |
US9318614B2 (en) * | 2012-08-02 | 2016-04-19 | Cbrite Inc. | Self-aligned metal oxide TFT with reduced number of masks and with reduced power consumption |
US8466027B2 (en) | 2011-09-08 | 2013-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide formation and associated devices |
US8723272B2 (en) | 2011-10-04 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of manufacturing same |
JP2013115223A (ja) | 2011-11-29 | 2013-06-10 | Toyota Motor Corp | 半導体装置 |
US8377779B1 (en) | 2012-01-03 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of manufacturing semiconductor devices and transistors |
US8735993B2 (en) | 2012-01-31 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET body contact and method of making same |
US8785285B2 (en) | 2012-03-08 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
US8716765B2 (en) | 2012-03-23 | 2014-05-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
US8860148B2 (en) | 2012-04-11 | 2014-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET integrated with capacitor |
US8643074B2 (en) | 2012-05-02 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device |
US8736056B2 (en) | 2012-07-31 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device for reducing contact resistance of a metal |
US8823065B2 (en) | 2012-11-08 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
US8772109B2 (en) | 2012-10-24 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for forming semiconductor contacts |
US9236300B2 (en) | 2012-11-30 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact plugs in SRAM cells and the method of forming the same |
US8986921B2 (en) * | 2013-01-15 | 2015-03-24 | International Business Machines Corporation | Lithographic material stack including a metal-compound hard mask |
US9041216B2 (en) * | 2013-03-14 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method of forming the same |
US9437484B2 (en) | 2014-10-17 | 2016-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch stop layer in integrated circuits |
-
2015
- 2015-04-17 US US14/689,929 patent/US9437484B2/en active Active
- 2015-05-11 DE DE102015107271.8A patent/DE102015107271B4/de active Active
- 2015-07-10 KR KR1020150098162A patent/KR101776387B1/ko active IP Right Grant
- 2015-09-21 TW TW104131085A patent/TWI581326B/zh active
- 2015-10-12 CN CN201510656689.8A patent/CN105529321B/zh active Active
-
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- 2016-08-23 US US15/244,961 patent/US10090242B2/en active Active
-
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- 2018-10-01 US US16/148,076 patent/US10720386B2/en active Active
-
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- 2020-07-20 US US16/933,551 patent/US11404368B2/en active Active
-
2022
- 2022-06-30 US US17/809,914 patent/US11942419B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200737285A (en) * | 2006-03-21 | 2007-10-01 | Taiwan Semiconductor Mfg Co Ltd | Method for forming a 3D interconnect and resulting structure |
TW201250044A (en) * | 2011-03-23 | 2012-12-16 | Hitachi Int Electric Inc | Method of manufacturing semiconductor device, substrate processing method and substrate processing apparatus |
TW201403710A (zh) * | 2012-03-09 | 2014-01-16 | Hitachi Int Electric Inc | 製造半導體裝置之方法、處理基板之方法、基板處理設備及非暫時性電腦可讀取記錄媒體 |
TW201436037A (zh) * | 2013-03-11 | 2014-09-16 | Taiwan Semiconductor Mfg | 半導體元件及其製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11018052B2 (en) | 2019-06-27 | 2021-05-25 | Yangtze Memory Technologies Co., Ltd. | Interconnect structure and method of forming the same |
TWI729651B (zh) * | 2019-06-27 | 2021-06-01 | 大陸商長江存儲科技有限責任公司 | 用於製造半導體元件的方法 |
Also Published As
Publication number | Publication date |
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CN105529321B (zh) | 2020-04-10 |
US9437484B2 (en) | 2016-09-06 |
KR101776387B1 (ko) | 2017-09-07 |
US11942419B2 (en) | 2024-03-26 |
TW201616568A (zh) | 2016-05-01 |
US11404368B2 (en) | 2022-08-02 |
DE102015107271B4 (de) | 2020-04-09 |
US20190043805A1 (en) | 2019-02-07 |
US20220336348A1 (en) | 2022-10-20 |
US10720386B2 (en) | 2020-07-21 |
US20160111325A1 (en) | 2016-04-21 |
US10090242B2 (en) | 2018-10-02 |
US20200350244A1 (en) | 2020-11-05 |
DE102015107271A1 (de) | 2016-04-21 |
CN105529321A (zh) | 2016-04-27 |
US20160358854A1 (en) | 2016-12-08 |
KR20160045550A (ko) | 2016-04-27 |
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