TWI578230B - 用於執行複數個乘法運算的方法和設備 - Google Patents

用於執行複數個乘法運算的方法和設備 Download PDF

Info

Publication number
TWI578230B
TWI578230B TW104105354A TW104105354A TWI578230B TW I578230 B TWI578230 B TW I578230B TW 104105354 A TW104105354 A TW 104105354A TW 104105354 A TW104105354 A TW 104105354A TW I578230 B TWI578230 B TW I578230B
Authority
TW
Taiwan
Prior art keywords
instruction
value
field
processor
job
Prior art date
Application number
TW104105354A
Other languages
English (en)
Chinese (zh)
Other versions
TW201602905A (zh
Inventor
羅傑 艾斯帕薩
吉勒姆 索羅
馬內爾 費南德茲
Original Assignee
英特爾股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英特爾股份有限公司 filed Critical 英特爾股份有限公司
Publication of TW201602905A publication Critical patent/TW201602905A/zh
Application granted granted Critical
Publication of TWI578230B publication Critical patent/TWI578230B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
TW104105354A 2014-03-28 2015-02-16 用於執行複數個乘法運算的方法和設備 TWI578230B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/229,183 US20150277904A1 (en) 2014-03-28 2014-03-28 Method and apparatus for performing a plurality of multiplication operations

Publications (2)

Publication Number Publication Date
TW201602905A TW201602905A (zh) 2016-01-16
TWI578230B true TWI578230B (zh) 2017-04-11

Family

ID=53016263

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104105354A TWI578230B (zh) 2014-03-28 2015-02-16 用於執行複數個乘法運算的方法和設備

Country Status (7)

Country Link
US (1) US20150277904A1 (enExample)
JP (2) JP6092904B2 (enExample)
KR (1) KR101729829B1 (enExample)
CN (1) CN104951278A (enExample)
DE (1) DE102015002253A1 (enExample)
GB (1) GB2526406B (enExample)
TW (1) TWI578230B (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170177361A1 (en) * 2015-12-22 2017-06-22 Michael Anderson Apparatus and method for accelerating graph analytics
US10387988B2 (en) 2016-02-26 2019-08-20 Google Llc Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
GB2548600B (en) * 2016-03-23 2018-05-09 Advanced Risc Mach Ltd Vector predication instruction
US10275243B2 (en) 2016-07-02 2019-04-30 Intel Corporation Interruptible and restartable matrix multiplication instructions, processors, methods, and systems
US10089110B2 (en) * 2016-07-02 2018-10-02 Intel Corporation Systems, apparatuses, and methods for cumulative product
CN115480730A (zh) 2016-10-20 2022-12-16 英特尔公司 用于经融合的乘加的系统、装置和方法
CN106951211B (zh) * 2017-03-27 2019-10-18 南京大学 一种可重构定浮点通用乘法器
US10417731B2 (en) * 2017-04-24 2019-09-17 Intel Corporation Compute optimization mechanism for deep neural networks
US10824938B2 (en) * 2017-04-24 2020-11-03 Intel Corporation Specialized fixed function hardware for efficient convolution
US10776699B2 (en) 2017-05-05 2020-09-15 Intel Corporation Optimized compute hardware for machine learning operations
WO2019066796A1 (en) * 2017-09-27 2019-04-04 Intel Corporation INSTRUCTIONS FOR THE VECTORIAL MULTIPLICATION OF WORDS SIGNED AT BOROUGH
WO2019066797A1 (en) * 2017-09-27 2019-04-04 Intel Corporation INSTRUCTIONS FOR VECTORIC MULTIPLICATION OF NOT SIGNED WORDS WITH BOROUGH
US10534838B2 (en) 2017-09-29 2020-01-14 Intel Corporation Bit matrix multiplication
US10802826B2 (en) * 2017-09-29 2020-10-13 Intel Corporation Apparatus and method for performing dual signed and unsigned multiplication of packed data elements
US10489154B2 (en) * 2017-11-28 2019-11-26 Intel Corporation Apparatus and method for complex multiply and accumulate
US10572568B2 (en) * 2018-03-28 2020-02-25 Intel Corporation Accelerator for sparse-dense matrix multiplication
US10459688B1 (en) * 2019-02-06 2019-10-29 Arm Limited Encoding special value in anchored-data element

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5606677A (en) * 1992-11-30 1997-02-25 Texas Instruments Incorporated Packed word pair multiply operation forming output including most significant bits of product and other bits of one input
US20040230774A1 (en) * 2003-05-12 2004-11-18 International Business Machines Corporation Multifunction hexadecimal instructions
US20050198472A1 (en) * 2004-03-04 2005-09-08 Sih Gilbert C. Digital signal processors with configurable dual-MAC and dual-ALU
US20110153993A1 (en) * 2009-12-22 2011-06-23 Vinodh Gopal Add Instructions to Add Three Source Operands
WO2013095619A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Super multiply add (super madd) instruction with three scalar terms

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2580371B2 (ja) * 1990-07-18 1997-02-12 株式会社日立製作所 ベクトルデ―タ処理装置
US8589663B2 (en) * 2006-06-27 2013-11-19 Intel Corporation Technique to perform three-source operations
US8583902B2 (en) * 2010-05-07 2013-11-12 Oracle International Corporation Instruction support for performing montgomery multiplication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5606677A (en) * 1992-11-30 1997-02-25 Texas Instruments Incorporated Packed word pair multiply operation forming output including most significant bits of product and other bits of one input
US20040230774A1 (en) * 2003-05-12 2004-11-18 International Business Machines Corporation Multifunction hexadecimal instructions
US20050198472A1 (en) * 2004-03-04 2005-09-08 Sih Gilbert C. Digital signal processors with configurable dual-MAC and dual-ALU
US20110153993A1 (en) * 2009-12-22 2011-06-23 Vinodh Gopal Add Instructions to Add Three Source Operands
WO2013095619A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Super multiply add (super madd) instruction with three scalar terms

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Intel, "IA-64 Application Developer's Architecture Guide", May 1999, http://www-users.cs.umn.edu/~chenh/ADAG.pdf *

Also Published As

Publication number Publication date
KR20150112779A (ko) 2015-10-07
JP6498226B2 (ja) 2019-04-10
DE102015002253A1 (de) 2015-10-01
JP2017142799A (ja) 2017-08-17
KR101729829B1 (ko) 2017-04-24
JP2015191661A (ja) 2015-11-02
GB2526406A (en) 2015-11-25
CN104951278A (zh) 2015-09-30
TW201602905A (zh) 2016-01-16
GB2526406B (en) 2017-01-04
JP6092904B2 (ja) 2017-03-08
GB201504489D0 (en) 2015-04-29
US20150277904A1 (en) 2015-10-01

Similar Documents

Publication Publication Date Title
TWI502499B (zh) 執行將寫入罩暫存器轉換成向量暫存器中的索引值列表的系統、裝置及方法
TW201602905A (zh) 用於執行複數個乘法運算的方法和設備
TWI587215B (zh) 排序加速度處理器，方法，系統，及指令
TWI756251B (zh) 執行複數的熔合乘-加指令的系統與方法
TWI567556B (zh) 無區域性提示向量記憶體存取之處理器、方法、系統與指令
TWI617978B (zh) 用於向量索引載入和儲存之方法和設備
TWI622930B (zh) 用於實施具有疊代相依條件之疊代的向量迴圈的處理器、方法和計算系統
CN104011657B (zh) 用于向量计算和累计的装置和方法
TWI550512B (zh) 擴展記憶體源至目的地暫存器及壓縮源暫存器至目的地記憶體位置之處理器
CN104081336B (zh) 用于检测向量寄存器内的相同元素的装置和方法
CN107003848B (zh) 用于融合乘法-乘法指令的装置和方法
CN104011667B (zh) 用于滑动窗口数据访问的设备和方法
CN104011663B (zh) 掩码寄存器上的广播操作
TWI498815B (zh) 用以響應於單一指令而執行橫向部分和之系統、裝置及方法
TWI622879B (zh) 考慮用於執行之載入資料元件中的空間區域性之裝置和方法
TWI486872B (zh) 向量緊縮壓縮及重複之實施系統、設備和方法
CN107003841B (zh) 用于融合加法-加法指令的装置和方法
TWI603261B (zh) 用以執行離心操作的指令及邏輯
TW201346752A (zh) 執行置換運算的設備與方法
TWI482086B (zh) 用以於緊縮資料元件上執行差分編碼之系統、裝置及方法
TW201732574A (zh) 用於改善向量通量的系統、方法及設備
TW201810034A (zh) 用於累和的系統、設備及方法
TW201732568A (zh) 用於巷道為主的跨類收集的系統、設備與方法
TWI539374B (zh) 映射源運算元至不同範圍的系統及其處理器
CN104025021A (zh) 用于滑动窗口数据收集的设备和方法