KR101729829B1 - 복수의 곱셈 연산들을 수행하는 방법 및 장치 - Google Patents

복수의 곱셈 연산들을 수행하는 방법 및 장치 Download PDF

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KR101729829B1
KR101729829B1 KR1020150027626A KR20150027626A KR101729829B1 KR 101729829 B1 KR101729829 B1 KR 101729829B1 KR 1020150027626 A KR1020150027626 A KR 1020150027626A KR 20150027626 A KR20150027626 A KR 20150027626A KR 101729829 B1 KR101729829 B1 KR 101729829B1
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uop
instruction
source operand
field
execution
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KR20150112779A (ko
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로저 에스파사
길렘 솔
마넬 페르난데즈
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인텔 코포레이션
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
KR1020150027626A 2014-03-28 2015-02-26 복수의 곱셈 연산들을 수행하는 방법 및 장치 Expired - Fee Related KR101729829B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/229,183 2014-03-28
US14/229,183 US20150277904A1 (en) 2014-03-28 2014-03-28 Method and apparatus for performing a plurality of multiplication operations

Publications (2)

Publication Number Publication Date
KR20150112779A KR20150112779A (ko) 2015-10-07
KR101729829B1 true KR101729829B1 (ko) 2017-04-24

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US (1) US20150277904A1 (enExample)
JP (2) JP6092904B2 (enExample)
KR (1) KR101729829B1 (enExample)
CN (1) CN104951278A (enExample)
DE (1) DE102015002253A1 (enExample)
GB (1) GB2526406B (enExample)
TW (1) TWI578230B (enExample)

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US20170177361A1 (en) * 2015-12-22 2017-06-22 Michael Anderson Apparatus and method for accelerating graph analytics
US10387988B2 (en) 2016-02-26 2019-08-20 Google Llc Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
GB2548600B (en) * 2016-03-23 2018-05-09 Advanced Risc Mach Ltd Vector predication instruction
US10089110B2 (en) * 2016-07-02 2018-10-02 Intel Corporation Systems, apparatuses, and methods for cumulative product
US10275243B2 (en) * 2016-07-02 2019-04-30 Intel Corporation Interruptible and restartable matrix multiplication instructions, processors, methods, and systems
EP3971711A1 (en) * 2016-10-20 2022-03-23 INTEL Corporation Systems, apparatuses, and methods for fused multiply add
CN106951211B (zh) * 2017-03-27 2019-10-18 南京大学 一种可重构定浮点通用乘法器
US10824938B2 (en) * 2017-04-24 2020-11-03 Intel Corporation Specialized fixed function hardware for efficient convolution
US10417731B2 (en) * 2017-04-24 2019-09-17 Intel Corporation Compute optimization mechanism for deep neural networks
US10776699B2 (en) * 2017-05-05 2020-09-15 Intel Corporation Optimized compute hardware for machine learning operations
US11221849B2 (en) 2017-09-27 2022-01-11 Intel Corporation Instructions for vector multiplication of unsigned words with rounding
US11392379B2 (en) * 2017-09-27 2022-07-19 Intel Corporation Instructions for vector multiplication of signed words with rounding
US10802826B2 (en) * 2017-09-29 2020-10-13 Intel Corporation Apparatus and method for performing dual signed and unsigned multiplication of packed data elements
US10572568B2 (en) * 2018-03-28 2020-02-25 Intel Corporation Accelerator for sparse-dense matrix multiplication
US10459688B1 (en) * 2019-02-06 2019-10-29 Arm Limited Encoding special value in anchored-data element

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US20070300049A1 (en) * 2006-06-27 2007-12-27 Avinash Sodani Technique to perform three-source operations
US20110153993A1 (en) * 2009-12-22 2011-06-23 Vinodh Gopal Add Instructions to Add Three Source Operands

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JP2580371B2 (ja) * 1990-07-18 1997-02-12 株式会社日立製作所 ベクトルデ―タ処理装置
US5606677A (en) * 1992-11-30 1997-02-25 Texas Instruments Incorporated Packed word pair multiply operation forming output including most significant bits of product and other bits of one input
US7254698B2 (en) * 2003-05-12 2007-08-07 International Business Machines Corporation Multifunction hexadecimal instructions
US7873815B2 (en) * 2004-03-04 2011-01-18 Qualcomm Incorporated Digital signal processors with configurable dual-MAC and dual-ALU
US8583902B2 (en) * 2010-05-07 2013-11-12 Oracle International Corporation Instruction support for performing montgomery multiplication
WO2013095619A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Super multiply add (super madd) instruction with three scalar terms

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US20070300049A1 (en) * 2006-06-27 2007-12-27 Avinash Sodani Technique to perform three-source operations
US20110153993A1 (en) * 2009-12-22 2011-06-23 Vinodh Gopal Add Instructions to Add Three Source Operands

Non-Patent Citations (1)

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Title
Kobayashi, Hideaki. "A fast multi-operand multiplication scheme." IEEE 5th Symposium on Computer Arithmetic. 1981.*

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Publication number Publication date
GB2526406B (en) 2017-01-04
TWI578230B (zh) 2017-04-11
CN104951278A (zh) 2015-09-30
JP6092904B2 (ja) 2017-03-08
US20150277904A1 (en) 2015-10-01
TW201602905A (zh) 2016-01-16
GB201504489D0 (en) 2015-04-29
GB2526406A (en) 2015-11-25
JP6498226B2 (ja) 2019-04-10
JP2015191661A (ja) 2015-11-02
KR20150112779A (ko) 2015-10-07
JP2017142799A (ja) 2017-08-17
DE102015002253A1 (de) 2015-10-01

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