TWI576921B - 矽晶粒上互連堆疊中之嵌入式記憶體 - Google Patents

矽晶粒上互連堆疊中之嵌入式記憶體 Download PDF

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TWI576921B
TWI576921B TW104114890A TW104114890A TWI576921B TW I576921 B TWI576921 B TW I576921B TW 104114890 A TW104114890 A TW 104114890A TW 104114890 A TW104114890 A TW 104114890A TW I576921 B TWI576921 B TW I576921B
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Taiwan
Prior art keywords
interconnects
substrate
forming
memory
device layer
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TW104114890A
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English (en)
Chinese (zh)
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TW201614734A (en
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唐諾德 尼爾森
麥 韋伯
派翠克 摩洛
全箕玟
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英特爾股份有限公司
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Publication of TW201614734A publication Critical patent/TW201614734A/zh
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/1579Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
TW104114890A 2014-06-16 2015-05-11 矽晶粒上互連堆疊中之嵌入式記憶體 TWI576921B (zh)

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SG11201608947SA (en) 2016-11-29
EP3155653A1 (de) 2017-04-19
CN106463406A (zh) 2017-02-22
EP3155653A4 (de) 2018-02-21
TW201614734A (en) 2016-04-16

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