TWI566359B - 具有直接附接至引線架的半導體晶粒的半導體封裝及方法 - Google Patents

具有直接附接至引線架的半導體晶粒的半導體封裝及方法 Download PDF

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TWI566359B
TWI566359B TW104119962A TW104119962A TWI566359B TW I566359 B TWI566359 B TW I566359B TW 104119962 A TW104119962 A TW 104119962A TW 104119962 A TW104119962 A TW 104119962A TW I566359 B TWI566359 B TW I566359B
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Taiwan
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conductive
lead frame
lead
semiconductor die
die
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TW104119962A
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TW201630144A (zh
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培中希
朴杜玄
李旺求
宋洋
姜成根
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艾馬克科技公司
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Description

具有直接附接至引線架的半導體晶粒的半導體封裝及方法
本發明一般而言關於電子器件，更特別而言關於半導體封裝、其結構及形成半導體封裝的方法。
一般而言，用於半導體封裝的引線架是藉由機械壓印或化學蝕刻金屬條而製造。引線架作為將半導體晶粒連接到外部電路的引線，並且作為將半導體封裝固定於外部電路的框架。
根據朝向半導體晶粒之高密度和高整合度的趨勢以及構件安裝方法，引線架可以具有多樣的形狀。為了使像是記憶體和中央處理單元(CPU)的半導體晶粒和引線架彼此電連接，從前的半導體封裝已經建構成使得半導體晶粒的結合襯墊和引線架藉由打線結合或使用導電凸塊而彼此連接。
具有前述組態的引線架電連接到半導體晶粒，接著使用囊封體來囊封，藉此完成半導體封裝。此種半導體封裝存在著幾個問題，包括額外的製造成本和時間以完成打線結合或導電凸塊過程、此種過程期間受損所引起之可靠度問題的可能性有所增加、封裝高度有所增加、包括在高電流應用下故障的不良效能。
據此，想要有方法和結構，其減少將半導體晶粒連接到引線 架的成本、減少製造期間受損的可能性以改善可靠度、改善在高電流應用下的效能。
就諸特色而言，本敘述尤其包括使用電化學形成層和/或導電黏著層而將半導體晶粒的導電襯墊和引線架彼此直接連接，該等層由相同於引線架的金屬所做成。這就不須要分開提供需要高成本的打線結合或導電凸塊結構。這也便於半導體晶粒的導電襯墊和引線架之間的電連接，其節省成本並且改善在高電流應用下的效能。
於一實施例，半導體封裝包括：半導體晶粒，其具有多個導電襯墊；以及引線架，其具有分別電連接到多個導電襯墊的多條引線，其中引線架進一步包括提供在多條引線上的電化學沉積層，並且多條引線藉由電化學沉積層而電連接到多個導電襯墊。
於另一實施例，半導體封裝包括：半導體晶粒，其具有第一 表面和相對於第一表面的第二表面，並且包括形成在其第一表面上的第一導電襯墊；以及引線架，其包括電連接到半導體晶粒之第二表面的晶粒襯墊，以及包括與晶粒襯墊隔開而往外延伸並且電連接到半導體晶粒之第一導電襯墊的第一引線，其中引線架進一步包括配置在第一引線上的鍍覆層，並且第一引線透過鍍覆層而電連接到第一導電襯墊。
於進一步實施例，形成半導體封裝的方法包括：提供半導體 晶粒，其包括多個導電襯墊；提供引線架，其具有多條引線；將多個導電襯墊放置成靠近多條引線；以及形成導電層以將多條引線電連接到多個導 電襯墊。於再進一步實施例，形成導電層包括：電化學形成導電層。
於另一實施例，半導體封裝包括：半導體晶粒，其具有第一 表面和相對於第一表面的第二表面，並且包括形成在其第一表面上的第一導電襯墊；引線架，其包括電連接到半導體晶粒之第二表面的晶粒襯墊，以及包括與晶粒襯墊隔開而往外延伸並且電連接到半導體晶粒之第一導電襯墊的第一引線；以及導電黏著層，其插置在引線架的引線和第一導電襯墊之間。
100‧‧‧半導體封裝
110‧‧‧引線架
110a‧‧‧第一表面
110b‧‧‧第二表面
111‧‧‧晶粒襯墊
112‧‧‧引線
112a‧‧‧第二側
113‧‧‧電化學形成層、電化學沉積層或鍍覆層
120‧‧‧半導體晶粒
120a‧‧‧第一表面
120b‧‧‧第二表面
121‧‧‧導電襯墊
122‧‧‧保護層
130‧‧‧囊封體
200‧‧‧半導體封裝
212b‧‧‧突起
300‧‧‧半導體封裝
311a‧‧‧釘銷凸塊
400‧‧‧半導體封裝
414‧‧‧絕緣層
500‧‧‧半導體封裝
512c‧‧‧通孔
600‧‧‧半導體封裝
610‧‧‧引線架
611‧‧‧晶粒襯墊
612‧‧‧引線
612a‧‧‧第一引線
612b‧‧‧第二引線
612c‧‧‧第三引線
613‧‧‧鍍覆層
614‧‧‧繫棒
615‧‧‧導線
620‧‧‧半導體晶粒
620a‧‧‧第一表面
620b‧‧‧第二表面
621‧‧‧第一導電襯墊
622‧‧‧第三導電襯墊
623‧‧‧焊料
630‧‧‧囊封體
700‧‧‧半導體封裝
713‧‧‧導電黏著層
圖1A和1B是示範根據本發明的實施例之半導體封裝的部分截面圖和部分放大截面圖；圖2A到2D是示範根據本發明的其他實施例之半導體封裝的部分放大截面圖；圖3A和3B是示範根據本發明另一實施例之半導體封裝的部分截面圖和立體圖；以及圖4是示範根據本發明另一實施例之半導體封裝的截面圖。
為了簡單和清楚示範，圖中的元件未必按照比例來繪製，並且不同圖中的相同參考數字一般而言代表相同的元件。附帶而言，為了簡單敘述而省略了熟知步驟和元件的敘述和細節。熟於此技藝者將體會如在此關於電路操作所使用的「於……期間」、「與……同時」、「當……時」等字眼不是意謂動作立即發生在開始動作之時的精確用語，而是在初始動作所開始的反應之間可以有某種小但合理的延遲，例如傳遞延遲。附帶而言，「與……同時」一詞意謂特定的動作至少是在起始動作的某個時間部分裡發 生。使用「差不多」或「實質」等字眼意謂元件的數值預期靠近狀態值或位置。然而，如此技藝所熟知的，總有次要的變異性而避免數值或位置恰如所述。如在此所用的，單數形式打算也包括複數形式，除非上下文清楚另有所指。將了解雖然可能在此使用第一、第二……等詞來描述多樣的構件、元件、區域、層和/或部分，但是這些構件、元件、區域、層和/或部分不受限於這些詞。這些詞僅用於區分某一構件、元件、區域、層和/或部分與另一構件、元件、區域、層和/或部分。因此，舉例而言，下面討論的第一構件、元件、區域、層和/或部分或可稱為第二構件、元件、區域、層和/或部分，而不偏離本發明的教導。
本敘述的多樣方面可以採取不同的形式來實現，並且不應解讀成受限於在此所列出的範例性實施例。提供本揭示的這些範例性實施例反而是要將本揭示的多樣方面傳遞給此技藝中的一般技術者。
參見圖1A和1B，示範的是根據第一實施例之半導體封裝100的部分截面圖和部分放大截面圖。如圖1所示範，半導體封裝100包括引線架110、半導體晶粒120、囊封體130。
於一實施例，引線架110包括晶粒襯墊111、繫棒(未顯示)、多條引線112以及電化學形成層113、電化學沉積層13或鍍覆層113(例如電鍍層113)。引線架110具有第一表面110a和相對於第一表面110a的第二表面110b，並且於一實施例，可以由銅所做成。依據本實施例，電化學形成層113(包括鍍覆層113)可以使用具有外部電流來源的電解質溶液(例如電鍍過程)或沒有外部電流來源的電解質溶液(例如無電鍍過程或使用自動催 化性鍍覆溶液的過程)而提供。
於某些實施例，晶粒襯墊111塑形為實質矩形板，並且具有 四側和四個角落。於一實施例，晶粒襯墊111形成為使得電化學沉積所形成的鍍覆層113覆蓋第一表面和相對於第一表面的第二表面。於一實施例，晶粒襯墊111的第一表面可以與引線架110的第一表面110a實質共平面，並且晶粒襯墊111的第二表面可以與引線架110的第二表面110b實質共平面。於一實施例，晶粒襯墊111可以透過鍍覆層113而電連接到半導體晶粒120。
於一實施例，繫棒可以從晶粒襯墊111的四個角落往外突出 了預定的長度。於一實施例，繫棒可以從晶粒襯墊111的角落而在往外和大致斜對角的方向上延伸。繫棒可以建構成維持引線架100的共平面性。
於某些實施例，多條引線112可以與晶粒襯墊111的四側隔 開以在垂直方向上安排到晶粒襯墊111的個別側。也就是說，多條引線112可以與晶粒襯墊111隔開，並且可以與晶粒襯墊111的外周緣隔開。多條引線112彼此隔開而彼此電斷連。於一實施例，多條引線112之每一者的第一表面是面向方向相同於晶粒襯墊111之第一表面的表面，並且可以與引線架110的第一表面110a實質共平面。附帶而言，多條引線112之每一者的第二表面是面向方向相同於晶粒襯墊111之第二表面的表面，並且可以與引線架110的第二表面110b實質共平面。於一實施例，多條引線112形成為使得電化學沉積所形成的鍍覆層113覆蓋第一表面110a和第二表面110b。依據本實施例，多條引線112透過鍍覆層113而電連接到半導體晶粒120。
於一實施例，在半導體晶粒120安裝在第一表面110a上之 後，然後可以藉由電化學沉積過程(例如電鍍或無電鍍)而形成鍍覆層113以整個覆蓋引線架110的外表面。
於一實施例，半導體晶粒120塑形為實質平板，並且具有第 一表面120a和相對於第一表面120a的第二表面120b。於一實施例，半導體晶粒120包括形成在第一表面120a上的多個導電襯墊121，並且可以包括形成為整個覆蓋半導體晶粒120之第一表面120a的保護層122，如此以將多個導電襯墊121暴露到外面。於某些實施例，保護層122可以由絕緣材料所做成。多個導電襯墊121是由導電材料所做成，例如銅或其他材料，如此技藝中的一般技術者所知的。
依據本實施例，半導體晶粒120安裝在引線架110上，使得 第一表面120a面對並且靠近引線架110的第一表面110a。於某些實施例，半導體晶粒120可以具有大於晶粒襯墊111的平面尺寸，如圖1A和1B所大致示範。
於一實施例，在安裝了多個導電襯墊121而使得引線架110 的多條引線112面對晶粒襯墊111之後，藉由電化學沉積而在引線架110上形成鍍覆層113，藉此允許半導體晶粒120將多個導電襯墊121電連接到引線架110。半導體晶粒120的多個導電襯墊121因此藉由鍍覆層113而電連接到多條引線112的第一側。依據本實施例，部分的鍍覆層113可以配置成貼近多個導電襯墊121之至少部分的側或側壁表面或其暴露於電化學沉積過程的表面。
依據一實施例，鍍覆層113可以從引線架110往外形成，直 到它連接到多個導電襯墊121為止。於一實施例，半導體晶粒120之不形成多個導電襯墊121的第一表面120a可以藉由保護層122和/或底填層(例如使用囊封體130所提供的模製底填層)而與鍍覆層113電斷連。
於一實施例，鍍覆層113形成在引線架110的多條引線112 和半導體晶粒120的多個導電襯墊121之間，藉此透過鍍覆層113而將多條引線112電連接到多個導電襯墊121。附帶而言，於某些實施例，鍍覆層113可以形成在引線架110的晶粒襯墊111和半導體晶粒120的多個導電襯墊121之間，藉此透過鍍覆層113而將晶粒襯墊111電連接到多個導電襯墊121。
依據一實施例，鍍覆層113插置在引線架110的多條引線 112和半導體晶粒120的多個導電襯墊121之間，以及在引線架110的晶粒襯墊111和半導體晶粒120的多個導電襯墊121之間，藉此將引線架110電連接到半導體晶粒120。於一實施例，鍍覆層113、引線架110、半導體晶粒120的多個導電襯墊121可以由相同的金屬所做成，舉例而言為銅。
囊封體130囊封引線架110和半導體晶粒120以保護它們免 於外部環境。於一實施例，囊封體130整個覆蓋引線架110之上面安裝了半導體晶粒120的第一表面110a和半導體晶粒120。於引線架110的多條引線112中，其連接到多個導電襯墊121的第一側可以定位在囊封體130的裡面，並且第二側112a可以暴露到囊封體130的外面。也就是說，於一實施例，多條引線112之每個第二側112a的第二表面可以暴露到囊封體130的外面。於一實施例，多條引線112的第二側112a可以由鍍覆層113所覆蓋。
依據本實施例，於半導體封裝100，半導體晶粒120的多個 導電襯墊121和引線架110透過鍍覆層113而彼此直接連接，該鍍覆層可以 由相同於多個導電襯墊121和引線架110的材料所做成，而不分開提供需要高成本的打線結合或導電凸塊，藉此便於半導體晶粒120的導電襯墊121和引線架110之間的電連接，而節省成本並且改善在高電流應用下的效能。
圖2A到2D示範針對圖1A和1B的半導體封裝100之替代性實施例的部分放大截面圖。
相較於圖1A所示範的半導體封裝100，圖2A到2D所示範的每個半導體封裝200、300、400、500可以進一步包括附加於引線架110、半導體晶粒120、囊封體130的額外構件。因此，下面的敘述將聚焦在圖1A所示範的半導體封裝100和圖2A到2D所示範的半導體封裝200、300、400、500之間的差異。
依據本實施例，圖2A所示範的半導體封裝200可以進一步包括突起212b，其形成在引線架110之面對半導體晶粒120之多個導電襯墊121的第一表面110a上，而該等突起大致朝向半導體晶粒120而突出或延伸。於一實施例，突起212b可以提供在引線架110之第一表面110a的位置係對應於半導體晶粒120之多個導電襯墊121的位置。於一實施例，突起212b可以提供於晶粒襯墊111和多條引線112中以電連接到引線架110中的多個導電襯墊121。於一實施例，突起212b可以與引線架110一體成形，並且可以在與形成引線架110的相同階段來形成。
於一實施例，突起212b可以由插置在引線架110和導電襯墊121之間的鍍覆層113所覆蓋。半導體封裝200的突起212b可以減少將多個導電襯墊121電連接到引線架110之鍍覆層113的厚度。也就是說，由於圖2A所示範的半導體封裝200包括突起212b，故半導體晶粒120的多個 導電襯墊121和引線架110之間的電連接可以是更方便的，即使鍍覆層113所形成的厚度小於圖1A所示範的半導體封裝亦然。
依據本實施例，圖2B所示範的半導體封裝300可以進一步 包括釘銷凸塊311a，其提供於半導體晶粒120的多個導電襯墊121中。釘銷凸塊311a可以由導電材料所做成，並且可以形成在半導體晶粒120的多個導電襯墊121上。釘銷凸塊311a可以從多個導電襯墊121突出而朝向一或更多個引線架110。
依據本實施例，釘銷凸塊311a是由插置在引線架110和導 電襯墊121之間的鍍覆層113所覆蓋。半導體封裝300的釘銷凸塊311a可以減少將多個導電襯墊121電連接到引線架110之鍍覆層113的厚度。也就是說，由於圖2B所示範的半導體封裝300包括釘銷凸塊311a，故半導體晶粒120的多個導電襯墊121和引線架110之間的電連接可以更方便，即使鍍覆層113所形成的厚度小於圖1A所示範的半導體封裝亦然。
依據本實施例，圖2C所示範的半導體封裝400可以進一步 包括絕緣層414，其形成為覆蓋引線架110的區域或部分，而非對應於半導體晶粒120之多個導電襯墊121的區域或部分。絕緣層414可以形成在引線架110的第一表面110a上，如此以僅將對應於多個導電襯墊121的區域暴露到外面。
於引線架110，在安裝了半導體晶粒120之後，鍍覆層113 可以藉由僅在引線架110之透過絕緣層414而暴露到外面的區域做電化學沉積而形成。於一實施例，由於半導體封裝400包括絕緣層414，故鍍覆層113僅形成在引線架110之對應於半導體晶粒120的多個導電襯墊121的區域， 藉此避免非必要的形成鍍覆層113。
依據本實施例，圖2D所示範的半導體封裝500可以進一步 包括多個通孔512c，其通過引線架110的第一表面110a和第二表面110b之間的區域，而對應於半導體晶粒120之多個導電襯墊121的每一者。於一實施例，每個通孔512c的裡面可以填充了鍍覆層113。於一實施例，在引線架110中，多個通孔512c可以形成於晶粒襯墊111和多條引線112中，並且每個通孔512c的裡面可以填充了鍍覆層113。
由於引線架110的鍍覆層113形成在通孔512c的裡面，故可以更方便的在引線架110的其他平面區域形成鍍覆層113。
依據本實施例，由於半導體封裝500包括形成在對應於多個導電襯墊121之區域中的通孔512c，故鍍覆層113的形成在形成了通孔512c的區域中有所增加，即使鍍覆層113所形成的厚度小於圖1A所示範之半導體封裝100的鍍覆層113亦然。因此，根據半導體封裝500，引線架110和多個導電襯墊121之間的電連接可以更方便，即使鍍覆層113的厚度相較於圖1A所示範的半導體封裝100情形有所減少而亦然。
圖3A和3B是示範根據另一實施例之半導體封裝600的部分截面圖和立體圖。
如圖3A和3B所示範，於一實施例，半導體封裝600包括引線架610、半導體晶粒620、囊封體630。於一實施例，引線架610包括晶粒襯墊611、繫棒614、多條引線612、鍍覆層613。引線架610具有第一表面610a和相對於第一表面610a的第二表面610b。於一實施例，引線架610可以由銅所做成。
於一實施例，晶粒襯墊611可以具有實質矩形板的形狀而有 四側和四個角落。於一實施例，晶粒襯墊611的第一表面可以與引線架610的第一表面610a實質共平面，並且晶粒襯墊611的第二表面可以與引線架610的第二表面610b實質共平面。
繫棒614可以從晶粒襯墊611的四個角落往外突出了預定的 長度。繫棒可以從晶粒襯墊611的角落而在往外和大致斜對角的方向上延伸。繫棒可以建構成維持引線架600的共平面性。
多條引線612的每一者可以包括：第一引線612a，其具有與 晶粒襯墊611之第一表面610a隔開的一側而大致平行於第一表面610a；第二引線612b，其從晶粒襯墊611延伸；以及第三引線612c，其與晶粒襯墊611的一側隔開。多條第一引線612a、多條第二引線612b、多條第三引線612c可以彼此隔開而彼此電斷連。依據本實施例，多條第一引線612a透過鍍覆層613而電連接到半導體晶粒620。
於引線架610，在半導體晶粒620安裝在第一表面610a上之 後，可以藉由電化學沉積過程(例如電鍍過程、無電鍍過程或此技藝中的一般技術者所知的其他類似技術)而形成鍍覆層613以整個覆蓋引線架610的外表面。
於一實施例，半導體晶粒620具有實質平板的形狀，並且具 有第一表面620a和相對於第一表面620a的第二表面620b。半導體晶粒620可以包括形成在第一表面620a上的多個第一導電襯墊621和形成為整個覆蓋半導體晶粒620之第一表面620a的保護層(未顯示)，如此以將多個第一導電襯墊621暴露到外面。多個第一導電襯墊621可以由銅或其他材料所做 成，如此技藝中的一般技術者所知的。
於一實施例，半導體晶粒620可以是高功率半導體裝置，例 如絕緣閘極雙極電晶體(insulated gate bipolar transistor，IGBT)或場效電晶體(field effect transistor，FET)。於一實施例，半導體晶粒620建構成高功率半導體裝置，其包括第一電極、第二電極、控制電極。於作為高功率半導體裝置的半導體晶粒620，高電流可以藉由施加到控制電極的電壓而在第一電極和第二電極之間流動。
於建構成高功率半導體裝置的半導體晶粒620，形成在第一 表面620a上的第一導電襯墊621可以是第一電極，並且形成在半導體晶粒620之第二表面620b上的第二導電襯墊(未顯示)可以是第二電極。附帶而言，與多個第一導電襯墊621電斷連的第三導電襯墊622可以進一步提供在半導體晶粒620的第一表面620a上。第三導電襯墊622可以是控制電極。
半導體晶粒620安裝在晶粒襯墊611的第一表面610a上。 附帶而言，半導體晶粒620的第二表面620b可以透過焊料623而電連接到晶粒襯墊611的第一表面610a。半導體晶粒620和晶粒襯墊611可以透過鍍覆層613而非焊料623來彼此電連接。為了允許鍍覆層613容易插置在半導體晶粒620和晶粒襯墊611之間，某些實施例可以使用各通過晶粒襯墊611的第一和第二表面610a、610b之間部分的多個通孔。
如上所述，半導體晶粒620的第二導電襯墊電連接到晶粒襯 墊611。附帶而言，從晶粒襯墊611延伸的每根第二引線612b可以具有連接到晶粒襯墊611的第一側和暴露到囊封體630之外面的第二側。
半導體晶粒620的第一導電襯墊621電連接到引線架610的 第一引線612a。鍍覆層613可以進一步插置在第一引線612a和第一導電襯墊621之間。
在半導體晶粒620安裝在晶粒襯墊611上之後，可以藉由電 化學形成而形成鍍覆層613以配置在第一引線612a和多個第一導電襯墊621之間的空間中，藉此將第一引線612a電連接到第一導電襯墊621。也就是說，可以形成鍍覆層613，直到第一引線612a連接到第一導電襯墊621為止。於圖3A和3B，鍍覆層613僅形成在第一引線612a上。然而，於其他實施例，鍍覆層613可以藉由整個鍍覆引線架610到預定的厚度而形成。鍍覆層613和第一導電襯墊621可以由相同的金屬所做成，舉例而言為銅。
第一引線612a各具有連接到半導體晶粒620的第一表面 620a上所形成之第一導電襯墊621的第一側，並且第二引線612b各具有連接到半導體晶粒620的第二表面620b上所形成之第二導電襯墊(未顯示)的第一側，此二者可以實質共平面。於一實施例，每根第一引線612a的第二側朝向第二引線612b而彎曲，並且每根第二引線612b的第二側朝向第一引線612a而彎曲，如此則第一引線612a的第二側和第二引線612b的第二側可以實質共平面。附帶而言，半導體晶粒620的第三導電襯墊623可以透過導線615而電連接到第三引線612c。於圖3A和3B，雖然第三導電襯墊622透過導線615而連接到第三引線612c，但是本揭示的諸方面不限於此。
半導體晶粒620的第三導電襯墊622和第三引線612c可以 透過鍍覆層613而彼此連接。為了透過鍍覆層613而將半導體晶粒620的第三導電襯墊622連接到第三引線612c，於一實施例，第三引線612c和第一引線612a可以具有相同的形狀。
於圖3A和3B，第三引線612c和第二引線612b具有實質相 同的形狀，例外的是第三引線612c和第二引線612b的第一側是由晶粒襯墊611而彼此隔開，並且第三引線612c可以與晶粒襯墊611電斷連。於一實施例，第三引線612c的第二側可以突出到囊封體630的外面。於一實施例，第一引線612a、第二引線612b、第三引線612c的第二側可以暴露到囊封體630的外面，並且可以採取實質共平面的方式來定位。
於某些實施例，囊封體630囊封引線架610和半導體晶粒 620以保護它們免於外部環境。於一實施例，囊封體630整個覆蓋上面安裝了半導體晶粒620的引線架610和半導體晶粒620。於一實施例，引線架610連接到半導體晶粒620之引線612的第一側可以定位在囊封體630裡面，並且引線612的第二側可以突出到囊封體630的外面。也就是說，第一引線612a、第二引線612b、第三引線612c的第二側可以突出到囊封體630的外面，並且可以採取實質共平面的方式來定位。
於半導體封裝600，當半導體晶粒620是高功率半導體裝置 時，依據本實施例，它透過鍍覆層613而直接連接到引線架610，藉此避免由於高電流而有導線損傷。附帶而言，於一實施例，半導體晶粒620和引線架610透過鍍覆層613而彼此連接，該鍍覆層由相同於多個第一導電襯墊621和引線架610的材料所做成，而不分開提供需要高成本的打線結合或導電凸塊，藉此便於多個第一導電襯墊621和引線架610之間的電連接以及節省成本。
圖4是示範根據另一實施例之半導體封裝700的截面圖。
如圖4所示範，半導體封裝700包括引線架610、半導體晶 粒620、囊封體630。圖4所示範的半導體封裝700和圖3A和3B所示範的半導體封裝600具有實質相同的組態，例外之處在於引線架610和半導體晶粒620之間的連接組態。
於一實施例，半導體晶粒620的第一導電襯墊621可以透過 導電黏著層713而電連接到引線架610的第一引線612a。於一實施例，導電黏著層713和第一導電襯墊621可以包括相同的金屬，舉例而言為銅和黏著劑。
於一實施例，導電黏著層713可以藉由以下而形成：將黏著 劑施加到半導體晶粒620的第一導電襯墊621和引線架610的第一引線612a之間的部分，並且藉由燒結來固化黏著劑，藉此使半導體晶粒620和引線架610彼此黏著。
於半導體封裝700，當半導體晶粒620是高功率半導體裝置 時，它可以透過鍍覆層613(示範於圖3A)而直接連接到引線架610，藉此避免由於高電流而有導線損傷。附帶而言，半導體晶粒620和引線架610可以透過導電黏著層713而彼此連接，該導電黏著層由相同於第一導電襯墊621和引線架610的材料所做成，而不分開提供需要高成本的打線結合或導電凸塊，藉此便於多個第一導電襯墊621和引線架610之間的電連接並且節省製造成本。
從以上全部所言，熟於此技藝者可以決定：根據另一實施 例，半導體封裝包括半導體晶粒，其具有第一表面和相對於第一表面的第二表面，並且包括形成在其第一表面上的第一導電襯墊。包括晶粒襯墊的引線架則電連接到半導體晶粒的第二表面，並且第一引線與晶粒襯墊隔開 而往外延伸並且電連接到半導體晶粒的第一導電襯墊。導電黏著層插置在引線架的引線和第一導電襯墊之間。
從以上全部所言，熟於此技藝者可以決定：根據進一步實施 例，半導體晶粒是絕緣閘極雙極電晶體(IGBT)或場效電晶體(FET)而作為高功率半導性裝置。於再進一步實施例，半導體封裝可以進一步包括囊封體，其囊封半導體晶粒、晶粒襯墊之上面安裝了半導體晶粒的第一表面、第一引線之連接到導電襯墊的第一側。於另一實施例，導電黏著層可以藉由燒結而固化。
雖然本發明已經特別參考其範例性實施例來示範和描述，不過此技藝中的一般技術者將了解當中的形式和細節可以做出多樣的改變，而不偏離本發明如下面請求項所界定的精神和範圍。因此本實施例想要在所有方面都視為示範性的而非限制性的，而要參考所附的申請專利範圍而非前面的敘述以指出本發明的範圍。
如下文的申請專利範圍所反映的，發明方面可以少於前面揭示之單一實施例的所有特色。因此，下文表達的申請專利範圍在此明確併入【實施方式】裡，而每個請求項各自獨立為本發明之分開的實施例。此外，雖然在此所述的某些實施例包括了其他實施例所包括的某些而非其他特色，不過不同實施例的特色組合意謂是在本發明的範圍裡，並且意謂形成不同的實施例，如熟於此技藝者會了解的。
100‧‧‧半導體封裝
110‧‧‧引線架
110a‧‧‧第一表面
110b‧‧‧第二表面
111‧‧‧晶粒襯墊
112‧‧‧引線
113‧‧‧電化學形成層、電化學沉積層或鍍覆層
120‧‧‧半導體晶粒
120a‧‧‧第一表面
120b‧‧‧第二表面
121‧‧‧導電襯墊
122‧‧‧保護層
130‧‧‧囊封體

Claims (20)

  1. 一種半導體封裝，其包括：半導體晶粒，其包括從該半導體晶粒的主要表面往外突出的多個導電襯墊；以及引線架，其具有分別電連接到該等多個導電襯墊的多條引線，其中該引線架進一步包括配置在該等多條引線上的電化學沉積層，並且該等多條引線藉由該電化學沉積層而電連接到該等多個導電襯墊，並且其中該電化學沉積層被附貼至每個導電襯墊的側表面。
  2. 如申請專利範圍第1項的半導體封裝，其中該等多條引線進一步包括在對應於該等多個導電襯墊之區域中的突起，該等突起朝向該等多個導電襯墊而突出。
  3. 如申請專利範圍第2項的半導體封裝，其中該電化學沉積層插置在該等引線的每一者和該等導電襯墊的每一者之間，如此以覆蓋該等突起。
  4. 如申請專利範圍第1項的半導體封裝，其中該等多條引線包括在對應於該等導電襯墊之區域中的通孔，該等通孔各自通過在該等引線之每一者的第一表面和相對於該第一表面的第二表面之間的部分，並且該等通孔填充了該電化學沉積層。
  5. 如申請專利範圍第1項的半導體封裝，其中該等多個導電襯墊進一步包括釘銷凸塊，其朝向該引線架而突出。
  6. 如申請專利範圍第5項的半導體封裝，其中該電化學沉積層插置在該等引線的每一者和該等導電襯墊的每一者之間，如此以覆蓋該釘銷凸塊。
  7. 如申請專利範圍第1項的半導體封裝，其中在該引線架的該等多條 引線中，該電化學沉積層提供在對應於該半導體晶粒之該等多個導電襯墊的該等區域中，並且絕緣層是在提供了該電化學沉積層之該等區域以外的區域中。
  8. 如申請專利範圍第1項的半導體封裝，其中該引線架包括：晶粒襯墊，其塑形為矩形板；該等多條引線安排成與該晶粒襯墊的各側彼此隔開，其中該晶粒襯墊透過該電化學沉積層而電連接到該等導電襯墊；以及該電化學沉積層包括電鍍層或無電鍍層中一者。
  9. 如申請專利範圍第1項的半導體封裝，其進一步包括囊封體，其覆蓋該引線架之上面安裝了該半導體晶粒的第一表面，並且覆蓋該半導體晶粒，並且其中該囊封體暴露該引線架之該等多條引線的某些區域。
  10. 如申請專利範圍第1項的半導體封裝，其中該引線架、該等多個導電襯墊、該電化學沉積層包括相同的金屬。
  11. 一種半導體封裝，其包括：半導體晶粒，其具有第一表面和相對於該第一表面的第二表面，並且包括從該第一表面往外突出的第一導電襯墊；以及引線架，其包括電連接到該半導體晶粒之該第二表面的晶粒襯墊，以及包括與該晶粒襯墊隔開而往外延伸並且電連接到該半導體晶粒之該第一導電襯墊的第一引線，其中該引線架進一步包括在該第一引線上的鍍覆層，並且該第一引線透過該鍍覆層而電連接到該第一導電襯墊，並且其中該鍍覆層被附貼至該第一導電襯墊的側表面。
  12. 如申請專利範圍第11項的半導體封裝，其中該第一引線具有相鄰於該第一導電襯墊的第一區域和與該第一導電襯墊隔開的第二區域，並且其中該鍍覆層在該第一區域要比在該第二區域來得厚。
  13. 如申請專利範圍第11項的半導體封裝，其中：該鍍覆層插置在該半導體晶粒的該第二表面和該晶粒襯墊之間，並且其中該鍍覆層包括電鍍層或無電鍍層當中一者；以及該半導體封裝進一步包括囊封體，其囊封該半導體晶粒、該晶粒襯墊之上面安裝了該半導體晶粒的第一表面、及該第一引線之連接到該導電襯墊的第一側。
  14. 如申請專利範圍第11項的半導體封裝，其中該第一引線包括第一部分和第二部分，並且其中該第一部分比該第二部分薄，並且其中該第一引線進一步包括在對應於該第一導電襯墊之區域中的通孔，該通孔通過在該第一引線的第一表面和相對於該第一表面的第二表面之間的該第一部分，其中該鍍覆層是在該通孔裡。
  15. 一種用於形成半導體封裝的方法，其包括：提供半導體晶粒，其包括從該半導體晶粒的主要表面往外突出的多個導電襯墊；提供引線架，其具有多條引線；將該等多個導電襯墊放置成靠近該等多條引線；以及形成導電層以將該等多條引線電連接到該等多個導電襯墊，並且其中該導電層被附貼至每個導電襯墊的側表面。
  16. 如申請專利範圍第15項的方法，其中： 在將該等多個導電襯墊放置成靠近該等多條引線之後才發生形成該導電層；以及形成該導電層包括：使用電鍍和無電鍍中一者而電化學形成該導電層。
  17. 如申請專利範圍第15項的方法，其中：提供該引線架包括提供該等多條引線，其包括形成在對應於該等導電襯墊之區域中的通孔，該等通孔各自通過在該等引線之每一者的第一表面和相對於該第一表面的第二表面之間的部分；以及形成該導電層包括在該等通孔裡形成該導電層。
  18. 如申請專利範圍第15項的方法，其進一步包括：提供囊封體，其覆蓋該引線架之上面安裝了該半導體晶粒的第一表面，並且覆蓋該半導體晶粒。
  19. 一種半導體封裝，其包括：半導體晶粒，其具有第一表面和相對於該第一表面的第二表面，並且包括形成在其第一表面上的第一導電襯墊；引線架，其包括電連接到該半導體晶粒之該第二表面的晶粒襯墊，並且包括與該晶粒襯墊隔開而往外延伸並且電連接到該半導體晶粒之該第一導電襯墊的第一引線；以及導電黏著層，其插置在該引線架的該引線和該第一導電襯墊之間。
  20. 如申請專利範圍第19項的半導體封裝，其進一步包括囊封體，其囊封該半導體晶粒、該晶粒襯墊之上面安裝了該半導體晶粒的第一表面、及該第一引線之連接到該導電襯墊的第一側，其中： 該半導體晶粒包括絕緣閘極雙極電晶體(IGBT)和場效電晶體(FET)中一者而作為高功率半導性裝置；以及該導電黏著層藉由燒結而固化。
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Families Citing this family (7)

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Publication number Priority date Publication date Assignee Title
JP6738020B2 (ja) * 2016-12-09 2020-08-12 豊田合成株式会社 電子装置
US10373895B2 (en) * 2016-12-12 2019-08-06 Infineon Technologies Austria Ag Semiconductor device having die pads with exposed surfaces
EP3608955B1 (en) * 2018-08-07 2022-10-05 Infineon Technologies Austria AG Leadframe, semiconductor package and method
US11049817B2 (en) * 2019-02-25 2021-06-29 Nxp B.V. Semiconductor device with integral EMI shield
US11217511B2 (en) * 2019-04-09 2022-01-04 Infineon Technologies Ag Quad package with conductive clips connected to terminals at upper surface of semiconductor die
EP3872855A1 (de) * 2020-02-27 2021-09-01 Siemens Aktiengesellschaft Substrathalbzeug für eine leistungselektronische baugruppe mit einer leitstruktur mit ausformungen und entsprechendes herstellungsverfahren
US20230245997A1 (en) * 2022-01-31 2023-08-03 International Business Machines Corporation Double resist structure for electrodeposition bonding

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007034893A1 (ja) * 2005-09-22 2007-03-29 Nihon Handa Co., Ltd. ペースト状金属粒子組成物、ペースト状金属粒子組成物の固化方法、金属製部材の接合方法およびプリント配線板の製造方法
US20110115069A1 (en) * 2009-11-13 2011-05-19 Serene Seoh Hian Teh Electronic device including a packaging substrate and an electrical conductor within a via and a process of forming the same
US20120061822A1 (en) * 2010-09-09 2012-03-15 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Base Substrate With Cavities Formed Through Etch-Resistant Conductive Layer for Bump Locking
US20130307144A1 (en) * 2012-05-18 2013-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4141782A (en) * 1978-01-30 1979-02-27 General Dynamics Corporation Bump circuits on tape utilizing chemical milling
KR960006970B1 (ko) * 1993-05-03 1996-05-25 삼성전자주식회사 필름 캐리어 및 그 제조방법
JP3230348B2 (ja) * 1993-09-06 2001-11-19 ソニー株式会社 樹脂封止型半導体装置及びその製造方法
US7200930B2 (en) * 1994-11-15 2007-04-10 Formfactor, Inc. Probe for semiconductor devices
JPH10303231A (ja) * 1997-04-24 1998-11-13 Hitachi Cable Ltd 半導体素子搭載用テープキャリアおよびそのテープキャリアを使用した半導体装置
US6246111B1 (en) * 2000-01-25 2001-06-12 Siliconware Precision Industries Co., Ltd. Universal lead frame type of quad flat non-lead package of semiconductor
JP2001237267A (ja) * 2000-02-24 2001-08-31 Sharp Corp 半導体装置
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
FR2812968B1 (fr) * 2000-08-11 2003-08-01 Thomson Csf Capteur micro-usine avec protection isolante des connexions
FR2812969B1 (fr) * 2000-08-11 2003-08-01 Thomson Csf Capteur micro-usine avec soudure electrolytique et procede de fabrication
JP3735526B2 (ja) * 2000-10-04 2006-01-18 日本電気株式会社 半導体装置及びその製造方法
KR100861511B1 (ko) * 2002-07-24 2008-10-02 삼성테크윈 주식회사 리이드 프레임과 그것을 구비한 반도체 팩키지 및, 반도체팩키지의 제조 방법
US8067823B2 (en) * 2004-11-15 2011-11-29 Stats Chippac, Ltd. Chip scale package having flip chip interconnect on die paddle
US8124459B2 (en) * 2005-04-23 2012-02-28 Stats Chippac Ltd. Bump chip carrier semiconductor package system
US20070117475A1 (en) * 2005-11-23 2007-05-24 Regents Of The University Of California Prevention of Sn whisker growth for high reliability electronic devices
DE102006022254B4 (de) * 2006-05-11 2008-12-11 Infineon Technologies Ag Halbleiterbauteil mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten, Anordnung für eine Mehrzahl von Halbleiterbauteilen und Verfahren zur Herstellung von Halbleiterbauteilen
JP2010171271A (ja) * 2009-01-23 2010-08-05 Renesas Technology Corp 半導体装置およびその製造方法
US8361899B2 (en) * 2010-12-16 2013-01-29 Monolithic Power Systems, Inc. Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing
US20120261689A1 (en) * 2011-04-13 2012-10-18 Bernd Karl Appelt Semiconductor device packages and related methods
US9293338B2 (en) * 2012-11-08 2016-03-22 Nantong Fujitsu Microelectronics Co., Ltd. Semiconductor packaging structure and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007034893A1 (ja) * 2005-09-22 2007-03-29 Nihon Handa Co., Ltd. ペースト状金属粒子組成物、ペースト状金属粒子組成物の固化方法、金属製部材の接合方法およびプリント配線板の製造方法
US20110115069A1 (en) * 2009-11-13 2011-05-19 Serene Seoh Hian Teh Electronic device including a packaging substrate and an electrical conductor within a via and a process of forming the same
US20120061822A1 (en) * 2010-09-09 2012-03-15 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Base Substrate With Cavities Formed Through Etch-Resistant Conductive Layer for Bump Locking
US20130307144A1 (en) * 2012-05-18 2013-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same

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