TWI563606B - Package substrate as well as manufacturing method thereof and semiconductor package as well as manufacturing method thereof - Google Patents

Package substrate as well as manufacturing method thereof and semiconductor package as well as manufacturing method thereof

Info

Publication number
TWI563606B
TWI563606B TW103103468A TW103103468A TWI563606B TW I563606 B TWI563606 B TW I563606B TW 103103468 A TW103103468 A TW 103103468A TW 103103468 A TW103103468 A TW 103103468A TW I563606 B TWI563606 B TW I563606B
Authority
TW
Taiwan
Prior art keywords
manufacturing
well
package
semiconductor package
package substrate
Prior art date
Application number
TW103103468A
Other languages
English (en)
Other versions
TW201530707A (zh
Inventor
Cheng Chia Chiang
Yu Po Wang
Lung Yuan Wang
Chia Kai Shih
Chu Chi Hsu
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW103103468A priority Critical patent/TWI563606B/zh
Priority to CN201410051570.3A priority patent/CN104810339B/zh
Publication of TW201530707A publication Critical patent/TW201530707A/zh
Application granted granted Critical
Publication of TWI563606B publication Critical patent/TWI563606B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
TW103103468A 2014-01-29 2014-01-29 Package substrate as well as manufacturing method thereof and semiconductor package as well as manufacturing method thereof TWI563606B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW103103468A TWI563606B (en) 2014-01-29 2014-01-29 Package substrate as well as manufacturing method thereof and semiconductor package as well as manufacturing method thereof
CN201410051570.3A CN104810339B (zh) 2014-01-29 2014-02-14 封装基板及其制法暨半导体封装件及其制法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103103468A TWI563606B (en) 2014-01-29 2014-01-29 Package substrate as well as manufacturing method thereof and semiconductor package as well as manufacturing method thereof

Publications (2)

Publication Number Publication Date
TW201530707A TW201530707A (zh) 2015-08-01
TWI563606B true TWI563606B (en) 2016-12-21

Family

ID=53695052

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103103468A TWI563606B (en) 2014-01-29 2014-01-29 Package substrate as well as manufacturing method thereof and semiconductor package as well as manufacturing method thereof

Country Status (2)

Country Link
CN (1) CN104810339B (zh)
TW (1) TWI563606B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10515901B2 (en) 2017-09-29 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. InFO-POP structures with TIVs having cavities
CN111243967A (zh) * 2020-02-26 2020-06-05 通富微电子股份有限公司 一种堆叠式封装方法
CN111312698A (zh) * 2020-02-26 2020-06-19 通富微电子股份有限公司 一种堆叠式封装器件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100044860A1 (en) * 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
US20120280377A1 (en) * 2011-05-05 2012-11-08 Byung Tai Do Integrated circuit packaging system with pad connection and method of manufacture thereof
TW201322349A (zh) * 2011-10-19 2013-06-01 Panasonic Corp 半導體封裝的製造方法、半導體封裝、以及半導體裝置
TW201401468A (zh) * 2012-06-20 2014-01-01 Fujitsu Ltd 半導體裝置及半導體裝置的製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US7557452B1 (en) * 2000-06-08 2009-07-07 Micron Technology, Inc. Reinforced, self-aligning conductive structures for semiconductor device components and methods for fabricating same
CN100446232C (zh) * 2005-10-27 2008-12-24 全懋精密科技股份有限公司 倒装片基板的表面结构
JP4842167B2 (ja) * 2007-02-07 2011-12-21 新光電気工業株式会社 多層配線基板の製造方法
CN101533811B (zh) * 2008-03-13 2010-10-20 力成科技股份有限公司 具有硅通孔的半导体芯片构造及其堆叠组合
WO2010056210A1 (en) * 2008-11-17 2010-05-20 Advanpack Solutions Private Limited Semiconductor substrate, package and device and manufacturing methods thereof
US8704354B2 (en) * 2012-03-28 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package structures and methods for forming the same
CN102751267A (zh) * 2012-05-28 2012-10-24 日月光半导体制造股份有限公司 用于堆叠的半导体封装构造及其制造方法
US8981559B2 (en) * 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100044860A1 (en) * 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
US20120280377A1 (en) * 2011-05-05 2012-11-08 Byung Tai Do Integrated circuit packaging system with pad connection and method of manufacture thereof
TW201322349A (zh) * 2011-10-19 2013-06-01 Panasonic Corp 半導體封裝的製造方法、半導體封裝、以及半導體裝置
TW201401468A (zh) * 2012-06-20 2014-01-01 Fujitsu Ltd 半導體裝置及半導體裝置的製造方法

Also Published As

Publication number Publication date
TW201530707A (zh) 2015-08-01
CN104810339B (zh) 2018-09-28
CN104810339A (zh) 2015-07-29

Similar Documents

Publication Publication Date Title
TWI563643B (en) Semiconductor structure and manufacturing method thereof
HK1212101A1 (zh) 製造半導體器件的方法
HK1231630A1 (zh) 半導體器件以及半導體器件的製造方法
EP3379588A4 (en) Semiconductor device manufacturing method
SG10201707563VA (en) Method of manufacturing semiconductor package
SG11201606536XA (en) Semiconductor device and manufacturing method thereof
EP3168862A4 (en) Semiconductor substrate and semiconductor substrate production method
EP3125274A4 (en) Method for manufacturing semiconductor device and semiconductor device
EP3128539A4 (en) Semiconductor device manufacturing method and semiconductor device
HK1223192A1 (zh) 半導體器件及其製造方法
SG10201505824YA (en) Semiconductor device and method of manufacturing the same
EP3279924A4 (en) Semiconductor device manufacturing method
TWI562323B (en) Semiconductor device package and method of manufacturing the same
SG10201605337UA (en) Manufacturing method of semiconductor device
SG11201709671YA (en) Semiconductor device manufacturing method
HK1221204A1 (zh) 包裝體及其製造方法
EP3240015A4 (en) Semiconductor device and semiconductor device manufacturing method
EP3101160A4 (en) Semiconductor substrate manufacturing method
SG11201605542RA (en) Semiconductor substrate, semiconductor device and manufacturing method for semiconductor substrate
TWI563665B (en) Semiconductor device and method of manufacturing the same
GB2556255B (en) Semiconductor device and semiconductor device manufacturing method
TWI560827B (en) Semiconductor package and its carrier structure and method of manufacture
EP3104399A4 (en) Semiconductor device and manufacturing method for semiconductor device
EP3243217A4 (en) Semiconductor package and method of manufacturing the same
SG11201703288UA (en) Resin composition, semiconductor device manufacturing method and semiconductor device