TWI555135B - 製造隔離電容器的方法 - Google Patents
製造隔離電容器的方法 Download PDFInfo
- Publication number
- TWI555135B TWI555135B TW100125494A TW100125494A TWI555135B TW I555135 B TWI555135 B TW I555135B TW 100125494 A TW100125494 A TW 100125494A TW 100125494 A TW100125494 A TW 100125494A TW I555135 B TWI555135 B TW I555135B
- Authority
- TW
- Taiwan
- Prior art keywords
- trenches
- isolation
- deep
- layer
- doped polysilicon
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 title claims description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000012212 insulator Substances 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 45
- 238000002955 isolation Methods 0.000 claims description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 38
- 229920005591 polysilicon Polymers 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000007943 implant Substances 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 238000003491 array Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 2
- 239000011810 insulating material Substances 0.000 claims 1
- 238000005304 joining Methods 0.000 claims 1
- 238000013461 design Methods 0.000 description 73
- 238000003860 storage Methods 0.000 description 11
- 238000012360 testing method Methods 0.000 description 11
- 238000012545 processing Methods 0.000 description 9
- 235000012431 wafers Nutrition 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 238000011960 computer-aided design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000002076 thermal analysis method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
本發明有關一種半導體結構及製造方法,尤其有關一種製造隔離電容器的方法及所產生的結構。
CMOS邏輯裝置的性能藉由使用SOI(絕緣體上矽)基板而大幅改良。而SOI邏輯晶片的進一步改良則藉由集成邏輯晶片中的DRAM隔室(如,SOI上的嵌入式DRAM)來達成。動態隨機存取記憶體(DRAM)是一種隨機存取記憶體的類型,其將每一位元的資料儲存在積體電路的個別電容器中。DRAM的優點是其結構上的簡單性;即每個位僅需要使用一個電晶體及一電容器,而SRAM需要使用六個電晶體。這允許DRAM達到非常高的密度。DRAM單元結構在這幾十年來已成功地縮小為越來越小的尺寸,因而允許降低製造成本及增加DRAM單元結構內的積體度。
儘管DRAM單元結構在這幾十年來已成功地縮小,但DRAM單元結構的縮小並非完全沒有問題。尤其,雖然實際上可針對動態隨機存取記憶體單元結構中的場效電晶體及儲存電容器二者達成此種縮小,但此縮小對於儲存電容器卻是有問題的,因為儲存電容器在大為縮小時可能沒有讓動態隨機存取記憶體單元結構正確操作的適當儲存電容。
然而,要在減少尺寸的情況下維持提高的性能卻變得越來越難。特別是,形成埋藏板電極變得極具挑戰性。例如,由於SOI中的深溝渠電容器,透過越來越小的深溝渠開口進行習用擴散摻雜或植入程序變得非常困難。也就是說,隨著深溝渠的開口變得比較小,變得越來越難將摻雜物植入開口中以從基板材料形成板電極之一。還有,在摻雜程序期間,不需要的植入物也會被植入SOI中。另外,由於深溝渠間的小間隔,DT陣列間的洩漏也會造成問題。此洩漏(即深溝渠間缺少隔離)導致相鄰的電容器同時開啟及關閉。此外,還發現在SOI接合/退火程序後,諸如磷的摻雜物傾向於從長晶層擴散至下伏基板中,因而造成隔離上的問題。
因此,本技術中需要克服上述缺點及限制。
在本發明之第一方面,一種方法包括同時形成複數個深溝渠及圍繞一群組或陣列之該複數個深溝渠的一或多個隔離溝渠通過一SOI及摻雜多晶矽層至一下伏絕緣體層。該方法另外包含用一絕緣體材料加襯該複數個深溝渠及一或多個隔離溝渠。該方法另外包含在該絕緣體材料上用一導電材料填充該複數個深溝渠及一或多個隔離溝渠。該等深溝渠形成深溝渠電容器,及該一或多個隔離溝渠形成一或多個隔離板,其隔離至少一個群組或陣列之該等深溝渠電容器與另一群組或陣列之該等深溝渠電容器。
在本發明之另一方面,一種方法包含在一基板上形成一絕緣體層。該方法另外包含在該絕緣體層上形成一摻雜多晶矽層。該方法另外包含將一絕緣體上矽(SOI)結構接合至該摻雜多晶矽層。該方法另外包含將複數個深溝渠及圍繞一陣列或群組之該複數個深溝渠的一或多個隔離溝渠形成至該摻雜多晶矽層及SOI結構中。該方法另外包含在該等深溝渠及該一或多個隔離溝渠的側壁上形成一絕緣體層。該方法另外包含在該絕緣體層之上形成一導電金屬。
在本發明之又另一方面,一種結構包含在一SOI及n+摻雜多晶矽層中形成之一或多個群組的深溝渠電容器。該等深溝渠電容器包含一絕緣體材料位在該n+摻雜多晶矽層及形成於一溝渠中之一導電板之間並與其直接接觸。該結構另外包含形成於該SOI及n+摻雜多晶矽層中的一或多個深溝渠隔離結構,其使該一或多個群組之深溝渠電容器的至少一個群組與另一群組隔離。
在本發明之另一方面,提供一種具體體現於機器可讀儲存媒體中以設計、製造、或測試積體電路的設計結構。該設計結構包含本發明的結構。在進一步具體實施例中,一種編碼於機器可讀資料儲存媒體上的硬體描述語言(HDL)設計結構包含以下元件:當在電腦輔助設計系統中處理時產生隔離電容器結構(ISC)的機器可執行表示法,其包含本發明的結構。在又進一步具體實施例中,提供一種在電腦輔助設計系統中產生ISC之功能設計模型的方法。該方法包含產生ISC之結構元件的功能表示法。
本發明有關一種半導體結構及製造方法,尤其有關一種製造隔離電容器的方法及所產生的結構。更明確地說,本發明係針對一種使用埋藏隔離板在SOI上製造eDRAM的方法。在具體實施例中,埋藏隔離板為多晶矽板。有利的是,埋藏隔離板在每個陣列或群組的電容器之間提供隔離,同時遏止在n能帶之間的洩漏。本發明亦遏止SOI中不需要的植入物,以及提高勝於習用方法的縮小能力。例如,藉由使用本發明,即可在不用顧慮植入通過較小深溝渠開口的情況下縮小裝置。
圖1顯示根據本發明的起始結構。起始結構包括例如具有氧化物層12的施體基板10。在具體實施例中,施體基板10是矽(SOI)。可使用熟悉本技術者已知的熱氧化程序沈積氧化物12。氧化物12可具有厚度約150 nm;但本發明亦考慮其他尺寸。
圖2顯示離子植入程序。例如,離子植入程序是形成層14的H+離子植入程序。圖1及圖2的結構是熟悉本技術者熟知的習用結構,因而在此不需要另外解說。
圖3顯示根據本發明的另一結構及處理步驟。在圖3中,在基板16上沈積絕緣體層18。絕緣體層18可具有厚度約1000 ;但本發明亦考慮其他尺寸。在具體實施例中,絕緣體層18可以是例如氧化物、氮化物、氧化鉿、高k材料或其他介電材料。在具體實施例中,絕緣體層18用作擴散障壁層,以防止摻雜物擴散至下伏層中。摻雜多晶矽層20沈積在絕緣體層18上。在具體實施例中,摻雜多晶矽層20是N+多晶矽層,其可使用習用的化學汽相沈積程序沈積。摻雜多晶矽層20厚度約4微米。此厚度有利地提供足夠的材料形成深溝渠,同時確保摻雜多晶矽層20可用作電容器板。
使用摻雜多晶矽層20便不需要如習用製程摻雜溝渠結構。還有,藉由使用摻雜多晶矽層20,很容易縮小結構為較小的節點,因為沒有在深溝渠結構內摻雜的另外處理需求。有利的是,摻雜多晶矽層20亦可防止SOI層10中不需要的植入物。
在圖4中,使用習用的接合技術,將圖2及圖3的結構接合一起。例如,圖2的結構可被翻轉過來並使用例如黏著接合技術接合至圖3的結構。因此,在形成摻雜多晶矽層20後,其可直接接合至氧化物層12。在圖5中,使用習用的分割程序分割施體基板10,以形成SOI層10。
在圖6中,使用習用的程序將光阻遮罩22放在SOI層10之上。例如,可使用CVD程序,藉由旋塗沈積光阻遮罩22於沈積在SOI層10上的襯墊薄膜(氧化物/氮化物)之上。在具體實施例中,接著使用習用的微影程序,圖案化光阻遮罩22。例如,可使光阻遮罩22曝光於光,以在其中開啟孔洞。孔洞將與結構中形成的溝渠一致。
在圖7a中,對結構進行蝕刻程序,以同時形成深溝渠24a及24b。在具體實施例中,深溝渠24a圍繞深溝渠24b,藉此隔離深溝渠24b。有利的是,可使用深溝渠24a形成埋藏隔離板(或槽溝),以在每個陣列或群組的電容器之間提供隔離結構,同時遏止陣列間的洩漏。依此方式,可將深溝渠24b形成為用於電容器結構(諸如eDRAM)的隔離板。深溝渠24a應形成延伸至絕緣體層18中,以提供適當的電隔離。在具體實施例中,深溝渠24b可形成於多晶矽層之內(圖7b)或延伸至絕緣體層18以提高電容。還有,在具體實施例中,在同時形成深溝渠24a、24b時,可蝕刻深溝渠24a、24b至相同的深度。
在圖8中,在深溝渠24a、24b中提供絕緣體材料26。更明確地說,深溝渠24a、24b同時用絕緣體材料26加襯,這包括加襯其側壁及底部。在具體實施例中,除了用於形成電容器的其他類型的已知絕緣體材料,絕緣體材料26可以是高k介電質、氮化物或氧化物。在具體實施例中,例如,可以熱生長氧化物。在具體實施例中,絕緣體材料26約100;但本發明亦考慮其他尺寸。絕緣體材料26的厚度應不會夾斷溝渠24a、24b。
在圖9中,例如使用習用的沈積程序,同時用導電材料28填充溝渠24a、24b。在具體實施例中,導電材料係多晶矽層28,其用作導電板以形成溝渠電容器24b1。絕緣體材料26位在多晶矽層28及摻雜多晶矽層20之間並與其直接接觸。在具體實施例中,可使用習用的蝕刻劑或平坦化程序,清除在SOI層10之表面上的任何過多導電材料28。溝渠電容器24b1保持由用作隔離溝槽的隔離板24a1圍繞。
圖10顯示圖9之結構的俯視圖。如圖10所示,隔離板24a1圍繞及隔離溝渠電容器24b1。在具體實施例中,隔離板24a1可形成以圍繞及隔離任何群組或陣列的溝渠電容器24b1。在具體實施例中,溝渠電容器24b1係電連接至電晶體30。
圖11為半導體設計、製造、及/或測試中所用設計程序的流程圖。圖11顯示例如在半導體IC邏輯設計、模擬、測試、布局及製造中使用之示範性設計流程900的方塊圖。設計流程900包括處理設計結構或裝置的程序、機器及/或機制,以產生上述及圖1-10所示設計結構及/或裝置在邏輯上或在功能上等效的表示法。設計流程900所處理及/或產生的設計結構可在機器可讀傳輸或儲存媒體上編碼,其包括資料及/或指令:當在資料處理系統上執行或以其他方式處理時,產生硬體組件、電路、裝置、或系統在邏輯上、結構上、機械上或在功能上等效的表示法。機器包括但不限於:在諸如設計、製造、或模擬電路、組件、裝置、或系統之IC設計程序中使用的任何機器。例如,機器可包括:微影機器、用於產生遮罩(如,電子束曝寫系統)的機器及/或裝備、用於模擬設計結構的電腦或裝備、在製造或測試程序中使用的任何設備、或將設計結構之功能上等效的表示法程式化於任何媒體的任何機器(如,用於程式化可程式閘陣列的機器)。
設計流程900可根據所設計的表示法類型而有所變化。例如,建立特定應用IC(ASIC)的設計流程900不同於設計標準組件的設計流程900,或不同於將設計體現成可程式陣列的設計流程900,可程式陣列例如Altera Inc.或Xilinx Inc.提供的可程式閘陣列(PGA)或場可程式閘陣列(FPGA)。
圖11圖解多個此類設計結構,其包括較佳是由設計程序910處理的輸入設計結構920。設計結構920可以是由設計程序910產生及處理的邏輯模擬設計結構,以產生硬體裝置之邏輯上等效的功能表示法。設計結構920亦可包含或替代地包含資料及/或程式指令:當由設計程序910處理時,產生硬體裝置實體結構的功能表示法。無論是表示功能及/或結構設計特色,均可使用如由核心開發者/設計者實施的電子電腦輔助設計(ECAD)產生設計結構920。當編碼於機器可讀資料傳輸、閘陣列或儲存媒體上時,可由設計程序910內的一或多個硬體及/或軟體模組存取及處理設計結構920,以模擬或在功能上表示電子組件、電路、電子或邏輯模組、設備、裝置、或系統,如圖1-10中所顯示的。因此,設計結構920可包含檔案或其他資料結構,包括人類及/或機器可讀原始碼、編譯結構、及電腦可執行碼結構:當由設計或模擬資料處理系統處理時,在功能上模擬或以其他方式表示硬體邏輯設計的電路或其他層級。此類資料結構可包括硬體描述語言(HDL)設計實體或其他資料結構,其符合及/或相容於低階HDL設計語言(如Verilog及VHDL)、及/或高階設計語言(如C或C++)。
設計程序910較佳是採用及併入硬體及/或軟體模組,以便合成、轉譯、或以其他方式處理圖1-10中所示組件、電路、裝置、或邏輯結構之設計/模擬功能等效物,以產生線路連接表980,其可含有如設計結構920的設計結構。線路連接表980可包含例如編譯或以其他方式處理的資料結構,其表示線路、離散組件、邏輯閘、控制電路、I/O裝置、模型等的清單,線路連接表描述積體電路設計中與其他元件及電路的連接。線路連接表980可使用反覆程序合成,其中根據裝置的設計規格及參數,將線路連接表980重新合成一或多次。如同本文所述的其他設計結構類型,可將線路連接表980記錄於機器可讀資料儲存媒體上或程式化於可程式閘陣列中。媒體可以是非揮發性儲存媒體(如磁碟機或光碟機)、可程式閘陣列、小型快閃記憶體或其他快閃記憶體。此外,或替代地,媒體可以是系統或快取記憶體、緩衝空間、或電氣或光學傳導裝置及工具,資料封包可經由網際網路或其他網路連接的合適構件在這些媒體上傳輸且在其間儲存。
設計程序910包括硬體及軟體模組,用於處理包括線路連接表980的各種輸入資料結構類型。此等資料結構類型例如可駐存在程式庫元件930內且包括一組常用元件、電路、及裝置,包括用於特定製造技術(如,不同的技術節點32 nm、45 nm、90 nm等)的模型、布局及符號表示法。資料結構類型另外包括設計規格940、特徵資料950、驗證資料960、設計規則970、及測試資料檔案985,測試資料檔案包括輸入測試模式、輸出測試結果、及其他測試資訊。設計程序910另外包括例如標準機械設計程序,如應力分析、熱分析、機械事件模擬、程序模擬,用於如鑄造、模製、及模壓形成等作業。在不脫離本發明範疇及精神下,機械設計的一般技術者應明白設計程序910中所使用的可能機械設計工具及應用程式的範圍。設計程序910亦可包括模組用於執行標準電路設計程序,諸如時序分析、驗證、設計規則檢查、配置與布線作業等。
設計程序910採用及併入邏輯及實體設計工具,如HDL編譯器及模擬模型建立工具,以處理設計結構920與所描繪支援資料結構的部分或全部以及任何額外機械設計或資料(若適用),以產生第二設計結構990。
設計結構990以交換機械裝置及結構之資料所使用的資料格式(如,以IGES、DXF、Parasolid XT、JT、DRG、或任何其他儲存或呈現此機械設計結構之合適格式儲存的資訊)駐存於儲存媒體或可程式閘陣列。類似於設計結構920,設計結構990較佳是包含一或多個檔案、資料結構、或其他電腦編碼資料或指令,其駐存於傳輸或資料儲存媒體及在由ECAD系統處理時,產生圖1-10所示本發明之一或多個具體實施例的邏輯上或功能上等效的形式。在一具體實施例中,設計結構990包含編譯、可執行的HDL模擬模型,其在功能上模擬圖1-10所示的裝置。
設計結構990亦可採用交換積體電路之布局資料所使用的資料格式及/或符號資料格式(如,以GDSII(GDS2)、GL1、OASIS、映射檔案、或任何其他儲存此設計資料結構之合適格式儲存的資訊)。設計結構990包含資訊如:符號資料、映射檔案、測試資料檔案、設計內容檔案、製造資料、布局參數、線路、金屬層級、介層、形狀、在生產線中遞送的資料、及製造商或其他設計者/開發者需要的任何其他資料,以產生上述及圖1-10所示的裝置或結構。設計結構990接著進行至階段995,其中(例如)設計結構990:進行至試產(tape-out)、發表以進行製造、送至遮罩廠、送至另一設計廠、送回客戶等。
上述方法可用於製造積體電路晶片。製造商可以原料晶圓的形式(即作為具有多個未封裝晶片的單一晶圓)、作為裸晶、或以封裝形式銷售所產生的積體電路晶片。在封裝形式的情況中,晶片係安裝於單一晶片封裝中(諸如引線已固定於母板的塑膠載板、或其他更高階載板)或安裝於多晶片封裝中(諸如具有表面互連線或埋藏互連線之一者或二者皆有的陶瓷載板)。在任何情況中,晶片接著將與其他晶片、離散電路元件、及/或其他信號處理裝置整合,作為(a)中間產品,諸如母板;或(b)終端產品的部分。終端產品可以是包括積體電路晶片的任何產品,其範圍涵蓋玩具及其他低階應用至具有顯示器、鍵盤、或其他輸入裝置、及中央處理器的進階電腦產品。
本文所用術語僅是為了描述特定具體實施例,而非用來限制本發明。除非文中另外清楚指示,預期本文使用的單數形包括複數形。另應明白,本文用語「包含」及/或「包括」在此說明書中使用時,代表所陳述特徵、整體、步驟、操作、元件及/或組件的存在,但並不排除存在或加入一或多個其他特徵、整體、步驟、操作、元件、組件及/或其群組。
在申請專利範圍中,只要適用,預期所有手段或步驟附加功能元件的對應結構、材料、動作、及等效物,包括任何結合其他如具體主張的主張元件而執行功能的結構、材料、或動作。本發明的說明係為解說與說明的目的而提出,其意不在窮舉式說明或限制本發明於所揭露的形式中。在不脫離本發明範疇及精神下,許多修改及變化對一般技術者將為顯而易見。具體實施例的選擇與說明係為了對本發明的原理及實際應用提出最好的解說,並讓一般技術者瞭解本發明各種具體實施例具有適於所設想特定使用的各種修改。因此,儘管本發明已針對各具體實施例進行說明,但熟習本技術者應明白,本發明可在修改後且在隨附申請專利範圍的精神及範疇之內施行。
10...施體基板/SOI層
12...氧化物層
14...層
16...基板
18...絕緣體層
20...摻雜多晶矽層
22...光阻遮罩
24a...深溝渠
24b...深溝渠
24a1...隔離板
24b1...溝渠電容器
26...絕緣體材料
28...導電材料
30...電晶體
900...設計流程
910...設計程序
920...設計結構
930...程式庫元件
940...設計規格
950...特徵資料
960...驗證資料
970...設計規則
980...線路連接表
985...測試資料檔案
990...第二設計結構
995...階段
本發明在「實施方式」中,參考提出的複數個圖式,利用本發明示範性具體實施例的非限制範例加以說明。
圖1顯示根據本發明諸方面的起始結構;
圖2-9顯示根據本發明諸方面的附加結構及相應的處理步驟;
圖10顯示圖9之結構的俯視圖;及
圖11為半導體設計、製造、及/或測試中所用設計程序的流程圖。
10...SOI層
12...氧化物層
16...基板
18...絕緣體層
20...摻雜多晶矽層
24a1...隔離板
24b1...溝渠電容器
28...導電材料
Claims (10)
- 一種製造隔離電容器的方法,其包含:沉積一絕緣體層於一絕緣體上矽(SOI)結構上;離子植入穿透該絕緣體層,透過該離子植入形成一植入區域於該絕緣體層下方;於該離子植入後,將沉積在該SOI結構上的該絕緣體層接合到形成於一基板上的一摻雜多晶矽層;分離該SOI結構;同時形成複數個深溝渠及圍繞一群組或陣列之該複數個深溝渠的一或多個隔離溝渠通過該SOI及該摻雜多晶矽層至一下伏絕緣體層;用一絕緣體材料加襯該複數個深溝渠及一或多個隔離溝渠;及在該絕緣體材料上用一導電材料填充該複數個深溝渠及一或多個隔離溝渠,其中該等深溝渠形成深溝渠電容器,及該一或多個隔離溝渠形成一或多個隔離板,其隔離至少一個群組或陣列之該等深溝渠電容器與另一群組或陣列之該等深溝渠電容器。
- 如申請專利範圍第1項所述的方法,其中該加襯絕緣體材料係一生長氧化物;或其中該加襯絕緣體材料係氮化物或高k介電質之一沈積。
- 如申請專利範圍第1項所述的方法,其中該導電材料是多晶矽材料。
- 如申請專利範圍第1項所述的方法,其中該摻雜多晶矽層係在形成該複數個深溝渠及一或多個隔離溝渠之前沈積;或其中該摻雜多晶矽層係一n+摻雜多晶矽層。
- 如申請專利範圍第1項所述的方法,其中該SOI係形成於一絕緣體層上,該SOI係接合至該摻雜多晶矽層,其中該摻雜多晶矽層係在該接合之前摻雜;或其中該摻雜多晶矽層係沈積至形成在一下伏基板上的該下伏絕緣體層上,該下伏絕緣體層用作一擴散障壁層;或其中該等深溝渠及一或多個隔離溝渠係在該摻雜多晶矽層內蝕刻至相同的深度。
- 如申請專利範圍第1項所述的方法,其中該等深溝渠電容器連接至電晶體,及該一或多個隔離板保持與該等電晶體隔離。
- 一種製造隔離電容器的方法,包含:沉積一第一絕緣體層於一絕緣體上矽(SOI)結構上;離子植入穿透該第一絕緣體層,透過該離子植入形成一下伏的植入區域於該SOI結構中;形成一第二絕緣體層於一基板上;形成一摻雜多晶矽層於該第二絕緣體層上;於該離子植入後,將該SOI結構的絕緣材料接合至該摻雜多晶矽層;分離該SOI結構;將複數個深溝渠及圍繞一陣列或群組之該複數個深溝渠的一或多個隔離溝渠形成至該摻雜多晶矽層及該SOI結構中; 形成一第三絕緣體層於該等深溝渠及該一或多個隔離溝渠的側壁上;及形成一導電金屬於該絕緣體層之上。
- 如申請專利範圍第7項所述的方法,其中該等深溝渠形成深溝渠電容器,及該一或多個隔離溝渠形成一或多個隔離板,其使該陣列或群組之該等深溝渠電容器互相隔離;或其中該等深溝渠及一或多個隔離溝渠係同時形成;或其中該等深溝渠及一或多個隔離溝渠係形成至相同的深度,該等深溝渠及一或多個隔離溝渠當用該第三絕緣體層及該導電層填充後,形成深溝渠電容器及一或多個陣列的一或多個隔離板,該一或多個隔離板從一或多個隔離溝渠形成,使該陣列的深溝渠電容器互相隔離;或其中該摻雜多晶矽層係在形成該等深溝渠及一或多個隔離溝渠之前形成。
- 如申請專利範圍第7項所述的方法,其中:該第三絕緣體層同時形成於該等深溝渠及該一或多個隔離溝渠的側壁上;及該導電金屬係同時沈積在該等深溝渠及該一或多個隔離溝渠中的該第三絕緣體層之上。
- 如申請專利範圍第7項所述的方法,其中:該摻雜多晶矽層係沈積在該第二絕緣體層上的一n+摻雜多晶矽層,其用作一擴散層;及該n+摻雜多晶矽層係在該接合及形成該複數個深溝渠及一或 多個隔離溝渠、絕緣體層、及導電材料之前沈積。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/838,515 US8652925B2 (en) | 2010-07-19 | 2010-07-19 | Method of fabricating isolated capacitors and structure thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201230254A TW201230254A (en) | 2012-07-16 |
TWI555135B true TWI555135B (zh) | 2016-10-21 |
Family
ID=45466298
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW100125494A TWI555135B (zh) | 2010-07-19 | 2011-07-19 | 製造隔離電容器的方法 |
Country Status (7)
Country | Link |
---|---|
US (4) | US8652925B2 (zh) |
JP (1) | JP5767703B2 (zh) |
CN (1) | CN102986021B (zh) |
DE (1) | DE112011102414B4 (zh) |
GB (1) | GB2495457C (zh) |
TW (1) | TWI555135B (zh) |
WO (1) | WO2012012154A2 (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8652925B2 (en) * | 2010-07-19 | 2014-02-18 | International Business Machines Corporation | Method of fabricating isolated capacitors and structure thereof |
US9171848B2 (en) * | 2013-11-22 | 2015-10-27 | GlobalFoundries, Inc. | Deep trench MIM capacitor and moat isolation with epitaxial semiconductor wafer scheme |
US10134830B2 (en) | 2016-09-13 | 2018-11-20 | Texas Instruments Incorporated | Integrated trench capacitor |
US9991267B1 (en) | 2017-01-25 | 2018-06-05 | International Business Machines Corporation | Forming eDRAM unit cell with VFET and via capacitance |
CN109427785B (zh) * | 2017-08-21 | 2022-09-27 | 联华电子股份有限公司 | 包含电容的装置及其形成方法 |
US10811543B2 (en) | 2018-12-26 | 2020-10-20 | Texas Instruments Incorporated | Semiconductor device with deep trench isolation and trench capacitor |
CN110350026B (zh) * | 2019-07-15 | 2020-12-01 | 中国科学院上海微系统与信息技术研究所 | 一种基于soi衬底的电容隔离结构及其制备方法 |
US11037933B2 (en) * | 2019-07-29 | 2021-06-15 | Nanya Technology Corporation | Semiconductor device with selectively formed insulating segments and method for fabricating the same |
US11605701B2 (en) * | 2020-07-17 | 2023-03-14 | Infineon Technologies Austria Ag | Lateral coreless transformer |
US11183452B1 (en) | 2020-08-12 | 2021-11-23 | Infineon Technologies Austria Ag | Transfering informations across a high voltage gap using capacitive coupling with DTI integrated in silicon technology |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05167031A (ja) * | 1991-12-11 | 1993-07-02 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2006253684A (ja) * | 2005-03-08 | 2006-09-21 | Internatl Business Mach Corp <Ibm> | トレンチ・キャパシタ・アレイを含む構造およびその形成方法(soiチップ用の簡略化した埋込プレート構造およびプロセス) |
Family Cites Families (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4621414A (en) * | 1985-03-04 | 1986-11-11 | Advanced Micro Devices, Inc. | Method of making an isolation slot for integrated circuit structure |
US4816884A (en) | 1987-07-20 | 1989-03-28 | International Business Machines Corporation | High density vertical trench transistor and capacitor memory cell structure and fabrication method therefor |
US5358891A (en) * | 1993-06-29 | 1994-10-25 | Intel Corporation | Trench isolation with planar topography and method of fabrication |
US6004865A (en) * | 1993-09-06 | 1999-12-21 | Hitachi, Ltd. | Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator |
US5411913A (en) * | 1994-04-29 | 1995-05-02 | National Semiconductor Corporation | Simple planarized trench isolation and field oxide formation using poly-silicon |
US5926717A (en) * | 1996-12-10 | 1999-07-20 | Advanced Micro Devices, Inc. | Method of making an integrated circuit with oxidizable trench liner |
US5814547A (en) | 1997-10-06 | 1998-09-29 | Industrial Technology Research Institute | Forming different depth trenches simultaneously by microloading effect |
US6558998B2 (en) * | 1998-06-15 | 2003-05-06 | Marc Belleville | SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit |
JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
US6426252B1 (en) | 1999-10-25 | 2002-07-30 | International Business Machines Corporation | Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap |
IT1317516B1 (it) | 2000-05-11 | 2003-07-09 | St Microelectronics Srl | Dispositivo integrato con struttura d'isolamento a trench e relativoprocesso di realizzazione. |
DE10041748A1 (de) | 2000-08-27 | 2002-03-14 | Infineon Technologies Ag | SOI-Substrat sowie darin ausgebildete Halbleiterschaltung und dazugehörige Herstellungsverfahren |
US6350653B1 (en) | 2000-10-12 | 2002-02-26 | International Business Machines Corporation | Embedded DRAM on silicon-on-insulator substrate |
TW540154B (en) | 2001-06-04 | 2003-07-01 | Promos Technologies Inc | Deep trench capacitor structure and its manufacturing method |
US6737316B2 (en) | 2001-10-30 | 2004-05-18 | Promos Technologies Inc. | Method of forming a deep trench DRAM cell |
US6885080B2 (en) * | 2002-02-22 | 2005-04-26 | International Business Machines Corporation | Deep trench isolation of embedded DRAM for improved latch-up immunity |
US6787838B1 (en) | 2003-06-18 | 2004-09-07 | International Business Machines Corporation | Trench capacitor DRAM cell using buried oxide as array top oxide |
TWI229416B (en) | 2003-10-14 | 2005-03-11 | Promos Technologies Inc | Method of forming deep trench capacitor |
US7084460B2 (en) * | 2003-11-03 | 2006-08-01 | International Business Machines Corporation | Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates |
DE102004003084B3 (de) * | 2004-01-21 | 2005-10-06 | Infineon Technologies Ag | Halbleiterspeicherzelle sowie zugehöriges Herstellungsverfahren |
US7291541B1 (en) * | 2004-03-18 | 2007-11-06 | National Semiconductor Corporation | System and method for providing improved trench isolation of semiconductor devices |
JP4730581B2 (ja) * | 2004-06-17 | 2011-07-20 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
TW200629466A (en) * | 2004-10-14 | 2006-08-16 | Koninkl Philips Electronics Nv | Semiconductor device having a frontside contact and vertical trench isolation and method of fabricating same |
FR2880191B1 (fr) * | 2004-12-23 | 2007-03-16 | St Microelectronics Sa | Realisation de tranchees ou puits ayant des destinations differentes dans un substrat semiconducteur |
JP2006216826A (ja) * | 2005-02-04 | 2006-08-17 | Sumco Corp | Soiウェーハの製造方法 |
US7984408B2 (en) | 2006-04-21 | 2011-07-19 | International Business Machines Corporation | Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering |
US7910455B2 (en) * | 2006-04-27 | 2011-03-22 | Shin-Etsu Handotai Co., Ltd. | Method for producing SOI wafer |
US7880267B2 (en) * | 2006-08-28 | 2011-02-01 | Micron Technology, Inc. | Buried decoupling capacitors, devices and systems including same, and methods of fabrication |
US7791160B2 (en) | 2006-10-19 | 2010-09-07 | International Business Machines Corporation | High-performance FET device layout |
US7892928B2 (en) | 2007-03-23 | 2011-02-22 | International Business Machines Corporation | Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers |
TW200901327A (en) | 2007-06-23 | 2009-01-01 | Nanya Technology Corp | Method of forming self-aligned gates and transistors thereof |
US7681166B2 (en) * | 2007-09-28 | 2010-03-16 | Synopsys, Inc. | Method and apparatus for performing dummy-fill by using a set of dummy-fill cells |
US7951666B2 (en) * | 2007-10-16 | 2011-05-31 | International Business Machines Corporation | Deep trench capacitor and method |
US7955950B2 (en) | 2007-10-18 | 2011-06-07 | International Business Machines Corporation | Semiconductor-on-insulator substrate with a diffusion barrier |
US7888723B2 (en) * | 2008-01-18 | 2011-02-15 | International Business Machines Corporation | Deep trench capacitor in a SOI substrate having a laterally protruding buried strap |
CN101504930B (zh) * | 2008-02-06 | 2013-10-16 | 株式会社半导体能源研究所 | Soi衬底的制造方法 |
US7384842B1 (en) * | 2008-02-14 | 2008-06-10 | International Business Machines Corporation | Methods involving silicon-on-insulator trench memory with implanted plate |
US7955909B2 (en) * | 2008-03-28 | 2011-06-07 | International Business Machines Corporation | Strained ultra-thin SOI transistor formed by replacement gate |
KR100972864B1 (ko) | 2008-05-21 | 2010-07-28 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 및 반도체 메모리 소자의 캐패시터형성방법 |
FR2933234B1 (fr) * | 2008-06-30 | 2016-09-23 | S O I Tec Silicon On Insulator Tech | Substrat bon marche a structure double et procede de fabrication associe |
FR2935538B1 (fr) * | 2008-09-01 | 2010-12-24 | Commissariat Energie Atomique | Substrat pour composant electronique ou electromecanique et nanoelements. |
US8229255B2 (en) | 2008-09-04 | 2012-07-24 | Zena Technologies, Inc. | Optical waveguides in image sensors |
US8101497B2 (en) | 2008-09-11 | 2012-01-24 | Micron Technology, Inc. | Self-aligned trench formation |
JP2010114409A (ja) * | 2008-10-10 | 2010-05-20 | Sony Corp | Soi基板とその製造方法、固体撮像装置とその製造方法、および撮像装置 |
US7951657B2 (en) | 2009-05-21 | 2011-05-31 | International Business Machines Corporation | Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor |
US8222065B1 (en) * | 2009-10-02 | 2012-07-17 | National Semiconductor Corporation | Method and system for forming a capacitive micromachined ultrasonic transducer |
TWI433274B (zh) * | 2009-10-14 | 2014-04-01 | Inotera Memories Inc | 堆疊式動態隨機存取記憶體電容之單邊離子植入製程 |
US8298908B2 (en) * | 2010-02-11 | 2012-10-30 | International Business Machines Corporation | Structure and method for forming isolation and buried plate for trench capacitor |
US20110207306A1 (en) * | 2010-02-22 | 2011-08-25 | Sarko Cherekdjian | Semiconductor structure made using improved ion implantation process |
US8354675B2 (en) * | 2010-05-07 | 2013-01-15 | International Business Machines Corporation | Enhanced capacitance deep trench capacitor for EDRAM |
US8466501B2 (en) | 2010-05-21 | 2013-06-18 | International Business Machines Corporation | Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET |
US8652925B2 (en) | 2010-07-19 | 2014-02-18 | International Business Machines Corporation | Method of fabricating isolated capacitors and structure thereof |
US8196546B1 (en) * | 2010-11-19 | 2012-06-12 | Corning Incorporated | Semiconductor structure made using improved multiple ion implantation process |
-
2010
- 2010-07-19 US US12/838,515 patent/US8652925B2/en active Active
-
2011
- 2011-06-29 JP JP2013520722A patent/JP5767703B2/ja not_active Expired - Fee Related
- 2011-06-29 WO PCT/US2011/042289 patent/WO2012012154A2/en active Application Filing
- 2011-06-29 DE DE112011102414.2T patent/DE112011102414B4/de active Active
- 2011-06-29 CN CN201180033949.6A patent/CN102986021B/zh not_active Expired - Fee Related
- 2011-06-29 GB GB201301679A patent/GB2495457C/en not_active Expired - Fee Related
- 2011-07-19 TW TW100125494A patent/TWI555135B/zh not_active IP Right Cessation
-
2012
- 2012-06-26 US US13/533,099 patent/US8716776B2/en active Active
-
2013
- 2013-11-21 US US14/086,456 patent/US8940617B2/en active Active
-
2014
- 2014-03-31 US US14/230,039 patent/US8963283B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05167031A (ja) * | 1991-12-11 | 1993-07-02 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2006253684A (ja) * | 2005-03-08 | 2006-09-21 | Internatl Business Mach Corp <Ibm> | トレンチ・キャパシタ・アレイを含む構造およびその形成方法(soiチップ用の簡略化した埋込プレート構造およびプロセス) |
Also Published As
Publication number | Publication date |
---|---|
US20120012971A1 (en) | 2012-01-19 |
US8940617B2 (en) | 2015-01-27 |
US8716776B2 (en) | 2014-05-06 |
US8652925B2 (en) | 2014-02-18 |
JP2013535822A (ja) | 2013-09-12 |
TW201230254A (en) | 2012-07-16 |
US20140080281A1 (en) | 2014-03-20 |
GB201301679D0 (en) | 2013-03-13 |
WO2012012154A2 (en) | 2012-01-26 |
US20120267754A1 (en) | 2012-10-25 |
CN102986021A (zh) | 2013-03-20 |
GB2495457A (en) | 2013-04-10 |
GB2495457B (en) | 2014-08-20 |
DE112011102414B4 (de) | 2020-02-27 |
WO2012012154A3 (en) | 2012-04-26 |
US20140210039A1 (en) | 2014-07-31 |
JP5767703B2 (ja) | 2015-08-19 |
GB2495457C (en) | 2014-10-01 |
DE112011102414T5 (de) | 2013-06-06 |
US8963283B2 (en) | 2015-02-24 |
CN102986021B (zh) | 2015-01-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI555135B (zh) | 製造隔離電容器的方法 | |
US10818668B2 (en) | Metal trench capacitor and improved isolation and methods of manufacture | |
US8298906B2 (en) | Trench decoupling capacitor formed by RIE lag of through silicon via (TSV) etch | |
US8674472B2 (en) | Low harmonic RF switch in SOI | |
US8143135B2 (en) | Embedded series deep trench capacitors and methods of manufacture | |
US8836003B2 (en) | Lateral epitaxial grown SOI in deep trench structures and methods of manufacture | |
US9178012B2 (en) | Plated trench capacitor structures | |
US8642440B2 (en) | Capacitor with deep trench ion implantation | |
US8372725B2 (en) | Structures and methods of forming pre fabricated deep trench capacitors for SOI substrates | |
US8492214B2 (en) | Damascene metal gate and shield structure, methods of manufacture and design structures | |
US9006827B2 (en) | Radiation hardened memory cell and design structures |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |