TWI549233B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI549233B
TWI549233B TW103101746A TW103101746A TWI549233B TW I549233 B TWI549233 B TW I549233B TW 103101746 A TW103101746 A TW 103101746A TW 103101746 A TW103101746 A TW 103101746A TW I549233 B TWI549233 B TW I549233B
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Taiwan
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semiconductor package
encapsulant
dielectric
layer
forming
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TW103101746A
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English (en)
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TW201530704A (zh
Inventor
張江城
邱世冠
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矽品精密工業股份有限公司
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Priority to TW103101746A priority Critical patent/TWI549233B/zh
Publication of TW201530704A publication Critical patent/TW201530704A/zh
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Publication of TWI549233B publication Critical patent/TWI549233B/zh

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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

半導體封裝件及其製法
本發明係關於一種半導體封裝件及其製法，詳而言之，係關於一種具有介電質外層之導電通孔之半導體封裝件及其製法。
請參閱第1圖，揭露一種習知半導體封裝件，封裝膠體42包覆具有複數電極墊410之半導體晶片41，該封裝膠體42具有外露該複數電極墊410之第一表面421及相對於該第一表面421之第二表面422，並包含複數貫穿該第一表面421和該第二表面422之穿孔420，該穿孔420中形成有導電通孔43。
該封裝膠體42之第一表面421上形成有第一線路層44及具有複數外露部分該第一線路層44的第一開口440之第一介電層45，於該第一開口440中形成有第二導電元件46。該封裝膠體42之第二表面422上形成有第二線路層47及具有複數外露部分該第二線路層47的第二開口480之第二介電層48，於該第二開口480中形成第一導電元件49。該導電通孔43電性連接該第一線路層44與該第二線路層47。該第一導電元件49上承載另一半導體封裝件5，以構成堆疊封裝結構(Package on Package；POP)。
該導電通孔43之形成係先以雷射對該封裝膠體42鑽一貫穿 該封裝膠體42之穿孔420，再於該穿孔420中電鍍銅，然而，因該封裝膠體42之固有特性，以雷射鑽孔該封裝膠體42容易導致該穿孔420的孔壁不平整與粗糙，而使得電鍍的品質不佳，進而造成導電通孔之電性連接效果不佳。
因此，如何提出一種包括電性良好之導電通孔之半導體封裝件，實為當前急需解決之議題。
為克服習知技術之種種缺失，本發明提供一種半導體封裝件包括：半導體晶片，係具有複數電極墊；封裝膠體，用於包覆該半導體晶片，該封裝膠體具有外露該複數電極墊之第一表面及相對於該第一表面之第二表面，並包含複數形成於該封裝膠體中且貫穿該第一表面和該第二表面之第一穿孔；介電質，形成於該封裝膠體之第一穿孔中及該第二表面上，且該介電質於各該第一穿孔中形成有貫穿該介電質之第二穿孔；導電通孔，形成於各該第二穿孔中；線路重佈層，係形成於該介電質及該導電通孔上；以及電性連接結構，係形成於該封裝膠體之第一表面上且電性連接該半導體晶片，並藉由該導電通孔電性連接該線路重佈層。
本發明復提供一種半導體封裝件之製法包括以下步驟：於第一基板上設置具有複數電極墊之半導體晶片，該電極墊係連接該第一基板；於該第一基板及該半導體晶片上形成封裝膠體，以包覆該半導體晶片；移除該第一基板，以外露該半導體晶片之複數電極墊；於該半導體晶片及該封裝膠體上形成電性連接結構；於該封裝膠體中形成複數貫穿該封裝膠體之第一穿孔，以外露該電性連接結構；於該第一穿孔中及該封裝膠體上形成介電質，並於 各該第一穿孔中形成貫穿該介電質之第二穿孔，以外露該電性連接結構；以及於各該第二穿孔中形成導電通孔，並於該介電質上形成藉由該導電通孔電性連接該電性連接結構之線路重佈層。
由上可知，本發明於介電質之第二穿孔中形成導電通孔，該第二穿孔的孔壁的平整性較佳，藉此提昇導電通孔之電性品質。
10‧‧‧第一基板
11‧‧‧第一膠膜
20‧‧‧第二基板
21‧‧‧第二膠膜
22、41‧‧‧半導體晶片
220、410‧‧‧電極墊
23、42‧‧‧封裝膠體
231、421‧‧‧第一表面
232、422‧‧‧第二表面
230‧‧‧第一穿孔
24‧‧‧第一線路重佈層
24’‧‧‧基板
24”‧‧‧導線架
241‧‧‧內側第一線路層
242‧‧‧外側第一線路層
243、45‧‧‧第一介電層
244、440‧‧‧第一開口
25‧‧‧介電質
250‧‧‧第二穿孔
26、43‧‧‧導電通孔
27‧‧‧第二線路重佈層
271、47‧‧‧第二線路層
272、48‧‧‧第二介電層
273、480‧‧‧第二開口
28、46‧‧‧第二導電元件
29、49‧‧‧第一導電元件
30‧‧‧第三基板
31‧‧‧第三膠膜
3、3’、3”、5‧‧‧另一半導體封裝件
420‧‧‧穿孔
44‧‧‧第一線路層
第1圖係習知半導體封裝件之結構示意圖；第2A至2I圖係本發明之半導體封裝件之製法，其中，第2H圖為本發明之半導體封裝件之結構示意圖；第3圖為堆疊有另一半導體封裝件之本發明之半導體封裝件之實施例示意圖；以及第4圖為堆疊有另一半導體封裝件之本發明之半導體封裝件之另一實施例示意圖。
以下係藉由特定的具體實例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之優點及功效。本發明亦可以其它不同的方式予以實施，即，在不悖離本發明所揭示之範疇下，能予不同之修飾與改變。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。
請參閱第2H圖，其為本發明之半導體封裝件之結構示意圖，包括以下構件。
半導體晶片22係具有複數電極墊220。
封裝膠體23用於包覆該半導體晶片22，並具有外露該複數電極墊220之第一表面231及相對於該第一表面231之第二表面232，該封裝膠體23包含複數貫穿該第一表面231和該第二表面232之第一穿孔230。該第一穿孔230係以雷射鑽孔(laser drilling)方式實現。
介電質25係形成於該封裝膠體23之第一穿孔230中及該第二表面232上，且該介電質25於該第一穿孔230中形成有貫穿該介電質25之第二穿孔250。該第二穿孔250係以雷射鑽孔方式實現。該介電質25係例如為介電質乾膜(dielectric dry film)。
導電通孔26係形成於該第二穿孔250中。該導電通孔26係以在該第二穿孔250中電鍍銅、鋁、金或上述之任意組合來實現。
電性連接結構，於第2H圖中，為第一線路重佈層24，係形成於該封裝膠體23之第一表面231上且電性連接該半導體晶片22。該半導體晶片22係透過覆晶方式電性連接至該第一線路重佈層24，其中，該第一線路重佈層24包括形成於該封裝膠體23的第一表面231上之內側第一線路層241、與該內側第一線路層241電性連接之外側第一線路層242及具有複數外露部分該外側第一線路層242的第一開口244之第一介電層243。又，於該第一開口244中形成有與該外側第一線路層242電性連接之第一導電元件29，如第2I圖所示。第一介電層243之材質可為ABF(Ajinomoto Build-up Film)、BCB(Benzocyclo-buthene)、LCP(Liquid Crystal Polymer)、PI(Poly-imide)、PPE(Poly(phenylene ether))、PTFE(Poly(tetra-fluoroethylene))、FR4、FR5、BT(Bismaleimide Triazine)、芳香尼龍(Aramide)、或混合環氧樹脂玻璃纖維(Glass fiber)。
線路重佈層，於第2H圖中，為第二線路重佈層27，係形成於該介電質25及該導電通孔26上，並藉由該導電通孔26與該第一線路重佈層24電性連接，其中，該第二線路重佈層27包括形成於該介電質25上之第二線路層271及具有複數外露部分該第二線路層271的第二開口273之第二介電層272。於該二開口273中形成有與該第二線路層271電性連接之第二導電元件28。第二介電層272之材質可為ABF(Ajinomoto Build-up Film)、BCB(Benzocyclo-buthene)、LCP(Liquid Crystal Polymer)、PI(Poly-imide)、PPE(Poly(phenylene ether))、PTFE(Poly(tetra-fluoroethylene))、FR4、FR5、BT(Bismaleimide Triazine)、芳香尼龍(Aramide)、或混合環氧樹脂玻璃纖維(Glass fiber)。
此外，該第二導電元件28上可堆疊另一半導體封裝件3，而構成一堆疊封裝結構(Package on Package；POP)，如第2I圖所示。藉此，本發明第2H圖所示之半導體封裝件可作為扇出型堆疊封裝結構(FO-POP；Fan out POP)之下封裝件(base package)。
另外，本發明之半導體裝件之第一線路重佈層24可替換為基板24’，如第3圖所示，本發明之半導體裝件上可承載另一半導體封裝件3’。或者，本發明之半導體裝件之第一線路重佈層24可替換為導線架24”，如第4圖所示，本發明之半導體裝件上可 承載另一半導體封裝件3”。
接著，請參閱第2A至2H圖，其為本發明之半導體封裝件之製法的剖視圖。
如第2A圖所示，於第一基板10上形成第一膠膜11，於該第一膠膜11上設置具有複數電極墊220之半導體晶片22，該電極墊220係連接該第一膠膜11。
如第2B圖所示，於該第一膠膜11及該半導體晶片22上形成一封裝膠體23，以包覆該半導體晶片22；於該封裝膠體23上形成其表面有一第二膠膜21之第二基板20。
如第2C圖所示，移除該第一膠膜11及該第一基板10，以外露該半導體晶片22之複數電極墊220；於該半導體晶片22及該封裝膠體23上形成與該半導體晶片22電性連接之例如為第一線路重佈層24的電性連接結構，其中，該第一線路重佈層24包括形成於該封裝膠體23上之內側第一線路層241、與該內側第一線路層241電性連接之外側第一線路層242及具有複數外露部分該外側第一線路層242的第一開口244之第一介電層243。
如第2D圖所示，於該第一線路重佈層24上形成一其表面有一第三膠膜31之第三基板30，接著移除該第二膠膜21及該第二基板20。
如第2E圖所示，於該封裝膠體23中形成複數貫穿該封裝膠體23之第一穿孔230，以外露出該第一線路重佈層24。例如，該第一穿孔230係以雷射鑽孔方式形成。
如第2F圖所示，於該第一穿孔230中及該封裝膠體23上形成一例如為介電質乾膜之介電質25，及於該第一穿孔230中形成 貫穿該介電質25之第二穿孔250，以外露出該第一線路重佈層24。例如，該第二穿孔250係以雷射鑽孔方式形成。
如第2G圖所示，於該第二穿孔250中形成導電通孔26，於該介電質25上形成藉由該導電通孔26電性連接該第一線路重佈層24之第二線路重佈層27，該第二線路重佈層27包括形成於該介電質25上之第二線路層271及於該第二線路層271上之第二介電層272。該導電通孔26之材質選自銅、鋁、金或前述之任意組合。
如第2H圖所示，於該第二線路層271中形成複數外露部分該第二線路層271之第二開口273，於該第二開口273中形成第二導電元件28。接著，移除該第三膠膜31及該第三基板30。
另外，如第2I圖所示，於該第一開口244中形成第一導電元件29。執行切割(singulation)，並於該第二線路重佈層27上藉由該第二導電元件28設置另一半導體封裝件3，而構成一堆疊封裝結構(Package on Package；POP)。
綜上所述，本發明之半導體封裝件及其製法係於封裝膠體中先形成第一穿孔，再於該第一穿孔中形成介電質乾膜，並於該介電質乾膜中形成第二穿孔，俾於該第二穿孔中形成電性連接電性連接結構(例如實施方式之第一線路重佈層、基板或導線架)與線路重佈層(例如實施方式之第二線路重佈層)之導電通孔，由於該導電通孔之孔壁為該介電質乾膜，故第二穿孔具有較高的平整性，使導電通孔的形成(例如電鍍)品質較佳，藉此避免於堆疊另一半導體封裝件時之信賴性問題。因此，本發明之半導體封裝件可作為扇出型堆疊封裝結構(FO-POP；Fan out POP)之下封裝件 (base package)。
上述實施例僅為例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟悉此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如申請專利範圍所列。
22‧‧‧半導體晶片
220‧‧‧電極墊
23‧‧‧封裝膠體
230‧‧‧第一穿孔
231‧‧‧第一表面
232‧‧‧第二表面
24‧‧‧第一線路重佈層
241‧‧‧內側第一線路層
242‧‧‧外側第一線路層
243‧‧‧第一介電層
244‧‧‧第一開口
25‧‧‧介電質
250‧‧‧第二穿孔
26‧‧‧導電通孔
27‧‧‧第二線路重佈層
271‧‧‧第二線路層
272‧‧‧第二介電層
273‧‧‧第二開口
28‧‧‧第二導電元件

Claims (17)

  1. 一種半導體封裝件，包括：半導體晶片，係具有複數電極墊；封裝膠體，用於包覆該半導體晶片，該封裝膠體具有外露該複數電極墊之第一表面、相對於該第一表面之第二表面、及複數形成於該封裝膠體中且貫穿該第一表面和該第二表面之第一穿孔；介電質，形成於該封裝膠體之該第一穿孔中及該第二表面上，且該介電質於各該第一穿孔中形成有貫穿該介電質之第二穿孔；導電通孔，係形成於各該第二穿孔中；線路重佈層，係形成於該介電質上並電性連接該導電通孔；以及電性連接結構，係形成於該封裝膠體之該第一表面上且電性連接該半導體晶片，並藉由該導電通孔電性連接該線路重佈層。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路重佈層包含形成於該介電質上之第二線路層及具有複數外露部分該第二線路層的第二開口之第二介電層。
  3. 如申請專利範圍第2項所述之半導體封裝件，復包括複數第二導電元件，該第二導電元件係形成於該第二開口中。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該電性連接結構係另一線路重佈層，且該另一線路重佈層包含形成於該封裝膠體的該第一表面上之第一線路層及具有複數外露部分 該第一線路層的第一開口之第一介電層。
  5. 如申請專利範圍第4項所述之半導體封裝件，復包括複數第一導電元件，該第一導電元件係形成於該第一開口中。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該電性連接結構係基板或導線架。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該導電通孔之主要材質選自銅、鋁、金或上述之任意組合。
  8. 如申請專利範圍第1項所述之半導體封裝件，其中，該半導體晶片係透過覆晶方式電性連接至該電性連接結構。
  9. 一種半導體封裝件之製法，包括以下步驟：於第一基板上設置具有複數電極墊之半導體晶片，該電極墊係連接該第一基板；於該第一基板及該半導體晶片上形成封裝膠體，以包覆該半導體晶片；移除該第一基板，以外露該半導體晶片之複數電極墊；於該半導體晶片及該封裝膠體上形成電性連接結構；於該封裝膠體中形成複數貫穿該封裝膠體之第一穿孔，以外露該電性連接結構；於該第一穿孔中及該封裝膠體上形成介電質，並於各該第一穿孔中形成貫穿該介電質之第二穿孔，以外露該電性連接結構；以及於各該第二穿孔中形成導電通孔，並於該介電質上形成藉由該導電通孔電性連接該電性連接結構之線路重佈層。
  10. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，於 該介電質上形成線路重佈層之步驟包括：於該介電質上形成第二線路層及具有外露部分該第二線路層的第二開口之第二介電層。
  11. 如申請專利範圍第10項所述之半導體封裝件之製法，復包括於該第二開口中形成第二導電元件。
  12. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，於該半導體晶片及該封裝膠體上形成電性連接結構之步驟包括：於該半導體晶片及該封裝膠體上形成第一線路層及具有外露部分該第一線路層的第一開口之第一介電層。
  13. 如申請專利範圍第12項所述之半導體封裝件之製法，復包括於該第一開口中形成第一導電元件。
  14. 如申請專利範圍第9項所述之半導體封裝件之製法，於移除該第一基板之前，復包括於該封裝膠體上接置第二基板，並於形成該電性連接結構之後，復包括於該電性連接結構上接置第三基板並移除該第二基板，且於形成該線路重佈層之後，復包括移除該第三基板。
  15. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該第一穿孔或該第二穿孔係以雷射鑽孔方式形成。
  16. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該導電通孔之主要材質選自銅、鋁、金或上述之任意組合。
  17. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該電性連接結構係另一基板或導線架。
TW103101746A 2014-01-17 2014-01-17 半導體封裝件及其製法 TWI549233B (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201110285A (en) * 2009-09-08 2011-03-16 Unimicron Technology Corp Package structure having embedded semiconductor element and method of forming the same
TW201250980A (en) * 2011-05-30 2012-12-16 Samsung Electronics Co Ltd Semiconductor device, semiconductor package, and electronic device
US20130009308A1 (en) * 2011-07-06 2013-01-10 Heung-Kyu Kwon Semiconductor stack package apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201110285A (en) * 2009-09-08 2011-03-16 Unimicron Technology Corp Package structure having embedded semiconductor element and method of forming the same
TW201250980A (en) * 2011-05-30 2012-12-16 Samsung Electronics Co Ltd Semiconductor device, semiconductor package, and electronic device
US20130009308A1 (en) * 2011-07-06 2013-01-10 Heung-Kyu Kwon Semiconductor stack package apparatus

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