TWI547224B - Circuit board with electroplated type and manufacturing method thereof - Google Patents

Circuit board with electroplated type and manufacturing method thereof Download PDF

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TWI547224B
TWI547224B TW103101838A TW103101838A TWI547224B TW I547224 B TWI547224 B TW I547224B TW 103101838 A TW103101838 A TW 103101838A TW 103101838 A TW103101838 A TW 103101838A TW I547224 B TWI547224 B TW I547224B
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conductive layer
hole
substrate
circuit board
conductor
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TW103101838A
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TW201531190A (en
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李建成
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先豐通訊股份有限公司
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Description

電鍍式電路板結構及其製造方法 Electroplated circuit board structure and manufacturing method thereof

本發明是有關一種電路板結構及其製造方法,且特別是有關於一種電鍍式電路板結構及其製造方法。 The present invention relates to a circuit board structure and a method of fabricating the same, and more particularly to a plated circuit board structure and a method of fabricating the same.

一般電路板的基板多是利用絕緣紙、玻璃纖維布、或其他纖維材料經半固化樹脂(prepreg)疊合而成的積層板。該基板在高溫高壓下能於單面或雙面覆加銅膜,而後於將銅膜成形為所需之電路布局。 Generally, the substrate of the circuit board is a laminate which is laminated with a semi-cured resin (prepreg) using insulating paper, glass fiber cloth, or other fibrous material. The substrate can be coated with a copper film on one or both sides under high temperature and high pressure, and then the copper film is formed into a desired circuit layout.

現今的電路板之電路布局已能透過蝕刻方式在基板的單面上製作不同厚度之電路,進一步地說,所述基板的表面上須設有一厚銅箔,並將厚銅箔蝕刻成形所述之厚電路,再將厚銅箔其餘部位蝕刻降低其厚度,藉以成形所需之薄電路。 The circuit layout of today's circuit boards has been able to fabricate circuits of different thicknesses on one side of the substrate by etching. Further, a thick copper foil is required on the surface of the substrate, and the thick copper foil is etched into the surface. The thick circuit then etches the rest of the thick copper foil to reduce its thickness, thereby forming the thin circuit required.

然而,上述電路製作方式是屬於業界俗稱的減法技術,其在製作不同厚度之電路的過程中,將耗費大量的高價金屬,且反覆實施的蝕刻製程需耗費較多資源,亦會產生大量的汙染。更重要的是,上述電路製作方式所形成的不同厚度之電路,其在電路板表面將呈現顯著的高低落差,進而影響後續之表面處理與加工,甚至影響元件之裝配。 However, the above-mentioned circuit fabrication method is a commonly known subtraction technology in the industry. In the process of fabricating circuits of different thicknesses, a large amount of high-priced metal is consumed, and the etching process to be repeatedly performed requires a lot of resources, and a large amount of pollution is generated. . More importantly, the circuit of different thickness formed by the above circuit manufacturing method will exhibit a significant difference in the surface of the circuit board, thereby affecting the subsequent surface treatment and processing, and even affecting the assembly of components.

於是,本發明人有感上述缺失之可改善,乃特潛心研究並配合學理之運用,終於提出一種設計合理且有效改善上述缺失之本發明。 Therefore, the present inventors have felt that the above-mentioned deficiencies can be improved, and they have devoted themselves to research and cooperated with the application of the theory, and finally proposed a present invention which is reasonable in design and effective in improving the above-mentioned defects.

本發明目的在於提供一種電鍍式電路板結構及其製造方法,其經由加法技術而能使第一導電層外表面位於同平面的前提下,成形至少兩種不同厚度的電路。 SUMMARY OF THE INVENTION It is an object of the present invention to provide a plated circuit board structure and a method of fabricating the same, which can form at least two circuits of different thicknesses under the premise that the outer surface of the first conductive layer is in the same plane via an additive technique.

本發明提供一種電鍍式電路板結構的製造方法,其步驟包括:提供一板材,其中,該板材包含有一基板與一第一導電層,該基板具有位於相反側的一第一表面與一第二表面,該第一導電層位於該第一表面上,且該第一導電層的厚度小於該第一表面與該第二表面之間的距離;以一非化學蝕刻方式加工於該基板的第二表面,使該基板成形有一貫穿該第一表面與該第二表面的貫孔,而該貫孔對應於該基板第一表面之部位被該第一導電層所遮蔽;以一電鍍方式在該基板貫孔處充填成形一傳導體,且該傳導體的厚度大於該第一導電層的厚度;以及蝕刻該第一導電層以成形為相互分離的一第一線路與一第二線路,且該第一線路一體連接於該傳導體。再者,本發明亦提供一種如上述電鍍式電路板結構的製造方法所製造形成的電鍍式電路板結構。 The present invention provides a method of fabricating a plated circuit board structure, the method comprising: providing a board, wherein the board comprises a substrate and a first conductive layer, the substrate having a first surface and a second on opposite sides a surface, the first conductive layer is located on the first surface, and the first conductive layer has a thickness smaller than a distance between the first surface and the second surface; and processed in a non-chemically etched manner on the substrate Forming a through hole through the first surface and the second surface, and the portion of the through hole corresponding to the first surface of the substrate is shielded by the first conductive layer; Forming a conductor at the through hole, and the thickness of the conductor is greater than a thickness of the first conductive layer; and etching the first conductive layer to form a first line and a second line separated from each other, and the first A line is integrally connected to the conductor. Furthermore, the present invention also provides a plated circuit board structure manufactured by the above-described method for manufacturing a plated circuit board structure.

本發明又提供一種電鍍式電路板結構的製造方法,其步驟包括:提供一基板,其中,該基板具有位於相反側的一第一表面與一第二表面;以一非化學蝕刻方式加工於該基板,使該基板形成有一貫穿該第一表面與該第二表面的貫孔;將一第一導電層設在該基板的第一表面上,其中,該第一導電層的厚度小於該第一表面與該第二表面之間的距離,且該貫孔對應於該基板第一表面之部位被該第一導電層所遮蔽;以一電鍍方式在該基板貫孔處充填成形一傳導體,且該傳導體的厚度大於該第一導電層的厚度;以及蝕刻該第一導電層以成形為相互分離的一第一線路與一第二線路,且該第一線路一體連接於該傳導體。再者,本發明亦提供一種如上述電鍍式電路板結構的製造方法所製造形成的電鍍式電路板結構。 The present invention further provides a method for fabricating a plated circuit board structure, the method comprising: providing a substrate, wherein the substrate has a first surface and a second surface on opposite sides; the non-chemical etching process is performed on the substrate a substrate, the substrate is formed with a through hole penetrating the first surface and the second surface; a first conductive layer is disposed on the first surface of the substrate, wherein the first conductive layer has a thickness smaller than the first a distance between the surface and the second surface, and the portion of the through hole corresponding to the first surface of the substrate is shielded by the first conductive layer; a conductive body is filled at the through hole of the substrate by electroplating, and The conductor has a thickness greater than a thickness of the first conductive layer; and the first conductive layer is etched to form a first line and a second line separated from each other, and the first line is integrally connected to the conductor. Furthermore, the present invention also provides a plated circuit board structure manufactured by the above-described method for manufacturing a plated circuit board structure.

綜上所述,本發明所提供的電鍍式電路板結構及其製造方法,透過加法技術,使得電鍍式電路板結構能在第一導電層外表面位於同平面的前提下,成形至少兩種不同厚度的電路,藉以有效達到節省材料成本、避免浪費高價金屬、以及降低汙染源等功效。 In summary, the electroplated circuit board structure and the manufacturing method thereof provided by the present invention enable the electroplated circuit board structure to form at least two different conditions on the premise that the outer surface of the first conductive layer is in the same plane by the addition technique. Thickness of the circuit, in order to effectively save material costs, avoid wasting high-priced metals, and reduce pollution sources.

為使能更進一步瞭解本發明之特徵及技術內容,請參閱以下有關本發明之詳細說明與附圖,但是此等說明與所附圖式僅係用來說明本發明,而非對本發明的權利範圍作任何的限制。 The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

100‧‧‧電鍍式電路板結構 100‧‧‧Electroplated circuit board structure

1‧‧‧板材 1‧‧‧ plates

11‧‧‧基板 11‧‧‧Substrate

111‧‧‧第一表面 111‧‧‧ first surface

112‧‧‧第二表面 112‧‧‧ second surface

1121‧‧‧預留區域 1121‧‧‧ Reserved area

113‧‧‧貫孔 113‧‧‧through holes

114‧‧‧孔壁 114‧‧‧ hole wall

12‧‧‧第一導電層 12‧‧‧First conductive layer

121‧‧‧第一線路 121‧‧‧First line

122‧‧‧第二線路 122‧‧‧second line

13‧‧‧第二導電層 13‧‧‧Second conductive layer

131‧‧‧開孔 131‧‧‧ openings

14‧‧‧黏著層 14‧‧‧Adhesive layer

2‧‧‧傳導體 2‧‧‧ Conductor

3‧‧‧第一遮罩層 3‧‧‧First mask layer

4‧‧‧第二遮罩層 4‧‧‧Second mask layer

圖1為本發明第一實施例中步驟S101的示意圖。 FIG. 1 is a schematic diagram of step S101 in the first embodiment of the present invention.

圖2為本發明第一實施例中步驟S103的示意圖(一)。 FIG. 2 is a schematic diagram (1) of step S103 in the first embodiment of the present invention.

圖3為本發明第一實施例中步驟S103的示意圖(二)。 FIG. 3 is a schematic diagram (2) of step S103 in the first embodiment of the present invention.

圖4A為本發明第一實施例中步驟S105的示意圖(一)。 4A is a schematic view (1) of step S105 in the first embodiment of the present invention.

圖4B為本發明第一實施例中步驟S107的示意圖(一)。 FIG. 4B is a schematic diagram (1) of step S107 in the first embodiment of the present invention.

圖5A為本發明第一實施例中步驟S105的示意圖(二)。 FIG. 5A is a schematic diagram (2) of step S105 in the first embodiment of the present invention.

圖5B為本發明第一實施例中步驟S107的示意圖(二)。 FIG. 5B is a schematic diagram (2) of step S107 in the first embodiment of the present invention.

圖6為本發明第二實施例中步驟S201~S205的示意圖。 FIG. 6 is a schematic diagram of steps S201 to S205 in the second embodiment of the present invention.

圖7為本發明第三實施例中步驟S301的示意圖。 FIG. 7 is a schematic diagram of step S301 in the third embodiment of the present invention.

圖8為本發明第三實施例中步驟S303的示意圖。 FIG. 8 is a schematic diagram of step S303 in the third embodiment of the present invention.

圖9為本發明第三實施例中步驟S305的示意圖。 Figure 9 is a schematic diagram of step S305 in the third embodiment of the present invention.

圖10為本發明第三實施例中步驟S307的示意圖。 Figure 10 is a schematic diagram of step S307 in the third embodiment of the present invention.

圖11為本發明第三實施例中步驟S309的示意圖(一)。 Figure 11 is a schematic view (1) of step S309 in the third embodiment of the present invention.

圖12為本發明第三實施例中步驟S309的示意圖(二)。 Figure 12 is a schematic view (2) of step S309 in the third embodiment of the present invention.

[第一實施例] [First Embodiment]

請參閱圖1至圖5B,其為本發明的第一實施例,需先說明的是,本實施例對應圖式所提及之相關數量,僅用以具體地說明實施方式,以便於了解其內容,而非用以侷限本發明的權利範圍。 再者,本實施例中的相關圖式是以局部區塊作為示意說明之用。本實施例提供一種電鍍式電路板結構的製造方法,其步驟大致如下所述。 Please refer to FIG. 1 to FIG. 5B , which are the first embodiment of the present invention. It should be noted that the related quantity mentioned in the embodiment corresponds to the embodiment, and only the embodiment is specifically described to facilitate understanding thereof. The content is not intended to limit the scope of the invention. Furthermore, the correlation diagram in this embodiment is a partial block as a schematic description. This embodiment provides a method of manufacturing a plated circuit board structure, the steps of which are substantially as follows.

步驟S101:請參閱圖1所示,提供一板材1,其中,所述板材1包含有一基板11與一第一導電層12。上述基板11具有位於相反側的一第一表面111與一第二表面112,並且第一導電層12位於基板11的第一表面111上,而第一導電層12的厚度小於第一表面111與第二表面112之間的距離(亦即,第一導電層12的厚度小於基板11的厚度)。 Step S101: Referring to FIG. 1, a board 1 is provided, wherein the board 1 comprises a substrate 11 and a first conductive layer 12. The substrate 11 has a first surface 111 and a second surface 112 on opposite sides, and the first conductive layer 12 is located on the first surface 111 of the substrate 11, and the first conductive layer 12 has a smaller thickness than the first surface 111 and The distance between the second surfaces 112 (that is, the thickness of the first conductive layer 12 is less than the thickness of the substrate 11).

更詳細地說,基板11通常是以預浸材料層(Preimpregnated Material)來形成,依照不同的增強材料來分,預浸材料層可以是玻璃纖維預浸材(Glass fiber prepreg)、碳纖維預浸材(Carbon fiber prepreg)、環氧樹脂(Epoxy resin)等材料。不過,基板11也可以是以軟板材料來形成,也就是說,基板11大部分是由聚脂材料(Polyester,PET)或者是聚醯亞胺樹脂(Polyimide,PI)所組成而沒有含玻璃纖維、碳纖維等。然而,本發明並不對基板11的材料加以限定。 In more detail, the substrate 11 is usually formed of a preimpregnated material, and the prepreg layer may be a glass fiber prepreg or a carbon fiber prepreg according to different reinforcing materials. (Carbon fiber prepreg), epoxy resin (Epoxy resin) and other materials. However, the substrate 11 may also be formed of a soft board material, that is, the substrate 11 is mostly composed of a polyester material (Polyester, PET) or a polyimide (PI) without glass. Fiber, carbon fiber, etc. However, the present invention does not limit the material of the substrate 11.

再者,所述第一導電層12是由金屬薄片形成,而金屬薄片例如是銅箔片(copper foil)。有關第一導電層12的選用較佳為2盎司以下,亦即,第一導電層12的厚度較佳為70μm以下。板材1厚度較佳為大於140μm且小於700μm。然而,以上為本實施例所選用之板材1的相關說明,但於實際應用時,板材1的種類不受限於本實施例之條件。 Furthermore, the first conductive layer 12 is formed of a metal foil, and the metal foil is, for example, a copper foil. The selection of the first conductive layer 12 is preferably 2 ounces or less, that is, the thickness of the first conductive layer 12 is preferably 70 μm or less. The thickness of the sheet 1 is preferably greater than 140 μm and less than 700 μm. However, the above description of the sheet material 1 selected for the present embodiment is not limited to the conditions of the present embodiment in practical use.

步驟S103:請參閱圖2所示,以一非化學蝕刻方式加工於所述基板11的第二表面112,使基板11成形有一貫穿第一表面111與第二表面112的長條狀貫孔113,而上述貫孔113對應於基板11第一表面111之部位被第一導電層12所遮蔽。亦即,在成形貫孔113的過程中,須使第一導電層12能自貫孔113而暴露於外。 Step S103: Referring to FIG. 2, the second surface 112 of the substrate 11 is processed by a non-chemical etching method, and the substrate 11 is formed with a long through hole 113 penetrating through the first surface 111 and the second surface 112. The portion of the through hole 113 corresponding to the first surface 111 of the substrate 11 is shielded by the first conductive layer 12. That is, the first conductive layer 12 must be exposed from the through hole 113 during the formation of the through hole 113.

進一步地說,經由上述非化學蝕刻方式加工於基板11的第二表面112後,成形包圍定義出上述貫孔113的一孔壁114。其中,所述孔壁114整體垂直於第一導電層12,也就是說,孔壁114的相反兩端緣(如圖2中的孔壁114底端緣與頂端緣)分別垂直於基板11的第一表面111與第二表面112。 Further, after being processed on the second surface 112 of the substrate 11 by the non-chemical etching method, a hole wall 114 defining the through hole 113 is formed. Wherein, the hole wall 114 is entirely perpendicular to the first conductive layer 12, that is, the opposite end edges of the hole wall 114 (such as the bottom end edge and the top edge of the hole wall 114 in FIG. 2) are perpendicular to the substrate 11 respectively. The first surface 111 and the second surface 112.

再者,在成形貫孔113的過程中,貫孔113的深寬比與外型能依據設計者的需求而控制與調整。舉例來說,在成形貫孔113時,能如圖3所示,使貫孔113的深度大於貫孔113的寬度,並且可將貫孔113成形為細長條狀。 Moreover, in the process of forming the through hole 113, the aspect ratio and the shape of the through hole 113 can be controlled and adjusted according to the needs of the designer. For example, when the through hole 113 is formed, as shown in FIG. 3, the depth of the through hole 113 can be made larger than the width of the through hole 113, and the through hole 113 can be formed into an elongated strip shape.

需附帶說明的是,上述形成貫孔113的非化學蝕刻方式可以包括雷射鑽孔、電漿蝕刻、或銑床等方式。更詳細地說,以雷射鑽孔方式自第二表面112向下燒蝕基板11,據以形成貫孔113。或者,也可以運用銑床的方式自第二表面112向下加工,據以形成貫孔113。除此之外,貫孔113也可以是先以銑床的方式向下去除部分的基板11,然後再以雷射鑽孔的方式繼續去除基板11,據以形成貫孔113。而後,可以藉由化學方法以去除貫孔113內殘留於第一導電層12表面的基板11。 It should be noted that the non-chemical etching method for forming the through holes 113 may include laser drilling, plasma etching, or milling. In more detail, the substrate 11 is ablated downward from the second surface 112 by laser drilling to form a through hole 113. Alternatively, it may be processed from the second surface 112 by means of a milling machine to form a through hole 113. In addition, the through hole 113 may also remove a portion of the substrate 11 downward by a milling machine, and then continue to remove the substrate 11 by laser drilling, thereby forming a through hole 113. Then, the substrate 11 remaining in the surface of the first conductive layer 12 in the through hole 113 can be removed by a chemical method.

步驟S105:請參閱圖4A和圖5A所示,以一電鍍(plating)方式在上述基板11貫孔113處充填成形一傳導體2,並且上述傳導體2的厚度大於第一導電層12的厚度。其中,所述電鍍方式是指將金屬離子(如:銅離子)鍍設於貫孔113內,據以形成實心的傳導體2。須說明的是,在電鍍之前,先成形一遮罩層(圖略)覆蓋於第一導電層12,藉以防止金屬離子附著於第一導電層12之上;而在電鍍完成後,去除上述遮罩層。 Step S105: Referring to FIG. 4A and FIG. 5A, a conductor 2 is formed by filling in the through hole 113 of the substrate 11 by a plating method, and the thickness of the conductor 2 is greater than the thickness of the first conductive layer 12. . The plating method refers to plating metal ions (eg, copper ions) into the through holes 113 to form a solid conductor 2 . It should be noted that before the electroplating, a mask layer (not shown) is formed on the first conductive layer 12 to prevent metal ions from adhering to the first conductive layer 12; and after the electroplating is completed, the mask is removed. Cover layer.

更詳細地說,在基板11貫孔113處實施電鍍的過程中,能直至傳導體2的外表面齊平於基板11的第二表面112(如圖4A),或者,直至傳導體2的外表面突出於基板11的第二表面112(如圖5A)。或者,以其他方式而使傳導體2達到預定之高度,然而,傳 導體2所形成的高度並不受限於此。須說明的是,圖5A所示之傳導體2亦可依設計者需求而進行磨刷處理,以使傳導體2形成如同圖4A所示之外表面平整的傳導體2。 In more detail, during the plating process at the through hole 113 of the substrate 11, it is possible until the outer surface of the conductor 2 is flush with the second surface 112 of the substrate 11 (as shown in FIG. 4A), or until the outside of the conductor 2 The surface protrudes from the second surface 112 of the substrate 11 (as in Figure 5A). Or, in other ways, the conductor 2 is brought to a predetermined height, however, The height at which the conductor 2 is formed is not limited to this. It should be noted that the conductor 2 shown in FIG. 5A can also be subjected to a rubbing treatment according to the designer's requirements, so that the conductor 2 forms a conductor 2 having a flat surface as shown in FIG. 4A.

步驟S107:請參閱圖4B和圖5B所示,蝕刻所述第一導電層12以成形為相互分離的一第一線路121與一第二線路122,且第一線路121一體連接於傳導體2。 Step S107: Referring to FIG. 4B and FIG. 5B, the first conductive layer 12 is etched to form a first line 121 and a second line 122 which are separated from each other, and the first line 121 is integrally connected to the conductor 2 .

補充說明一點,本實施例所述之各個步驟,在合理的情況下是能將步驟之順序加以調整,換言之,本實施例並不以上述的步驟順序為限。 It should be noted that, in the respective steps described in this embodiment, the order of the steps can be adjusted under reasonable circumstances. In other words, the present embodiment is not limited to the above-described sequence of steps.

綜上所述,本實施例提供一種經由上述步驟所製造形成的電鍍式電路板結構100。須說明的是,透過本實施例之步驟S101~S107所載之加法技術,使得所述電鍍式電路板結構100能在第一導電層12外表面位於同平面的前提下,成形至少兩種不同厚度的電路(如:連接傳導體2的第一線路121、第二線路122)。藉此,本實施例之方法能有效達到節省材料成本、避免浪費高價金屬、以及降低汙染源等功效。 In summary, the embodiment provides a plated circuit board structure 100 formed through the above steps. It should be noted that, by the adding technique of steps S101 to S107 of the embodiment, the plated circuit board structure 100 can be formed into at least two different conditions on the premise that the outer surface of the first conductive layer 12 is on the same plane. A circuit of thickness (eg, a first line 121 connecting the conductor 2, a second line 122). Thereby, the method of the embodiment can effectively achieve the effects of saving material cost, avoiding waste of high-priced metals, and reducing pollution sources.

而於所述電鍍式電路板結構100應用時,連接傳導體2的第一線路121(即較厚之電路)能用以傳送大功率之驅動電流,藉以降低驅動電流之阻抗,進而避免電路燒毀或因過熱而降低運作效能。再者,連接傳導體2的第一線路121亦能用以作為熱能排放通道,使得所述電鍍式電路板結構100得以長效維持應有的工作效能。另,第二線路122(即較薄之電路)能用以作為控制訊號傳遞之用。 When the electroplated circuit board structure 100 is applied, the first line 121 (ie, the thicker circuit) connecting the conductor 2 can be used to transmit a high-power driving current, thereby reducing the impedance of the driving current, thereby avoiding the circuit burning. Or reduce operating efficiency due to overheating. Furthermore, the first line 121 connecting the conductors 2 can also be used as a heat energy discharge channel, so that the plated circuit board structure 100 can be used to maintain the desired working efficiency for a long time. In addition, the second line 122 (ie, the thinner circuit) can be used for control signal transmission.

此外,本實施例所述之電鍍式電路板結構100亦能與各式電路板結構進行疊板(lay-up)製程,而所述疊板製程屬於習用技術,因此,本實施例不針對疊板製程加以贅述。 In addition, the plated circuit board structure 100 of the embodiment can also be subjected to a lay-up process with various circuit board structures, and the stack process is a conventional technique. Therefore, the embodiment is not for the stack. The board process is described in detail.

[第二實施例] [Second embodiment]

請參閱圖6,其為本發明的第二實施例,本實施例與第一實施例類似,相同處則不再複述,而兩者的差異特徵主要在於:板材1是運用增層法製程來形成,具體而言,本實施例所提供之電鍍式電路板結構的製造方法,包括步驟如下:步驟S201:提供一基板11,其中,基板11具有位於相反側的一第一表面111與一第二表面112。 Please refer to FIG. 6 , which is a second embodiment of the present invention. This embodiment is similar to the first embodiment, and the same points are not repeated. The difference between the two is mainly because the sheet 1 is processed by a build-up process. Forming, in particular, the manufacturing method of the electroplated circuit board structure provided by the embodiment includes the following steps: Step S201: providing a substrate 11 having a first surface 111 and a first surface on opposite sides Two surfaces 112.

步驟S203:以一非化學蝕刻方式加工於基板11,使基板11形成有一貫穿第一表面111與第二表面112的貫孔113。 Step S203: processing the substrate 11 in a non-chemical etching manner, so that the substrate 11 is formed with a through hole 113 penetrating the first surface 111 and the second surface 112.

步驟S205:將一第一導電層12透過一黏著層14(如:半固化樹脂)而設在(如:高溫壓合)基板11的第一表面111上,其中,第一導電層12的厚度小於第一表面111與第二表面112之間的距離,且貫孔113對應於基板11第一表面111之部位被第一導電層12所遮蔽。再者,黏著層14的輪廓大致切齊基板11的輪廓。 Step S205: A first conductive layer 12 is disposed on the first surface 111 of the substrate 11 (eg, high temperature bonding) through an adhesive layer 14 (eg, a semi-cured resin), wherein the thickness of the first conductive layer 12 It is smaller than the distance between the first surface 111 and the second surface 112, and the portion of the through hole 113 corresponding to the first surface 111 of the substrate 11 is shielded by the first conductive layer 12. Furthermore, the contour of the adhesive layer 14 is substantially aligned with the contour of the substrate 11.

本實施例於步驟S205之後,接續第一實施例的步驟S105和步驟S107,因此,有關本實施例於步驟S205之後的相關步驟在此不加以複述。補充說明一點,本實施例所述之各個步驟,在合理的情況下是能將步驟之順序加以調整,換言之,本實施例並不以上述的步驟順序為限。 After the step S205, the step S105 and the step S107 of the first embodiment are continued. Therefore, the related steps after the step S205 in this embodiment are not repeated herein. It should be noted that, in the respective steps described in this embodiment, the order of the steps can be adjusted under reasonable circumstances. In other words, the present embodiment is not limited to the above-described sequence of steps.

綜上所述,本實施例提供一種經由上述步驟所製造形成的電鍍式電路板結構。 In summary, the embodiment provides a plated circuit board structure formed through the above steps.

[第三實施例] [Third embodiment]

請參閱圖7至圖12,其為本發明的第三實施例,本實施例與第一實施例類似,相同處則不再複述,而為便於說明,本實施例的圖式以平面剖視圖呈現。具體來說,本實施例所提供之電鍍式電路板結構的製造方法,大致包括步驟如下。 Referring to FIG. 7 to FIG. 12, which is a third embodiment of the present invention, the present embodiment is similar to the first embodiment, and the same portions are not described again. For convenience of description, the drawings of the present embodiment are presented in a plan sectional view. . Specifically, the manufacturing method of the electroplated circuit board structure provided by this embodiment generally includes the following steps.

步驟S301:請參閱圖7所示,提供板材110,其中,所述板材1包含有一基板11、一第一導電層12、及一第二導電層13。上 述基板11具有位於相反側的一第一表面111與一第二表面112,所述第一導電層12位於基板11的第一表面111上,而第二導電層13位於基板11的第二表面112上。並且,所述第一導電層12的厚度小於第一表面111與第二表面112之間的距離(亦即,第一導電層12的厚度小於基板11的厚度)。再者,所述第一導電層12以及第二導電層13是由金屬薄片形成,而金屬薄片例如是銅箔片,但不受限於此。 Step S301: Referring to FIG. 7, a board 110 is provided, wherein the board 1 includes a substrate 11, a first conductive layer 12, and a second conductive layer 13. on The substrate 11 has a first surface 111 and a second surface 112 on opposite sides, the first conductive layer 12 is located on the first surface 111 of the substrate 11, and the second conductive layer 13 is located on the second surface of the substrate 11. 112 on. Moreover, the thickness of the first conductive layer 12 is smaller than the distance between the first surface 111 and the second surface 112 (that is, the thickness of the first conductive layer 12 is smaller than the thickness of the substrate 11). Furthermore, the first conductive layer 12 and the second conductive layer 13 are formed of a metal foil, and the metal foil is, for example, a copper foil, but is not limited thereto.

步驟S303:請參閱圖8所示,加工第二導電層13以成形一開孔131,進一步地說,可以藉由微影蝕刻的方式,去除部分第二導電層13以形成開孔131。據此,開孔131得以露出部分的基板11第二表面112。 Step S303: Referring to FIG. 8, the second conductive layer 13 is processed to form an opening 131. Further, a portion of the second conductive layer 13 may be removed by photolithography to form the opening 131. Accordingly, the opening 131 is exposed to a portion of the second surface 112 of the substrate 11.

步驟S305:請參閱圖9所示,以一非化學蝕刻方式加工於基板11第二表面112自開孔131顯露於外的部位,以使成形的貫孔113孔徑不大於開孔131孔徑。換言之,於開孔131的位置,向基板11方向向下形成貫孔113,並使貫孔113裸露第一導電層12,而貫孔113的孔徑小於開孔131的孔徑。 Step S305: Referring to FIG. 9, the second surface 112 of the substrate 11 is exposed from the opening 131 by a non-chemical etching method so that the formed through hole 113 has a hole diameter not larger than the opening 131. In other words, at the position of the opening 131, the through hole 113 is formed downward in the direction of the substrate 11, and the through hole 113 is exposed to the first conductive layer 12, and the aperture of the through hole 113 is smaller than the aperture of the opening 131.

再者,所述基板11第二表面112定義有一預留區域1121,而預留區域1121相當於位在所述開孔131的側壁與貫孔113的側壁之間。換言之,第二導電層13並未全面覆蓋基板11第二表面112,預留區域1121定義為開孔131的側壁與貫孔113的側壁之間所相距的區域。 Furthermore, the second surface 112 of the substrate 11 defines a reserved area 1121, and the reserved area 1121 is located between the side wall of the opening 131 and the side wall of the through hole 113. In other words, the second conductive layer 13 does not completely cover the second surface 112 of the substrate 11, and the reserved region 1121 is defined as a region between the sidewall of the opening 131 and the sidewall of the through hole 113.

此外,本實施例也可採用類似第二實施例之方法,亦即,板材1是運用增層法製程來形成(圖略)。詳細而言,先提供基板11。接著,於基板11上形成貫孔113。之後,在基板11第一表面111與第二表面112分別透過黏著層14而與第一導電層12以及第二導電層13疊合,其中第二導電層13已事先形成有開孔131。亦即,第二導電層13並未覆蓋預留區域1121。然後,進行高溫壓合,從而形成板材1。 Further, this embodiment can also adopt a method similar to that of the second embodiment, that is, the sheet material 1 is formed by a build-up process (not shown). In detail, the substrate 11 is provided first. Next, a through hole 113 is formed on the substrate 11. Thereafter, the first surface 111 and the second surface 112 of the substrate 11 are respectively superposed on the first conductive layer 12 and the second conductive layer 13 through the adhesive layer 14, wherein the second conductive layer 13 has been previously formed with the opening 131. That is, the second conductive layer 13 does not cover the reserved area 1121. Then, high temperature pressing is performed to form the sheet material 1.

接著,形成第一遮罩層3覆蓋於第一導電層12,形成一第二遮罩層4覆蓋於第二導電層13以及預留區域1121,並暴露貫孔H2。具體而言,第一遮罩層3以及第二遮罩層4可以是抗蝕刻乾,膜(anti-etching dry film)、光阻(photo resist)或者其他絕緣材料。其中,第一遮罩層3以及第二遮罩層4皆沒有覆蓋在貫孔113所裸露出的第一導電層12。 Then, the first mask layer 3 is formed to cover the first conductive layer 12, and a second mask layer 4 is formed to cover the second conductive layer 13 and the reserved area 1121, and the through hole H2 is exposed. Specifically, the first mask layer 3 and the second mask layer 4 may be an anti-etching dry film, a photo resist or other insulating material. The first mask layer 3 and the second mask layer 4 do not cover the first conductive layer 12 exposed by the through hole 113.

步驟S307:請參閱圖10所示,以第二遮罩層4為遮罩,利用電鍍方式形成傳導體2於貫孔113內。詳細而言,以電鍍方式,將銅金屬鍍滿貫孔113,據以形成實心的傳導體2。一般而言,以習知電鍍法製備傳導體時,金屬離子(例如銅離子)容易堆積於金屬層的邊緣,例如線路的邊緣或金屬層開口的邊緣,以至於金屬層的邊緣容易形成多餘的金屬瘤,例如銅瘤(copper nodule),從而降低產品良率。 Step S307: Referring to FIG. 10, the second mask layer 4 is used as a mask, and the conductor 2 is formed in the through hole 113 by electroplating. In detail, copper metal is plated through the through holes 113 by electroplating to form a solid conductor 2. In general, when a conductor is prepared by a conventional electroplating method, metal ions (for example, copper ions) are easily deposited on the edge of the metal layer, such as the edge of the line or the edge of the opening of the metal layer, so that the edge of the metal layer is easily formed redundantly. Metal tumors, such as copper nodules, reduce product yield.

然而,相較於習知電鍍技術而言,本實施例由於第二遮罩層4覆蓋於第二導電層13以及預留區域1121,所以在電鍍製備傳導體2的過程中,貫孔113的邊緣不容易因金屬離子的堆積而形成金屬瘤。據此,得以透過電鍍以促使傳導體2完整地形成。此外,第一遮罩層3覆蓋於第一導電層12的外表面,主要用於防止金屬離子附著於第一導電層12之上。 However, in the present embodiment, since the second mask layer 4 covers the second conductive layer 13 and the reserved region 1121, the through hole 113 is formed during electroplating to prepare the conductor 2, compared to the conventional plating technique. The edges are not easily formed into metal tumors due to the accumulation of metal ions. According to this, it is possible to cause the conductor 2 to be completely formed by electroplating. In addition, the first mask layer 3 covers the outer surface of the first conductive layer 12, and is mainly used to prevent metal ions from adhering to the first conductive layer 12.

步驟S309:請參閱圖11所示,去除第一遮罩層3以及第二遮罩層4。由於第一遮罩層3以及第二遮罩層4可以是抗蝕刻乾膜(anti-etching dry film)或者光阻(photo resist),所以可以透過含氫氧化鈉的水溶液而去除。接著,可以進行後續的蝕刻線路製程,以蝕刻第一導電層12從而形成第一線路121以及第二線路122,並且第二導電層13亦可蝕刻形成所需的線路圖案。不過,本發明並不對蝕刻線路製程加以限制。 Step S309: Referring to FIG. 11, the first mask layer 3 and the second mask layer 4 are removed. Since the first mask layer 3 and the second mask layer 4 may be an anti-etching dry film or a photo resist, they may be removed through an aqueous solution containing sodium hydroxide. Next, a subsequent etch line process can be performed to etch the first conductive layer 12 to form the first line 121 and the second line 122, and the second conductive layer 13 can also be etched to form a desired line pattern. However, the present invention does not limit the etching circuit process.

此外,依據使用者的不同需求,本實施例電鍍式電路板結構的製造方法更包括對傳導體2進行一磨刷處理。具體而言,可以 透過砂帶研磨機將傳導體2的頂端磨整,從而形成頂面平整的傳導體2(如圖12)。傳導體2可以具有不同的高度,亦即,傳導體2的頂端可以是齊平於第二導電層13的表面,也可以是高於第二導電層13的表面。於本實施例中,透過砂帶研磨機將傳導體2的頂端磨整至大致與第二導電層13的表面齊平。 In addition, according to different needs of the user, the manufacturing method of the electroplated circuit board structure of the embodiment further includes performing a brushing process on the conductor 2. Specifically, you can The tip of the conductor 2 is ground by a belt grinder to form a top planar conductor 2 (Fig. 12). The conductors 2 may have different heights, that is, the tips of the conductors 2 may be flush with the surface of the second conductive layer 13, or may be higher than the surface of the second conductive layer 13. In the present embodiment, the tip end of the conductor 2 is ground to a level substantially flush with the surface of the second conductive layer 13 by a belt grinder.

補充說明一點,本實施例所述之各個步驟,在合理的情況下是能將步驟之順序加以調整,換言之,本實施例並不以上述的步驟順序為限。 It should be noted that, in the respective steps described in this embodiment, the order of the steps can be adjusted under reasonable circumstances. In other words, the present embodiment is not limited to the above-described sequence of steps.

綜上所述,本實施例提供一種經由上述步驟所製造形成的電鍍式電路板結構100。 In summary, the embodiment provides a plated circuit board structure 100 formed through the above steps.

[本發明實施例的可能效果] [Possible effects of the embodiments of the present invention]

綜上所述,本發明實施例所提供的電鍍式電路板結構的製造方法,透過上述實施例之步驟所載之加法技術,使得所述電鍍式電路板結構能在第一導電層外表面位於同平面的前提下,成形至少兩種不同厚度的電路(如:連接傳導體的第一線路、第二線路)。藉此,本實施例之方法能有效達到節省材料成本、避免浪費高價金屬、以及降低汙染源等功效。 In summary, the manufacturing method of the electroplated circuit board structure provided by the embodiment of the present invention enables the electroplated circuit board structure to be located on the outer surface of the first conductive layer through the adding technique carried out in the steps of the above embodiments. On the premise of the same plane, at least two circuits of different thicknesses (for example, the first line connecting the conductor and the second line) are formed. Thereby, the method of the embodiment can effectively achieve the effects of saving material cost, avoiding waste of high-priced metals, and reducing pollution sources.

而於電鍍式電路板結構應用時,連接傳導體的第一線路(即較厚之電路)能用以傳送大功率之驅動電流,藉以降低驅動電流之阻抗,進而避免電路燒毀或因過熱而降低運作效能。再者,連接傳導體的第一線路亦能用以作為熱能排放通道,使得所述電鍍式電路板結構得以長效維持應有的工作效能。另,第二線路(即較薄之電路)能用以作為控制訊號傳遞之用。 In the application of the electroplated circuit board structure, the first line connecting the conductors (ie, the thicker circuit) can be used to transmit a high-power driving current, thereby reducing the impedance of the driving current, thereby preventing the circuit from being burned or being lowered due to overheating. Operational efficiency. Furthermore, the first line connecting the conductors can also be used as a heat energy discharge channel, so that the electroplated circuit board structure can maintain the desired working efficiency for a long time. In addition, the second line (ie, the thinner circuit) can be used as a control signal transmission.

又,由於貫孔的成形是採用非化學蝕刻方式,所以貫孔的深寬比與外型能依據設計者的需求而控制與調整。亦即,貫孔的深度能大於貫孔的寬度,並且可將貫孔成形為長條狀,進而令電鍍式電路板結構具有較廣的應用範圍。 Moreover, since the through hole is formed by a non-chemical etching method, the aspect ratio and the shape of the through hole can be controlled and adjusted according to the designer's needs. That is, the depth of the through hole can be larger than the width of the through hole, and the through hole can be formed into a long strip shape, thereby making the plated circuit board structure have a wide application range.

以上所述僅為本發明之較佳可行實施例,其並非用以侷限本發明之專利範圍,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the invention, and the equivalent variations and modifications of the scope of the invention are intended to be within the scope of the invention.

100‧‧‧電鍍式電路板結構 100‧‧‧Electroplated circuit board structure

1‧‧‧板材 1‧‧‧ plates

11‧‧‧基板 11‧‧‧Substrate

111‧‧‧第一表面 111‧‧‧ first surface

112‧‧‧第二表面 112‧‧‧ second surface

12‧‧‧第一導電層 12‧‧‧First conductive layer

121‧‧‧第一線路 121‧‧‧First line

122‧‧‧第二線路 122‧‧‧second line

2‧‧‧傳導體 2‧‧‧ Conductor

Claims (5)

一種電鍍式電路板結構的製造方法,其步驟包括:提供一板材,其中,該板材包含有一基板、一第一導電層、及一第二導電層,該基板具有位於相反側的一第一表面與一第二表面,該第一導電層位於該第一表面上,該第二導電層位於該第二表面上,且該第一導電層的厚度小於該第一表面與該第二表面之間的距離;加工該第二導電層以成形一開孔;以一非化學蝕刻方式加工於該基板第二表面自該開孔顯露於外的部位,使該基板成形有一貫穿該第一表面與該第二表面的貫孔,並使成形的該貫孔孔徑小於該開孔孔徑,而該貫孔對應於該基板第一表面之部位被該第一導電層所遮蔽,該開孔的側壁與該貫孔的側壁之間所相距的區域定義為一預留區域;形成一第一遮罩層覆蓋於該第一導電層;且形成一第二遮罩層覆蓋於該第二導電層與該預留區域,並暴露該貫孔;以一電鍍方式在該基板貫孔處充填成形一傳導體,且該傳導體的厚度大於該第一導電層的厚度;去除該第一遮罩層與該第二遮罩層;以及蝕刻該第一導電層以成形為相互分離的一第一線路與一第二線路,且該第一線路一體連接於該傳導體。 A method of manufacturing a plated circuit board structure, the method comprising: providing a board, wherein the board comprises a substrate, a first conductive layer, and a second conductive layer, the substrate having a first surface on the opposite side And a second surface, the first conductive layer is located on the first surface, the second conductive layer is located on the second surface, and the thickness of the first conductive layer is less than between the first surface and the second surface The second conductive layer is processed to form an opening; and is processed in a non-chemically etched manner on the second surface of the substrate from the exposed portion, so that the substrate is formed through the first surface and the a through hole of the second surface, and the formed aperture of the through hole is smaller than the aperture of the aperture, and the portion of the through hole corresponding to the first surface of the substrate is shielded by the first conductive layer, and the sidewall of the opening An area between the sidewalls of the through hole is defined as a reserved area; a first mask layer is formed to cover the first conductive layer; and a second mask layer is formed to cover the second conductive layer and the pre- Leave the area and expose it Forming a conductor at a through hole of the substrate by electroplating, and the thickness of the conductor is greater than a thickness of the first conductive layer; removing the first mask layer and the second mask layer; and etching the The first conductive layer is formed into a first line and a second line separated from each other, and the first line is integrally connected to the conductor. 如請求項1所述之電鍍式電路板結構的製造方法,其中,在成形該傳導體時,在該基板貫孔處實施電鍍,並且使該傳導體的外表面突出於該基板的第二表面。 The method of manufacturing a plated circuit board structure according to claim 1, wherein, when the conductor is formed, plating is performed at the through hole of the substrate, and an outer surface of the conductor protrudes from a second surface of the substrate . 如請求項1所述之電鍍式電路板結構的製造方法,其中,在該基板成形該貫孔時,是經由該非化學蝕刻方式加工於該基板的第二表面,而成形包圍定義出該貫孔的一孔壁,且該孔壁整體垂直於該第一導電層。 The method of manufacturing a plated circuit board structure according to claim 1, wherein when the through hole is formed in the substrate, the second surface of the substrate is processed by the non-chemical etching, and the through hole defines the through hole. a hole wall, and the hole wall is entirely perpendicular to the first conductive layer. 如請求項1所述之電鍍式電路板結構的製造方法,其中,在該基板成形該貫孔時,控制該貫孔的深寬比,以使該貫孔的深度大於該貫孔的寬度。 The method of manufacturing a plated circuit board structure according to claim 1, wherein when the through hole is formed in the substrate, the aspect ratio of the through hole is controlled such that the depth of the through hole is larger than the width of the through hole. 一種如請求項1所述之電鍍式電路板結構的製造方法所製造形成的電鍍式電路板結構。 A plated circuit board structure produced by the method of manufacturing a plated circuit board structure according to claim 1.
TW103101838A 2014-01-17 2014-01-17 Circuit board with electroplated type and manufacturing method thereof TWI547224B (en)

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