TWI521668B - 具有可變複數阻抗之連接器用接收電路 - Google Patents

具有可變複數阻抗之連接器用接收電路 Download PDF

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TWI521668B
TWI521668B TW099111284A TW99111284A TWI521668B TW I521668 B TWI521668 B TW I521668B TW 099111284 A TW099111284 A TW 099111284A TW 99111284 A TW99111284 A TW 99111284A TW I521668 B TWI521668 B TW I521668B
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Taiwan
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receiving
semiconductor die
inter
circuit
capacitor
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TW099111284A
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TW201130101A (en
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羅伯特 多斯特
羅伯特 霍金斯
周懷恩
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奧瑞可美國股份有限公司
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Description

具有可變複數阻抗之連接器用接收電路
本發明係有關於減輕由於半導體晶粒上的連接器與一或更多微彈簧(microspring)或各向異性膜組件間連接器之間的可變複數阻抗所造成的訊號失真之電路。
隨著積體電路(IC)技術持續縮小至更小的關鍵尺寸，現有的晶片間連接愈來愈難以提供適當的通訊特徵，例如：高頻寬、低功率、可靠度及低成本。已提出數種技術來解決此問題。這些所提出的技術包含：近接通訊或PxC(舉例而言，具有電容式晶片間接觸)、晶片間微彈簧(具有導電式晶片間接觸)、各向異性膜(舉例而言，其中，各向異性膜包含彈性體)、及PxC與微彈簧的組合(具有電容式晶片間接觸)。但是，這些所提出的技術常常導入額外的封裝及可靠度挑戰。
以電容式晶片間接觸為基礎的PxC提供密集的晶片間連接，具有相鄰墊之間的間距為10-100μm的等級。但是，PxC典型上要求類似等級的機械對齊。使用低成本晶片封裝組件，在振動及熱應力存在下，可能難以維持此對齊。此外，晶片間接觸的電容可以是小的，其使得使用PxC來耦合高容量電源供應充滿挑戰性。
可以在各種不同的表面上或是IC本身的表面上製造微彈簧，而各種不同的表面包含：印刷電路板(PCB)、有機或陶瓷IC封裝組件。它們可以被製造於高性能IC上而具有超過輸入/輸出(I/O)訊號的密度之晶片間連接的面積密度，並且，它們可以提供電接觸而不需使用銲料。此外，微彈簧可以被設計成比單獨使用PxC所可能具有的順服性具有更多的順服性，其增加對機械移動及不對齊之寬容度。但是，典型上要求微彈簧與IC上的連接器產生及維持導電接觸。為了達成此種導電接觸，微彈簧典型上具有尖銳的頂端，這些頂端可在搓刷製程(scrub-in process)期間刮過IC上的連接器上方的任何氧化物或鈍化層，其增加微彈簧的製造成本。此外，藉由增加微彈簧與晶片封裝組件中IC上的連接器之間的力量，常常可以達成導電接觸，這也增加成本。此外，尖銳的頂端及大的力量可產生外來粒子(例如，碎片)，其可隨著時間而低接觸的導電率，因而降低可靠度及限制配對週期的數目。
藉由將導電元件導入絕緣彈性膜中，以使得導電元件大致上排齊而垂直於膜的表面，以製造各向異性導電膜。然後，藉由將各向異性膜置靠在晶片墊上並將其壓縮，導電元件可以達成導電接觸，而非導電膜使鄰近的晶片墊之間維持隔離。與微彈簧不同的是，經由各向異性膜的傳導典型上係有關晶片墊與其在各向異性膜中的近接導電元件之間的傳導、以及在各向異性膜內彼此相鄰的不同導電元件之間的傳導。類似於微彈簧，各向異性膜常常苦於可靠度問題，此可靠度問題導因於用於導電元件的電位無法使彼此適當接觸及與晶片墊適當接觸。雖然藉由增加壓縮力可以增加可靠度，但是，晶片封裝組件典型上必須提供及維持此更高的力量。一般而言，晶片封裝組件內愈高的力量會以其它方式降低晶片封裝可靠度以及增加封裝成本。
為了克服此搓刷(scrub-in)及可靠度問題，已提出結合PxC與微彈簧或各向異性膜之晶片間連接。但是，此方式會導入額外的挑戰。舉例而言，用於PxC中的電容式(或電感式)發訊技術典型上無法忍受導電的晶片間接觸。因此，IC上的連接器上方的氧化物層需要夠厚及夠硬，以防止會造成導電接觸的斷裂。此較厚的氧化物層降低晶片之間電容性地耦合之能量，而更難以接收電訊號。此外，其限制經由電性式耦合的微彈簧或各向異性膜而供應給IC的功率量。
因此，需要可以達成晶片間連接而無上述問題之技術。
本發明的一個實施例提供半導體晶粒，其包含接收連接器，而接收連接器係鄰近或在半導體晶粒的表面上。此接收連接器以機械方式或電氣方式耦合至一或更多個第一組件間連接器，藉以界定接收連接器與一或更多個第一組件間連接器之間的接收可變複數阻抗。注意，接收可變複數阻抗對應於與第一電容器並聯連接的第一電阻器。此外，半導體晶粒包含接收電路，而接收電路係電耦合至接收電訊號之接收連接器。此接收電路減輕與接收變數複數阻抗有關的訊號失真。
在一些實施例中，接收電路可被適當地配置成減輕接收到的電訊號之訊號失真。因此，可以直接或間接地至少部份根據接收可變複數阻抗來選擇接收電路的配置。舉例而言，可藉由調整接收電路中的RC電路的時間常數成為約等於第一電阻器的電阻與第一電容器的電容之乘積，以配置接收電路。此外，半導體晶粒可以包含控制邏輯電路，而控制邏輯電路使接收可變複數阻抗特徵化以及選擇接收電路的配置。
注意，取決於接收連接器與一或更多個第一組件間連接器之間的電連接，第一電阻器的電阻可在0.001-100GΩ之間。
為了解決此變化性，半導體晶粒可以包含串聯電耦合於接收連接器與接收電路之間的內部阻抗，其中，在與接收到的電訊號相關連的整個頻率範圍之上，內部阻抗的阻抗為接收可變複數阻抗的主要部份。注意，內部阻抗可以包含電感器及/或第二電容器。舉例而言，第二電容器的電容可以顯著地小於第一電容器的電容。此外，第二電容器的電容可以由半導體晶粒中的介電層來予以界定。
在一些實施例中，接收到的電訊號包含調整於具有大於零的基本頻率之載波上的訊號。此外，接收到的電訊號可以包含資料及/或功率訊號。對於功率訊號而言，接收電路可以包含整流器電路，以從接收到的電訊號中恢復DC功率訊號。
注意，半導體晶粒可以包含一或更多個近接且相鄰於接收連接器之靜電於電保護連接器。除此之外，半導體晶粒可以包含與接收電路並聯之電耦合至接收連接器的靜電放電保護組件及/或近接且相鄰於第二電容器之邊緣場屏蔽。
在一些實施例中，半導體晶粒包含近接於或在半導體晶粒的表面上的發送連接器。此發送連接器以機械方式及電氣方式耦合至一或更多個第二組件間連接器，藉以界定發送連接器與一或更個多組件間連接器之間的發送可變複數阻抗。注意，發送可變複數阻抗對應於與第二電容器並聯之第二電阻器。此外，半導體晶粒可以包含電耦合至發送連接器之發送電路，而發送電路發送其它電訊號。
在一些實施例中，一或更多個第一組件間連接器包含微彈簧或各向異性膜。
另一實施例提供一系統，其包含半導體晶粒、另一半導體晶粒、及互連組件，互連組件以機械方式及電方式耦合半導體晶粒及其它半導體晶粒。此互連組件包含一或更多個第一及/或一或更多個第二組件間連接器。
另一實施例提供傳達電訊號的方法，可藉由半導體晶粒(或是半導體晶粒上的一或更多個電路)來予以執行。在操作期間，半導體晶粒從接收連接器接收電訊號，接收連接器以機械方式及電方式耦合至一或更多個組件間連接器。注意，在接收連接器與一或更多個組件間連接器之間，有接收可變複數阻抗，且此接收可變複數阻抗對應於第一電阻器並聯第一電容器。然後，至少部份根據接收到的電訊號，半導體晶粒將接收可變複數阻抗特徵化。接著，至少部份根據接收可變複數阻抗的特徵，半導體晶粒將接收電路配置成減輕與接收可變複數阻抗相關連的訊號失真。
下述說明使任何習於此技藝者能夠做成及使用本發明，且以特定應用的上下文及其需求來作說明。習於此技藝者可以容易瞭解所揭示的實施例之不同修改，並且在不悖離本發明的精神及範圍之下，在此所界定的一般原理可以被應用至其它實施例及應用。因此，本發明並非要受限於所揭示的實施例，而是要依符合此處所揭示的原理及特點之最廣範圍來做解釋。
說明用於具有可變複數阻抗(可以是導電式的、電容式的或二者皆具)之晶片間連接的電路實施例、包含該電路的系統、及通訊技術。此晶片間連接可以形成於微彈簧或各向異性膜與晶片表面上或近接於晶片表面之金屬連接器之間。此外，電路可以減輕與可變複數阻抗相關連的訊號失真。舉例而言，電路可以包含內部阻抗，內部阻抗與金屬連接器串聯電耦合，並且，在操作頻率的整個範圍之上，內部阻抗具有可變複數阻抗的主要阻抗。分開地或添加地，電路可適以校正訊號失真。
藉由容許晶片間連接的可變複數阻抗(並且，特別是，可為導電式的及/或電容式的複數阻抗)，此通訊技術可以降低或消除對金屬連接器之上氧化物或鈍化層的需求及靈敏度，其可增加經由微彈簧或各向異性膜與金屬連接器之間的晶片間連接而被傳送的訊號能量。此外，通訊技術可允許：降低微彈簧尖端尖銳度或各向異性膜導電率；降低接觸力；去除搓刷(scrub-in)處理；增加晶片間連接及系統的可靠度；降低對微彈簧或各向異性膜接觸與金屬連接器間之未對齊的靈敏度；更小的靜電放電(ESD)保護組件(其佔據有價值的晶片面積；降低最大操作頻率及耗電)；及/或降低微彈簧或各向異性膜與系統的封裝組件之製造和組裝成本。
我們現在說明晶片間連接技術的實施例。圖1A顯示方塊圖，其顯示現有的晶片間連接技術100，其中，結合PxC地使用微彈簧114-1。在此晶片間連接技術中，微彈簧114-1降低例如金屬墊112-1等有距離之使用PxC通訊的連接器或墊之間的電容。注意，由於PxC收發器118無法容許任意值的導電接觸或耦合，所以，IC或晶片110-1的表面塗著有鈍化層116-1(例如，玻璃層)以防止微彈簧114-1導電地接觸金屬墊112-1。此外，鈍化層116-1、微彈簧114-1及金屬墊112-1可具有相當小的電容。舉例而言，假使微彈簧114-1的尖端具有約15×15μm2的面積(A)，並且，鈍化層116-1具有約1μm的厚度(d)以及7.5的介電常數(ε r )，則其至金屬墊112-1的電容(Cpad)為
其中，ε o 是自由空間的電容率(8.85 pF/m)。使用此例中的值，Cpad是15 fF。
假定此電容，我們現在考慮有多少功率可以經由一個金屬墊藉由方波功率訊號而被轉移。假定3.3V功率訊號振盪於500 MHz，並且，在每一個循環期間轉移儲存於電容器中的所有能量(其為有點樂觀的假設)，則平均功率(Poweravg)為
Poweravg=Cpad‧(Vswing)2‧T 0 . 5 ,
其中，T0.5是半週期。使用15 fF的Cpad及1 ns的T0.5，Poweravg為0.16 mW。
此外，由高頻5 Gbps資料訊號所見的接觸之串聯阻抗(R)的量值係給定如下：
其中，f是5 Gbps的一半或2.5 GHz。因此，R是4.3 kΩ。雖然能夠以如此大的電阻來轉移電訊號，但是，假使阻抗較低，則將會更容易。類似地，雖然某些功率可以經由鈍化層116-1來予以傳送，但是，為了供應供應即使1 W的功率，將需要10,000個以上的微彈簧。
圖1B呈現方塊圖，顯示現有的晶片間連接技術150，其中，各向異性膜接觸發生於各向異性膜160而非發生於一或更多個微彈簧。舉例說明的各向異性膜包含PariPoser材料(來自麻省Fall River之Paricon Technologies,Inc.)、以及一些有專利的膜，包含：美國專利第5,624,268號，案名為「使用各向異性導電膜之電導體(“Electrical Conductors Using Anisotropic Conductive Films”)」，以及，美國專利4,778,950號，案名為「各向異性彈性互連系統(“Anisotropic Elastomeric Interconnecting System”)」。圖1B顯示PariPoser型各向異性導電彈性膜之剖面。在各向異性膜160中，小的導電球係懸浮於矽氧橡膠中，以致於球通常排成柱(例如，柱162)，並且提供垂直於各向異性膜160之表面但並未與其相切的傳導。類似於圖1A，金屬墊112-1可具有例如保護層116-1等鈍化層，以防止任何複雜導電接觸。結果，現有的晶片間連接技術150可能苦於相當可觀的限制，其包括經由接觸之有限的功率或訊號能量轉移。
在後續的說明中，使用微彈簧與微彈簧接觸作為本揭示中的實施例說明。但是，應瞭解這些實施例也可被應用至各向異性膜及各向異性膜接觸。
圖2A呈現方塊圖，顯示用於接收電路210之晶片間連接技術200，圖2B呈現方塊圖，顯示用於發送電路260之晶片間連接技術250。在圖2A及2B中，例如微彈簧114-1等之一或更多個微彈簧分別接觸晶片110的表面上或近接晶片110的表面之接觸金屬墊112-1、以及相關連的接收電路210或發送電路260等，以接收或發送導電式或電容式耦合資料或功率訊號。注意，微彈簧114-1耦合至金屬墊112-1，其中，藉由晶片110的鈍化層116-2中的切口(cut)，金屬墊112-1係曝露於空氣中。此外，晶片110-2包含ESD元件212-1(例如，接地之二極體)，以及，晶片110-3可以包含選加的ESD元件212-2(因為發送電路260可能對ESD較不敏感)。
假使曝露於空氣之金屬墊112-1上的氧化物的厚度(d)為2至3 nm(舉例而言，其為空氣中的純鋁上之自行限制氧化物生長)，則耦合的電容器的平均電流增加且等效阻抗減少500-333倍。使用來自先前計算的值，Poweravg為54 mW且R為13Ω。結果，我們可以僅使用約40個微彈簧(例如，20個供應供應電流，20個汲取供應電流)，即可供應1 W的功率。由於可以在晶片上圖案化數以萬計的微彈簧，所以，可以供應數百瓦的功率。
注意，對於功率轉移，與ESD元件212相關連之大的寄生電容是可以接受的(典型上，對於接合墊而言為2-8 pF)。但是，對於訊號傳送，此ESD組件電容可能會令人無法接受地衰減高頻資訊或導入符際干擾。
圖3A呈現方塊圖，顯示用於接收電路210的晶片間連接技術300。在圖3A中，導電式或電容式耦合金屬墊112-1藉由電容器312-1而與接收電路210以電容方式相隔離。更一般而言，晶片110-4包含串聯電耦合於金屬墊112-1與接收電路210之間的內部阻抗，例如，電感器及/或電容器。注意，電容器312-1的電容可對應於沈積於晶片110-4上之層的厚度及介電常數。
在本實施例中，用以保護電容式耦合接收電路210之ESD元件310-1可以顯著地減少。因此，由於藉由接近的曝露於空氣的ESD保護器墊(於下，如同參考圖4所進一步說明者)，可以保護金屬墊112-1免於ESD侵入，所以，ESD元件310-1可以加上小很多的寄生負載(典型上，低至2 fF)。
晶片間連接技術300也可以提供優於現有的晶片間連接技術100的顯著優點(圖1A)。在現有的晶片間連接技術100(圖1A)中，藉由小於金屬墊112-1之寄生電容的一半，金屬墊112-1典型上係僅電容式耦合至微彈簧114-1。此有限的電容進一步降低電訊號。相反地，在圖3A中，在金屬墊112-1與輸入至接收電路210之間的電容器312-1可以相對於寄生電容而被設計成具有非常高的耦合比例。
由於不同的ESD靈敏度，以及在圖3A中包含接收電路210的晶片上使用電容式耦合，所以，設有發送電路之相對應的晶片可以不需要包含例如電容器312-1等電容器。但是，在某些實施例中，設有發送電路之相對應的晶片包含此電容器。這被顯示於圖3B中，其呈現一方塊圖，顯示用於設有選加的電容器312-2之發送電路260的晶片間連接技術350。在某些實施例中，晶片110-5包含選加的ESD元件310-2。在下述說明中，如所示般使用晶片110中的接收電路。在某些實施例中，與晶片110中的發送電路分開地或添加地使用所述的組件及技術。
圖4呈現方塊圖，其顯示晶片間連接技術400，其中，叉合的金屬指狀物形成屏蔽電容器410，屏蔽電容器410將非常少的寄生電容加至晶片110-6中的接收電路210的輸入節點。因此，接收到的訊號可以是相當大的。注意，非導電式屏蔽電容器410連接金屬墊112-1至接收電路210。此外，邊緣場屏蔽412也降低寄生電容。餘留的寄生電容可以藉由與微彈簧114-1相接觸的阻抗而被很快地驅動。雖然圖4顯示在一個金屬層中的叉合，但是，可以使用更多金屬層以進一步增加比例。
圖4也顯示在訊號金屬墊112-1的任一側上之ESD曝露於空氣的金屬墊414。這些金屬墊、及相關連的ESD元件416允許小型ESD元件418(例如，比ESD元件310具有更小的寄生負載的接地之二極體或電容器)來保護電容式屏蔽接收器輸入免於自kV等級的ESD事故。ESD曝露於空氣的金屬墊414可以由多個電容式或導電式耦合微彈簧金屬墊或連接所共用，以降低有效面積成本。
圖5顯示等效電路500，其具有與例如耦合至晶片上的金屬墊或連接器之微彈簧等晶片間連接相關連的可變複數阻抗。此等效電路具有與電容器(Ccontact) 512並聯的電阻器(Rcontact) 510。取決於微彈簧尖端是否穿過金屬墊上的氧化物及穿透程度，Rcontact 510典型上具有在0.01Ω至無限大阻抗之間的值。取決於微彈簧尖端與金屬墊之間重疊的面積、以及氧化物的厚度和微彈簧尖端與金屬墊之間的氣隙，Ccontact 512典型上具有1-10 pF數量級的值。為了使經由接觸所傳送的訊號或功率最大化，接觸阻抗(Zcontact)應該儘可能地小。Zcontact係給定如下
其中，j是-1的方根，w是角頻率。根據等式(1)，降低Rcontact 510確保無論Ccontact 512為何，Zcontact在所有頻率均為小。但是，假使Rcontact 510為大或無限大，則在高頻的Ccontact 512仍然造成小的接觸阻抗。因此，在某些實施例中，無論電阻式及電容式接觸的混合為何，藉由AC調變功率及/或資料訊號，仍然可以取得小的接觸阻抗。
圖6A代表方塊圖，顯示發送電路600，圖6B呈現時序圖650，其顯示相關連的電訊號。在發送電路600中，未編碼的訊號Datain 610藉由時脈訊號(Clk)612而被調變以產生DC平衡(50%高及50%低)訊號Txdata 614。此調變技術有時被稱為1b2b，其意指一個位元的資料已分散於成二位元的編碼資料上。因此，此調變技術具有與頻寬相關之50%的編碼額外負擔(coding overhead)。例如4b6b或8b10b或64b65b等其它調變技術具有更低的編碼額外負擔，但是典型上要求更複雜的編碼及解碼電路、以及更高的增加潛時。在某些實施例中，使用備用頻道(spare channels)以週期性地更新發送頻道，使得Datain 610不須被編碼成為DC平衡的。此外，在某些實施例中，使用容許具有最大執行長度限制的輸入之接收電路偏壓而不是例如Txdata 614等之DC平衡訊號。
圖7及8呈現方塊圖，其顯示與Txdata 614一起工作的接收電路700及800。在圖7中，晶片間連接被來自ESD元件的Cshield 718及以Cesd 720表示之其寄生電容所屏蔽。
我們現在說明輸入節點710與接收輸入節點(Rxin)714之間的有效阻抗。因為Ccontact 512典型上具有約1-10 pF的值，所以Cshield 718可以被設計成具有總是遠小於Ccontact 512的電容，例如0.1 pF。假定叉合Cshield(如圖4所示)，則寄生電容器Cshpar 722的電容可約為Cshield 718的一半或0.05 pF。假使Rcontact 510為無限大，並且使用以接收墊節點712(Rxpad)作為連接至輸入節點710、Rxin 714、及接地(經由Cshpar 722)的中央節點之y-Δ(delta)轉換時，則輸入節點710與Rxin 714之間的有效阻抗(Zeff)為：
假使Rcontact 510係小於無限大，則隨著Zeff相對於Cshield 718及Cshpar 722而更小，此近似變得更接近於係正確的。
此外，假使AC調變為在遠大於由Rbias 724所導入的極點一零點對(高通濾波器)的頻率處，則雖然有來自Cshield 718與Cesd 720和放大器726的輸入電容的總合之間的電容分壓器之衰減，但是，Txdata 614被未失真地傳送至Rxin 714。注意，因為Cesd 720可能僅為數毫微-微法拉，所以此衰減可為小的，並且，相較於Cshield 718，放大器726的輸入電容可為小的。
在接收電路800中，由於沒有Cshield 718，所以，耦合至接收輸入節點(Rxonshield)810的淨訊號能量將比耦合至Rxin 714的淨訊號能量更多(圖7)。不幸的是，耦合至Ronoshield 810的訊號可能會因其可在不同頻率處遭受不同的衰減及相位偏移而失真。但是，假使由Rcontact 510及Ccontact 512的乘積所給定的時間常數符合接收電路800的內部時間常數，亦即，Rbias 724與Csed 720及放大器726的輸入電容的總合的乘積。
由於Rcontact 510及/或與微彈簧和金屬連接器或墊之間的耦合相關連的Contact 512之可能的變化，所以，在某些實施例中，藉由選取或調整Rbias 724及Cesd 720和放大器726的輸入電容的總合中的任一者或二者，可以調整接收電路800的內部時間常數。此調整可以至少部份根據來自控制邏輯812(或控制邏輯電路)的指令或訊號。此外，在直接或間接地特徵化與晶片間連接相關連的可變阻抗(例如，Rcontact 510、Ccontact 512及/或它們的乘積)之後，控制邏輯812可以調整接收電路800的內部時間常數。舉例而言，假使接收電路800的內部時間常數太大，則Txdata 614上的方波將失真且在每一個轉變(transition)之後立即欠量不足(undershoot)。或者，假使接收電路800的內部時間常數太小，則Txdata 614在每一個轉變之後立即超量(overshoot)。控制邏輯812可以在每一個轉變之後取樣Rxnoshield 810二次，並且使用訊號的斜率可決定是否增加或降低Rbias 724、Cesd 720及/或放大器726的輸入電容的可控制值。
注意，雖然以固定的配置(因為圖7中的Cshield 718可具有總是遠小於Ccontact 512的電容)來說明接收電路700(圖7)，但是，在某些實施例中，接收電路700(圖7)包含選加的直接或間接特徵化晶片間連接的控制邏輯728(或控制邏輯電路)，且因此選取或調整接收電路700的內部時間常數(圖7)。
此外，雖然圖7及8均各自顯示有一個訊號路徑，但是，在其它實施例中，至少資料訊號的差動訊號路徑被用來降低對雜訊源的易感受性。在這些實施例中，圖7及8中的Vthreshold 730被第二訊號路徑所取代。
圖9A呈現時序圖，其顯示功率訊號TXpower 910，及圖9B呈現方塊圖，其顯示相關連的功率電路950。由於晶片間連接可以是電容式的，所以，TXpower 910可以當作AC訊號被傳送。此訊號可以從電源直接取得，或是使用DC對AC轉換器電路而被產生。注意，TXpower 910的訊號擺幅可以比晶片核心960需要的還大兩個二極體壓降，以使補償在功率電路950的每一臂中的兩個二極體壓降。舉例而言，假使晶片核心960需要1.8V，且每一個二極體壓降為0.15V(舉例而言，針對肖特基二極體)，則TXpower 910可以是2.1V。圖9A也顯示在功率電路950之後的淨功率訊號(Vddcore)912。注意，Vddcore 912中的漣波會隨著晶片核心960的電流汲取而增加(圖9B)，並且，隨著更多的旁通電容加被至晶片核心960(圖9B)而減少(圖9B)。此外，漣波隨著接觸阻抗Zcontact的下降而下降。
雖然圖9B中的功率電路950係顯示為橋式整流器，但是，在其它實施例中，功率電路950使用切換式電容整流器而分開或額外地整流TXpower 910。此方式也允許整流器視需要而使振幅步升或步降。此外，在功率電路950之後，可能有DC對DC轉換器電路。為了使功率轉移最大化，在某些實施例中，功率訊號頻道中的發送晶片及接收晶片均未包含屏蔽電容器。
我們現在說明系統的實施例，而在該系統中，半導體晶片或晶片使用微彈簧而彼此耦合(直接地或間接地)。圖10呈現方塊圖，其顯示設有使用微彈簧1014-1而被耦合的晶片1010-1及1012-1之系統1000。微彈簧1014-1可以被集成於晶片1012-1上，並且，玻璃切口中的接觸墊1016-1可以被集成於晶片1010-1上。在本實施例的變型中，對於不同的金屬墊1016-1可以有分開的玻璃切口；使用微彈簧，晶片1010-1及1012-1可以接觸額外的晶片(如圖11中下部所示般)，或者，單一晶片可以具有微彈簧1014-1及設有墊1016-1的玻璃切口，用以接觸一或更多個其它的晶片。
圖11呈現方塊圖，其顯示系統1100，系統1100具有使用微彈簧1014-1及1014-2而被耦合的晶片1010-2及1010-3。在圖11中，耦合係藉由在二面上皆設有微彈簧1014-1和1014-2之插入晶片1110而被調停(mediated)。晶片1010-2及1010-3上的金屬墊1016經由插入晶片1110而連通訊。注意，在晶片1012與1013之間的給定連接包含串聯的二個導電式或電容式接點。藉由將對應的轉換函數分解成二個串聯的轉換函數，仍然可以應用先前所述的分析。
在圖11中，插入晶片1110提供所有的微彈簧1014-1及1014-2，以供接觸至晶片1010-2及1010-3。注意，從插入晶片1110的其中一面上之微彈簧1014-1至另一面上的微彈簧1014-2之連接並未顯示出。這些連接可以在二表面上從左至右，以相同的次序來連接微彈簧，可以包含微彈簧配對的某些重新排序，或是假使需要時，可連接一個微彈簧至多個其它的微彈簧。在其它實施例中，插入晶片1110針對至少連接的某些組提供接觸之金屬墊部份而非微彈簧。此外，插入晶片1110可以延伸至左方及右方，並且接觸增加的晶片。再者，插入晶片1110內部中之微彈簧或金屬墊之間的連接可以允許給定的晶片與中間插入晶片1110之二側上的任何或所有晶片相通訊。
圖12呈現方塊圖，其顯示系統1200，系統1200設有使用共同基板1210(例如，陶瓷或有機基板材料)的其中一側上的微彈簧1014-1及1014-2而被耦合的晶片1010-2及1010-3。此為系統1100(圖11)的變型，其中，所有的晶片在插入晶片1110(圖11)的其中一側上，而插入晶片1110己被改稱為基板1210。因為此配置更便於將功率及訊號導入封裝置的其中一面，並且將熱從相反面移除出去，所以該配置對於封裝晶片而言可說是有用的。在某些實施例中，基板1210藉由球狀柵格陣列(BGA)或接腳柵格陣列(PGA)而被耦合至選加的電路板1212。
在某些實施例中，發送電路或接收電路在連接的微彈簧側或金屬墊側上。如同先前所述般，發送電路也可以使用晶片上屏蔽電容器而非導電式地耦合到晶片間連接。雖然，相對於導電式連接至頻道，所傳送的能量將被降低，但是，此方式可以縮小耦合至發送電路之一或更多個ESD組件的尺寸，因此，可以降低耗電。
由於先前實施例中的微彈簧不再需要尖銳的頂端搓刷，所以，這些微彈簧可以具有各種不同的形狀，例如長方形、圓形及/或指狀。這些形狀可以使得微彈簧的製造更容易、增加可靠度、及/或增加接觸電容。雖然使用屏蔽電容器來顯示非導電式屏蔽，但是，在其它實施例中，可以使用例如耦合的螺旋金屬電感器(其有效地用作為變壓器)等一或更多個電感器。
此外，在某些實施例中，在給定晶片上可以有二或更多個微彈簧幾何形狀。舉例而言，資料-訊號微彈簧可以是短的且具有鈍的末端，而功率訊號微彈簧可以是較長的且具有較尖銳的頂端。依此方式，功率訊號微彈簧可以更容易搓刷以及形成電阻式連接，藉由使功率轉換最大化，並且可以允許更簡單的DC功率傳輸。此外，藉由包含多餘的功率訊號微彈簧，即使某些功率訊號微彈簧喪失導電式連接，仍然可以提高產能及長期可靠度。由於這些連接可以使用容許導電式及/或電容式接觸之電路(例如，圖7及8中的接收電路700及800)，所以，資料訊號微彈簧可以被設計成具有較低的插入力，藉以簡化封裝設計。
在某些實施例中，使用電子對齊技術來校正例如圖10-12中所示的系統之系統中之平面的機械不對齊。舉例而言，假使給定的微彈簧接觸發送或接收微墊或微條陣列，則電子對齊可以和導電式一電容式接觸一起被使用。
由於表面粗糙度或不平坦度，所以，氧化物的厚度及給定的微彈簧與金屬墊之間的氣隙可以大於氧化物層單獨的厚度。為了增加接觸的電容，在某些實施例中，可以將導電液、導電膠或導電膜加至接觸面以填充任何間隙。這也對增加重疊面積至液體、膠或膜延伸至給定的微彈簧的邊緣之外的程度，具有有利的功效。
注意，先前的實施例可以包含較少的組件或增加的組件。舉例而言，在具有各向異性彈性膜的實施例中，晶片金屬墊的曝露金屬具有一或更多個增加的層添加至它們，使得它們的上表面延伸超過晶片鈍化層的高度。此外，二或更多個組件可以被結合成單一組件及/或一或更多個組件的位置可以改變。在某些實施例中，如同此技術中所知般，以較多的硬體及較少的軟體、或是較少的硬體及較多的硬體來實施該功能性。此外，可以使用PMOS及/或NMOS來實施電路，並且，訊號可以包含具有近似離散值的數位訊號、及/或具有連續值的類比訊號。
我們現在說明用以傳達電訊號的程序之實施例，其可藉由半導體晶粒(或者，半導體晶粒上的一或更多個電路)來予以執行。圖13呈現流程圖，其顯示用以傳達電訊號之程序1300。在操作期間，半導體晶粒從以機械方式及電方式耦合至一或更多個組件間連接器(1310)之接收連接器接收電訊號。注意，在接收連接器與一或更多個組件間連接器之間有接收可變複數阻抗，並且，此接收可變複數阻抗相當於第一電阻器並聯第一電容器。然後，半導體晶粒至少部份根據接收到的電訊號(1312)，特徵化接收可變複數阻抗。接著，半導體晶粒將接收電路配置成至少部份根據接收可變複數阻抗(1314)的特徵，減輕與接收可變複數阻抗相關連的訊號失真。
在程序1300的某些實施例中，有增加的或更少的操作。此外，操作的次序可以改變，及/或，二或更多個操作可以被結合成單一操作。
僅為顯示及說明而作出本發明的實施例的上述說明。它們並非是詳盡無漏的或是要將本發明限定於所揭示的形式。因此，習於此技藝者清楚可知很多修改及變化。此外，上述揭示並非要限定本發明。本發明的範圍係藉由後附的申請專利範圍來予以界定。
100．．．晶片間連接技術
110-1．．．晶片
110-2．．．晶片
110-3．．．晶片
110-4．．．晶片
110-5．．．晶片
110-6．．．晶片
112-1．．．金屬墊
114-1．．．微彈簧
116-1．．．保護層
116-2．．．保護層
118．．．收發器
150．．．晶片間連接技術
160．．．各向異性膜
162．．．柱
200．．．晶片間連接技術
210．．．接收電路
212-1．．．靜電放電元件
212-2．．．靜電放電元件
250．．．晶片間連接技術
260．．．發送電路
300．．．晶片間連接技術
310-1．．．靜電放電元件
310-2．．．靜電放電元件
312-1．．．電容器
312-2．．．電容器
350．．．晶片間連接技術
400．．．晶片間連接技術
412．．．邊緣場屏蔽
414-1．．．金屬墊
414-2．．．金屬墊
416-1．．．靜電放電元件
416-2．．．靜電放電元件
418．．．小型靜電放電組件
500．．．等效電路
510．．．電阻器
512．．．電容器
600．．．發送電路
700．．．接收電路
726．．．放大器
728．．．控制邏輯
800．．．接收電路
826．．．放大器
812．．．控制邏輯
950．．．功率電路
960．．．晶片核心
1000．．．系統
1010-1．．．晶片
1012-1．．．晶片
1014-1．．．微彈簧
1016-1．．．墊
1100．．．系統
1010-2．．．晶片
1010-3．．．晶片
1014-1．．．微彈簧
1014-2．．．微彈簧
1016-1．．．墊
1016-2．．．墊
1110．．．插入晶片
1200．．．系統
1210．．．基板
1212．．．電路板
圖1A是方塊圖，顯示現有之設有微彈簧的晶片間連接技術。
圖1B是方塊圖，顯示現有之設有各向異性膜的晶片間連接技術。
圖2A是方塊圖，顯示依據本發明的實施例之晶片間連接技術。
圖2B是方塊圖，顯示依據本發明的實施例之晶片間連接技術。
圖3A是方塊圖，顯示依據本發明的實施例之晶片間連接技術。
圖3B是方塊圖，顯示依據本發明的實施例之晶片間連接技術。
圖4是方塊圖，顯示依據本發明的實施例之晶片間連接技術。
圖5顯示依據本發明的實施例之與晶片間連接相關連的可變複數阻抗的等效電路。
圖6A是方塊圖，顯示依據本發明的實施例之發送電路。
圖6B是時序圖，顯示依據本發明的實施例之電訊號。
圖7是方塊圖，顯示依據本發明的實施例之接收電路。
圖8是方塊圖，顯示依據本發明的實施例之接收電路。
圖9A是時序圖，顯示依據本發明的實施例之功率訊號。
圖9B是方塊圖，顯示依據本發明的實施例之功率電路。
圖10是方塊圖，顯示依據本發明的實施例之設有使用微彈簧耦合的晶片之系統。
圖11是方塊圖，顯示依據本發明的實施例之設有使用微彈簧耦合的晶片之系統。
圖12是方塊圖，顯示依據本發明的實施例之設有使用微彈簧耦合的晶片之系統。
圖13是流程圖，顯示依據本發明的實施例之傳達電訊號的程序。
注意，圖式中類似的代號意指對應的部份。
110-2．．．晶片
110-3．．．晶片
112-1．．．金屬墊
114-1．．．微彈簧
116-2．．．保護層
210．．．接收電路
212-1．．．靜電放電元件
212-2．．．靜電放電元件
250．．．晶片間連接技術
260．．．發送電路

Claims (18)

  1. 一種半導體晶粒，包括：接收連接器，近接該半導體晶粒的表面，係配置成以機械方式及電方式耦合至一或更多個第一組件間連接器，藉以界定該接收連接器與該一或更多個第一組件間連接器之間的接收可變複數阻抗，其中，該接收可變複數阻抗相當於第一電阻器並聯第一電容器；以及接收電路，係電耦合至該接收連接器，以接收電訊號，其中，該接收電路係配置成減輕與該接收可變複數阻抗相關連的訊號失真，其中，該接收電路可配置成減輕該接收到的電訊號的訊號失真，並且其中，配置該接收電路包含調整該接收電路中的RC電路的時間常數至幾乎等於該第一電阻器的電阻與該第一電容器的電容的乘積。
  2. 如申請專利範圍第1項之半導體晶粒，其中，該一或更多個第一組件間連接器包含微彈簧或各向異性膜。
  3. 如申請專利範圍第1項之半導體晶粒，其中，至少部份地根據該接收可變複數阻抗來選擇該接收電路的配置。
  4. 如申請專利範圍第3項之半導體晶粒，又包括控制邏輯電路，係配置成特徵化該接收可變複數阻抗及選擇該接收電路的配置。
  5. 如申請專利範圍第1項之半導體晶粒，又包括串 聯地電耦合於該接收連接器與該接收電路之間的內部阻抗，其中，該內部阻抗的阻抗在與該接收到的電訊號相關連的整個頻率範圍之上為該接收可變複數抗的主要部份，且，其中，該內部阻抗包含電感器或第二電容器。
  6. 如申請專利範圍第5項之半導體晶粒，其中，該第二電容器的電容顯著地小於該第一電容器的電容。
  7. 如申請專利範圍第5項之半導體晶粒，其中，該接收到的電訊號包含具有大於零的基本頻率之載波上調變的訊號。
  8. 如申請專利範圍第5項之半導體晶粒，其中，該接收到的電訊號包含資料或功率訊號。
  9. 如申請專利範圍第8項之半導體晶粒，其中，該接收電路包含整流器電路，以從該接收到的電訊號恢復DC功率訊號。
  10. 如申請專利範圍第5項之半導體晶粒，其中，該第二電容器的電容係由該半導體晶粒中的介電層來予以界定。
  11. 如申請專利範圍第5項之半導體晶粒，又包括近接於且相鄰於該接收連接器之一或更多個靜電放電保護連接器。
  12. 如申請專利範圍第11項之半導體晶粒，又包括靜電放電保護元件，係電耦合至與該接收電路並聯的該接收連接器。
  13. 如申請專利範圍第5項之半導體晶粒，又包括近 接於且相鄰於該第二電容器之邊緣場屏蔽。
  14. 如申請專利範圍第1項之半導體晶粒，其中，該等接收到的電訊號包含用於該半導體晶粒之資料或功率。
  15. 如申請專利範圍第1項之半導體晶粒，其中，該接收連接器在該半導體晶粒的表面上。
  16. 如申請專利範圍第1項之半導體晶粒，又包括：發送連接器，近接該半導體晶粒的表面，係配置成以機械方式及電方式耦合至一或更多個第二組件間連接器，藉以界定該發送連接器與該一或更多個組件間連接器之間的發送可變複數阻抗，其中，該發送可變複數阻抗相當於第二電阻器並聯第二電容器，以及，發送電路，係電耦合至該發送連接器，以發送另一電訊號。
  17. 一種具有使用微彈簧耦合之晶片的系統，包括：第一半導體晶粒；互連組件，以機械方式及電方式耦合至該第一半導體晶粒，其中，該互連組件包含多個組件間連接器；第二半導體晶粒，以機械方式及電方式耦合至該互連組件，其中，該第二半導體晶粒包含：接收連接器，在該半導體晶粒的表面上，係配置成以機械方式及電方式耦合至一或更多個該組件間連接器，藉以界定該接收連接器與該一或更多個該組件間連接器之間的接收可變複數阻抗，其中，該接收可變複數阻抗相當於第一電阻器並聯第一電容器；以及 接收電路，係電耦合至該接收連接器，以接收電訊號，其中，該接收電路係配置成減輕與該接收可變複數阻抗相關連的訊號失真。
  18. 一種傳達電訊號之方法，包括：在半導體晶粒上接收來自以機械方式及電方式耦合至一或更多個組件間連接器之接收連接器的該電訊號，其中，在該接收連接器與該一或更多個組件間連接器之間有接收可變複數阻抗，且，其中，該接收可變複數阻抗相當於第一電阻器並聯第一電容器；至少部份根據該接收到的電訊號，特徵化該接收可變複數阻抗；以及至少部份根據該接收可變複數阻抗，將接收電路配置成減輕與該接收可變複數阻抗相關連的訊號失真，其中，該接收電路可配置成減輕該接收到的電訊號的訊號失真，並且其中，配置該接收電路包含調整該接收電路中的RC電路的時間常數至幾乎等於該第一電阻器的電阻與該第一電容器的電容的乘積。
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